            PRELIMINARY


                                                                                                                                                  Advanced
   Am79C90                                                                                                                                           Micro
   CMOS Local Area Network Controller for Ethernet (C-LANCE)                                                                                       Devices

   DISTlNCTlVE CHARACTERISTICS
   ■ Compatible with Ethernet and IEEE 802.3                                     ■ Diagnostic Routines
     10BASE 5 Type A, and 10BASE 2 Type B,                                         — Internal/external loop back
     “Cheapernet,” 10BASE-T
                                                                                   — CRC logic check
   ■ Easily interfaced with 80x86, 680x0, Am29000,
                                                                                   — Time domain reflectometer
     Z8000TM, LSI-IITM microprocessors
                                                                                 ■ Low power consumption for power sensitive
   ■ On-board DMA and buffer management,                                           applications
     64-byte Receive, 48-byte Transmit FIFOs
                                                                                 ■ Completely software and hardware compatible
   ■ 24-bit wide linear addressing (Bus Master                                     to AMD’s LANCE device (Am7990)
     Mode)                                                                         (see Appendix B)
   ■ Network and packet error reporting
   ■ Back-to-back packet reception with as little as
     0.5 µs interframe spacing


   GENERAL DESCRIPTION
   The Am79C90 CMOS Local Area Network Controller for                            microprocessor, is intended to provide the user with a
   Ethernet (C-LANCE) is a 48-pin VLSI device designed                           complete interface module for an Ethernet network. The
   to greatly simplify interfacing a microcomputer or mini-                      Am79C90 is designed using a scalable CMOS technol-
   computer to an IEEE 802.3/Ethernet Local Area Net-                            ogy and is compatible with a variety of microprocessors.
   work. The C-LANCE, in conjunction with the Am7992B                            On-board DMA, advanced buffer management, and ex-
   Serial Interface Adapter (SIA), Am7996 or Am79C98                             tensive error reporting and diagnostics facilitate design
   Transceiver, and closely coupled local memory and                             and improve system performance.


   BLOCK DIAGRAM

          DAL15:0                   Parallel
                                      Bus
                                   Interface
            A23:16                                                             DMA/Data
                                                                                                                    Microprogram
                                                                                 Path
                                                                                                                        Store
                                                                                Control


                 INTR
                HOLD
  Local         HLDA
  CPU
               ALE/AS
Interface
                   CS
                  ADR             C-LANCE/
                  DAS                CPU                                                                                                               RX
                DALO                Control
                                      Bus                                                                                                              RCLK
                 DALI                                                                                                                                  TX
                                   Interface           Station                                                                                                Am7992B
                READ                                                                       Retry                          Serial I/O
                                                      Address                                                                                          TCLK      SIA
            BM0/BYTE                                                                       Logic                          Interface
                                                      Detection                                                                                        CLSN   Interface
          BM1/BUSAKO
               READY                                                                                                                                   TENA
               RESET                                                                                                                                   RENA
                                                                                                                                                        17881B-1
    Publication# 17881 Rev. B   Amendment /0   This document contains information on a product under development at Advanced Micro Devices, Inc.
                                               The information is intended to help you to evaluate this product. AMD reserves the right to change or
                                                                                                                                                               1-3
    Issue Date: May 1994
                                               discontinue work on this proposed product without notice.
        AMD                                           PRELIMINARY

  RELATED AMD PRODUCTS
   Part No.            Description
   Am7996              IEEE 802.3/Ethernet/Cheapernet Tap Transceiver
   Am79C100            Twisted-Pair Ethernet Transceiver Plus (TPEX+)
   Am79C900            Integrated Local Area Communications ControllerTM (ILACCTM)
   Am79C940            Media Access Controller for Ethernet (MACETM)
   Am79C960            PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
   Am79C961            PCnet-ISA Single-Chip Ethernet Controller (with Microsoft Plug n’ Play support)
   Am79C965            PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386DX, 486 and VL buses)
   Am79C970            PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
   Am79C974            PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
   Am79C98             Twisted-Pair Ethernet Transceiver (TPEX)
   Am79C981            Integrated Multiport Repeater PlusTM (IMR+TM)
   Am79C987            Hardware Implemented Management Information BaseTM (HIMIBTM)

  CONNECTION DIAGRAMS
                           DIP                                                                 PLCC

           VSS    1                   48     VDD
         DAL7     2                   47     DAL8                                                                                      HOLD/BUSRQ


                                                                                                                           BM1/BUSRQ
         DAL6     3                   46     DAL9                                                    NC
                                                                                                                                       ALE/AS
                                                                                     READ    DALI    DAS
                                                                       DAL1
         DAL5                                DAL10
                                                                              DAL0
                  4                   45
                                                                                             DALO
         DAL4     5                   44     DAL11                                   INTR    NC      BM0/BYTE   NC   NC                HLDA         NC
         DAL3     6                   43     DAL12                     9 8 7 6 5 4 3 2                  1 68 67 66 65 64 63 62 61
         DAL2     7                   42     DAL13          NC    10                                                                                 60    NC
         DAL1     8                   41     DAL14          NC    11                                                                                 59    CS
         DAL0                                             DAL2    12                                                                                 58    NC
                  9                   40     DAL15
                                                          DAL3    13                                                                                 57    NC
         READ     10                  39     A16
                                                          DAL4    14                                                                                 56    ADR
          INTR    11                  38     A17                                                                                                           READY
                                                          DAL5    15                                                                                 55
          DALI    12                  37     A18          DAL6    16                                                                                 54    RESET
         DALO                                             DAL7    17                                                                                 53    NC
                  13                  36     A19
                                                           VSS    18                                                                                 52    NC
          DAS     14                  35     A20
                                                           VDD    19                                                                                 51    VSS
  BM0/BYTE        15                  34     A21          DAL8    20                                                                                 50    TCLK
BM1/BUSAKO        16                  33                  DAL9    21                                                                                 49    TENA
                                             A22
HOLD/BUSRQ                                              DAL10     22                                                  48                                   RCLK
                  17                  32     A23
                                                        DAL11     23                                                  47                                   CLSN
        ALE/AS    18                  31     RX
                                                        DAL12     24                                                  46                                   TX
         HLDA     19                  30     RENA         NC      25                                                  45                                   NC
           CS     20                  29     TX           NC      26                                                  44                                   NC
                                                                    27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
          ADR     21                  28     CLSN
                                                                       NC            DAL13
                                                                                                                                        A22
                                                                              NC
                                                                                             DAL15   A18
        READY     22                  27     RCLK                                                    A19        NC   A20    A21         A23
                                                                                               A16   NC                                  RX
        RESET     23                  26     TENA                                    DAL14     A17                                     RENA

           VSS    24                  25     TCLK
                                                                                                                                                17881B-3
                                         17881B-2
  Note:
  Pin 1 is marked for orientation.

  1-4                                                        Am79C90
                                        PRELIMINARY                                                 AMD

TYPICAL ETHERNET/CHEAPERNET NODE
                                                                                                    TAP
                                                                                   MAU



                                                              AUI
                                             DTE             Cable
                                                                                    Am7996
ETHERNET                                                                           Transceiver

      Local             Local      Am79C90         Am7992B
      CPU              Memory      C-LANCE           SIA

                                                                                    Power
                       Local Bus                                                    Supply




                                                                                                    ETHERNET
                                             DTE                                                      COAX
CHEAPERNET



      Local             Local      Am79C90         Am7992B            Am7996
      CPU              Memory      C-LANCE           SIA             Transceiver
                                                                                                  RG58A/U or
                                                                                                  RG58C/U
                                                                                                  BNC “T”

                                                                      Power
                                                                      Supply
                       Local Bus



AUI – Attachment Unit Interface                                                                  17881B-4
DTE – Data Terminal Equipment
MAU – Medium Attachment Unit




                                              Am79C90                                                       1-5
      AMD                                      PRELIMINARY

ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:



      AM79C90                         P        C      B


                                                                       OPTIONAL PROCESSING
                                                                       Blank = Standard Processing
                                                                         TR = Tape and Reel Packaging


                                                                       TEMPERATURE RANGE
                                                                       C = Commercial (0°C to +70°C)


                                                                       PACKAGE TYPE
                                                                       P = 48-Pin Plastic DIP (PD 048)
                                                                       J = 68-Pin Plastic Leaded Chip Carrier (PL 068)




                                                                       SPEED OPTION
                                                                       Not Applicable



                           DEVICE NUMBER/DESCRIPTION
                           Am79C90
                           CMOS Local Area Network Controller for Ethernet




                     Valid Combinations                                         Valid Combinations
             AM79C90            PC, JC, JCTR                    Valid Combinations list configurations planned to be
                                                                supported in volume for this device. Consult the lo-
                                                                cal AMD sales office to confirm availability of specific
                                                                valid combinations and to check on newly released
                                                                combinations.




1-6                                                  Am79C90
                                                 PRELIMINARY                                                 AMD

PIN DESCRIPTION                                                     BM1                BM0           Selection
A16 – A23                                                           LOW                LOW           Whole Word
High Order Address Bus (Output Three State)                         LOW                HIGH          Upper Byte
Additional address bits to access a 24-bit address.                HlGH                LOW           Lower Byte
These lines are driven as a Bus Master only.                       HlGH                HIGH          None

ADR                                                          BYTE, BUSAKO – If CSR3 (00) BCON = 1
Register Address Port Select (Input)
                                                             PIN 15 = BYTE (Output Three-state) (48-Pin DlPs)
When the C-LANCE is a slave, ADR indicates which of          PIN 16 = BUSAKO (Output) (48-Pin DIPs)
the two register ports is selected. ADR LOW selects reg-
ister data port; ADR HIGH selects register address port.     Byte selection may also be done using the BYTE line
ADR must be valid throughout the data portion of the         and DAL00 line, latched during the address portion of
bus cycle and is only used by the C-LANCE when CS is         the bus cycle. The C-LANCE drives BYTE only as a Bus
LOW.                                                         Master and ignores it when a Bus Slave selection is
                                                             done (similar to BM0, BM1). Byte selection is done as
ALE/AS                                                       outlined in the following table:
Address Latch Enable (Output, Three-State)
Used to demultiplex the DAL lines and define the ad-                BYTE               DAL00          Selection
dress portion of the bus cycle. This l/O pin is program-            LOW                 LOW           Whole Word
mable through bit (01) of CSR3.                                     LOW                HIGH           Illegal Condition

As ALE (CSR3 (01), ACON = 0), the signal transitions                HlGH                LOW           Lower Byte
from a HIGH to a LOW during the address portion of the              HlGH               HIGH           Upper Byte
transfer and remains LOW during the data portion. ALE
can be used by a Slave device to control a latch on the      BUSAKO is a bus request daisy chain output. If the chip
bus address lines. When ALE is HIGH, the latch is open,      is not requesting the bus and it receives HLDA,
and when ALE goes LOW, the latch Is closed.                  BUSAKO will be driven LOW. If the C-LANCE is re-
                                                             questing the bus when it receives HLDA, BUSAKO wlll
As AS (CSR3 (01), ACON = 1), the signal pulses LOW           remain HIGH.
during the address portion of the bus transaction. The
LOW-to-HlGH transition of AS can be used by a Slave          Byte Swapping
device to strobe the address into a register.                In order to be compatible with the variety of 16-bit micro-
The C-LANCE drives the ALE/AS line only as a Bus             processors available to the designer, the C-LANCE may
Master.                                                      be programmed to swap the position of the upper and
                                                             lower order bytes on data involved in transfers with the
BM0/BYTE, BM1/BUSAKO                                         internal FIFOs.
(Output, Three-State)
                                                             Byte swapping is done when BSWP = 1. The most sig-
The two pins are programmable through bit (00) of            nificant byte of the word in this case will appear on DAL
CSR3                                                         lines 7–0 and the least significant byte on DAL lines
                                                             15–8.
BM0, BM1 – If CSR3 (00) BCON = 0
PIN 15 = BM0 (Output Three-state) (48-Pin DlPs)              When BYTE = H (indicating a byte transfer) the table in-
PIN 16 = BM1 (Output Three-state) (48-Pin DlPs)              dicates on which part of the 16-bit data bus the actual
                                                             data will appear.
BM0, BM1 (Byte Mask). This indicates the byte(s) on the
DAL are to be read or written during this bus transaction.   Whenever byte swap is activated, the only data that is
The C-LANCE drives these lines only as a Bus Master. It      swapped is data traveling to and from the Transmit/
ignores the Byte Mask lines when it is a Bus Slave and       Receive FIFOs.
assumes word transfers.
Byte selection using Byte Mask is done as described by
the following table:




                                                       Am79C90                                                       1-7
      AMD                                            PRELIMINARY

                                     Mode Bits                  DAS
                        BSWP = 0             BSWP = 1           Data Strobe (Input/Output, Three-State)
 Signal Line          and BCON = 1         and BCON = 1         Defines the data portion of the bus transaction. DAS is
 BYTE = L and              Word                  Word           high during the address portion of a bus transaction and
 DAL00 = L                                                      low during the data portion. The LOW-to-HlGH transi-
 BYTE = L and              Illegal               Illegal        tion can be used by a Slave device to strobe bus data
 DAL00 = H                                                      into a register. DAS is driven only as a Bus Master.
 BYTE = H and           Upper Byte           Lower Byte         HLDA
 DAL00 = H
                                                                Bus Hold Acknowledge (Input)
 BYTE = H and           Lower Byte           Upper Byte
                                                                A response to HOLD. When HLDA is LOW in response
 DAL00 = L
                                                                to the chip’s assertion of HOLD, the chip is the Bus
                                                                Master.
CLSN
Collision (Input)                                               During bus master operation the C-LANCE waits for
A logical input that indicates that a collision is occurring    HLDA to be deasserted HIGH before reasserting HOLD
on the channel.                                                 LOW. This insures proper bus handshake under all
                                                                situations.
CS
Chip Select (Input)                                             HOLD/BUSRQ
                                                                Bus Hold Request (Output, Open Drain)
Indicates, when asserted, that the C-LANCE is the slave
device of the data transfer. CS must be valid throughout        Asserted by the C-LANCE when it requires access to
the data portion of the bus cycle. CS must not be as-           memory. HOLD is held LOW for the entire ensuing bus
serted when HLDA is LOW.                                        transaction. The function of this pin is programmed
                                                                through bit (00) of CSR3. Bit (00) of CSR3 is cleared
DAL00 – DAL15                                                   when RESET is asserted.
Data/Address Lines (Input/Output, Three-State)
                                                                When CSR3 (00) BCON= 0
The time multiplexed Address/Data bus. During the ad-
dress portion of a memory transfer, DAL00 – DAL15               PIN 17 = HOLD
contains the lower 16 bits of the memory address. The           (Output Open Drain and input sense) (48-Pin DIPs)
upper 8 bits of address are contained in A16 – A23.
                                                                When CSR3 (00) BCON = 1
During the data portion of a memory transfer, DAL00 –
DAL15 contains the read or write data, depending on the         PIN 17 = BUSRQ (I/O Sense, Open Drain) (48-Pin DlPs)
type of transfer.                                               If the C-LANCE wants to use the bus, it looks at
The C-LANCE drives these lines as a Bus Master and as           HOLD/BUSRQ; if it is HIGH the C-LANCE can pull it
a Bus Slave.                                                    LOW and request the bus. If it is already LOW, the
                                                                C-LANCE waits for it to go inactive-HlGH before re-
DALI                                                            questing the bus.
Data/Address Line In (Output, Three-State)
                                                                INTR
An external bus transceiver control line. DALI is as-
                                                                Interrupt (Output, Open Drain)
serted when the C-LANCE reads from the DAL lines. It
will be LOW during the data portion of a READ transfer          An attention signal that indicates, when active, that one
and remain HIGH for the entire transfer if it is a WRITE.       or more of the following CSR0 status flags is set: BABL,
DALI is driven only when C-LANCE is a Bus Master.               MERR, MISS, RINT, TINT or IDON. INTR is enabled by
                                                                bit 06 of CSR0 (INEA = 1). INTR remains asserted until
DALO                                                            the source of Interrupt is removed.
Data/Address Line Out (Output, Three-State)
                                                                RCLK
An external bus transceiver control line. DALO is as-
                                                                Receive Clock (Input)
serted when the C-LANCE drives the DAL lines. DALO
will be LOW only during the address portion if the trans-       A 10 MHz square wave synchronized to the Receive
fer is a READ. It will be LOW for the entire transfer if the    data and only active while receiving an Input Bit Stream.
transfer is a WRITE. DALO is driven only when
C-LANCE is a Bus Master.




1-8                                                        Am79C90
                                                  PRELIMINARY                                                   AMD

READ                                                           RESET
(Input/Output, Three-State)                                    Reset (Input)
Indicates the type of operation to be performed in the         Reset causes the C-LANCE to cease operation, clear its
current bus cycle. This signal is an output when the           internal logic, force all three-state buffers to the high im-
C-LANCE is a Bus Master.                                       pedance state, and enter an idle state with the stop bit of
                                                               CSR0 set. It is recommended that a 3.3 kΩ pullup resis-
High – Data is taken off the DAL lines by the                  tor be connected to this pin.
       C-LANCE.
Low    – Data is placed on the DAL lines by the                RX
         C-LANCE.                                              Receive (Input)
                                                               Receive Input Bit Stream.
The signal is an input when the C-LANCE is a Bus
Slave.                                                         TCLK
High – Data is placed on the DAL lines by the                  Transmit Clock (Input)
       C-LANCE.                                                10 MHz clock.
Low    – Data is taken off the DAL lines by the
         C-LANCE.
                                                               TENA
                                                               Transmit Enable (Output)
READY                                                          Transmit Output Bit Stream enable. When asserted, it
(Input/Output, Open Drain)                                     enables valid transmit output (TX).
When the C-LANCE is a Bus Master, READY is an
asynchronous acknowledgment from the bus memory                TX
that it will accept data in a WRITE cycle or that it has put   Transmlt (Output)
data on the DAL lines in a READ cycle.                         Transmit Output Bit Stream.
As a Bus Slave, the C-LANCE asserts READY when it              VDD
has put data on the DAL lines during a READ cycle or is        Power Supply Pin +5 V ±5%
about to take data off the DAL lines during a write cycle.
READY is a response to DAS and will return High after          It is recommended that 0.1 µF and 10 µF decoupling ca-
DAS has gone High. READY is an input when the                  pacitors be used between VDD and VSS.
C-LANCE is a Bus Master and an output when the
                                                               VSS
C-LANCE is a Bus Slave.
                                                               Ground
RENA                                                           Pin 1 and 24 (48-Pin DlPs) should be connected to-
Receive Enable (Input)                                         gether externally, as close to the chip as possible.
A logical input that indicates the presence of carrier on
the channel.




                                                         Am79C90                                                        1-9
       AMD                                         PRELIMINARY

FUNCTIONAL DESCRIPTION
The parallel interface of the CMOS Local Area Network           Strobe signal compatible with microprocessors such as
Controller for Ethernet (C-LANCE) has been designed             the 68000. A programmable polarity on the Address
to be “friendly” or easy to interface to a variety of popular   Strobe signal eliminates the need for external logic. The
microprocessors. These microprocessors include the              C-LANCE interfaces with both multiplexed and de-
Am29000, 80x86, 680x0, Z8000 and LSI-11. The                    multiplexed data busses and features control signals for
C-LANCE has a 24-bit wide linear address space when             address/data bus transceivers. The C-LANCE is pin-for-
it is in the Bus Master Mode. A programmable mode of            pin compatible with AMD’s LANCE device (Am7990).
operation allows byte addressing in one of two ways:            Please refer to Appendix B for a complete comparison
a Byte/Word control signal compatible with the 80x86            between the C-LANCE and LANCE devices.
and Z8000 or an Upper Data Strobe and Lower Data


                                      Data and    Address
                                      Address       Bits
                                      Bits 0–15    16–23 Control



    A16–A23                Buffer


    CPU

                           Buffer
DAL0–DAL15
          ALE
                                                                               A16–A23



                                                                                                                C-LANCE
                                                                                       DAL0 – DAL15
                                                                     Buffer

                                                                                                                ALE



                                                                                                                ADR

                                                                                         Latch


                                                                         ALE                        Decoder     CS
                                                                        A16–A23




                                    DAL0–DAL15 A16–A23 Control
                                                                                                                 17881B-5


                                Figure 1. C-LANCE/CPU Interfacing Multiplexed Bus




1-10                                                      Am79C90
                                                   PRELIMINARY                                                 AMD

                               Address
                    Data Bus     Bus


                                                                                  Data/Address
                                                                                  Bits 0-15
                                         A0–A15
                                                      Latch
                                                                                  ALE
                                         A16–A23
                                                      Buffer                      Address
                                                                                  Bits 16-23
                                                                                     C-LANCE




                                       A0–A23
                                                     Decode                       CS


                                                                                                           17881B-6

                               Figure 2. C-LANCE/CPU Interfacing Demultiplexed Bus


During initialization, the CPU loads the starting address      loads into the 48-byte Transmit FIFO; the C-LANCE
of the initialization block into two internal control regis-   then begins to transmit preamble while simultaneously
ters. The C-LANCE has four internal control and status         loading the rest of the packet into Transmit FIFO for
registers (CSR0, 1, 2, 3) which are used for various           transmission.
functions, such as the loading of the initialization block
address, and programming different modes and status            In the receive mode, packets are sent via the Am7992B
conditions. The host processor communicates with the           SlA to the C-LANCE. The packets are loaded into the
C-LANCE during the initialization phase, for demand            64-byte Receive FIFO for preparation of automatic
transmission, and periodically to read the status bits fol-    downloading into buffer memory. A CRC is calculated
lowing interrupts. All other transfers to and from the         and compared with the CRC appended to the data pack-
memory are automatically handled as DMA.                       et. If the calculated CRC does not agree with the packet
                                                               CRC, an error bit is set.
Interrupts to the microprocessor are generated by the
C-LANCE upon:                                                  Addressing
                                                               Packets can be received using three different destina-
   completion of its initialization routine
                                                               tion addressing schemes: physical, logical and
   the reception of a packet                                   promiscuous.
   the transmission of a packet
                                                               The first type is a full comparison of the 48-bit destina-
   transmitter timeout error                                   tion address in the packet with the node address that
   a missed packet                                             was programmed into the C-LANCE during an initializa-
   memory error                                                tion cycle. There are two types of logical addresses.
                                                               One is group type mask where the 48-bit address in the
The cause of the interrupt is ascertained by reading           packet is put through a hash filter to map the 48-bit
CSR0. Bit (06) of CSR0, (INEA), enables or disables            physical addresses into 1 of 64 logical groups. If any of
interrupts to the microprocessor. In systems where poll-       these 64 groups have been preselected as the logical
ing is used in place of interrupts, bit (07) of CSR0,          address, then the 48-bit address is stored in main mem-
(INTR), indicates an interrupt condition.                      ory. At this time, a look up is performed by the host com-
                                                               puter comparing the 48-bit incoming address with the
The basic operation of the C-LANCE consists of two dis-        pre-stored 48-bit logical address. This mode can be
tinct modes: transmit and receive. In the transmit mode,       useful if sending packets to all of a particular type of de-
the C-LANCE chip directly accesses data (in a transmit         vice simultaneously (i.e., send a packet to all file servers
buffer) in memory. It prefaces the data with a preamble,       or all printer servers). Additional details on logical ad-
start frame delimiter (SFD), and calculates and appends        dressing can be found in the INITIALIZATION section
a 32-bit CRC. On transmission, the first byte of data

                                                         Am79C90                                                      1-11
       AMD                                       PRELIMINARY

under “Logical Address Filter.” The second logical ad-       System errors include:
dress is a broadcast address where all nodes on the net-
work receive the packet. The last receive mode of                Babbling Transmitter
operation is referred to as “promiscuous mode” in which          — Transmitter attempting to transmit more than
a node will accept all packets on the medium regardless             1518 bytes, excluding preamble and start frame
of their destination address.                                       delimiter
                                                                 Collision
Collision Detection and Implementation
                                                                 — Collision detection circuitry nonfunctional
The Ethernet and IEEE 802.3 CSMA/CD network ac-
                                                                 Missed Packet
cess algorithms are implemented completely within the
C-LANCE. In addition to listening for a clear medium be-         — Insufficient buffer space
fore transmitting, Ethernet handles collisions in a prede-       Memory timeout
termined way. Should two transmitters attempt to seize           — Memory response failure
the medium at the same time, they will collide and the
data on the medium will be garbled. The transmitting         Packet-related errors:
nodes listen while they transmit, detect the collision,
                                                                 CRC
then continue to transmit for a predetermined length of
time to “jam” the network and ensure that all nodes have         — Invalid data
recognized the collision. The transmitting nodes then            Framing
delay a random amount of time according to the Ether-            — Packet did not end on a byte boundary
net “truncated binary backoff” algorithm in order that the
                                                                    Overflow/Underflow
colliding nodes do not try to repeatedly access the net-
work at the same time. The C-LANCE also offers a se-             — Indicates abnormal latency in servicing a DMA
lectable Modified Backoff Algorithm for better                      request
performance on busy networks. Up to 16 attempts to ac-           Buffer
cess the network are made by the C-LANCE before re-              — Insufficient buffer space available
porting an error due to excessive collisions.
                                                             The C-LANCE performs several diagnostic routines
Error Reporting and Diagnostics                              which enhance the reliability and integrity of the system.
Extensive error reporting is provided by the C-LANCE.        These include a CRC check and two loop back modes
Error conditions reported relate either to the network as    (internal/external). Errors may be introduced into the
a whole or to individual data packets. Network-related       system to check error detection logic. A Time Domain
errors are recorded as flags in the CSRs and are exam-       Reflectometer is incorporated into the C-LANCE to aid
ined by the CPU following interrupt. Packet-related er-      system designers in locating faults in the Ethernet physi-
rors are written into descriptor entries corresponding to    cal medium. Shorts and opens manifest themselves in
the packet.                                                  reflections which are sensed by the TDR.




1-12                                                   Am79C90
              PRELIMINARY                                             AMD




                                                Initialization
                                                Block




      Transmit Descriptor for 1st Data Buffer
                                                   Transmit
      Transmit Descriptor for 2nd Data Buffer      Descriptor
      Transmit Descriptor for 3rd Data Buffer      Ring
                                                   (4 words
                                                   per entry)

      Transmit Descriptor for Nth Data Buffer


      Receive Descriptor for 1st Data Buffer
      Receive Descriptor for 2nd Data Buffer       Receive
                                                   Descriptor
      Receive Descriptor for 3rd Data Buffer       Ring
                                                   (4 words
                                                   per entry)
      Receive Descriptor for Nth Data Buffer


             Transmit Data Buffer #1

             Transmit Data Buffer #2
                                                   Transmit
             Transmit Data Buffer #3               Data
                                                   Buffers


             Transmit Data Buffer #N

             Receive Data Buffer #1

             Receive Data Buffer #2
                                                   Receive
             Receive Data Buffer #3                Data
                                                   Buffers


             Receive Data Buffer #N
                                                           17881B-7

Figure 2-1. C-LANCE/Processor Memory Interface




                     Am79C90                                                1-13
       AMD                                       PRELIMINARY

                                                             Receive Descriptor Ring             Receive Buffer
             C-LANCE CSR Registers
             Pointer to Initialization Block                                                         Data
                                                             Address of Receive Buffer 1            Packet
                                                             Buffer 1 Status                          1
                                                             Buffer 1 Byte Count
                                                             Buffer 1 Message Count                  Data
                                                                                                    Packet
                                                                          2                           2
                                                                          2
             Initialization
             Block                                                        2
                                                                          2
              Mode of Operation
              Physical Address
                                                                         N
              Logical Address Filter                                                                 Data
                                                                         N
                                                                                                    Packet
                                                                         N                            N
              Pointer to Receive Ring
                                                                         N
              Number of Receive Entries (N)
              Pointer to Transmit Ring                       Transmit Descriptor Ring           Transmit Buffer
              Number of Transmit Entries (M)
                                                                                                     Data
                                                             Address of Transmit Buffer 1           Packet
                                                             Buffer 1 Status                          1
                                                             Buffer 1 Byte Count
                                                             Buffer 1 Error Status                   Data
                                                                          2                         Packet
                                                                                                      2
                                                                          2
                                                                          2
                                                                          2


                                                                         M
                                                                         M                           Data
                                                                         M                          Packet
                                                                         M                            M



                                                                                                             17881B-8


                                       Figure 2-2. C-LANCE Memory Management


Buffer Management                                              the “own” bit is reset, allowing the host processor to
                                                               process the data in the buffer.
A key feature of the C-LANCE and its on-board DMA
channel is the flexibility and speed of communication          C-LANCE Interface
between the C-LANCE and the host microprocessor
through common memory locations. The basic organi-             CSR bits such as ACON, BCON and BSWP are used for
zation of the buffer management is a circular queue of         programming the pin functions used for different inter-
tasks in memory called descriptor rings as shown in            facing schemes. For example, ACON is used to pro-
Figures 2-1 and 2-2. There are separate descriptor rings       gram the polarity of the Address Strobe signal
to describe transmit and receive operations. Up to 128         (ALE/AS).
tasks may be queued up on a descriptor ring awaiting           BCON is used for programming the pins, for handling
execution by the C-LANCE. Each entry in a descriptor           either the BYTE/WORD method for addressing word or-
ring holds a pointer to a data memory buffer and an entry      ganized, byte addressable memories where the BYTE
for the length of the data buffer. Data buffers can be         signal is decoded along with the least significant ad-
chained or cascaded to handle a long packet in multiple        dress bit to determine upper or lower byte, or an explicit
data buffer areas. The C-LANCE searches the descrip-           scheme in which two signals labeled as BYTE MASK
tor rings in a “lookahead” manner to determine the next        (BM0 and BM1) indicate which byte is addressed. When
empty buffer in order to chain buffers together or to han-
dle back-to-back packets. As each buffer is filled,


1-14                                                   Am79C90
                                                 PRELIMINARY                                                AMD

the BYTE scheme is chosen, the BM1 pin can be used           Write Sequence (Slave Mode)
for performing the function BUSAKO.
                                                             This cycle is similar to the read cycle, except that during
BCON is also used to program pins for different DMA          this cycle, READ is not asserted (READ is LOW). The
modes. In a daisy chain DMA scheme, 3 signals are            DAL buffers are tristated which configures these lines as
used (BUSRQ, HLDA, BUSAKO). In systems using a               inputs. The assertion of READY by C-LANCE indicates
DMA controller for arbitration, only HOLD and HLDA are       to the memory device that the data on the DAL lines
used.                                                        have been stored by C-LANCE in its appropriate CSR
                                                             register. CS, READ, DAS, ADR and DAL 15:00 must re-
C-LANCE in Bus Slave Mode                                    main stable throughout the write cycle. Refer to
The C-LANCE enters the Bus Slave Mode whenever CS            Figure 4.
becomes active. This mode must be entered whenever           Note: Setting the STOP bit in the C-LANCE will gener-
writing or reading the four status control registers         ate a C-LANCE reset, which will cause all bus control
(CSR0, CSR1, CSR2, and CSR3) and the Register Ad-            output signals (including READY) to float. To guarantee
dress Pointer (RAP). RAP and CSR0 may be read or             slave write timing when the STOP bit is being set in
written to at anytime, but the C-LANCE must be stopped       CSR0, the C-LANCE will latch the STOP bit and will wait
(by setting the stop bit in CSR0) for CSR1, CSR2, and        for the slave cycle to complete before resetting itself and
CSR3 access.                                                 floating the output signals.

Read Sequence (Slave Mode)                                   C-LANCE in Bus Master Mode
At the beginning of a read cycle, CS, READ, and DAS          All data transfers from the C-LANCE in the bus Master
are asserted. ADR must be valid at this time. (If ADR is a   mode are timed by ALE, DAS, and READY. The auto-
“1,” the contents of RAP are placed on the DAL lines.        matic adjustment of the C-LANCE cycle by the READY
Otherwise the contents of the CSR register addressed         signal allows synchronization with variable cycle time
by RAP are placed on the DAL lines.) After the data on       memory due either to memory refresh or to dual port ac-
the DAL lines become valid, the C-LANCE asserts              cess. Transfers are a minimum of 600 ns in length ex-
READY, CS, READ, DAS, and ADR must remain stable             cept for the first transfer of a bus mastership period in
throughout the cycle. Refer to Figure 3.                     which the minimum is 700 ns. Transfers can be in-
                                                             creased in 100 ns increments.




                                                       Am79C90                                                    1-15
       AMD                                       PRELIMINARY


DAL0–DAL15                                                                          Read Data



                                                     See
                                                     Note 1
             DAS




         READ


      READY
  (Output from
    C-LANCE)                                                                                    O.D.




         HOLD



             CS




          ADR


Note:                                                                                             17881B-9
1. There are two types of delays which depend on which internal register is accessed.
   Type 1 refers to access of CSR0, CSR3 and RAP.
   Type 2 refers to access of CSR1 and CSR2 which are longer than Type 1 delay.

                                          Figure 3. Bus Slave Read Timing




1-16                                                    Am79C90
                                                PRELIMINARY                                                 AMD


 DAL0–DAL15                                                          Write Data




          DAS




        READ

       READY
   (Output from
     C-LANCE)
                                                                                                         O.D.



        HOLD




           CS




          ADR



                                                                                                           17881B-10


                                         Figure 4. Bus Slave Write Timing


Read Sequence (Master Mode)                                 The bus transceiver controls, DALI and DALO, are used
                                                            to control the bus transceivers. DALI directs data toward
A read cycle is begun by placing a valid address on
                                                            the C-LANCE, and DALO directs data or addresses
DAL00 – DAL15 and A16 – A23. The BYTE MASK sig-
                                                            away from the C-LANCE. During a read cycle, DALO
nals are asserted to indicate a word, upper byte or lower
                                                            goes inactive before DALI becomes active to avoid
byte memory reference. READ indicates the type of cy-
                                                            “spiking” of the bus transceivers.
cle. ALE or AS is pulsed, and the trailing edge of either
can be used to latch addresses. DAL00 – DAL15 go into       Write Sequence (Master Mode)
a 3-state mode, and DAS falls LOW to signal the begin-
ning of the memory access. The memory responds by           The write cycle is similar to the read cycle except that the
placing READY LOW to indicate that the DAL lines have       DAL00 – DAL15 lines change from containing ad-
valid data. The C-LANCE then latches memory data on         dresses to data after either ALE or AS goes inactive.
the rising edge of DAS, which in turn ends the memory       After data is valid on the bus, DAS goes active. Data to
cycle and READY returns HIGH. Refer to Figure 5-1.          memory is held valid after DAS goes inactive. Refer to
                                                            Figure 5-2.




                                                      Am79C90                                                     1-17
       AMD                             PRELIMINARY

                                                                         TWAIT

                     T0         T1         T2          T3           T4           T5         T6

                0         100        200         300          400         500         600        700

        TCLK




        HOLD
                                                                                                       O.D.




        HLDA




   A16–A23
                                                            Address, BM0, BM1
  BM0, BM1



         ALE




         DAS




       READY



DAL0–DAL15
                                       Address                                  Data In
     (Read)


        DALO
       (Read)


         DALI
       (Read)



        READ
       (Read)
                                                                                                       17881B-11
                    Figure 5-1. Bus Master Read Timing (Single DMA Cycle)




1-18                                            Am79C90
                                      PRELIMINARY                                                     AMD

                                                                        TWAIT
                     T0         T1         T2          T3          T4           T5         T6

                0         100        200         300         400          500        600        700

      TCLK




      HOLD
                                                                                                      O.D.




      HLDA




   A16–A23
                                                            Address, BM0, BM1
  BM0, BM1



        ALE




        DAS



     READY




DAL0–DAL15
     (Write)                           Address                                  Data Out



       DALO
      (Write)


       DALI
      (Write)


       READ
      (Write)


                                                                                                      17881B-12




                    Figure 5-2. Bus Master Write Timing (Single DMA Cycle)




                                                Am79C90                                                      1-19
       AMD                                      PRELIMINARY

Differences Between Ethernet Versions 1                     A list of significant differences between Ethernet and
and 2                                                       IEEE 802.3 at the physical layer include the following:
a. Version 2 specifies that the collision detect of the                              IEEE 802.3       Ethernet
   transceiver must be activated during the inter-
                                                            End of Transmission       Half Step   Full Step (Rev 1)
   packet gap time.
                                                            State                                         or
b. Version 2 specifies some network management                                                    Half Step (Rev 2)
   functions, such as reporting the occurrence of colli-    Common Mode Voltage        ±5.5 V         0 – +5 V
   sions, retries and deferrals.
                                                            Common Mode Current Less than 1 mA      1.6 mA ±40%
c. Version 2 specifies that when transmission is ter-
                                                            Receive±, Collision±
   minated, the differential transmit lines are driven to
   0 volt differentially (half step).                       Input Threshold           ±160 mV         ±175 mV
                                                            Fault Protection            16 V            0V
Differences Between IEEE 802.3 and
Ethernet
a. IEEE 802.3 specifies a 2-byte length field rather
   than a type field. The length field (802.3) describes
   the actual amount of data in the frame.
b. IEEE 802.3 allows the use of a PAD field in the
   data section of a frame, while Ethernet specifies
   the minimum packet size at 64 bytes. The use of a
   PAD allows the user to send and receive packets
   which have less than 46 bytes of data.




1-20                                                  Am79C90
                                             PRELIMINARY                                                   AMD

PROGRAMMING                                                     The C-LANCE loads itself with the information con-
                                                                tained within the initialization block.
This section defines the Control and Status Registers
and the memory data structures required to program the          The C-LANCE accesses the descriptor rings for
Am79C90 (C-LANCE).                                              packet handling.
                                                          CONTROL AND STATUS REGISTERS
Programming the Am79C90 (C-LANCE)
                                                          There are four Control and Status Registers (CSRs) on
The Am79C90 (C-LANCE) is designed to operate in an
                                                          the chip. The CSRs are accessed through two bus ad-
environment that includes close coupling with local
                                                          dressable ports, an address port (RAP) and a data port
memory and microprocessor (HOST). The Am79C90
                                                          (RDP).
C-LANCE is programmed by a combination of registers
and data structures resident within the C-LANCE and       Accessing the Control and Status
memory registers. There are four Control and Status
                                                          Registers
Registers (CSRs) within the C-LANCE which are pro-
grammed by the HOST device. Once enabled, the             The CSRs are read (or written) in a two step operation.
C-LANCE has the ability to access memory locations to     The address of the CSR to be accessed is written into
acquire additional operating parameters.                  the RAP during a bus slave transaction. During a subse-
                                                          quent bus slave transaction, the data being read from
The Am79C90 has the ability to do independent buffer      (or written into) the RDP is read from (or written into) the
management as well as transfer data packets to and        CSR selected in the RAP.
from the Ethernet. There are three memory structures
accessed by the Chip:                                     Once written, the address in RAP remains unchanged
                                                          until rewritten.
   Initialization Block—12 words in contiguous mem-
   ory starting on a word boundary. It also contains      To distinguish the data port from the address port, a dis-
   the operating parameters necessary for device op-      crete input pin is provided.
   eration. The initialization block is comprised of:
                                                          ADR Input Pin       Port
   — Mode of Operation
                                                               L              Register Data Port (RDP)
   — Physical Address
                                                               H              Register Address Port (RAP)
   — Logical Address Mask
   — Location to Receive and Transmit Descriptor          Register Data Port (RDP)
       Rings
   — Number of Entries in Receive and Transmit            15                                                          0
       Descriptor Rings                                                           CSR DATA
   Receive and Transmit Descriptor Rings—Two ring
                                                                                                          17881B-13
   structures, one for incoming and outgoing packets.
   Each entry in the rings is 4 words long and each
   entry must start on a quadword boundary. The De-       Bit          Name       Description
   scriptor Rings are comprised of:
   — The address of a data buffer                         15:00      CSR Data     Writing data into RDP writes the data
   — The length of that data buffer                                               into the CSR selected in RAP. Read-
                                                                                  ing the data from the RDP reads the
   — Status information associated with the buffer                                data from the CSR selected in RAP.
   Data Buffers—Contiguous portions of memory                                     CSR1, CSR2 and CSR3 are acces-
   reserved for packet buffering. Data buffers may                                sible only when the STOP bit of
   begin on arbitrary byte boundaries.                                            CSR0 is set.
In general, the programming sequence of the C-LANCE                               If the STOP bit is not set while at-
                                                                                  tempting to access CSR1, CSR2 or
may be summarized as:
                                                                                  CSR3, the C-LANCE will return
                                                                                  READY, but a READ operation will
   Program the C-LANCE’s CSRs by a host device to
                                                                                  return undefined data. WRITE op-
   locate an initialization block in memory. The byte                             eration is ignored.
   control, byte address, and address latch enable
   modes are also defined here.




                                                     Am79C90                                                     1-21
       AMD                                           PRELIMINARY

Register Address Port (RAP)                                        Bit   Name   Description


                                                                   14    BABL   BABBLE is a transmitter timeout er-
                                                                                ror. It indicates that the transmitter
                                                                                has been on the channel longer than
                                                      CSR 1:0                   the time required to send the maxi-
                                                      RES                       mum length packet.
                                                   17881B-14                    BABL is a flag which indicates ex-
                                                                                cessive length in the transmit buffer.
                                                                                It will be set after 1519 bytes have
Bit           Name       Description                                            been transmitted, excluding pream-
                                                                                ble and start frame delimiter; the
                                                                                C-LANCE will continue to transmit
15:02          RES       Reserved. Read as zeroes. Write as                     until the whole packet is transmitted
                         zeroes.                                                or until there is a failure before the
01:00       CSR(1:0)     CSR address select. READ/WRITE.                        whole packet is transmitted. When
                         Selects the CSR to be accessed                         BABL error occurs, an interrupt will
                         through the RDP. RAP is cleared by                     be generated if INEA = 1.
                         Bus RESET.                                             BABL is READ/CLEAR ONLY and is
                           CSR(1 :0)          CSR                               set by the C-LANCE, and cleared by
                                                                                writing a “1” into the bit. Writing a ”0”
                               00                CSR0                           has no effect. It is cleared by RESET
                               01                CSR1                           or by setting the STOP bit.
                               10                CSR2              13    CERR   COLLISION ERROR indicates that
                               11                CSR3                           the collision input to the C-LANCE
                                                                                was not asserted during the trans-
                                                                                mission, nor within 4.0 µs after the
                                                                                transmit completed. The collision af-
Control and Status Register Definition                                          ter transmission is a transceiver test
Control and Status Register 0 (CSR0)                                            feature. This function is also known
                                                                                as heartbeat or SQE (Signal Quality
       15                                               0                       Error) test.
                                                                                CERR is READ/CLEAR ONLY and
                                                                                is set by the C-LANCE and cleared
                                                                                by writing a “1” into the bit. Writing a
 ERR                                                        INIT                “0” has no effect. It is cleared by RE-
BABL                                                        STRT                SET or by setting the STOP bit.
                                                                                CERR error will not cause an inter-
CERR                                                        STOP                rupt to occur (INTR = 0).
MISS                                                        TDMD   12    MISS   MISSED PACKET is set when the
MERR                                                        TXON                receiver loses a packet because it
                                                                                does not own any receive buffer, in-
RINT                                                        RXON                dicating loss of data.
TINT                                                        INEA                FIFO overflow is not reported be-
IDON                                                        INTR                cause there is no receive ring entry
                                                                                in which to write status.
      The C-LANCE updates CSR0 by logical “ORing” the pre-                      When MISS is set, an interrupt will
      vious and present value of CSR0.                                          be generated if INEA = 1.
                                                   17881B-15                    MISS is READ/CLEAR ONLY, and is
                                                                                set by the C-LANCE and cleared by
                                                                                writing a “1” into the bit. Writing a “0”
                                                                                has no effect. It is cleared by RESET
Bit           Name       Description
                                                                                or by setting the STOP bit.

15             ERR       ERROR summary is set by the
                         “ORing” of BABL, CERR, MISS and
                         MERR. ERR remains set as long as
                         any of the error flags are true.
                         ERR is read only; writing it has no ef-
                         fect. It is cleared by Bus RESET, set-
                         ting the STOP bit, or clearing the
                         individual error flags.




1-22                                                          Am79C90
                                           PRELIMINARY                                           AMD

Bit   Name   Description                                 Bit   Name   Description


11    MERR   MEMORY ERROR is set when the                07    INTR   INTERRUPT FLAG is set by the
             C-LANCE is the Bus Master and has                        “ORing” of BABL, MISS, MERR,
             not received READY within 25.6 µs                        RINT, TINT and IDON. If INEA = 1
             after asserting the address on the                       and INTR = 1, the INTR pin will be
             DAL lines.                                               LOW.
             When a Memory Error is detected,                         INTR is READ ONLY; writing this bit
             the receiver and transmitter are                         has no effect. INTR is cleared by
             turned off (CSR0, TXON = 0, RXON                         RESET, by setting the STOP bit, or
             = 0) and an interrupt is generated if                    by clearing the condition causing the
             INEA = 1.                                                interrupt.
             MERR is READ/CLEAR ONLY, and                06    INEA   INTERRUPT ENABLE allows the
             is set by the C-LANCE and cleared                        INTR pin to be driven LOW when the
             by writing a “1” into the bit. Writing a                 Interrupt Flag is set. If INEA = 1 and
             “0” has no effect. It is cleared by                      INTR = 1, the INTR pin will be Low. If
             RESET or by setting the STOP bit.                        INEA = 0, the INTR pin will be HIGH,
                                                                      regardless of the state of the Inter-
10    RINT   RECEIVER INTERRUPT is set                                rupt Flag.
             when the C-LANCE updates an en-
             try in the Receive Descriptor Ring for                   INEA is READ/WRITE and cleared
             the last buffer received or reception                    by RESET or by setting the STOP
             is stopped due to a failure.                             bit.
             When RINT is set, an interrupt is                        INEA can be set at any time, regard-
             generated if INEA = 1.                                   less of the state of the STOP bit.
                                                                      (reference Appendix B).
             RINT is READ/CLEAR ONLY, and is
             set by the C-LANCE and cleared by           05    RXON   RECEIVER ON indicates that the re-
             writing a “1” into the bit. Writing a “0”                ceiver is enabled. RXON is set when
             has no effect. It is cleared by RESET                    STRT is set if DRX = 0 in the MODE
             or by setting the STOP bit.                              register in the initialization block and
                                                                      the initialization block has been read
09    TINT   TRANSMITTER INTERRUPT is set                             by the C-LANCE by setting the INIT
             when the C-LANCE updates an en-                          bit. RXON is cleared when IDON is
             try in the transmit descriptor ring for                  set from setting the INIT bit and DRX
             the last buffer sent or transmission is                  = 1 in the MODE register, or a mem-
             stopped due to a failure.                                ory error (MERR) has occurred.
             When TINT is set, an interrupt is                        RXON is READ ONLY; writing this
             generated if INEA = 1.                                   bit has no effect. RXON is cleared by
             TINT is READ/CLEAR ONLY and is                           RESET or by setting the STOP bit.
             set by the C-LANCE and cleared by           04    TXON   TRANSMITTER ON indicates that
             writing a “1” into the bit. Writing a “0”                the transmitter is enabled. TXON is
             has no effect. It is cleared by RESET                    set when STRT is set if DTX = 0 in
             or by setting the STOP bit.                              the MODE register in the initializa-
08    IDON   INITIALIZATION DONE indicates                            tion block and the INIT bit has been
             that the C-LANCE has completed                           set. TXON is cleared when IDON is
             the initialization procedure started                     set and DTX = 1 in the MODE regis-
             by setting the INIT bit. When IDON is                    ter, or an error, such as MERR,
             set, the C-LANCE has read the In-                        UFLO or BUFF, has occurred during
             itialization Block from memory and                       transmission.
             stored the new parameters.                               TXON is READ ONLY; writing this bit
             When IDON is set, an interrupt is                        has no effect. TXON is cleared by
             generated if INEA = 1.                                   RESET or by setting the STOP bit.

             IDON is READ/CLEAR ONLY, and is
             set by the C-LANCE and cleared by
             writing a “1” into the bit. Writing a “0”
             has no effect. It is cleared by RESET
             or by setting the STOP bit.




                                                  Am79C90                                               1-23
       AMD                                      PRELIMINARY

Bit          Name   Description                               Control and Status Register 1 (CSR1)
                                                              READ/WRITE:        Accessible only when the STOP bit
03           TDMD   TRANSMIT DEMAND, when set,                                   of CSR0 is a ONE and RAP = 01.
                    causes the C-LANCE to access the                             The C-LANCE preserves the con-
                    Transmit Descriptor Ring without                             tents of CSR1 after STOP.
                    waiting for the polltime interval to            15                                     1 0
                    elapse. TDMD need not be set to
                    transmit a packet; it merely hastens
                    the C-LANCE’s response to a Trans-
                    mit Descriptor Ring entry insertion by
                    the host.                                                                                   ‘0’
                                                                                                     IADR
                    TDMD is WRITE WITH ONE ONLY                                                      (15:01)
                    and is cleared by the microcode after
                    it is used. It may read as a “1” for a                                            17881B-16
                    short time after it is written because
                    the microcode may have been busy
                    when TDMD was set. It is also
                    cleared by RESET or by setting the        Bit        Name    Description
                    STOP bit. Writing a “0” in this bit has
                    no effect.
                                                              15:01      IADR    The low order 15 bits of the address
02           STOP   STOP disables the C-LANCE from
                                                                                 of the first word (lowest address) in
                    all external activity when set and
                                                                                 the Initialization Block.
                    clears the internal logic. Setting
                    STOP is the equivalent of asserting       00                 Must be zero.
                    RESET. The C-LANCE remains in-
                    active and STOP remains set until
                    the STRT or INIT bit is set. If STRT,     Control and Status Register 2 (CSR2)
                    INIT and STOP are all set together,
                    STOP will override the other bits and     READ/WRITE:        Accessible only when the STOP bit
                    only STOP will be set.                                       of CSR0 is a ONE and RAP = 10.
                                                                                 The C-LANCE preserves the con-
                    STOP is READ/WRITE WITH ONE                                  tents of CSR2 after STOP.
                    ONLY and set by RESET. Writing a
                    “0” to this bit has no effect. STOP is          15              8 7                        0
                    cleared by setting either INIT or
                    STRT. CSR3 must be reloaded
                    when the STOP bit is set.
01           STRT   START enables the C-LANCE to
                    send and receive packets, perform                                                  IADR (23:16)
                    direct memory access, and do buffer                                                       RES
                    management. The STOP bit must be                                                   17881B-17
                    set prior to setting the STRT bit. Set-
                    ting STRT clears the STOP bit.
                    STRT is READ/WRITE and is set
                    with one only. Writing a “0” into this    Bit        Name    Description
                    bit has no effect. STRT is cleared by
                    RESET or by setting the STOP bit.
                                                              15:08      RES     Reserved. Read as zeroes. Write as
00           INIT   INITIALIZE, when set, causes the
                                                                                 zeroes.
                    C-LANCE to begin the initialization
                    procedure and access the Initializa-      07:00      IADR    The high order 8 bits of the address
                    tion Block. The STOP bit must be set                         of the first word (lowest address) in
                    prior to setting the INIT bit. Setting                       the initialization Block.
                    INIT clears the STOP bit.
                    INIT is READ/WRITE WITH “1”
                    ONLY. Writing a “0” into this bit has
                    no effect. INIT is cleared by RESET
                    or by setting the STOP bit.
                    The C-LANCE latches CSR0 during
                    a slave read; therefore, the CSR0
                    status bits are guaranteed to be sta-
                    ble for the duration of the CSR0
                    access.




1-24                                                   Am79C90
                                                 PRELIMINARY                                                 AMD

Control and Status Register 3 (CSR3)                          Initialization
CSR3 allows redefinition of the Bus Master interface.         Initialization Block
READ/WRITE:           Accessible only when the STOP bit       Chip initialization includes the reading of the initializa-
                      of CSR0 is ONE and RAP = 11.            tion block in memory to obtain the operating parame-
                      CSR3 is cleared by RESET or by          ters. The following is a definition of the Initialization
                      setting the STOP bit in CSR0.           Block.
     15                                3 2 1 0
                                                              The Initialization Block is read by the C-LANCE when
                                                              the INIT bit in CSR0 is set. The INIT bit should be set be-
                                                              fore or concurrent with the STRT bit to insure proper pa-
                                                    BCON      rameter initialization and chip operation. After the
                                                    ACON      C-LANCE has read the Initialization Block, IDON is set
                                                    BSWP      in CSR0 and an interrupt is generated if INEA = 1.
                                                    RES       Higher Address         TLEN–TDR (23:16) IADR +22
                                             17881B-18                               TDRA (15:00)      IADR +20
                                                                                     RLEN–RDRA (23:16) IADR +18
                                                                                     RDRA (15:00)      IADR +16
Bit        Name       Description                                                    LADRF (63:48)     IADR +14
                                                                                     LADRF (47:32)     IADR +12
                                                                                     LADRF (31:16)     IADR +10
15:03      RES        Reserved. Read as zeroes. Write as
                      zeroes.                                                        LADRF (15:00)     IADR +08
                                                                                     PADR (47:32)      IADR +06
02        BSWP        BYTE SWAP allows the chip to oper-                             PADR (31:16)      IADR +04
                      ate in systems that consider bits                              PADR (15:00)      IADR +02
                      (15:08) of data to be pointed at an
                      even address and bits (07:00) to be     Base Address of Block MODE                    IADR +00
                      pointed at an odd address.              Mode
                      When BSWP = 1, the C-LANCE will
                      swap the high and low bytes on DMA      The Mode Register allows alteration of the C-LANCE’s
                      data transfers between the Receive      operating parameters. Normal operation is with the
                      FIFO and bus memory. Only data          Mode Register clear.
                      from the Receive FIFO transfers is
                      swapped; the Initialization Block
                      data and the Descriptor Ring entries
                      are NOT swapped.                             15 14                  8 7 6 5 4 3 2 1 0
                      BSWP is READ/WRITE and cleared
                      by RESET or by setting the STOP bit
                      in CSR0.
01        ACON        ALE CONTROL defines the asser-                                                             DRX
                      tive state of ALE when the C-LANCE                                                         DTX
                      is a Bus Master. ACON is READ/
                      WRITE and cleared by RESET and                                                             LOOP
                      by setting the STOP bit in CSR0.                                                           DTCR
                         ACON                 ALE                                                                COLL
                             0         Asserted HIGH                                                             DRTY
                             1            Asserted LOW                                                           INTL
00        BCON        BYTE CONTROL redefines the Byte                                                            EMBA
                      Mask and Hold l/O pins. BCON is                                                            RES
                      READ/WRITE and cleared by
                      RESET or by setting the STOP bit in                                                        PROM
                      CSR0.
                                                                                                            17881B-19
                       BCON      Pin 16    Pin 15 Pin 17
                         0        BM1   BM0 HOLD
                         1       BUSAKO BYTE BUSRQ

All data transfers from the C-LANCE in the Bus Master
mode are in words. However, the C-LANCE can handle
odd address boundaries and/or packets with an odd
number of bytes.



                                                         Am79C90                                                   1-25
       AMD                                      PRELIMINARY

Bit          Name   Description                               Bit   Name   Description


15           PROM   PROMISCUOUS mode. When                    04    COLL   FORCE COLLISION. This bit allows
                    PROM = 1, all incoming packets are                     the collision logic to be tested. The
                    accepted.                                              C-LANCE must be in internal loop-
14:08        RES    RESERVED. Read as zeroes. Write                        back mode for COLL to be valid. If
                    as zeroes.                                             COLL = 1, a collision will be forced
                                                                           during the subsequent transmission
07           EMBA   Enable Modified Back-off Algorithm.                    attempt. This will result in 16 total
                    When set (EMBA=1), enables the                         transmission attempts with a retry er-
                    modified backoff algorithm. EMBA                       ror reported in TMD3.
                    is cleared by activation of the RESET
                    pin or setting the STOP bit.              03    DTCR   DISABLE TRANSMIT CRC. When
                                                                           DTCR = 0, the transmitter will gener-
06           INTL   INTERNAL LOOPBACK is used with                         ate and append a CRC to the trans-
                    the LOOP bit to determine where the                    mitted packet. When DTCR = 1, the
                    loopback is to be done. Internal loop-                 CRC logic is allocated to the receiver
                    back allows the chip to receive its                    and no CRC is generated and sent
                    own transmitted packet. Since this                     with the transmitted packet. The
                    represents full duplex operation, the
                                                                           ADD_FCS bit (bit 13, TMD1) can be
                    packet size is limited to 8–32 bytes.
                                                                           used to override a DTCR=1 setting
                    Internal loopback in the C-LANCE is
                                                                           on a per packet basis.
                    operational when the packets are
                    addressed to the node itself.                          During loopback, DTCR = 0 will
                                                                           cause a CRC to be generated on the
                    The C-LANCE will not receive any
                                                                           transmitted packet, but no CRC
                    packets externally when it is in inter-
                                                                           check will be done by the receiver
                    nal loopback mode.
                                                                           since the CRC logic is shared and
                    EXTERNAL LOOPBACK allows the                           cannot generate and check CRC at
                    C-LANCE to transmit a packet                           the same time. The generated CRC
                    through the SIA transceiver cable                      will be written into memory with the
                    out to the Ethernet medium. It is                      data and can be checked by the host
                    used to determine the operability of                   software.
                    all circuitry and connections be-
                                                                           If DTCR = 1 during loopback, the
                    tween the C-LANCE and the physi-
                                                                           host software must append a CRC
                    cal medium. Multicast addressing in
                                                                           value to the transmit data.
                    external loopback is valid only when
                    DTCR = 1 (user needs to append the                     The receiver will check the CRC on
                    4 bytes CRC).                                          the received data and report any
                                                                           errors.
                    In external loopback, the C-LANCE
                    also receives packets from other          02    LOOP   LOOPBACK allows the C-LANCE to
                    nodes. The FIFOs READ/WRITE                            operate in full duplex mode for test
                    pointers may misalign in the                           purposes. The packet size is limited
                    C-LANCE under heavy traffic. The                       to 8–32 bytes.The received packet
                    packet could then be corrupted or                      can be up to 36 bytes (32 + 4 bytes
                    not received. Therefore, the external                  CRC) when DTCR = 0. During loop-
                    loopback execution may need to be                      back, the runt packet filter is disabled
                    repeated. See specific discussion                      because the maximum packet is
                    under “Loopback” in later section.                     forced to be smaller than the
                                                                           minimum size Ethernet packet
                    INTL is only valid if LOOP = 1; other-
                                                                           (64 bytes).
                    wise, it is ignored.
                                                                           LOOP = 1 allows simultaneous
                      LOOP        INTL     LOOPBACK
                                                                           transmission and reception for a
                        0         X       No loopback,                     message constrained to fit within the
                                          normal                           Transmit FIFO. The C-LANCE waits
                        1          0      External                         until the entire message is in the
                                                                           Transmit FIFO before serial trans-
                        1          1      Internal                         mission begins. The incoming data
05           DRTY   DISABLE RETRY. When DRTY = 1,                          stream fills the Receive FIFO. Mov-
                    the C-LANCE will attempt only one                      ing the received message out of the
                    transmission of a packet. If there is a                Receive FIFO to memory does not
                    collision on the first transmission at-                begin until reception has ceased.
                    tempt, a Retry Error (RTRY) will be
                    reported in Transmit Message De-
                    scriptor 3 (TMD3).




1-26                                                   Am79C90
                                                PRELIMINARY                                                      AMD

Bit        Name       Description                            hardware maps this address into one of 64 categories
                                                             which correspond to 64 bits in the Logical Address Filter
                                                             Register. The hardware then accepts or rejects the
                      In loopback mode, transmit data
                      chaining is not possible. Receive      packet depending on the state of the bit in the Logical
                      data chaining is possible if receive   Address Filter Register which corresponds to the se-
                      buffers are 32 bytes long to allow     lected category. For example, if the address maps into
                      time for lookahead.                    category 24, and bit 24 of the logical address filter regis-
01          DTX       DISABLE THE TRANSMITTER                ter is set, the packet is accepted.
                      causes the C-LANCE to not access
                      the Transmitter Descriptor Ring, and   A node can be made a member of several groups by set-
                      therefore, no transmissions are at-    ting the appropriate bits in the logical address filter
                      tempted. DTX = 1 will clear the
                      TXON bit in CSR0 when initialization
                                                             register.
                      is complete.
                                                             The details of the hardware mapping algorithm are as
00          DRX       DISABLE THE RECEIVER causes            follows:
                      the C-LANCE to reject all incoming
                      packets and not access the Receive     If the first bit of an incoming address is a “1” [PADR (0)
                      Descriptor Ring. DRX = 1 will clear
                      the RXON bit in the CSR0 when in-
                                                             =1], the address is deemed logical and is passed
                      itialization is complete.              through the logical address filter.
                                                             The logical address filter is a 64-bit mask composed of
      47                                        1 0          four sixteen-bit registers, LADRF (63:00) in the initiali-
                                                             zation block, that is used to accept incoming Logical Ad-
                                                             dresses. The incoming address is sent through the CRC
                                                             circuit. After all 48 bits of the address have gone through
                                                  ‘0’        the CRC circuit, the high order 6 bits of the resultant
                                        PADR (47:01)         CRC (32-bit CRC) are strobed into a register. This regis-
                                              17881B-20      ter is used to select one of the 64-bit positions in the
                                                             Logical Address Filter. If the selected filter bit is a “1,” the
47:00      PADR       PHYSICAL ADDRESS is the unique         address is accepted and the packet will be put in mem-
                      48-bit physical address assigned to    ory. The logical address filter only assures that there is a
                      the C-LANCE. PADR (0) must be          possibility that the incoming logical address belongs to
                      zero.                                  the node. To determine if it belongs to the node, the in-
                                                             coming logical address that is stored in main memory is
Logical Address Filter                                       compared by software to the list of logical addresses to
                                                             be accepted by this node.
      63                                           0
                         LADRF
                                                             The task of mapping a logical address to one of 64-bit
                                                             positions requires a simple computer program (see Ap-
                                           17881B-21         pendix A) which uses the same CRC algorithm (used in
                                                             C-LANCE and defined per Ethernet) to calculate the
63:00      LADRF      The 64-bit mask used by the            HASH (see Figure 7).
                      C-LANCE    to  accept logical
                      addresses.                             Driver software that manages a list of multicast ad-
                                                             dresses can work as follows. First the multicast address
                                                             list and the logical address filter must be initialized.
The purpose of logical (or group or multicast) addresses     Some sort of management function such as the driver
is to allow a group of nodes in a network to receive the     initialization routine passes to the driver a list of ad-
same message. Each node can maintain a list of multi-        dresses. For each address in the list the driver uses a
cast addresses that it will respond to. The logical ad-      subroutine similar to the one listed in the appendix to set
dress filter mechanism in the C-LANCE is a hardware          the appropriate bit in a software copy of the logical ad-
aide that reduces the average amount of host computer        dress filter register. When the complete list of addresses
time required to determine whether or not an incoming        has been processed, the register is loaded.
packet with a multicast destination address should be
                                                             Later, when a packet is received, the driver first looks at
accepted.
                                                             the Individual/Group bit of the destination address of the
The logical address filter hardware is an implementation     packet to find out whether or not this is a multicast ad-
of a hash code searching technique commonly used by          dress. If it is, the driver must search the multicast ad-
software programmers. If the multicast bit of the desti-     dress list to see if this address is in the list. If it is not in
nation address of an incoming packet is set, the             the list, the packet is discarded.


                                                        Am79C90                                                         1-27
       AMD                                            PRELIMINARY

The Broadcast address, which consists of all ones is a              Bit         Name       Description
special multicast address. Packets addressed to the
broadcast address must be received by all nodes. Since
                                                                    31:29       RLEN       RECEIVE RING LENGTH is the
broadcast packets are usually more common than other                                       number of entries in the receive ring
multicast packets, the broadcast address should be the                                     expressed as a power of two.
first address in the multicast address list.                                                   RLEN       Number of Entries
The Broadcast address does not go through the Logical                                            0                  1
Address Filter and is always enabled. If the Logical Ad-                                         1                  2
dress Filter is loaded with all zeroes, all incoming logical                                     2                  4
                                                                                                 3                  8
addresses except broadcast will be rejected. The multi-
                                                                                                 4                 16
cast addressing in external loopback is operational only
                                                                                                 5                 32
when DTCR in the mode register is set to 1.                                                      6                 64
                                                                                                 7                 128
                                                                    28:24        RES       RESERVED. Read as zeroes. Write
                            32-Bit Resultant CRC                                           as zeroes.
                            31       26        0                    23:03       RDRA       RECEIVE DESCRIPTOR RING AD-
 Destination                                                                               DRESS is the base address (lowest
 Address                                                                                   address) of the Receive Descriptor
                     CRC                                                                   Ring.
47           1 0                                Logical Address
                     Gen                                            02:00                  MUST BE ZEROES. These bits are
                                                     Filter
                                               63             0                            RDRA (02:00) and must be zeroes
                                                                                           because the Receive Ring is aligned
               “1”     Enable                                                              on a quadword boundary.
                                          64

                                                                    Transmit Descriptor Ring Pointer
                                      MUX
                                                        Match*            31 29 28 24 23                            3 2 0
                                 6
                                      Select

*Match - 1, the packet is accepted
                                                                                        RES           000 ‘(Quadword
 Match - 0, the packet is rejected                 17881B-22
                                                                                                          Boundary)’
                                                                                        TLEN
       Figure 7. Logical Address Filter Operation                                                     TDRA (23:03)
                                                                                                                  17881B-24

Receive Descriptor Ring Pointer
                                                                    31:29        TLEN      TRANSMIT RING LENGTH is the
     31 29 28 24 23                                 3 2 0                                  number of entries in the Transmit
                                                                                           Ring expressed as a power of two.
                                                                                               TLEN      Number of Entries
                                                                                                 0                  1
                     RES             000 ‘(Quadword                                              1                  2
                                         Boundary)’                                              2                  4
                     RLEN
                                     RDRA (23:03)                                                3                  8
                                                                                                 4                 16
                                                   17881B-23
                                                                                                 5                 32
                                                                                                 6                 64
                                                                                                 7                 128
                                                                    28:24        RES       RESERVED. Read as zeroes. Write
                                                                                           as zeroes.
                                                                    23:03       TDRA       TRANSMIT DESCRIPTOR RING
                                                                                           ADDRESS is the base address (low-
                                                                                           est address) of the Transmit De-
                                                                                           scriptor Ring.
                                                                    02:00                  MUST BE ZEROES. These bits are
                                                                                           TDRA (02:00) and must be zeroes
                                                                                           because the Transmit Ring is
                                                                                           aligned on a quadword boundary.



1-28                                                           Am79C90
                                                     PRELIMINARY                                                AMD

Buffer Management                                                  Receive Message Descriptor 1 (RMD1)
Buffer Management is accomplished through message                  15                87                        0
descriptors organized in ring structures in memory.
Each message descriptor entry is four words long.
There are two rings allocated for the device: a Receive
ring and a Transmit ring. The device is capable of polling                                                         HADR
each ring for buffers to either empty or fill with packets to                                                      ENP
or from the channel. The device is also capable of enter-
ing status information in the descriptor entry. C-LANCE                                                            STP
polling is limited to looking one ahead of the descriptor                                                          BUFF
entry the C-LANCE is currently working with.
                                                                                                                   CRC
The location of the descriptor rings and their length are
found in the initialization block, accessed during the in-                                                         OFLO
itialization procedure by the C-LANCE. Writing a “ONE”                                                             FRAM
into the STRT bit of CSR0 will cause the C-LANCE to
start accessing the descriptor rings and enable it to send                                                         ERR
and receive packets.                                                                                               OWN
The C-LANCE communicates with a HOST device                                                                 17881B-26
through the ring structures in memory. Each entry in the
ring is either owned by the C-LANCE or the HOST.                   Bit      Name     Description
There is an ownership bit (OWN) in the message de-
scriptor entry. Mutual exclusion is accomplished by a
                                                                   15       OWN      This bit indicates that the descriptor
protocol which states that each device can only relin-                               entry is owned by the host (OWN = 0)
quish ownership of the descriptor entry to the other de-                             or by the C-LANCE (OWN = 1). The
vice; it can never take ownership, and no device can                                 C-LANCE clears the OWN bit after
change the state of any field in any entry after it has relin-                       filling the buffer pointed to by the de-
quished ownership.                                                                   scriptor entry. The host sets the
                                                                                     OWN bit after emptying the buffer.
                                                                                     Once the C-LANCE or host has relin-
Descriptor Ring
                                                                                     quished ownership of a buffer, it
Each descriptor in a ring in memory is a 4-word entry.                               must not change any field in the four
The following is the format of the receive and the trans-                            words that comprise the descriptor
                                                                                     entry.
mit descriptors.
                                                                   14       ERR      ERROR summary is the OR of
Receive Message Descriptor Entry                                                     FRAM, OFLO, CRC or BUFF.
                                                                   13       FRAM     FRAMING ERROR indicates that
Receive Message Descriptor 0 (RMD0)                                                  the incoming packet contained a
      15                                                0                            non-integer multiple of eight bits and
                                                                                     there was a CRC error. If there was
                           LADR                                                      not a CRC error on the incoming
                                                                                     packet, then FRAM will not be set
                                              17881B-25                              even if there was a non-integer multi-
                                                                                     ple of eight bits in the packet. FRAM
                                                                                     is not valid in internal loopback
Bit         Name         Description                                                 mode. FRAM is valid only when ENP
                                                                                     is set and OFLO is not.
15:00       LADR         The LOW ORDER 16 address bits of
                         the buffer pointed to by this descrip-
                         tor. LADR is written by the host and is
                         not changed by the C-LANCE.




                                                            Am79C90                                                    1-29
       AMD                                         PRELIMINARY

Bit          Name     Description                                Receive Message Descriptor 3 (RMD3)
                                                                       15    12 11                                  0
12           OFLO     OVERFLOW error indicates that the
                      receiver has lost all or part of the in-
                      coming packet due to an inability to
                      store the packet in a memory buffer
                      before the internal Receive FIFO
                                                                                                                  MCNT
                      overflowed. OFLO is valid only when
                      ENP is not set.
                                                                                                                  RES
11           CRC      CRC indicates that the receiver has
                      detected a CRC error on the incom-                                                    17881B-28
                      ing packet. CRC is valid only when
                      ENP is set and OFLO is not.
10           BUFF     BUFFER ERROR is set any time the           15:12      RES      RESERVED. Read as zeroes. Write
                      C-LANCE does not own the next                                  as zeroes.
                      buffer while data chaining a received      11:00      MCNT     MESSAGE BYTE COUNT is the
                      packet. This can occur in either of                            length in bytes of the received mes-
                      two ways: 1) the OWN bit of the next                           sage. MCNT is valid only when ERR
                      buffer is zero, or 2) the Receive FIFO                         is clear and ENP is set. MCNT is writ-
                      overflow occurred before the                                   ten by the chip and cleared by the
                      C-LANCE         has     performed      a                       host.
                      lookahead poll of the next receive
                      descriptor.
                      If a Buffer Error occurs, an Overflow      Transmit Message Descriptor Entry
                      Error may also occur internally in the
                      Receive FIFO, but will not be re-          Transmit Message Descriptor 0 (TMD0)
                      ported in the descriptor status entry
                                                                       15                                           0
                      unless both BUFF and OFLO errors
                      occur at the same time.                                             LADR
09           STP      START OF PACKET indicates that
                      this is the first buffer used by the                                                   17881B-29
                      C-LANCE for this packet. It is used
                      for data chaining buffers.
                                                                 Bit        Name     Description
08           ENP      END OF PACKET indicates that this
                      is the last buffer used by the
                      C-LANCE for this packet. It is used        15:00      LADR     The LOW ORDER 16 address bits of
                      for data chaining buffers. If both STP                         the buffer pointed to by this descrip-
                      and ENP are set, the packet fits into                          tor. LADR is written by the host and is
                      one buffer and there is no data                                not changed by the C-LANCE.
                      chaining.
07:00        HADR     The HIGH ORDER 8 address bits of
                      the buffer pointed to by this descrip-     Transmit Message Descriptor 1 (TMD1)
                      tor. This field is written by the host
                                                                 15                  87                       0
                      and unchanged by the C-LANCE.


Receive Message Descriptor 2 (RMD2)
      15      12 11                                  0                                                            HADR
                                                                                                                  ENP

                                                                                                                  STP
                                                                                                                  DEF
                                                     BCNT
                                                                                                                  ONE
                                           Must be Ones
                                                  17881B-27                                                       MORE
15:12                 MUST BE ONES. This field is written                                                         ADD_FCS
                      by the host and is not changed by the
                      C-LANCE.                                                                                    ERR
11:00        BCNT     BUFFER BYTE COUNT is the length
                      of the buffer pointed to by this de-                                                        OWN
                      scriptor, expressed as a two’s com-                                                  17881B-30
                      plement number. This field is written
                      by the host and is not changed by the
                      C-LANCE. Minimum buffer size is 64
                      bytes for the first buffer of packet.

1-30                                                      Am79C90
                                                PRELIMINARY                                                 AMD

Bit      Name     Description                                 Transmit Message Descriptor 2 (TMD2)
                                                                    15    12 11                                  0
15       OWN      This bit indicates that the descriptor
                  entry is owned by the host (OWN =
                  O) or by the C-LANCE (OWN = 1).
                  The host sets the OWN bit after filling
                  the buffer pointed to by this descrip-
                                                                                                                BCNT
                  tor. The C-LANCE clears the OWN
                  bit after transmitting the contents of
                  the buffer. Neither the host nor the C-                                                       ONES
                  LANCE may alter a descriptor entry                                                        17881B-31
                  after it has relinquished ownership.
14       ERR      ERROR summary is the “OR” of
                  LCOL, LCAR, UFLO or RTRY.                   Bit        Name     Description
13      ADD_FCS   Setting ADD_FCS=1, instructs the
                  controller to append a CRC to this          15:12      ONES     Must be ones. This field is set by the
                  transmitted frame, regardless of the                            host and is not changed by the
                  setting of the DTCR bit (bit 3 in the                           C-LANCE.
                  Mode Register). The ADD_FCS bit             11:00      BCNT     BUFFER BYTE COUNT is the us-
                  allows the controller to be configured                          able length in bytes of the buffer
                  to append CRC on a per packet ba-                               pointed to by this descriptor ex-
                  sis, when DTCR=1. ADD_FCS is                                    pressed as a negative two’s comple-
                  only valid when STP=1.                                          ment number. This is the number of
12       MORE     MORE indicates that more than one                               bytes from this buffer that will be
                  retry was needed to transmit a                                  transmitted by the C-LANCE. This
                  packet.                                                         field is written by the host and is not
11       ONE      ONE indicates that exactly one retry                            changed by the C-LANCE. The first
                  was needed to transmit a packet.                                buffer of a packet has to be at least
                  The ONE flag is not valid when                                  100 bytes minimum when data
                  LCOL is set.                                                    chaining and 64 byte (DTCR = 1) or
                                                                                  60 bytes (DCTR = 0) when not data
10       DEF      DEFERRED indicates that the                                     chaining.
                  C-LANCE had to defer while trying to
                  transmit a packet. This condition oc-
                  curs if the channel is busy when the
                  C-LANCE is ready to transmit.
09        STP     START OF PACKET indicates that
                  this is the first buffer to be used by
                  the C-LANCE for this packet. It is
                  used for data chaining buffers. STP
                  is set by the host and is not changed
                  by the C-LANCE. The STP bit must
                  be set in the first buffer of the packet,
                  or the C-LANCE will skip over this
                  descriptor and poll the next descrip-
                  tor(s) until the OWN and STP bits
                  are set.
08       ENP      END OF PACKET indicates that this
                  is the last buffer to be used by the C-
                  LANCE for this packet. It is used for
                  data chaining buffers. If both STP
                  and ENP are set, the packet fits into
                  one buffer and there is no data
                  chaining. ENP is set by the host and
                  is not changed by the C-LANCE.
07:00    HADR     The HIGH ORDER 8 address bits of
                  the buffer pointed to by this descrip-
                  tor. This field is written by the host
                  and is not changed by the C-LANCE.




                                                       Am79C90                                                       1-31
       AMD                                          PRELIMINARY

Transmit Message Descriptor 3 (TMD3)                             10         RTRY        RETRY ERROR indicates that the
                                                                                        transmitter has failed in 16 attempts
15             10 9                             0                                       to successfully transmit a message
                                                                                        due to repeated collisions on the me-
                                                                                        dium. If DRTY = 1 in the MODE reg-
                                                                                        ister, RTRY will set after 1 failed
                                                                                        transmission attempt.
                                                    TDR
                                                                 09:00       TDR        TIME DOMAIN REFLECTOMETRY
                                                    RTRY                                reflects the state of an internal C-
                                                                                        LANCE counter that counts from the
                                                    LCAR                                start of a transmission to the occur-
                                                                                        rence of a collision. This value is
                                                    LCOL                                useful in determining the approxi-
                                                                                        mate distance to a cable fault. The
                                                    RES                                 TDR value is written by the
                                                                                        C-LANCE and is valid only if RTRY
                                                    UFLO                                is set.
                                                    BUFF         Ring Access Mechanism in the C-LANCE
                                                17881B-32        Once the C-LANCE is initialized through the initializa-
                                                                 tion block and started, the CPU and the C-LANCE com-
Bit          Name     Description                                municate via transmit and receive rings, for packet
                                                                 transmission and reception.
15           BUFF     BUFFER ERROR is set by the                 There are 2 sets of RAM locations (four 16-bit register
                      C-LANCE during transmission when           per set, corresponding to the 4 entries in each descrip-
                      the C-LANCE does not find the ENP
                      flag in the current buffer and does
                                                                 tor) in the C-LANCE. The first set points to the current
                      not own the next buffer. This can oc-      buffer, and they are the working registers which are
                      cur in either of two ways: either the      used for transferring the data for the packet. The second
                      OWN bit of the next buffer is zero, or     set contains the pointers to the next buffer in the ring
                      Transmit FIFO underflow occurred           which the C-LANCE obtained from the lookahead
                      before the C-LANCE has performed
                      a lookahead poll of the next transmit      operation.
                      descriptor. BUFF is set by the
                      C-LANCE and cleared by the host.           There are three types of ring access in the C-LANCE.
                      BUFF error will turn off the transmit-     The first type is when the C-LANCE polls the rings to
                      ter (CSR0, TXON = 0).                      own a buffer. The second type is when the buffers are
                      If a Buffer Error occurs, an Underflow     data chained. The C-LANCE does a lookahead opera-
                      Error will also occur. BUFF error is       tion between the time that it is transferring data to/from
                      not valid when LCOL or RTRY error          the Transmit/Receive FIFOs; this lookahead is done
                      is set during TX data chaining.
                                                                 only once. The third type is when the C-LANCE tries to
14           UFLO     UNDERFLOW ERROR indicates                  own the next descriptor in the ring when it clears the
                      that the transmitter has truncated a
                      message due to data late from mem-         OWN bit for the current buffer.
                      ory. UFLO indicates that the Trans-
                      mit FIFO has emptied before the end        Transmit Ring Buffer Management
                      of the packet was reached.                 When there is no Ethernet activity, the C-LANCE will
                      Upon UFLO error, transmitter is            automatically poll the transmit ring in the memory once it
                      turned off (CSR0, TXON = 0).               has started (CSR0, STRT = 1). This polling occurs every
13           RES      RESERVED bit. The C-LANCE will             1.6 ms, (CSR0 TDMD bit = 0) and consists of reading
                      write this bit with a “0.”                 the status word of the transmit descriptor, TMD1, until
12           LCOL     LATE COLLISION indicates that a            the C-LANCE owns the descriptor. The C-LANCE will
                      collision has occurred after the slot      read TMD0 and TMD2 to get the rest of the buffer ad-
                      time of the channel has elapsed. The
                                                                 dress and the buffer byte count when it owns the de-
                      C-LANCE does not retry on late
                      collisions.                                scriptor. Each of these memory reads is done
11           LCAR     LOSS OF CARRIER is set when the            separately with a new arbitration cycle for each transfer.
                      carrier input (RENA) to the
                      C-LANCE goes false during a                If the transmit buffers are data chained (current buffer
                      C-LANCE-initiated          transmission.   ENP = 0), the C-LANCE will look ahead to the next de-
                      The C-LANCE does not retry upon            scriptor in the ring while transferring the current buffer
                      loss of carrier. It will continue to       into the Transmit FIFO (see Figure 8-1). The C-LANCE
                      transmit the whole packet until done.
                                                                 does this lookahead only once. If it does not own the
                      LCAR is not valid in INTERNAL
                      LOOPBACK MODE.                             next transmit Descriptor Table Entry (DTE) (2nd TX ring



1-32                                                      Am79C90
                                                  PRELIMINARY                                                   AMD

for this packet) it will transmit the current buffer and up-   the Receiver Ring once for a buffer. If it still does not own
date the status of current Ring with the BUFF and UFLO         the buffer, it will set the MISS error in CSR0 and will not
error bits set. If the C-LANCE owns the 2nd DTE, it will       poll the receive ring until the packet ends.
also read the buffer address and the buffer byte count of
this entry. Once the C-LANCE has finished emptying the         Assuming the C-LANCE owns a receive buffer when the
current buffer, it clears the OWN bit for this buffer, and     packet arrives, it will perform a lookahead operation on
immediately starts loading the Transmit FIFO from the          the next DTE between periods when it is dumping the re-
next (2nd) buffer. Between DMA bursts, starting from           ceived data from the Receive FIFO to the first receive
the 2nd buffer, the C-LANCE does a lookahead again to          buffer in case the current buffer requires data chaining.
check if it owns the next (3rd) buffer. This activity goes     When the C-LANCE owns the buffer, the lookahead op-
on until the last transmit DTE indicates the end of the        eration consists of three separate single word DMA
packet (TMD1, ENP = 1). Once the last part of the pack-        reads: RMD1, RMD0, and RMD2. When the C-LANCE
et has been transmitted out from the Transmit FIFO to          does not own the next buffer, the lookahead operation
the medium, the C-LANCE will update the status in              consists of only one single DMA read, RMD1. Either
TMD1, TMD3 (TMD3 is updated only when there is an              lookahead operation is done only once. Following the
error) and will relinquish the last buffer to the CPU. The     lookahead operation, whether C-LANCE owns the next
C-LANCE tries to own the next buffer (first buffer of the      buffer or not, the C-LANCE will transfer the data from
next packet), immediately after it relinquishes the last       Receive FIFO to the first receive buffer for this packet in
buffer of the current packet. This guarantees the back-        burst mode (8 word transfer per one DMA cycle
to-back transmission of the packets. If the C-LANCE            arbitration).
does not own the next buffer, it then polls the TX ring        If the packet being received requires data chaining, and
every 1.6 ms.                                                  the C-LANCE does not own the second DTE, the
When an error occurs before all of the buffers get trans-      C-LANCE will update the current buffer status, RMD1,
mitted, the status, TMD3 , is updated in the current DTE,      with the BUFF and/or OFLO error bits set. If the
own bit is cleared in TMD1, and TINT bit is set in CSR0        C-LANCE does own the next buffer (second DTE) from
which causes an interrupt if INEA = 1. The C-LANCE will        previous lookahead, the C-LANCE will relinquish the
then skip over the rest of the descriptors for this packet     current buffer and start filling up the second buffer for
(clears the OWN bit and sets the TINT bit in CSR0) until       this packet. Between the time that the C-LANCE is
it finds a buffer with both the STP and OWN bit being set      transferring data from the Receive FIFO to the second
(this indicates the first buffer for the next packet).         buffer, it does a lookahead operation again to see if it
                                                               owns the next (third) buffer. If the C-LANCE does own
When the transmit buffers are not data chained (current        the third DTE, it will also read RMD0, and RMD2 to get
descriptor’s ENP = 1), the C-LANCE will not perform any        the rest of buffer pointer address and buffer byte count.
lookahead operation. It will transmit the current buffer,
update the TMD3 if any error, and then update the              This activity continues on until the C-LANCE recognizes
status and clear the OWN bit in TMD1 . The C-LANCE             the end of the packet (physical medium is idle); it then
will then immediately check the next descriptor in the         updates the current buffer status with the end of packet
ring to see if it owns it. If it does, the C-LANCE will also   bit (ENP) set. The C-LANCE will also update the mes-
read the rest of the entries from the descriptor table. If     sage byte count (RMD3) with the total number of bytes
the C-LANCE does not own it, it will poll the ring once        received for this packet in the current buffer (the last
every 1.6 ms until it owns it. User may set the TDMD bit       buffer for this packet).
in CSR0 when it has relinquished a buffer to the               The dual FIFOs in the C-LANCE are utilized by the inter-
C-LANCE. This will force the C-LANCE to check the              nal microcode to guarantee that continuous receive ac-
OWN bit at this buffer without waiting for the polling time    tivity does not prevent the servicing of pending transmit
to elapse.                                                     packets. The microcode includes a single transmit de-
Receive Ring Buffer Management                                 scriptor poll operation at the beginning of buffer DMA
                                                               operations for an incoming receive packet. This single
Receive Ring access is similar to the transmit ring ac-        transmit descriptor poll is performed only once during
cess. Once the receiver is enabled, the C-LANCE will al-       the receive microcode routine for each packet that is re-
ways try to have a receive buffer available, should there      ceived. If the OWN bit in the transmit descriptor is set,
be a packet addressed to this node for reception. There-       burst transfers to the Transmit FIFO are interleaved with
fore, when the C-LANCE is idle, it will poll the receive       burst transfers from the Receive FIFO. By interleaving
ring entry once every 1.6 ms, until it owns the current re-    the transmit buffer transfers with the receive buffer
ceive DTE. Once the C-LANCE owns the buffer, it will           transfers, the beginning of the transmit packet is
read RMD0 and RMD2 to get the rest of buffer address           preloaded in the Transmit FIFO, ready to be transmitted
and buffer byte count. When a packet arrives from the          immediately following the end of the receive packet on
physical medium, after the Address Recognition Logic           the wire.
accepts the packet, the C-LANCE will immediately poll

                                                         Am79C90                                                      1-33
       AMD                                                                       PRELIMINARY

                                                                                               (HOLD dwell time). Burst DMAs are always 8 transfer
                   1       2                                                                   cycles unless there are fewer than 8 words left to be
          0                            3                                                       transferred to/from the Transmit/Receive FIFO, or if
                                                                                               there are fewer than 8 words left to be transferred to/
                                                                         C
                                                                                               from the RX/TX buffer. Transmit DMAs may be shorter
 127                                       4                             A                     than 8 words if a collision is detected during the DMA.
                                                                         B                     Single Word DMA Transfer
                                   5
                                                                                               The C-LANCE initiates single word DMA transfers to ac-
                  7        6                                                                   cess the transmit and receive rings or the initialization
                  Output                             A               B               C         block. The C-LANCE will not initiate any burst DMA
                  Packet                                                                       transfers while reading the initialization block. The
                                                                             17881B-33
                                                                                               C-LANCE will not initiate any burst DMA transfers be-
              Figure 8-1. Data Chaining (Transmit)                                             tween the time that it discovers ownership of a descrip-
                                                                                               tor and the time that it reads the buffer pointer and buffer
                                                                                               byte count entries of that descriptor.
C-LANCE 1                      2       CPU                   1                   2
                                                                                     C-LANCE
      0               X    Y               3
                                                   CPU                                         FIFO Operation
                                   Z                             B           C
              W                (Note                0                                D 3       The dual FIFOs provide temporary buffer storage for
                                 1)                      A                       (Note         data being transferred between the parallel bus l/O pins
                                                                                   2)
127                                            4                                               and serial I/O pins. The capacity of the Transmit FIFO is
                                                                                               48 bytes and the Receive FIFO is 64 bytes.
                                                   127                                   4
                                                                                               Transmit
                                       5
                                                                                               Data is loaded into the Transmit FIFO under internal
                  7     6                                                    5
                                                                                               microprogram control. The Transmit FIFO has to have
                  Transmit                                       Receive                       more than 16 bytes empty before the C-LANCE re-
                                                                             17881B-34         quests the bus (HOLD is asserted). The C-LANCE will
Notes:
                                                                                               start sending the preamble (if the line is idle) as soon as
1. W, X, Y, Z are the packets queued for transmission.
                                                                                               the first byte is loaded to the Transmit FIFO from
2. A, B, C, D are the packets received by the C-LANCE.                                         memory.
 Figure 8-2. Buffer Management Descriptor Rings                                                Receive
                                                                                               Data is loaded into the Receive FIFO from the serial in-
                                                                                               put shift register during reception. Data leaves the Re-
C-LANCE DMA Transfer                                                                           ceive FIFO under microprogram control. The C-LANCE
(Bus Master Mode)                                                                              microcode will wait until there are at least 16 bytes of
There are two types of DMA Transfers with the                                                  data in the Receive FIFO before initiating a DMA burst
C-LANCE:                                                                                       transfer. Preamble and Start Frame Delimiter (SFD) are
                                                                                               not loaded into the Receive FIFO.
      Burst mode DMA
      Single word DMA                                                                          FIFOs – Memory Byte Alignment
                                                                                               Memory buffers may begin and end on arbitrary byte
Burst Mode DMA
                                                                                               boundaries. Parallel data is byte aligned between the
Burst DMA is used for Transmission or Reception of the                                         Transmit or Receive FIFO and DAL lines
Packets, (Read/Write from/to Memory).                                                          (DAL0–DAL15). Byte alignment can be reversed by set-
                                                                                               ting the Byte Swap (BSWP) bit in CSR3.
The Burst Transfers are 8 consecutive word reads
(transmit) or writes (receive) that are done in a single                                       TRANSMISSION – WORD READ FROM EVEN MEM-
bus arbitration cycle. In other words, once the C-LANCE                                        ORY ADDRESS
receives the bus acknowledge, (HLDA = LOW), it will do
8 word transfers (8 DMA cycle, min. at 600 ns per cycle)                                       BSWP=0:       FIFO BYTE n     gets DAL <07:00>
without releasing the bus request signal (HOLD =                                                             FIFO BYTE n + 1 gets DAL <15:08>
LOW). If there are more than 16 bytes empty in the                                             BSWP=1:       FIFO BYTE n     gets DAL <15:08>
Transmit FIFO, in transmit mode, or at least 16 bytes of                                                     FIFO BYTE n + 1 gets DAL <07:00>
data, in the Receive FIFO in receive mode, when the
C-LANCE releases the bus (HOLD deasserted), the                                                TRANSMISSION – BYTE READ FROM EVEN
C-LANCE will request the bus again within 700 ns                                               MEMORY ADDRESS


1-34                                                                                     Am79C90
                                                    PRELIMINARY                                                              AMD

BSWP=0:       FIFO BYTE n          gets DAL <07:00>              ACON, and BSWP are used; BCON, ACON, and BSWP
              –don’t care          gets DAL <15:08>              default values are 0, 0, and 0 respectively). Only then
                                                                 the user may set the INIT bit in CSR0.
BSWP=1:       FIFO BYTE n          gets DAL <15:08>
              –don’t care          gets DAL <07:00>              It is recommended that the C-LANCE not be re-started,
TRANSMISSION – BYTE READ FROM ODD                                once it has been stopped (STOP = 1 in CSR0), by set-
MEMORY ADDRESS                                                   ting the STRT bit in CSR0 without reinitialization. Re-
                                                                 starting the C-LANCE in this way puts the C-LANCE in
BSWP=0:       FIFO BYTE n          gets DAL <15:08>              operation in accordance with the parameters set up in
              –don’t care          gets DAL <07:00>              the mode register, but the contents of the descriptor
BSWP=1:       FIFO BYTE n          gets DAL <07:00>              pointers in the C-LANCE will not be guaranteed.
              –don’t care          gets DAL <15:08>
                                                                 Frame Formatting
RECEPTION – WORD WRITE TO EVEN MEMORY
                                                                 The C-LANCE performs the encapsulation/decapsula-
ADDRESS
                                                                 tion function of the data link layer (second layer of ISO
BSWP=0:       DAL <07:00>          gets FIFO BYTE n              model) as follows:
              DAL <15:08>          gets FIFO BYTE n + 1
                                                                 Transmlt
BSWP=1:       DAL <15:08>          gets FIFO BYTE n              In transmit mode, the user must supply the destination
              DAL <07:00>          gets FIFO BYTE n + 1          address, source address, and Type Field (or Length
RECEPTION – BYTE WRITE TO EVEN MEMORY                            Field) as a part of data in transmit data buffer memory.
ADDRESS                                                          The C-LANCE will append the preamble, SFD, and
                                                                 CRC (FCS) to the frame as is shown in Figures 9-1
BSWP=0:       DAL <07:00>          gets FIFO BYTE n              and 9-2.
              DAL <15:08>          –undefined
                                                                 Receive
BSWP=1:       DAL <15:08>          gets FIFO BYTE n
              DAL <07:00>          –undefined                    In receive mode, the C-LANCE strips off the preamble
                                                                 and SFD and transfers the rest of the frame, including
RECEPTION – BYTE WRITE TO ODD MEMORY                             the CRC bytes (4 bytes), to the memory. The C-LANCE
ADDRESS                                                          will discard packets with less than 64 bytes (runt packet)
BSWP=0:       DAL <07:00>          –undefined                    and will reuse the receive buffer for the next packet. This
              DAL <15:08>          gets FIFO BYTE n              is the only case where the packet is discarded after the
                                                                 packet has been transferred to the receive buffer. A runt
BSWP=1:       DAL <15:08>          –undefined                    packet is normally the result of a collision.
              DAL <07:00>          gets FIFO BYTE n

The C-LANCE Recovery and                                           Preamble       Synch      Dest.     Source
                                                                  1010 ... 1010   1   1      ADR        ADR Type            Data   FCS
Reinitialization
The transmitter and receiver section of the C-LANCE                   62            2          6         6       2 46–1500   4
                                                                      Bits         Bits      Bytes     Bytes   Bytes Bytes Bytes
are turned on via the initialization block (MODE REG:
DRX, DTX bits). The state of the transmitter and the re-                                                                     17881B-35
ceiver are monitored through the CSR0 register (RXON,                        Figure 9-1. Ethernet Frame Format
TXON bits). The C-LANCE must be reinitialized if the
transmitter and/or the receiver has not been turned on
during the original initialization, and later it is desired to     Preamble       SFD      Dest.   Source            LLC
                                                                  1010 ... 1010 10101011   ADR      ADR Length       Data     PAD FCS
have them turned on. When either the transmitter or re-
ceiver shuts off because an error (MERR, UFLO, TX                    56            8         6         6       2     46–1500         4
BUFF error), it is necessary to reinitialize the C-LANCE             Bits         Bits     Bytes     Bytes   Bytes    Bytes        Bytes
to turn the transmitter and/or receiver back on again.                                                                       17881B-36
The user should rearrange the descriptors in the trans-               Figure 9-2. IEEE 802.3 MAC Frame Format
mit or receive ring prior to reinitialization. This is neces-
sary since the transmit and receive descriptor pointers
are reset to the beginning of the ring upon initialization.      Framing Error (Dribbling Bits)
To reinitialize the C-LANCE, the user must first stop the        The C-LANCE can handle up to 7 dribbling bits when a
C-LANCE by setting the stop bit in CSR0. The user                received packet terminates; the input to the C-LANCE,
needs to reprogram CSR3 because its contents get                 RCLK, stops following the deassertion of RENA. During
cleared when the stop bit gets set (CSR3 reprogram-              the reception, the CRC is generated on every serial bit
ming is not needed when default values of BCON,                  (including the dribbling bits) coming from the medium,

                                                           Am79C90                                                                 1-35
       AMD                                           PRELIMINARY

and the CRC gets sampled internally on every byte                 continues to send the preamble, and sends the JAM pat-
boundary. The framing error is reported to the user as            tern following the preamble. If collision occurs after the
follows:                                                          preamble, the C-LANCE will send the JAM pattern fol-
                                                                  lowing the transmission of the current byte. The JAM
   If the number of the dribbling bits is 1 to 7 bits and         pattern is any pattern except the CRC bytes.
   there is no CRC error, then there is no Framing
   error (FRAM = 0).                                              Receive Based Collision
   If the number of the dribbling bits is less than 8             If CLSN becomes asserted during the reception of a
   and there is a CRC error, then there is also a                 packet, this reception is immediately terminated. De-
   Framing error (FRAM = 1).                                      pending on the timing of COLLISION DETECTION, one
   If the number of the dribbling bits = 0, then there is         of the following will occur. A collision that occurs within 6
   no Framing error. There may or may not be a CRC                byte times of the detection of the SFD (4.8 µs) will result
   error.                                                         in the packet being rejected because of an address mis-
                                                                  match; the Receive FIFO write pointer will be reset. A
Interframe Spacing (IFS)                                          collision that occurs within 64 byte times (51.2 µs) will
The C-LANCE implements the two-part deferral algo-                result in the packet being rejected since it is a runt pack-
rithm following both receive and transmit activity, as            et. A collision that occurs after 64 byte times (late colli-
specified as an option in the IEEE 802.3 Standard (ISO/           sion) will result in a truncated packet being written to the
IEC 8802-3 1990). With two-part deferral, the interframe          memory buffer with the CRC error bit most likely being
spacing, which begins immediately after the negation of           set in the Status Word of the Receive Ring. Late collision
RENA, is divided into two parts, IFS1 and IFS2. If RENA           error is not reported in receive mode.
is asserted during IFS1, the interframe spacing counter           Transmit Based Collision
is continually reset until RENA is deasserted (any pend-
ing transmissions will defer to the incoming receive traf-        When a transmission attempt has been terminated due
fic and the incoming frame may be received by the                 to the assertion of CLSN, (a collision that occurs within
C-LANCE). Once the interframe spacing counter                     64 byte times), the C-LANCE will attempt to retry trans-
reaches IFS2, the counter proceeds, regardless of the             mission 15 more times. The scheduling of the
state of RENA. When IFS2 expires, the C-LANCE may                 retransmissions is determined by a controlled random-
begin transmitting a frame if there is one pending.               ized process called “truncated binary exponential back-
                                                                  off.” Upon the negation of the COLLISION JAM interval,
In the C-LANCE, IFS1 is 6.0 µs and IFS2 is 3.6 µs, mak-           the C-LANCE calculates a delay before retransmitting.
ing the minimum possible interframe spacing 9.6 µs.               The delay is an integral multiple of the SLOT TIME. The
The 9.6 µs minimum interframe spacing complies with               SLOT TIME is 512 bit times. The number of SLOT
IEEE 802.3 specifications.                                        TIMES to delay before the nth retransmission is chosen
                                                                  as a uniformly distributed random integer in the range:
Following each frame transmission, the C-LANCE                    0≤ r ≤ 2k where k = min (n, 10).
blinds itself from any receive activity for the first 4.1 µs of
the interframe spacing. The C-LANCE begins looking                When the Modified Backoff Algorithm is enabled
for the 011 start frame delimiter pattern after 800ns (8 bit      (EMBA), the backoff time may be longer than the mini-
times) of preamble has passed. Hence, if RENA is as-              mum time specified above. Specifically, the backoff
serted during the first 4.1 µs of the interframe spacing,         count will be suspended whenever a carrier is detected
there must be at least 8 bits of preamble left following          on the network. The backoff count will resume when the
the end of the 4.1 µs window in order for the frame to be         carrier drops. This behavior has the effect of making the
received correctly.                                               backoff interval equal to the SUM of an integral number
                                                                  of SLOT TIMES plus the total duration of the carrier on
Following each frame reception, the C-LANCE blinds it-            the network during the backoff interval.
self from any receive activity for the first 0.5 µs of the in-
terframe spacing.                                                 If all 16 attempts fail, the C-LANCE sets the RTRY bit in
                                                                  the current Transmit Message Descriptor 3, TMD3, in
Collision Detection and Collision JAM                             memory, gives up ownership (sets the own bit to zero)
Collisions are detected by monitoring the CLSN pin. If            for this packet, and processes the next packet in trans-
CLSN becomes asserted during a frame transmission,                mit ring for transmission. If there is a late collision (colli-
TENA will remain asserted for at least 32 (but not more           sion occurring after 64 byte times), the C-LANCE will not
than 40) additional bit times (including CLSN synchroni-          attempt to transmit this packet again; it will terminate the
zation). This additional transmission after collision is          transmission, note the LCOL error in TMD3, and trans-
referred to as COLLISION JAM. If collision occurs                 mit the next packet in the ring.
during the transmission of the preamble, the C-LANCE



1-36                                                        Am79C90
                                                 PRELIMINARY                                                 AMD

Collision—Microcode Interaction                                  RECEPTION – MODE <02> LOOP = 0. The
                                                                 C-LANCE performs a check on the input bit stream
The microprogram uses the time provided by COLLI-
                                                                 from the first bit following the SFD to the last bit in
SION JAM, INTERPACKET DELAY, and the backoff
                                                                 the frame. The C-LANCE continually samples the
interval to restore the address and byte counts internally
                                                                 state of the CRC check on framed byte bounda-
and starts loading the Transmit FIFO in anticipation of
                                                                 ries, and, when the incoming bit stream stops, the
retransmission. It is important that C-LANCE be ready
                                                                 last sample determines the state of the CRC error.
to transmit when the backoff interval elapses to utilize
                                                                 Framing error (FRAM) is not reported if there is no
the channel properly.
                                                                 CRC error.
If, during the backoff interval, RENA and CLSN are               LOOPBACK – MODE <02> LOOP =1, MODE
never asserted (no wire activity), the C-LANCE does not          <03> DTRC = 0. The C-LANCE generates and
re-poll the OWN bit and does not re-read the buffer ad-          appends the CRC value to the outgoing bit stream
dress and byte count in the transmit descriptor before           as in Transmission but does not perform the CRC
reloading the transmit data and retransmitting the trans-        check of the incoming bit stream.
mit packet. However, if RENA or CLSN are asserted
                                                                 LOOPBACK – MODE <02> LOOP = 1 MODE
during the backoff interval, the C-LANCE must re-poll
                                                                 <03> DTRC = 1. C-LANCE performs the CRC
the OWN bit and re-read the buffer address and byte
                                                                 check on the incoming bit stream as in Reception,
count in the transmit descriptor before starting the DMA
                                                                 but does not generate or append the CRC value to
access of the transmit buffer and performing the retry.
                                                                 the outgoing bit stream during transmission.
Note that the re-polling of the transmit descriptor could
be preceeded by receive DMA operations if an incoming        Loopback
packet arrives during the backoff interval and an ad-
                                                             The normal operation of the C-LANCE is as a half-
dress match is detected or when the C-LANCE is in pro-
                                                             duplex device. However, to provide an on-line opera-
miscuous mode.
                                                             tional test of the C-LANCE, a pseudo-full duplex mode is
Time Domain Reflectometry                                    provided. In this mode simultaneous transmission and
                                                             reception of a loopback packet are enabled with the fol-
The C-LANCE contains a time domain reflectometry
                                                             lowing constraints:
counter. The TDR counter is ten bits wide. It counts at a
10 MHz rate. It is cleared by the microprogram and               The packet length must be no longer than
counts upon the assertion of RENA during transmission.           32 bytes, and no shorter than 8 bytes, exclusive of
Counting ceases if CLSN becomes true, or RENA goes               the CRC.
inactive. The counter does not wrap around. Once all             Serial transmission does not begin until the Trans-
ONEs are reached in the counter, the counter value is            mit FIFO contains the entire output packet.
held until cleared. The value in the TDR is written into
memory following the transmission of the packet. TDR is          Moving the input packet from the Receive FIFO to
used to determine the location of suspected cable faults.        the memory does not begin until the serial input bit
                                                                 stream terminates.
Heartbeat                                                        CRC may be generated and appended to the out-
During the interpacket gap time following the negation of        put serial bit stream or may be checked on the in-
TENA, the CLSN input is asserted by some transceivers            put serial bit stream. CRC may not be used for
as a self-test. If the CLSN input is not asserted within         both transmission and reception simultaneously.
4 µs following the completion of transmission, then the          In internal loopback, the packets should be ad-
C-LANCE will set the CERR bit in CSR0. CERR error                dressed to the node itself.
will not cause an interrupt to occur (INTR = 0).
                                                                 In external loopback, multicast addressing can be
Cyclic Redundancy Check (CRC)                                    used only when DTCR = 1 is in the mode register.
                                                                 In this case, the user needs to append the CRC
The C-LANCE utilizes the 32-bit CRC function as de-              bytes.
scribed in the IEEE 802.3 standard section 3.2.8 to gen-
erate the Frame Check Sequence (FCS) field. The              Loopback is controlled by bits <06, 03, 02> INTL, DTCR,
C-LANCE requirements for the CRC logic are the               and LOOP of the MODE register.
following:
   TRANSMISSION – MODE <02> LOOP = 0, MODE
   <03> DTCR = 0. The C-LANCE calculates the
   CRC from the first bit following the SFD to the last
   bit of the data field. The CRC value inverted is ap-
   pended onto the transmission in one unbroken bit
   stream.

                                                       Am79C90                                                     1-37
       AMD                                     PRELIMINARY

Serial Transmission                                        Serial Reception
Serial transmission consists of sending an unbroken bit    Serial reception consists of receiving an unbroken bit
stream from the TX output pin consisting of:               stream on the RX input pin consisting of:
   Preamble/SFD: 56 alternating ONES and ZEROES                Preamble/SFD: Two ONES occurring a minimum
   terminating with the SFD byte (10101011).                   of 8 bit times after the assertion of RENA.
   Data: The serialized bit stream from the Transmit           Destination Address: The 48 bits (6 bytes) follow-
   FIFO Shifted out with LSB first.                            ing the SFD.
   CRC: The inverted 32-bit polynomial calculated              Data: The serial bit stream following the Destina-
   from the data, address, and type field. CRC is not          tion Address. The last 4 complete bytes of data are
   transmitted if:                                             the CRC. The Destination Address and the data
                                                               are framed into bytes and enter the Receive FIFO.
   — Transmission of the data field is truncated for           Source Address and Length field are part of the
     any reason.
                                                               data which are transparent to the C-LANCE.
   — CLSN becomes asserted any time during
     transmission.                                         Reception is indicated at the input pin by the assertion of
   — MODE <03> DTCR = 1 in a normal or loopback            RENA and the presence of clock on RCLK while TENA
     transmission mode, and ADD_FCS=0 in the               is inactive. The C-LANCE does not sample the received
     transmit descriptor.                                  data until about 800 ns after RENA goes high.
The Transmission is indicated at the output pin by the
assertion of TENA with the first bit of the preamble and
the negation of TENA after the last transmitted bit.
The C-LANCE starts transmitting the preamble when
the following are satisfied:
   There is at least one byte of data to be transmitted
   in the Transmit FIFO.
   The interpacket delay has elapsed.
   The backoff interval has elapsed, if doing a
   retransmission.




1-38                                                 Am79C90
                                                        PRELIMINARY                                                                       AMD

ABSOLUTE MAXIMUM RATINGS                                                  OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C                 Commercial (C) Devices
Ambient Temperature with                                                  Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to +70°C
Power Applied . . . . . . . . . . . . . . . . . –25°C to +125°C           Supply Voltage (VDD) . . . . . . . . . . +4.75 V to +5.25 V
Supply Voltages to Ground Potential                                       VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V
Continuous . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
                                                                          Operating ranges define those limits between which the func-
Stresses above those listed under Absolute Maximum Rat-                   tionality of the device is guaranteed.
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.


DC CHARACTERISTICS over operating ranges unless otherwise specified
   Parameter                                                                                                     Commercial
    Symbol          Parameter Description                             Test Conditions                     Min       Typ     Max                Unit
        VIL         Input LOW Voltage                                                                                              0.8           V
        VIH         Input HIGH Voltage                                                                      2                                    V
       VOL          Output LOW Voltage                                IOL = 3.2 mA                                                 0.5           V
       VOH          Output HIGH Voltage                               IOH = –0.4 mA                       2.4                                    V
        IIL         Input Leakage                                     VIN = 0.4 V to VCC                                           ±10          µA
       IDD*         Power Supply Current                                                                                           50           mA
*IDD is measured while running a functional pattern with spec. value IOH and IOL load applied.


CAPACITANCE** (TA = 25°C; VDD = 0)
   Parameter
    Symbol          Parameter Description                             Test Conditions                     Min         Typ         Max          Unit
        CIN         Input Pin Capacitance                             f = 1 MHz                                                    10           pF
       COUT         Output Pin Capacitance                            f = 1 MHz                                                    15           pF
        CIO         I/O Pin Capacitance                               f = 1 MHz                                                    20           pF
**Parameters are not tested.




                                                               Am79C90                                                                            1-39
       AMD                                       PRELIMINARY

SWITCHING CHARACTERISTICS
        Parameter                                               Test
 No.     Symbol      Parameter Description                    Conditions      Min       Typ     Max        Unit
  1          tTCT    TCLK Period                                              99                 101       ns
  2          tTCL    TCLK LOW Time                                            45                 55        ns
  3          tTCH    TCLK HIGH Time                                           45                 55        ns
  4          tTCR    Rise Time of TCLK                         (Note 3)                           8        ns
  5          tTCF    Fall Time of TCLK                         (Note 3)                           8        ns
  6          tTEP    TENA Propagation Delay After the                                            60        ns
                     Rising Edge of TCLK
  7          tTEH    TENA Hold Time After the Rising                           5                           ns
                     Edge of TCLK
  8          tTDP    TX Data Propagation Delay After the                                         60        ns
                     Rising Edge of TCLK
  9          tTDH    TX Data Hold Time After the Rising                        5                           ns
                     Edge of TCLK
  10         tRCT    RCLK Period                               (Note 3)       85                 118       ns
  11         tRCH    RCLK HIGH Time                            (Note 2)       38                           ns
  12         tRCL    RCLK LOW Time                             (Note 2)       38                           ns
  13         tRCR    Rise Time of RCLK                         (Note 3)                           8        ns
  14         tRCF    Fall Time of RCLK                         (Note 3)                           8        ns
  15         tRDR    RX Data Rise Time                         (Note 3)                           8        ns
  16         tRDF    RX Data Fall Time                         (Note 3)                           8        ns
  17         tRDH    RX Data Hold Time (RCLK to RX             (Note 2)        5                           ns
                     Data Change)
  18         tRDS    RX Data Setup Time (RX Data Stable        (Note 2)       35                           ns
                     to the Rising Edge of RCLK)
  19         tDPL    RENA LOW Time                                         1tTCT + 20                      ns
  20         tCPH    CLSN HIGH Time                                           80                           ns
  21         tDOFF   Bus Master Driver Disable After Rising                                      50        ns
                     Edge of HOLD
  22         tDON    Bus Master Driver Enable After Falling                   50              2tTCT + 50   ns
                     Edge of HLDA
  23         tHHA    Delay to Falling Edge of HLDA from                        0                           ns
                     Falling Edge of HOLD (Bus Master)
  24         tRW     RESET Pulse Width LOW                     (Note 7)      2tTCT                         ns
  25     tCYCLE      Read/Write, Address/Data Cycle Time       (Note 1)      6tTCT                         ns
  26         tXAS    Address Setup Time to the Falling                        75                           ns
                     Edge of ALE
  27         tXAH    Address Hold Time After the Rising                       35                           ns
                     Edge of DAS
  28          tAS    Address Setup Time to the Falling                        75                           ns
                     Edge of ALE
  29          tAH    Address Hold Time After the Falling                      35                           ns
                     Edge of ALE
  30         tRDAS   Data Setup Time to the Rising Edge                       40                           ns
                     of DAS (Bus Master Read)




1-40                                                      Am79C90
                                                  PRELIMINARY                                         AMD

SWITCHING CHARACTERISTICS (continued)
      Parameter                                                   Test
No.    Symbol Parameter Description                             Conditions       Min    Typ     Max     Unit
31      tRDAH   Data Hold Time After the Rising Edge                              0                     ns
                of DAS (Bus Master Read)
32      tDDAS   Data Setup Time to the Falling Edge                              10                     ns
                of DAS (Bus Master Write)
33      tWDS    Data Setup Time to the Rising Edge                               200                    ns
                of DAS (Bus Master Write)
34      tWDH    Data Hold Time After the Rising Edge                             35                     ns
                of DAS (Bus Master Write)
35      tSD01   Data Driver Delay After the Falling          (CSR0, CSR3, RAP)         4tTCT            ns
                Edge of DAS (Bus Slave Read)                      (Note 6)
36      tSD02   Data Driver Delay After the Falling              (CSR1, 2)             12tTCT           ns
                Edge of DAS (Bus Slave Read)                      (Note 6)
37      tSRDH   Data Hold Time After the Rising                                   0             55      ns
                Edge of DAS (Bus Slave Read)
38      tSWDH   Data Hold Time After the Rising                                   0                     ns
                Edge of DAS (Bus Slave Write)
39      tSWDS   Data Setup Time to the Falling Edge                               0                     ns
                of DAS (Bus Slave Write)
40      tALEW   ALE Width HIGH                                                   120                    ns
41      tDALE   Delay from Rising Edge of DAS to the                             70                     ns
                Rising Edge of ALE
42      tDSW    DAS Width LOW                                                    200                    ns
43      tADAS   Delay from the Falling Edge of ALE                               80             130     ns
                to the Falling Edge of DAS
44      tRIDF   Delay from the Rising of DALO to the                             15                     ns
                Falling Edge of DAS (Bus Master Read)
45      tRDYS   Delay from the Falling Edge of READY                             65             250     ns
                to the Rising Edge of DAS
46      tROIF   Delay from the Rising Edge of DALO to                            15                     ns
                the Falling Edge of DALI (Bus Master Read)
47       tRIS   DALI Setup Time to the Rising Edge of                            135                    ns
                DAS (Bus Master)
48      tRIH    DALI Hold Time After the Rising Edge of                           0                     ns
                DAS (Bus Master Read)
49      tRIOF   Delay from the Rising Edge of DALI to the                        55                     ns
                Falling Edge of DALO (Bus Master Read)
50       tOS    DALO and READ Setup Time to the Falling                          110                    ns
                Edge of ALE (Bus Master Write and Read)
51      tROH    DALO Hold Time After the Falling Edge of                         35                     ns
                ALE (Bus Master Read)
52      tWDSI   Delay from the Rising Edge of DAS to the                         35                     ns
                Rising Edge of DALO (Bus Master Write)
53      tCSH    CS Hold Time After the Rising Edge of DAS                         0                     ns
                (Bus Slave)
54      tCSS    CS Setup Time to the Falling Edge of DAS                          0                     ns
                (Bus Slave)




                                                       Am79C90                                              1-41
       AMD                                          PRELIMINARY

SWITCHING CHARACTERISTICS (continued)
       Parameter                                                        Test
 No.    Symbol Parameter Description                                  Conditions           Min       Typ        Max        Unit
 55       tSAH     ADR Hold Time After the Rising Edge of
                   DAS (Bus Slave)                                                          0                               ns
 56       tSAS     ADR Setup Time to the Falling Edge of
                   DAS (Bus Slave)                                                          0                               ns
 57      tARYD     Delay from the Falling Edge of ALE to the                                                     80         ns
                   Falling Edge of READY to insure a
                   Minimum Bus Cycle Time (600 ns)                      (Note 5)
 58      tSRDS     Data Setup Time to the Falling Edge of
                   READY (Bus Slave Read)                                                  75                               ns
 59      tRDYH     READY Hold Time After the Rising Edge of
                   DAS (Bus Master)                                                         0                               ns
 60      tSR01     READY Driver Turn On After the Falling         (CSR0, CSR3, RAP)                  6tTCT                  ns
                   Edge of DAS (Bus Slave)                           (Notes 4, 6)
 61      tSR02     READY Driver Turn On After the Falling              (CSR1, 2)                    14tTCT                  ns
                   Edge of DAS (Bus Slave)                              (Note 6)
 62      tSRYH     READY Hold Time After the Rising Edge
                   of DAS (Bus Slave)                                                       0                    35         ns
 63       tSRH     READ Hold Time After the Rising Edge of
                   DAS (Bus Slave)                                                          0                               ns
 64       tSRS     READ Setup Time to the Falling Edge of
                   DAS (Bus Slave)                                                          0                               ns
 65       tCHL     TCLK Rising Edge to HOLD LOW or High                                                          95         ns
                   Delay
 66       tCAV     TCLK to Address Valid                                                                         100        ns
 67       tCCA     TCLK Rising Edge to Control Signals Active                                                    75         ns
 68      tCALE     TCLK Falling Edge to ALE LOW                                                                  90         ns
 69       tCDL     TCLK Falling Edge to DAS Falling Edge                                                         90         ns
 70       tRCS     Ready Setup Time to TCLK Falling Edge                (Note 5)            0                               ns
 71       tCDH     TCLK Rising Edge to DAS HIGH                                                                  90         ns
 72       tHCS     HLDA Setup to TCLK Falling Edge                                          0                               ns
 73      tRENH     RENA Hold Time After the Rising Edge of                                  0                               ns
                   RCLK
 74       tCSR     CS recovery time between deassertion                                  tTCT+60                            ns
                   of CS or HOLD and assertion of CS
Notes:
1. Not shown in the timing diagrams, specifies the minimum bus cycle for a single DMA data transfer. Tested by functional data
   pattern.
2. Applicable parameters associated with Receive circuit are tested at tRCT (RCLK Period) = 100 ns, tTCT = 100 ns
   (TCLK Period).
3. Not tested.
4. CSR0 write access time (tSR01) when STOP bit is being set can be as long as 12tTCT.
5. It is guaranteed that no wait states will be added by the C-LANCE if either parameter #57 or #70 is met.
6. Parameter is for design reference only.
7. Reset must be asserted for at least two rising and two falling edges of TCLK for the device to be reset. If reset is deasserted
   before TCLK starts, the device behavior is undefined.




1-42                                                       Am79C90
              PRELIMINARY                                   AMD




                                IOL




                                                    1.5 V


     100 pF




                                IOH



                                                17881B-37


        A. Normal and Three-State Outputs




                                IOL




                                            1.5 V


     100 pF


                                                17881B-38


B. Open-Drain Outputs (INTR, HOLD/BUSRQ, READY)




                   Am79C90                                        1-43
       AMD                     PRELIMINARY

KEY TO SWITCHING WAVEFORMS

                        WAVEFORM         INPUTS              OUTPUTS


                                         Must Be             Will Be
                                         Steady              Steady


                                         May                 Will Be
                                         Change              Changing
                                         from H to L         from H to L


                                         May                 Will Be
                                         Change              Changing
                                         from L to H         from L to H


                                         Don’t Care,         Changing,
                                         Any Change          State
                                         Permitted           Unknown


                                         Does Not            Center
                                         Apply               Line is High-
                                                             Impedance
                                                             “Off” State
                                                                       KS000010



SWITCHING WAVEFORMS (Note 1)


                 CLSN                     20

                         Serial Link Timing (Collision)                     17881B-39



                                                               10
                                                       12              11

       RCLK

                               18               16      13                         14

         RX
                                                15
                                    17

       RENA

                                                                       73               19

                                                                                             17881B-40
                          Serial Link Timing (Receive)




1-44                                 Am79C90
                                                 PRELIMINARY                                                     AMD

SWITCHING WAVEFORMS
                                                                                1
                                                                           3            2

  TCLK
                           8                       9            4                       5

    TX


 TENA
                                                                                                    7
                          6
                                                                                                    *
 RENA

                                                                                                               17881B-41




*During transmit, RENA input must be asserted (HIGH) and remain active-HIGH before TENA goes inactive (LOW). If RENA is
deasserted before TENA is deasserted, LCAR will be reported in TMD3 after the transmission is completed by the C-LANCE.

                                            Serial Link Timing (Transmit)




  HOLD
                                                                                                        O.D.
                                                                                                        21

  HLDA
                          23
                                     22
    Bus
 Master                                                               Drivers Enabled
 Drivers

                                                                        24
 RESET



                                                                                                               17881B-42
Note:
1. RESET is an asynchronous input to the C-LANCE and is not part of the Bus Acquisition timing. When RESET is asserted, the
   C-LANCE becomes a Bus Slave.

                                                Bus Acquisition Timing




                                                        Am79C90                                                        1-45
       AMD                                         PRELIMINARY

SWITCHING WAVEFORMS


DAL0–DAL15                                                                              Read Data


                                              64         35    36                  58               37
                                                     See
                                                     Note 1
                                                              60    61                     63
             DAS




         READ


       READY                                                                               62
  (Output from
    C-LANCE)
                                                                                                         O.D
                                  74



         HOLD



             CS

                                                        54                                          53


          ADR

                                              56                                          55


                                                                                                          17881B-45
Note:
1. There are two types of delays which depend on which internal register is accessed.
   Type 1 refers to access of CSR0 CSR3 and RAP.
   Type 2 refers to access of CSR1 and CSR2 which are longer than Type 1 delay.


                                                Bus Slave Read Timing




1-46                                                    Am79C90
                            PRELIMINARY                                      AMD

SWITCHING WAVEFORMS


 DAL0–DAL15                                      Write Data


                                       39                          38

                               64                                  63
                                       60   61                62
        DAS




      Read

     READY
 (Output from
   C-LANCE)
                                                                             O.D
                      74



       HOLD
                                       54                               53

          CS




        ADR

                               56                             55

                                                                             17881B-46




                           Bus Slave Write Timing




                                 Am79C90                                           1-47
1-48
                                   1st DMA                                            TWAIT                             8th DMA                                   TWAIT
                                                                                                                                                                                                                                          AMD
                                   T0          T1          T2         T3         T4           T5         T6         T1            T2          T3             T4           T5         T6

                              0          100        200         300        400         500         600        700         100           200            300         400         500         600

               TCLK


                                                                                                                                                      69           70                        65
               HOLD                 67                          68                      70                                             68                                                                 O.D.
                        65                                                                                                                                                                           21
                              72                    66
                                                                                                                                                                                                                  SWITCHING WAVEFORMS

                                                                                                                                                                               71
               HLDA
                                        22           26                                                   27                     26                                                        27
                         23

            A16–A23                                                         Address, BM0, BM1                                                      Address, BM0, BM1
           BM0, BM1
                                                                                                              41
                ALE                             40
                                                                                                                            40

                                                                                                                                                                    42
                 DAS
Am79C90

                                                                                                         59                                      43                                  59
                                                                                                                                                                                                                                        PRELIMINARY

              READY
                                                          28                                 45                                                                      45
                                                                                                                                  28              57
                                                                           29                                      31                                 29                                        31
                                                                                              30                                                                        30
          DAL0–DAL15
               (Read)                                    Address                             Data In                            Address                             Data In

                                                                                                                                            51
                                                         50                                                                       50
                DALO
               (Read)
                                                                                         47                         49                             44
                                                                                                         48                                                         47
                 DALI                                                                                                                                                                 48
               (Read)                                                                                                                                 46


                READ
               (Read)

                                                                                                                                                                                                      17881B-43
                                                                                 Bus Master Read Timing (Burst DMA)
                                    1st DMA                                               TWAIT                          8th DMA                                  TWAIT

                                    T0         T1             T2          T3         T4           T5         T6          T1          T2          T3          T4           T5          T6

                               0         100         200            300        400         500         600         700        100          200         300         400         500         600

                 TCLK


                                                                                            70                                                        69           70                       65
                HOLD                     67                        68                                                                     68                                                            O.D.
                    65                                                                                                                                                                           21
                               72
                                                                                                                                                                               71
                                                                                                                                                                                                               SWITCHING WAVEFORMS

                                                    66
                HLDA
                          23         22                  26                                                   27                     26

             A16–A23                                                            Address, BM0, BM1                                                     Address, BM0, BM1
            BM0, BM1
                                                                                                                  41
                  ALE                           40                                                                              40

                                                                                                                                                                   42
                 DAS
Am79C90

                                                                                                             59                                  43                                  59
               READY
                                                                                                                                                                                                                                     PRELIMINARY

                                                          28                                     45                                                                 45
                                                                                                                                     28           57
                                                                               29
                                                                                                                  34                 29                       32
          DAL0–DAL15
               (Write)                                    Address                                Data Out                           Address                         Data Out

                                                                                                 33                                                                 33                     52
                                                          50
                 DALO
                (Write)

                 DALI
                (Write)


                 READ
                (Write)

                                                                                                                                                                                                  17881B-44                            AMD
                                                                                     Bus Master Write Timing (Burst DMA)
1-49
       APPENDIX A


Hash Filter Generation Programs for
Logical Addressing

80x86 computer program example to generate the hash filter, for multicast addressing in the C-LANCE.
6                         ;          SUBROUTINE TO SET A BIT IN THE HASH FILTER FROM A
7                         ;          GIVEN ETHERNET LOGICAL ADDRESS
8                         ;          ON ENTRY Sl POINTS TO THE LOGICAL ADDRESS WITH LSB FIRST
9                         ;                     Dl POINTS TO THE HASH FILTER WITH LSB FIRST
10                        ;          ON RETURN Sl POINTS TO THE BYTE AFTER THE LOGICAL ADDRESS
11                        ;                ALL OTHER REGISTERS ARE UNMODIFIED
12                        ;
13                                   PUBLIC SETHASH
14                                   ASSUME CS:CSE61
15                        ;
16     = 1DB6             POLYL      EOU       1DB6H          ;CRC POLYNOMINAL TERMS
17     = 04C1             POLYH      EQU       04C1H
18                        ;
19     0000               CSE61      SEGMENT PUBLIC ‘CODE’
20                        ;
21     0000               SETHASH PROC         NEAR
22     0000 50                       PUSH      AX             ;SAVE ALL REGISTERS
23     0001 53                       PUSH      BX
24     0002 51                       PUSH      CX
25     0003 52                       PUSH      DX
26     0004 55                       PUSH      BP
27                        ;
28     0005 B8 FFFF                  MOV       AX,0FFFFH      ;AX,DX =CRC ACCUMULATOR
29     0008 BA FFFF                  MOV       DX,0FFFFH      ;PRESET CRC ACCUMULATOR TO ALL 1’S
30     000B B5 03                    MOV       CH,3           ;CH =WORD COUNTER
31                        ;
32     000D 8B 2C         SETH10:    MOV       BP,[S1]        ;GET A WORD OF ADDRESS
33     000F 83 C6 02                 ADD       S1,2           ;POINT TO NEXT ADDRESS
34     0012 B1 10                    MOV       CL,16          ;CL=BIT COUNTER
35                        ;
36     0014 8B DA         SETH20:    MOV       BX,DX          ;GET HIGH WORD OF CRC
37     0016 D1 C3                    ROL       BX,1           ;PUT CRC31 TO LSB
38     0018 33 DD                    XOR       BX,BP          ;COMBINE CRC31 WITH INCOMING BIT
39     001A D1 E0                    SAL       AX,1           ;LEFT SHIFT CRC ACCUMULATOR
40     001C D1 D2                    RCL       DX,1
41     001E 81 E3 0001               AND       BX,0001H       ;BX=CONTROL BIT
42     0022 74 07                    JZ        SETH30         ;DO NOT XOR IF CONTROL BIT = 0
43                        ;
44                        ;          PERFORM XOR OPERATION WHEN CONTROL BIT= 1


1-50                                                Am79C90
                                                                                                    AMD

45                        ;
46    0024 35 1D 86                  XOR       AX,POLYL
47    0027 81 F2 04C1                XOR       DX,POLYH
48                        ;
49    002B 0B C3          SETH30:    OR        AX,BX          ;PUT CONTROL BIT IN CRC0
50    002D D1 CD                     ROR       BP,1           ;ROTATE ADDRESS WORD
51    002F FE C9                     DEC       CL             ;DECREMENT BIT COUNTER
52    0031 75 E1                     JNZ       SETH20
53    0033 FE CD                     DEC       CH             ;DECREMENT WORD COUNTER
54    0035 75 D6                     JNZ       SETH10
55                        ;          FORMATION OF CRC COMPLETE, AL CONTAINS THE REVERSED HASH
56                        ;          CODE
58    0037 B9 000A                   MOV       CX,10
49    003A D0 E0          SETH40:    SAL       AL,1           ;REVERSE THE ORDER OF BITS IN AL
60    003C D0 DC                     RCR       AH,1           ;AND PUT IT IN AH
61    003E E2 FA                     LOOP      SETH40
62
63                        ;          AH NOW CONTAINS THE HASH CODE
64                        ;
65    0040 8A DC                     MOV       BL,AH          ;BL = HASH CODE, BH IS ALREADY ZERO
66    0042 B1 03                     MOV       CL,3           ;DIVIDE HASH CODE BY 8
67    0044 D2 EB                     SHR       BL,CL          ;TO GET TO THE CORRECT BYTE
68    0046 B0 01                     MOV       AL,01H         ;PRESET FILTER BIT
69    0048 80 E45 07                 AND       AH,7H          ;EXTRACT BIT COUNT
70    004B 8A CC                     MOV       CL,AH
71    004D D2 E0                     SHL       AL,CL          ;SHIFT BIT TO CORRECT POSITION
72    004F 08 01                     OR        [Dl + BX],AL   ;SET IN HASH FILTER
73    0051 5D                        POP       BP
74    0052 5A                        POP       DX
75    0053 59                        POP       CX
76    0054 5B                        POP       BX
77    0055 58                        POP       AX
78    0056 C3                        RET
79                        ;
80    0057                SETHASH ENDP
81                        ;
82    0057                CSEG1      ENDS
83                        ;
84                                   END


Program example in BASIC to generate the hash filter, for multicast addressing, in the C-LANCE.
100   REM
110   REM PROGRAM TO GENERATE A HASH NUMBER GIVEN AN ETHERNET ADDRESS
120   REM
130   DEFINT A–Z
140   DIM A(47): REM ETHERNET ADDRESS. 48 BITS.
150   DIM A$(6): REM INPUT FROM KEYBOARD
160   DIM C(32): REM CRC REGISTER–32 BITS

                                                    Am79C90                                               1-51
       AMD

170    PRINT “ENTER ETHERNET ADDRESS AS 6 HEXADECIMAL NUMBERS SEPARATED ”
180    PRINT “BY BLANKS. EACH NUMBER REPRESENTS ONE BYTE. THE LEAST ”
190    PRINT “SIGNIFICANT BIT OF THE FIRST BYTE IS THE FIRST BIT TRANSMITTED.”
200    PRINT “”
210    PRINT “ENTER ETHERNET ADDRESS”;
220    INPUT A$(0), A$(1), A$(2), A$(3), A$(4), A$(5)
240    REM
250    REM UNPACK ETHERNET ADDRESS INTO ADDRESS ARRAY
260    REM
270    M=0
280    FOR I = 0 TO 47: A(I) = 0: NEXT I
290    FOR I = 0 TO 5
300    IF LEN(A$(I)) = 1 THEN A$(I) = “0” + A$(I)
310    A$(I) = UCASE$(A$(I))
320    FOR N = 2 TO 1 STEP –1
330    Y$ = MID$(A$(I), N, 1)
340    IF Y$ = “0” THEN 510
350    IF Y$ = “1” THEN A(M) = 1: GOTO 510
360    IF Y$ = “2” THEN A(M + 1) = 1: GOTO 510
370    IF Y$ = “3” THEN A(M + 1) = 1: A(M) = 1: GOTO 510
380    IF Y$ = “4” THEN A(M + 2) = 1: GOTO 510
390    IF Y$ = “5” THEN A(M + 2) = 1: A(M) = 1: GOTO 510
400    IF Y$ = “6” THEN A(M + 2) = 1: A(M + 1) = 1: GOTO 510
410    IF Y$ = “7” THEN A(M + 2) = 1: A(M + 1) = 1: A(M) = 1: GOTO 510
420    A(M + 3) = 1
430    IF Y$ = “8” THEN 510
440    IF Y$ = “9” THEN A(M) = 1: GOTO 510
450    IF Y$ = “A” THEN A(M + 1) = 1: GOTO 510
460    IF Y$ = “B” THEN A(M + 1) = 1: A(M) = 1: GOTO 510
470    IF Y$ = “C” THEN A(M + 2) = 1: GOTO 510
480    IF Y$ = “D” THEN A(M + 2) = 1: A(M) = 1: GOTO 510
490    IF Y$ = “E” THEN A(M + 2) = 1: A(M + 1) = 1: GOTO 510
500    IF Y$ = “F” THEN A(M + 2) = 1: A(M + 1) = 1: A(M) = 1
510    M=M+4
520    NEXT N
530    NEXT I
540    REM
550    REM PERFORM CRC ALGORITHM ON ARRAY A(0–47)
560    REM
570    FOR I = 0 TO 31: C(I) = 1: NEXT I
580    FOR N = 0 TO 47
590    REM SHIFT CRC REGISTER BY 1
600    FOR I = 32 TO 1 STEP –1: C(l) = C(I–1): NEXT I
610    C(0) = 0
620    T = C(32) XOR A(N): REM T = CONTROL BIT
630    IF T = 0 THEN 700: REM JUMP IF CONTROL BIT=0

1-52                                                    Am79C90
                                                                                             AMD

640   C(1) = C(1) XOR 1: C(2) = C(2) XOR 1: C(4) = C(4) XOR 1
650   C(5) = C(5) XOR 1: C(7) = C(7) XOR 1: C(8) = C(8) XOR 1
660   C(10) = C(10) XOR 1: C(11) = C(11) XOR 1: C(12) = C(12) XOR 1
670   C(16) = C(16) XOR 1: C(22) = C(22) XOR 1: C(23) = C(23) XOR 1
680   C(26) = C(26) XOR 1
690   C(0) = 1
700   NEXT N
710   REM
720   REM CRC COMPUTATION COMPLETE, EXTRACT HASH NUMBER FROM C(0) TO C(5)
730   REM
740   HH=32*C(0)+16*C(1)+8*C(2)+4*C(3)+2*C(4)+C(5)
750   PRINT “THE HASH NUMBER FOR ”;
760   PRINT A$(0); “ ”; A$(1); “ ”; A$(2); “ ”; A$(3); “ ”; A$(4); “ ”; A$(5);
770   PRINT “IS”; HH
780   GOTO 210
Program example in C to generate the hash filter, for multicast addressing in the C-LANCE.



/************************************************************
* hash.c         Rev 0.1
* Generate a logical address filter value from a list of
* Ethernet multicast addresses.
*
* Input:
*     User is prompted to enter an Ethernet address in
*     Ethernet hex format: First octet entered is the first
*          octet to appear on the line. LSB of most
*          significant octet is the first bit on the line.
*          Octets are separated by blanks.
*     After results are printed, user is prompted for
*     another address.
*
*     (Note that the first octet transmitted is stored in
*     the C-LANCE as the least significant byte of the Physical
*     Address Register.)
* Output:
*     After each address is entered, the program prints the
*     hash code for the last address and the cumulative
*     address filter function. The filter function is
*     printed as 8 hex bytes, least significant byte first.
****************************************************************/
#include <stdio.h>
void updateCRC (int bit);
   int adr[6], /* Ethernet address */
       ladrf[8], /* Logical address filter */
       CRC[33], /* CRC register, 1 word/bit + extra control bit */
       poly[] = /* CRC polynomial. poly[n] = coefficient of
                   the x**n term of the CRC generator polynomial. */
          {1,1,1,0, 1,1,0,1,
           1,0,1,1, 1,0,0,0,
           1,0,0,0, 0,0,1,1,
           0,0,1,0, 0,0,0,0
       };
void main()

                                                               Am79C90                             1-53
        AMD

{
       int k,i, byte; /* temporary array indices */
       int hashcode; /* the object of this program */
       char buf[80]; /* holds input characters */



     for (i=0;i<8;i++) ladrf[i] = 0; /* clear log. adr. filter */


     printf (”Enter Ethernet addresses as 6 octets separated by blanks.\n”);
     printf (”Each octet is one or two hex characters. The first octet \n”);
     printf (”entered is the first octet to be transmitted. The LSB of \n”);
     printf (”the first octet is the first bit transmitted. After each \n”);
     printf (”address is entered, the Logical Address Filter contents \n”);
     printf (”are displayed, least significant byte first, with the \n”);
     printf (”appropriate bits set for all addresses entered so far.\n”);
     printf (”     To exit press the <Enter> key.\n\n”);
    while (1)
    {
    loop:
       printf (”\nEnter address: ”);

       /* If 1st character = CR, quit, otherwise read address. */
       gets (buf);
       if ( buf[0] == ’\0’) break;
       if (sscanf (buf, ”%x %x %x %x %x %x”,
             &adr[0], &adr[1], &adr[2],&adr[3],&adr[4],&adr[5])
           != 6)
           { printf
              (”Address must contain 6 octets separated by blanks.\n”);
              goto loop;
            }
       if ((adr[0] & 1) == 0)
            { printf (”First octet of multicast address ”);
              printf (”must be an odd number.\n”);
              goto loop;
            }

       /* Initialize CRC */
       for (i=0; i<32; i++) CRC[i] = 1;

       /* Process each bit of the address in the order of transmission.*/

       for (byte=0; byte<6; byte++)
         for (i=0; i<8; i++)
            updateCRC ((adr[byte] >> i) & 1);

       /* The hash code is the 6 least significant bits of the CRC
          in reverse order: CRC[0] = hash[5], CRC[1] = hash[4], etc.
       */

       hashcode = 0;
       for (i=0; i<6; i++) hashcode = (hashcode << 1) + CRC[i];

       /* Bits 3–5 of hashcode point to byte in address filter.
          Bits 0–2 point to bit within that byte. */

       byte = hashcode >> 3;


1-54                                                                Am79C90
                                                                        AMD

        ladrf[byte] |= (1 << (hashcode & 7));
        printf (”hashcode = %d (decimal) ladrf[0:63] = ”, hashcode);
        for (i=0; i<8; i++)
          printf (”%02X ”, ladrf[i]);
        printf (” (LSB first)\n”);
    }
}

void updateCRC (int bit)
{
  int j;

    /* shift CRC and control bit (CRC[32]) */
    for (j=32; j>0; j––) CRC[j] = CRC[j–1];
    CRC[0] = 0;

    /* If bit XOR (control bit) = 1, set CRC = CRC XOR polynomial. */
    if (bit ^ CRC[32])
       for (j=0; j<32; j++) CRC[j] ^= poly[j];
}




                                                             Am79C90          1-55
       AMD

Table A-1 “Mapping of Logical Address to Filter Mask”             Addresses in this table are shown in the standard Ether-
can be used to find a multicast address that maps into a          net format. The leftmost byte is the first byte to appear
particular address filter bit. For example, address BB 00         on the network with the least significant bit appearing
00 00 00 00 maps into bit 15. Therefore, any node that            first.
has bit 15 set in its logical address filter register will re-
ceive all packets addressed to BB 00 00 00 00 00. The
table also shows that bit 15 is located in bit 7 of byte 1 of
the Logical Address Filter Register.

                                Table A-1. Mapping of Logical Address to Filter Mask

 Byte        Bit     LAF                Destination               Byte   Bit      LAF               Destination
 Pos         Pos      Bit            Address Accepted             Pos    Pos       Bit           Address Accepted
   0          0       0        85   00     00   00     00    00    4       0       32     21   00    00    00   00   00
   0          1       1       A5    00     00   00     00    00    4       1       33     01   00    00    00   00   00
   0          2       2       E5    00     00   00     00    00    4       2       34     41   00    00    00   00   00
   0          3       3       C5    00     00   00     00    00    4       3       35     71   00    00    00   00   00
   0          4       4        45   00     00   00     00    00    4       4       36     E1   00    00    00   00   00
   0          5       5        65   00     00   00     00    00    4       5       37     C1   00    00    00   00   00
   0          6       6        25   00     00   00     00    00    4       6       38     81   00    00    00   00   00
   0          7       7        05   00     00   00     00    00    4       7       39     A1   00    00    00   00   00
   1          0       8       2B    00     00   00     00    00    5       0       40     8F   00    00    00   00   00
   1          1       9       0B    00     00   00     00    00    5       1       41     BF   00    00    00   00   00
   1          2       10      4B    00     00   00     00    00    5       2       42     EF   00    00    00   00   00
   1          3       11      6B    00     00   00     00    00    5       3       43     CF   00    00    00   00   00
   1          4       12      EB    00     00   00     00    00    5       4       44     4F   00    00    00   00   00
   1          5       13      CB    00     00   00     00    00    5       5       45     6F   00    00    00   00   00
   1          6       14      8B    00     00   00     00    00    5       6       46     2F   00    00    00   00   00
   1          7       15      BB    00     00   00     00    00    5       7       47     0F   00    00    00   00   00
   2          0       16      C7    00     00   00     00    00    6       0       48     63   00    00    00   00   00
   2          1       17      E7    00     00   00     00    00    6       1       49     43   00    00    00   00   00
   2          2       18      A7    00     00   00     00    00    6       2       50     03   00    00    00   00   00
   2          3       19       87   00     00   00     00    00    6       3       51     23   00    00    00   00   00
   2          4       20       07   00     00   00     00    00    6       4       52     A3   00    00    00   00   00
   2          5       21       27   00     00   00     00    00    6       5       53     83   00    00    00   00   00
   2          6       22       67   00     00   00     00    00    6       6       54     C3   00    00    00   00   00
   2          7       23       47   00     00   00     00    00    6       7       55     E3   00    00    00   00   00
   3          0       24       69   00     00   00     00    00    7       0       56     CD   00    00    00   00   00
   3          1       25       49   00     00   00     00    00    7       1       57     ED   00    00    00   00   00
   3          2       26       09   00     00   00     00    00    7       2       58     AD   00    00    00   00   00
   3          3       27       29   00     00   00     00    00    7       3       59     8D   00    00    00   00   00
   3          4       28      A9    00     00   00     00    00    7       4       60     0D   00    00    00   00   00
   3          5       29       89   00     00   00     00    00    7       5       61     2D   00    00    00   00   00
   3          6       30      C9    00     00   00     00    00    7       6       62     6D   00    00    00   00   00
   3          7       31      E9    00     00   00     00    00    7       7       63     4D   00    00    00   00   00




1-56                                                        Am79C90
     APPENDIX B


Comparison Between C-LANCE (Am79C90)
and LANCE (Am7990) Devices

OVERVIEW                                                The C-LANCE device is available in both 48-pin plastic
                                                        DIP and 68-pin PLCC packages. These packages are
The Am79C90 C-LANCE device is a pin-for-pin equiva-
                                                        socket compatible with the LANCE packages.
lent for the Am7990 LANCE device. Using an advanced
0.8-micron CMOS process, the C-LANCE device con-        This document provides a comparison of the C-LANCE
sumes less power than the LANCE device, which is im-    and LANCE devices. Table 1 provides a summary of the
plemented in an outdated NMOS process. In addition to   comparison between the two devices. The remainder of
the inherent advantages provided by the advanced        the document gives details on each item listed in
CMOS process, the C-LANCE device includes several       Table B-1.
functional enhancements over the LANCE device.




                                                  Am79C90                                                1-57
       AMD

                    Table B-1. Comparison Summary of the C-LANCE and LANCE Devices
                 Description                    Am79C90 C-LANCE                            Am7990 LANCE
 1      Process/Power Consumption        0.8-micron CS-21S CMOS process           NS-8B NMOS process
                                         ICC ≤ 50 mA                              ICC ≤ 270 mA
 2      FIFOs                            Dual FIFOs: 48-byte TX, 64-byte RX       Single FIFO: 48-byte TX/RX
 3      Transmit Lockout Due to          Will not occur with dual FIFOs and       May occur in high receive rate
        Receive                          enhanced microcode.                      situations with “less than optimal”
                                                                                  bus latencies.
 4      Per-Packet FCS                   Transmit descriptor bit is used to       No per packet CRC control
                                         allow per packet addition of CRC         provided.
                                         when DTCR is set in the MODE
                                         register.
 5      Backoff Algorithm                Selectable Modified Backoff Algorithm    Only standard backoff algorithm
                                         or standard backoff algorithm.           available.
 6      TX Descriptor Zero Buffer Byte   Allows TX buffer byte count of zero.     No capability for TX buffer byte
        Count Capability                                                          count of zero.
 7      Interframe Spacing (IFS)         a) Implements 2-part deferral after      a) One-part deferral after transmit
        Behavior                            transmit
                                         b) Part 1 of two part deferral after     b) Part 1 of 2-part deferral after
                                            receive is 6 µs                          receive is 4.1 µs
                                         c) Heartbeat window = 4 µs               c) Heartbeat window = 2 µs
                                         d) Receive blind time after receive      d) Receive blind time after receive
                                            less than 500 ns                         = 4.1 µs
 8      “Heartbeat OK”                   Heartbeat OK if collision is asserted    Heartbeat OK if collision is
        (no CERR) Definition             at any time from the beginning of the    asserted during the heartbeat
                                         transmission to the end of the           window.
                                         heartbeat window.
 9      Receive Lockup                   Will not occur.                          May occur when bus latency is
                                                                                  large.
 10     ALE Behavior                     ALE may be driven HIGH at end of         ALE may be driven LOW at end of
                                         bus mastership when ACON is set          bus mastership when ACON is set
                                         to 0. When ACON is set to 1, ALE         to 1. When ACON is set to 0, ALE
                                         is not driven LOW at end of bus          is not driven HIGH at end of bus
                                         mastership period.                       mastership period.
 11     External Loopback on a           No problems.                             May receive invalid loopback failure
        Live Network                                                              indications.
 12     Software Reset (STOP bit)        a) STOP bit in CSR0 is latched.          a) STOP bit in CSR0 not latched
        Handling                            When STOP is set, the slave cycle        and will reset the device
                                             is allowed to complete before the       immediately when written.
                                            C-LANCE resets.
                                         b) CSR1 and CSR2 contents are            b) CSR1 and CSR2 are not
                                            preserved when the STOP bit is           preserved when the STOP bit is
                                            set to one.                              set to one.
 13     CSR0 Slave Read Data Stability   CSR0 latched during slave reads to       CSR0 not latched during slave
                                         guarantee timing on DAL lines.           read cycles (could give timing
                                                                                  violations on DAL lines).
 14     INEA bit behavior                INEA bit can be set in CSR0 at           INEA cannot be set in CSR0 while
                                         any time, regardless of the state        the STOP bit is set.
                                         of the STOP bit.
 15     Effect of setting the STOP       Setting the STOP bit in CSR0 when        Setting the STOP bit in CSR0 causes
        bit on CSR0 bits.                the STOP bit is already set does not     all of the other bits in CSR0 to clear,
                                         effect any of the other bits in CSR0     regardless of the previous state of the
                                         (they are not cleared).                  STOP bit.
 16     AC Specification Changes         #06 (tTEP) maximum = 60 ns               #06 (tTEP) maximum = 70 ns
                                         #08 (tTDP) maximum = 60 ns               #08 (tTDP) maximum = 70 ns
                                         #18 (tRDS) minimum = 35 ns               #18 (tRDS) minimum = 40 ns
                                         #30 (tRDAS) minimum = 40 ns              #30 (tRDAS) minimum = 50 ns
                                         #45 (tRDYS) minimum = 65 ns              #45 (tRDYS) minimum = 75 ns
 17     Burn-In Option                   The burn-in option for the C-LANCE
                                         is no longer available.
 18     RX Descriptor Zero Buffer        Unpredictable results when the RX        Interprets a BCNT field setting of zero
        Byte Count Handling              Descriptor Buffer Byte Count is set to   in a receive descriptor as a 4096 byte
                                         zero.                                    buffer.


1-58                                                 Am79C90
                                                                                                             AMD

Detailed Description of Enhancements                          3. Transmit Lockout Due to Receive
1. Process/Power Consumption                                  As discussed in item 2, the dual FIFO architecture and
                                                              modified microcode implemented in the C-LANCE
By using an advanced 0.8 micron CMOS process, the
                                                              device eliminates the possibility of Transmit Lockout
ICC specification for the C-LANCE device is reduced to
                                                              Due to Receive from occurring.
50 mA maximum, compared to the 270 mA maximum
ICC specification for the LANCE device.                       4. Per-Packet FCS
2. FIFOs                                                      In the LANCE device, addition of the Frame Check Se-
                                                              quence (FCS or CRC) to each transmit packet is con-
The C-LANCE device incorporates a dual FIFO (48
                                                              trolled on a per-initialization basis. In other words, when
bytes Transmit, 64 bytes Receive) architecture to help it
                                                              the DTCR (Disable Transmit CRC) bit is set in the mode
compete for bandwidth on busy networks. The LANCE
                                                              register at initialization, the only way that packets can
device’s single 48-byte FIFO architecture and its associ-
                                                              subsequently be transmitted with an FCS attached is by
ated microcode has problems transmitting packets out
                                                              re-initializing the device with the DTCR bit cleared.
on busy networks. This problem is known as the “Trans-
mit Lockout due to Receive” problem. It occurs when           The C-LANCE device provides the capability to override
minimum or near minimum IFS traffic is continually re-        the DTCR setting on a per-packet basis. If DTCR was
ceived by the LANCE device and bus latency is not             set in the mode register at initialization, the ADD_FCS
“good” (“good” = latency < approximately 3 µs). In this       bit in the transmit descriptor can be used to append FCS
situation, the LANCE device’s microcode and bus inter-        to transmitted packets on a per-packet basis, overriding
face is locked servicing receive packets, and is not able     the DTCR setting. If DTCR is cleared in the mode regis-
to poll the pending transmit descriptor (until the receive    ter, the ADD_FCS bit is a “don’t care.”
traffic stops or does not pass address match).
                                                              The ADD_FCS bit is located in bit 13 of TMD1 in the
The C-LANCE device addresses this problem by includ-          C-LANCE device. This bit is RESERVED in the LANCE
ing dual FIFOs and microcode that is modified to take         device. Table 2 below summarizes the operation of the
advantage of the dual FIFOs. The microcode is changed         ADD_FCS bit. Note that the ADD_FCS bit is only mean-
so that a transmit descriptor poll operation occurs some-     ingful in the first descriptor of a transmit buffer chain
time early (exact time depends on bus latencies and           (STP=1).
whether the receive buffer was owned before the re-
ceive packet arrived) in the receive DMA operations for       This feature should be compatible with existing imple-
each packet. If the OWN bit in the TX descriptor is found     mentations. Non-bridge nodes normally run with FCS
set, transmit FIFO loading DMA is interleaved with the        enabled (DTCR cleared). Bridges run with FCS dis-
receive FIFO emptying DMA for the packet being re-            abled. It is assumed that existing software in these
ceived. The transmit packet is then ready to be transmit-     applications do not set bit 13 of TMD1, which was
ted immediately following the end of the receive packet       previously RESERVED.
on the wire. The dual FIFOs and microcode changes
                                                              The ADD_FCS bit is also implemented as bit 13 of
eliminate the possibility of transmit activity being locked
                                                              TMD1 in the PCnetTM-ISA (Am79C960) and operates
out due to high receive activity.
                                                              identically to the way in which it operates in the
Interleaving the transmit DMA activity with receive DMA       C-LANCE device.
activity at the beginning of a reception has the effect of
                                                              As a side note, this feature can be used by software to
increasing the bus latency for receive DMA operations.
                                                              identify the C-LANCE device from LANCE device. The
To ensure that the C-LANCE device can tolerate the
                                                              LANCE device writes bit 13 of TMD1 to zero when up-
same bus latency as the LANCE device, the receive
                                                              dating transmit status in the transmit descriptor. The
FIFO in the C-LANCE device is increased to 64 bytes.
                                                              C-LANCE device will write this bit with the value read, so
The transmit FIFO in the C-LANCE device holds
                                                              if it is set to one it will be returned as a one.
48 bytes.




                                                        Am79C90                                                    1-59
       AMD

                                        Table B-2. ADD_FCS Bit Operation
       DTCR in Mode Reg.                   STP                      ADD_FCS                      FCS Added?
              0                             X                           X                             Yes
              1                             0                           X                             N/A
              1                             1                           0                              No
              1                             1                           1                             Yes

5. Backoff Algorithm                                        device checks for the case where all 16 bits in TMD2 are
A selectable Modified Backoff Algorithm is provided in      zero before starting any transmit DMA from the buffer. If
the C-LANCE device which can improve throughput in          all 16 bits are zero, a zero length buffer is assumed, and
busy networks. Bit 7 of the Mode register (EMBA bit) is     the C-LANCE device immediately clears the OWN in the
used to enable the Modified Backoff Algorithm. This bit     descriptor without starting any transmit activity on the
is RESERVED in the LANCE device.                            network. Note that since all 16 bits are checked, com-
                                                            patibility with the LANCE device is preserved for
With the Modified Backoff Algorithm, counting of the IFS    non-Ethernet-compliant implementations which may
interval is suspended when receive carrier sense is de-     use buffer lengths of 4096 bytes.
tected. The count resumes when receive carrier sense
goes away. This algorithm increases throughput in large     Zero Transmit Buffer Byte Count Capability is included
networks with heavy traffic (many collisions). It can be    in the PCnet-ISA device.
considered as an “adaptive” backoff algorithm. This         7. Interframe Spacing Behavior
mode should only be used in network segments in which
all nodes are using this mode. Otherwise, the nodes that    a) 2-Part Deferral After Transmit: 2-part deferral after
are using it will be at a disadvantage to those that are       receive has always been an option in the IEEE
not.                                                           802.3 specification. However, 2-part deferral after
                                                               transmit was recently added as an option in the
Note that this mode does not conflict with IEEE require-       802.3 specification by the IEEE committee. With
ments for compliance. The IEEE 802.3 specification             2-part deferral, the IFS is divided into two parts,
specifies only the minimum amount of time for the back-        IFS1 and IFS2. If there is activity on the wire dur-
off interval. This leaves open the possibility of backing      ing IFS1, the IFS counter is reset until the wire is
off more than the minimum, which is precisely how the          clear again. The IFS counter is not reset once it
Modified Backoff Algorithm works.                              enters IFS2. When the IFS counter expires the
The Modified Backoff Algorithm is included as an option        chip will begin to transmit if it has anything to send.
in the MACETM (Am79C940) and PCnet-ISA                          The specification’s wording for 2-part deferral after
(Am79C960) devices.                                             transmit is identical to the way that 2-part deferral
                                                                after receive has been worded all along. That is,
6. TX Descriptor Zero Buffer Byte Count
                                                                the specification specifies that part 1 of the two
   Capability
                                                                parts can be anywhere from 0 to 2/3 of the IFS
The 12-bit BCNT field in the transmit descriptor of the         (9.6 µs). If part 1 = 0 (perfectly legal), it is equiva-
LANCE and C-LANCE devices is loaded with the 2’s                lent to not implementing 2-part deferral at all.
complement of the number of bytes that must be trans-           Hence, the LANCE device, which implements
mitted from the buffer. With the 2’s complement repre-          2-part deferral after receive but not after transmit,
sentation, a simple incrementer is used in the chip to          complies with IEEE specifications. However, imple-
count through the byte count as bytes are being read            mentation of 2-part deferral after both transmit and
from the transmit buffer. When the 2’s complement               receive eliminates a possible scenario where pack-
number reaches all 0’s, the count has expired. The              ets cannot be received (due to very small or 0 IFS)
LANCE device does not check for the all 0’s case when           but there is no indication of this fact through a colli-
the BCNT field is first loaded from the descriptor.             sion indication at the transmitter. Hence, although
Hence, the all 0’s case is interpreted by the LANCE de-         this scenario is very rare, the C-LANCE device
vice as a buffer count of 4096 (212), preventing zero           implements 2-part deferral after transmit in addi-
length TX buffers in the LANCE device. In addition, the         tion to after receive.
LANCE device ignores the upper 4 bits in TMD2, which
                                                            b) The IEEE 802.3 specifications state that part 1 of
are adjacent to the BCNT field. These bits are indicated
                                                               2-part deferral can be anywhere from 0 to 2/3 of
as “must be ones” in the LANCE data sheet.
                                                               the IFS (9.6 µs). The LANCE device only imple-
The C-LANCE device actually uses all 16 bits in TMD2           ments 2-part deferral after receive, with part
as the BCNT field. Compatibility with the LANCE device         1 = 4.1 µs and part 2 = 5.5 µs (compliant). The
is preserved as long as the upper 4 bits in TMD2 are 1’s,      C-LANCE device implements 2-part deferral after
as specified in the LANCE data sheet. The C-LANCE              both transmit and receive with part 1 = 6.0 µs and

1-60                                                  Am79C90
                                                                                                                AMD

   part 2 = 3.6 µs. Since the receiver is blinded fol-          1) IEEE 802.3 specifications state that the heartbeat
   lowing a transmit for 4.0 µs (see below), part 1 of             window should begin when the input becomes idle
   2-part deferral after a transmit had to be extended             (RENA de-asserts), not when the output becomes
   beyond 4.1 µs or else part 1 would effectively only             idle (TENA de-asserts).
   be from 4.0 µs to 4.1 µs during the IFS. Hence, in           2) If a collision occurs, the IEEE 802.3 specifications
   the C-LANCE device, part 1 of 2-part deferral after             indicate that the DTE should not look for the SQE
   transmit was set at 6.0 µs and the same value was               test signal.
   used for part 1 following a receive.
                                                                3) As mentioned in 7c), the window should end no
c) IEEE 802.3 specifications state that the Signal                 earlier than 4.0 µs after when RENA de-asserts.
   Quality Error (SQE) test window should be at least
   4.0 µs and no more than 8.0 µs. The LANCE de-                The C-LANCE device implements the heartbeat test in
   vice implements a 2 µs window which is not com-              full compliance with IEEE specifications. In the
   pliant with this specification. This generally turns         C-LANCE device, the heartbeat window begins when
   out to be a non-issue because 802.3 also specifies           RENA de-asserts and ends 4 µs later. In addition, the
   that the MAU must generate the collision signal              C-LANCE device does not look for the heartbeat signal
   within 0.6 µs to 1.6 µs after the end of the transmit        whenever the packet being transmitted suffers a
   packet, which is typically early enough for the              collision.
   LANCE device to detect it, even with its non-                The PCnet-ISA and MACE devices use the same heart-
   compliant 2 µs window. However, to comply with               beat OK definition as the C-LANCE device.
   IEEE standards, the C-LANCE device implements
   an SQE test window of 4 µs.                                  Details on the LANCE device’s violations of IEEE Speci-
d) IEEE specifications require that receive be blinded          fications: The consequences of the violations of the
   following transmit for 4 µs to prevent the controller        standard by the LANCE device are very little in practice.
   from responding to any trash that may be gener-              Item 1 (window begins when TENA de-asserts not
   ated by the MAU when it generates the SQE test               RENA) actually prevents the LANCE from being penal-
   signal. However, IEEE specifications do not state            ized by Item 2 (Heartbeat expected following a colli-
   that the receiver should be blinded following a re-          sion). That is, if the LANCE device did not violate Item 1
   ceive. The LANCE device implements a 4.1 µs                  and started its window when RENA de-asserted instead
   blinding time following receive, violating IEEE              of TENA, then the LANCE device could get false CERR
   specifications. This was erroneously implemented             indications when a packet it is transmitting suffers a col-
   in the LANCE device since it was thought to be a             lision. This can happen as follows. In the event of a colli-
   moot issue under the assumption that there should            sion, the network may remain active for a while after one
   be no valid data on the wire within 4.1 µs of the            node stops transmitting its JAM sequence (other nodes
   end of a receive anyway. However, since 2-part               involved in the collision may still have their JAM on the
   deferral after transmit and receive are both op-             wire). At a node that ends its JAM sequence relatively
   tional, as mentioned in 7a), there are rare situ-            early, the heartbeat signal can overlap with the collision
   ations where legal packets may arrive with an IFS            or the end of the collision fragment since the MAU times
   of less than 4.1 µs. To better handle this situation,        the heartbeat signal generation from when the controller
   the C-LANCE device reduces the blind time follow-            stops transmitting. If this node uses a LANCE device as
   ing a receive to less than 500 ns. The blind time            its controller, the LANCE device will see this heartbeat
   allows time to store and then clear the status that          signal only because of the violation given in Item 1. If the
   was generated by the ending reception.                       LANCE device started its window when RENA de-
                                                                asserted instead of TENA, it would miss the heartbeat
8. “Heartbeat OK” (No CERR) Definition                          signal, since the heartbeat passes by while the collision
The heartbeat test or Signal Quality Error (SQE) test is        is still on the wire. This would give false CERR indica-
performed to verify the ability of the AUI to pass the colli-   tions. Hence, the violation of Item 1 in the LANCE device
sion (SQE) indication to the DTE. The LANCE and                 is not a problem. In fact, it makes the violation of Item 2
C-LANCE devices indicate a heartbeat test failure by            generally a non-issue.
setting the CERR bit in CSR0 (bit 13).
                                                                Although the violation of Item 1 masks the violation of
At the conclusion of each transmission, the DTE opens           Item 2 as just described, the violation of Item 2 (heart-
a time window during which it expects to see a collision        beat still expected by the LANCE device when collision
indication. In the LANCE device, this window begins im-         occurs) can still lead to false CERR indications when the
mediately following when TENA de-asserts and ends               LANCE device is used with a non-802.3-compliant
2.0µs after when RENA de-asserts. The heartbeat sig-            MAU. The IEEE 802.3 specifications state that the MAU
nal is expected by the LANCE device even if the packet          is to generate the SQE test signal after every transmit,
being transmitted suffers a collision. This implementa-         even when the transmit suffers a collision. However,
tion violates IEEE requirements in three ways:                  some MAUs on the market have been found to not

                                                          Am79C90                                                     1-61
       AMD

comply with this requirement. When operating with a            12. Software Reset (STOP Bit) Handling
non-compliant MAU that does not generate the heart-            a) Latching of the STOP bit: In the LANCE device,
beat signal after a collided transmission, the LANCE              writing the STOP bit in CSR0 causes all bus sig-
device can give false CERR indications.                           nals to immediately float. With READY pulled up
As mentioned in 7c), Item 3 is generally a non-issue.             externally (READY is open drain), this causes
                                                                  READY to de-assert prematurely during the slave
9. Receive Lockup                                                 cycle. If DAS and CS remain active, the LANCE
The LANCE device has an errata where the receiver                 device can erroneously start another slave cycle.
locks up when the system bus latency is very high. This           The C-LANCE device latches the STOP bit and,
errata is fixed in the C-LANCE device.                            when it is set, allows the slave cycle in progress to
                                                                  complete before resetting the part.
10. ALE Behavior                                               b) Preservation of CSR1 and CSR2: The LANCE
The LANCE device may drive the ALE pin LOW at the                 device does not preserve the contents of CSR1
end of each bus mastership period when ACON=1                     and CSR2 during the initialization process. Hence,
(ALE/AS active low – AS mode). When the bus                       when the STOP bit is set, the contents of CSR1
mastership period ends, the ALE pin is tri-stated hence,          and CSR2 are not the same as they were before
if ALE is pulled HIGH by external logic, a glitch on ALE          initialization and they must be rewritten before re-
results. The glitch occurs about when the LANCE device            initializing. This is not really a problem in the
is releasing the bus by bringing HOLD high. The C-                LANCE device but it can add extra instructions to
LANCE device incorporates redesigned ALE logic to                 software. The C-LANCE device removes this soft-
prevent this glitch from occurring.                               ware burden by preserving the contents of CSR1
                                                                  and CSR2 during initialization so that when the
However, in the C-LANCE, when ACON=0 (active high                 STOP bit is set, they do not have to be reloaded
ALE), ALE is driven high before it is tri-stated at the end       before re-initializing. Note, however, that if the de-
of every bus mastership period. In the LANCE, when                fault values of CSR3 (defaults for BCON, ACON,
ACON=0 (active high ALE), ALE is not driven high                  and BSWP are 0, 0, and 0, respectively) are not
before it is tri-stated at the end of every bus mastership        used, CSR3 must still be reloaded after setting the
period.                                                           STOP bit in the C-LANCE device since CSR3 is
This difference will not cause any problems in designs            cleared when the STOP bit is set.
which set ACON=1 (AS; active low ALE). It could cause          13. CSR0 Slave Read Data Stability
problems in designs in which ACON=0. The ALE signal            In the LANCE device, the status bit latches in CSR0 may
is intended to provide a strobe signal for an external ad-     change at any time, as governed by the occurrence of
dress latch. The rising edge, coupled with a subsequent        the external events which they monitor. Hence, the
falling edge that will occur if the pin is externally pulled   ERR, BABL, CERR, MISS, IDON, and INTR bits in
down, will cause an invalid address to be strobed into         CSR0 may change during a slave read cycle in which
the external address latch. However, since this occurs         they are being accessed. This can cause timing viola-
at the end of the bus mastership period, and further           tions on the DAL lines. In the C-LANCE device, CSR0 is
master cycles are not performed by the C-LANCE sub-            latched in a shadow register during a read so that timing
sequent to the invalid address being strobed (until the        on the DAL lines is guaranteed.
next bus mastership period), the invalid address gener-
ally has no effect. A design could have problems with          14. INEA Behavior
this if external logic is continuously decoding the latched    With the C-LANCE device, INEA bit can be set in CSR0
address and taking some action on it even though the           at any time, regardless of the state of the STOP bit. This
C-LANCE is not executing any master cycles.                    actually removes a restriction that was present in the
11. External Loopback on a Live Network                        LANCE device in which the INEA bit in CSR0 could be
                                                               not be set while STOP bit was set.
The LANCE device has an errata which causes loop-
back failures when external loopback is run on a live net-     This difference between the two devices does not effect
work. This errata is fixed in the C-LANCE device.              normal device operation but could disrupt diagnostic
                                                               code written for the LANCE device.




1-62                                                     Am79C90
                                                                                                         AMD

15. Effect of Setting the STOP bit on CSR0 Bits           17. Elimination of Burn-In Option
In the LANCE device, CSR0 is reset when the STOP bit      The burn-in option for the C-LANCE is no longer avail-
in CSR0 is set. This reset happens even if the STOP       able. Thus, the ordering part number Am79C90PCB is
bit was already set. When the reset occurs, all of the    no longer valid (see page 4 of the C-LANCE data sheet).
other bits in CSR0 are cleared. In the C-LANCE, CSR0
is reset when the STOP bit is set in CSR0 only if the     18. RX Descriptor Zero Buffer Byte Count
STOP bit was not already set.                                 Handling
                                                          The 12-bit BCNT field in the receive descriptor of the
This difference between the two devices does not effect   LANCE and C-LANCE devices is loaded with the 2’s
normal device operation but could disrupt diagnostic      complement of the number of bytes allocated to the as-
code written for the LANCE device.                        sociated receive buffer. In the LANCE device, when all
16. AC Specification Changes                              0’s are written to the BCNT field in a receive descriptor,
                                                          a buffer length of 4096 (212) bytes is assumed. In the
The following differences in AC specification exist       C-LANCE device the case of all 0’s in the receive de-
between the C-LANCE and the LANCE.                        scriptor may produce unpredictable results.
                             C-LANCE        LANCE         This difference should not cause problems in 802.3
 #06 (tTEP) maximum            60 ns         70 ns        compliant networks, because 802.3 has a maximum
 #08 (tTDP) maximum            60 ns         70 ns        packet length specification of 1518 bytes.
 #18 (tRDS) minimum            35 ns         40 ns
 #30 (tRDAS) minimum           40 ns         50 ns
 #45 (tRDYS) minimum           65 ns         75 ns




                                                     Am79C90                                                   1-63
