diff --git a/harness/mame/DUART_REPORT.md b/harness/mame/DUART_REPORT.md
index 6231109..ff8b759 100644
--- a/harness/mame/DUART_REPORT.md
+++ b/harness/mame/DUART_REPORT.md
@@ -546,3 +546,90 @@ Final state of the acceptance instrument (900 frames):
 'LEVEL1/2 ERROR -> HOST PORT - 15 '      <-- unchanged
 regression (no VT1200_* env): PC=3FDCE400 samples=199   HOLD
 ```
+
+---
+
+# CAUSALITY AUDIT (four-config A/B) — the failure is PRE-EXISTING
+
+Reviewed after the owner flagged that "the failure moved backwards" and that my two
+MAME edits are both *timing* changes while the newly-blamed sub-test is a *timer* test.
+Method: four configurations of the MAME tree (IRQ wiring kept in all four — without it
+the test fails even earlier), built with `harness/mame/hp_ab.sh <cfg>`:
+
+| cfg | IRQ | TxRDY edit | overrun edit | console | L3FA6E4B0 return |
+|---|---|---|---|---|---|
+| 1 | on | on | on | `HOST PORT - 15` | 6 |
+| 2 | on | reverted | on | `HOST PORT - 15` | 6 |
+| 3 | on | on | reverted | `HOST PORT - 15` | 6 |
+| 4 | on | reverted | reverted | `HOST PORT - 15` | 6 |
+
+**Verdict: PRE-EXISTING.** The console line and the caller's return are identical in all
+four configurations, including cfg 4 where both MAME edits are reverted to stock. Neither
+`mc68681` edit causes or relocates the failure; they only change `RXCHECK`'s own flag
+word (Section UPDATE). Variant files are kept in `harness/mame/mame_edits/` (`*.cfg1`,
+`*.cfg2`, `*.cfg3`, `*.upstream`).
+
+## Methodology correction (important)
+
+My earlier `hp_ret.lua` attached labels to the **wrong `rets` addresses**, so the return
+values I quoted were mis-attributed. Verified against the disassembly, the correct
+`rets` sites and their owning functions (prologue register mask) are:
+
+| `rets` | function | return |
+|---|---|---|
+| `3FA71BB0` | **`L3FA6E4B0`** (the generic port-test routine) | 6 |
+| `3FA753C0` | `L3FA71BC0` (baud/timer sub-test) | `0x00900040` |
+| `3FA767D0` | `L3FA753D0` (RXCHECK sub-test) | `0x00000408` |
+| `3FA77800` | `L3FA767E0` (XMITPASS sub-test) | 0 |
+
+`harness/mame/hp_ret2.lua` uses the corrected addresses. So the owner's premise "6 comes
+from `L3FA71BC0`" is off: **`L3FA71BC0` returns `0x00900040`**; the `6` is
+`L3FA6E4B0`'s own return.
+
+## What `6` actually is — not a failure code
+
+`L3FA6E4B0` (the routine the level-1 host-port caller invokes) ends its body by reducing
+five descriptor fields to a 5-bit value (`3FA718D0`–`3FA71B50`) and returning it:
+
+```
+bit0 <- (struct+0x60 != 0)      bit3 <- (struct+0xc0 != 0)
+bit1 <- (struct+0x80 != 0)      bit4 <- (struct+0xe0 != 0)
+bit2 <- (struct+0xa0 != 0)
+```
+
+with `struct+0x80`/`struct+0xa0`/`struct+0xc0`/`struct+0xe0` set from the four
+sub-test calls (`L3FA71BC0`, `L3FA753D0` x2 each). So:
+
+* **`6` = `0b00110`** — a *bitmap of which sub-tests returned nonzero*, not a device
+  status code: `L3FA71BC0` non-zero and `L3FA753D0` non-zero; `L3FA767E0` returned 0, and
+  the second-trio fields were never written (the caller aborts after the first trio).
+* The host-port caller (`3FA85000`) is `move a8,a8 ; jreq <continue>`: **any** nonzero
+  value takes the error path, which returns `0x400` (`3FA853A0`). `0x400` is what the
+  status dispatcher turns into `LEVEL1/2 ERROR -> HOST PORT - 15`.
+
+**Unresolved, and flagged:** the polarity is suspicious. `L3FA753D0` (RXCHECK) returns
+`0x408` *while all four of its own checks pass* (flag word 0 — see UPDATE), so "sub-test
+returned nonzero" is **not** the same as "sub-test failed its checks". Either its success
+path leaves a stale `a8`, or the five fields are pass flags and the caller's test is
+inverted relative to my reading. I could not settle this, so `6` should **not** be
+treated as a plain failure code until it is.
+
+## The two leads
+
+1. **Counter spuriously active — checked, not the cause.** `ISR` bit `0x08`
+   (`COUNTER_READY`) is set from frame 1, but MAME sets it in the *Start Counter Command*
+   read path (`mc68681.cpp` `case 0x0e: start_ct(); set_ISR_bits(INT_COUNTER_READY)`),
+   and the firmware itself performs that read at boot (`R 0640000E pc=3F200150`). It is
+   **not** masked into the IRQ (`IMR` = 7 = TxRDYA|RxRDYA|DeltaBreakA, no bit 3), and the
+   DUART ISR `L3FA78D90` does not handle ISR bit 3, so it cannot disturb the test. `ACR`
+   reads `0x0000` except when the sub-test writes `0x60`.
+2. **DUART clock — unverified.** The service guide has no crystal/baud figure for the
+   DUART (`grep -i '3.6864|crystal|oscillator' docs/EK-V1000-SV-002_service-guide.txt`
+   → nothing; its only "baud" hit is test 16 "Test all baud rates", a level-2+ test).
+   3.6864 MHz is the 68681 datasheet's nominal and remains the only evidence; **I could
+   not confirm it** against the guide.
+
+## Acceptance / regression (cfg 1, committed state)
+
+* Console: `LEVEL1/2 TESTING **` then `LEVEL1/2 ERROR -> HOST PORT - 15` — **unchanged**.
+* Regression (no `VT1200_*`): `PC=3FDCE400 samples=199` — **holds**.
diff --git a/harness/mame/hp_ab.sh b/harness/mame/hp_ab.sh
new file mode 100755
index 0000000..cc6dbd0
--- /dev/null
+++ b/harness/mame/hp_ab.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+# hp_ab.sh <label> -- build the current MAME tree and report the L3FA71BC0
+# return value (hp_ret.lua) and the console transcript (cap.lua).
+set -e
+HERE=$(cd "$(dirname "$0")" && pwd)
+M=/home/arti/code/k-space/mame0289/vt1200
+LABEL=${1:-cfg}
+
+JOBS=8 "$HERE/build.sh" >/dev/null
+cd "$HERE"
+echo "== $LABEL =="
+export VT1200_VRAM=1 VT1200_BOARD_MODEL=handshake VT1200_BOARD_BUSY_TICKS=2
+export VT1200_BOARD_SWITCH="0640000D:70:70" VT1200_DUART=1 VT1200_DUART_SEL=1
+
+rm -f debug.log
+timeout 300 "$M" vt1200 -rompath roms -video none -sound none -nothrottle \
+  -debug -debugger none -debuglog -autoboot_script "$HERE/hp_ret.lua" -autoboot_delay 0 >/dev/null 2>&1 || true
+echo "-- returns (hp_ret) --"
+grep -v "Breakpoint\|^Currently\|^MAME" debug.log | grep -v '^$' | head -12
+
+rm -f debug.log
+CAP_MAX=900 timeout 300 "$M" vt1200 -rompath roms -video none -sound none -nothrottle \
+  -debug -debugger none -debuglog -autoboot_script "$HERE/cap.lua" -autoboot_delay 0 >/dev/null 2>&1 || true
+echo "-- console --"
+grep PRINT debug.log | head -6
diff --git a/harness/mame/hp_ctr.lua b/harness/mame/hp_ctr.lua
new file mode 100644
index 0000000..cd2a031
--- /dev/null
+++ b/harness/mame/hp_ctr.lua
@@ -0,0 +1,15 @@
+local machine = manager.machine
+local cpu = machine.devices[':maincpu']
+local dbg = machine.debugger
+local prog = cpu.spaces['program']
+local rd = function(a) return prog:read_u16(a) end
+local last={}
+local keys={ ISR=0x06400050, IMR=0x06400050, ACR=0x06400040, CUR=0x06400060 }
+local n=0
+emu.register_frame_done(function()
+  n=n+1
+  local isr=rd(0x06400050) & 0xff
+  if last.isr~=isr then print(string.format("f%4d ISR=%02X ACR=%04X", n, isr, rd(0x06400040))); last.isr=isr end
+  if n>=520 then machine:exit() end
+end,"ctr")
+dbg.execution_state='run'
diff --git a/harness/mame/hp_ret2.lua b/harness/mame/hp_ret2.lua
new file mode 100644
index 0000000..f5d3c6e
--- /dev/null
+++ b/harness/mame/hp_ret2.lua
@@ -0,0 +1,23 @@
+-- hp_ret2.lua -- return values, with the rets addresses verified from the disassembly:
+--   L3FA71BC0 rets @ 3FA753C0, L3FA753D0 (RXCHECK) @ 3FA767D0,
+--   L3FA767E0 (XMITPASS) @ 3FA77800.
+local machine = manager.machine
+local cpu = machine.devices[':maincpu']
+local dbg = machine.debugger
+if not dbg then print("ERROR: no debugger"); machine:exit(); return end
+local function bp(addr, msg)
+  dbg:command('bpset ' .. addr .. ',,{ printf "' .. msg ..
+    ' a8=%08X a7=%08X a9=%08X a11=%08X a13=%08X\\n", a8, a7, a9, a11, a13 ; g }')
+end
+bp("3fa753c0", "RET-BC0")
+bp("3fa767d0", "RET-RXCHECK")
+bp("3fa77800", "RET-XMITPASS")
+bp("3fa84fe0", "RET-L3FA6E4B0")
+bp("3fa6e4b0", "ENTER-GENERIC")
+local n = 0
+emu.register_frame_done(function()
+  n = n + 1
+  if n >= tonumber(os.getenv("HP_FRAMES") or "700") then print("done "..n); machine:exit() end
+end, "vt1200-hp-ret2")
+dbg.visible_cpu = cpu
+dbg.execution_state = 'run'
diff --git a/harness/mame/mame_edits/mc68681.cpp.cfg1 b/harness/mame/mame_edits/mc68681.cpp.cfg1
new file mode 100644
index 0000000..077cc0a
--- /dev/null
+++ b/harness/mame/mame_edits/mc68681.cpp.cfg1
@@ -0,0 +1,1948 @@
+// license:BSD-3-Clause
+// copyright-holders:Mariusz Wojcieszek, R. Belmont, Joseph Zatarski
+/*
+    2681 DUART
+    68681 DUART
+    28C94 QUART
+    68340 serial module
+    XR68C681 DUART (backwards compatible with 68681 with some improvements)
+
+    Written by Mariusz Wojcieszek
+    Updated by Jonathan Gevaryahu AKA Lord Nightmare
+    Improved interrupt handling by R. Belmont
+    Rewrite and modernization in progress by R. Belmont
+    Addition of the duart compatible 68340 serial module support by Edstrom
+    Support for the Exar XR68C681 by Joseph Zatarski (July of 2018)
+    Support for Freescale/NXP ColdFire UART module by NaokiS (June 2025)
+
+    The main incompatibility between the 2681 and 68681 (Signetics and Motorola each
+    manufactured both versions of the chip) is that the 68681 has a R/W input and
+    generates a 68000-compatible DTACK signal, instead of using generic RD and WR
+    strobes as the 2681 does. The 68681 also adds a programmable interrupt vector,
+    with an IACK input replacing IP6.
+
+    The command register addresses should never be read from. Doing so may place
+    the baud rate generator into a test mode which drives the parallel outputs with
+    internal counters and causes serial ports to operate at uncontrollable rates.
+
+    Exar XR68C681
+
+    The XR68C681 is an improvement upon the MC68681 which supports more baud
+    rates, adds an additional MISR (masked ISR) register, and adds a low-power
+    standby mode. There may be other differences, but these are the most
+    notable.
+
+    The extra baud rates are implemented by an 'X' bit for each channel. The X
+    bit chooses between two baud rate tables, in addition to the ACR[7] bit.
+    The X bit is changed by additional commands that are written to CRA and CRB.
+
+    The MISR is a read only register that takes the place of the 'BRG Test'
+    register on the MC68681.
+
+    The low power standby mode is entered and left by a command written to CRA
+    or CRB registers. Writing the commands to either register affects the whole
+    DUART, not just one channel. Resetting the DUART also leaves low power mode.
+
+    On the ColdFire MCF5206e, the UART modules are essentially just a pair of
+    MC68681s with only the A port visible and no counter/timer. The ACR on the
+    coldfire uarts shoud be updated to reflect this. Additionally, the
+    Baud Rate Generator prescaler reg should be used to set the baud.
+*/
+
+#include "emu.h"
+#include "mc68681.h"
+
+#include <algorithm>
+
+//#define VERBOSE 1
+//#define LOG_OUTPUT_FUNC printf
+#include "logmacro.h"
+
+
+static const char *const duart68681_reg_read_names[0x10] =
+{
+	"MRA", "SRA", "BRG Test", "RHRA", "IPCR", "ISR", "CTU", "CTL", "MRB", "SRB", "1X/16X Test", "RHRB", "IVR", "Input Ports", "Start Counter", "Stop Counter"
+};
+
+static const char *const duart68681_reg_write_names[0x10] =
+{
+	"MRA", "CSRA", "CRA", "THRA", "ACR", "IMR", "CTUR", "CTLR", "MRB", "CSRB", "CRB", "THRB", "IVR", "OPCR", "Set OP Bits", "Reset OP Bits"
+};
+
+static const char *const mcf5206e_duart_reg_read_names[0x10] =
+{
+	"UMR", "USR", "NO ACCESS", "URB", "UIPCR", "UISR", "UBG1", "UBG2", "NO ACCESS", "NO ACCESS", "NO ACCESS", "NO ACCESS", "UIVR", "UIP Input Ports", "NO ACCESS", "NO ACCESS"
+};
+
+static const char *const mcf5206e_duart_reg_write_names[0x10] =
+{
+	"UMR", "UCSR", "UCRA", "UTB", "UACR", "UIMR", "UBG1", "UBG2", "NO ACCESS", "NO ACCESS", "NO ACCESS", "NO ACCESS", "IVR", "NO ACCESS", "Set OP Bits", "Reset OP Bits"
+};
+
+static const int baud_rate_ACR_0[] =     { 50, 110, 134, 200, 300,  600,   1200,  1050,  2400,   4800, 7200, 9600, 38400, 0, 0, 0 }; /* xr68c681 X=0 */
+static const int baud_rate_ACR_0_X_1[] = { 75, 110, 134, 150, 3600, 14400, 28800, 57600, 115200, 4800, 1800, 9600, 19200, 0, 0, 0 };
+static const int baud_rate_ACR_1[] =     { 75, 110, 134, 150, 300,  600,   1200,  2000,  2400,   4800, 1800, 9600, 19200, 0, 0, 0 }; /* xr68c681 X=0 */
+static const int baud_rate_ACR_1_X_1[] = { 50, 110, 134, 200, 3600, 14400, 28800, 57600, 115200, 4800, 7200, 9600, 38400, 0, 0, 0 };
+
+static const int baud_rate_ACR_0_340[] = { 50, 110, 134, 200, 300,  600,   1200,  1050,  2400,   4800, 7200, 9600, 38400, 76800, 0, 0 }; /* xr68c681 ACR:7=0 */
+static const int baud_rate_ACR_1_340[] = { 75, 110, 134, 150, 300,  600,   1200,  2000,  2400,   4800, 1800, 9600, 19200, 38400, 0, 0 }; /* xr68c681 ACR:7=1 */
+
+#define INT_INPUT_PORT_CHANGE       0x80
+#define INT_DELTA_BREAK_B           0x40
+#define INT_RXRDY_FFULLB            0x20
+#define INT_TXRDYB                  0x10
+#define INT_COUNTER_READY           0x08
+#define INT_DELTA_BREAK_A           0x04
+#define INT_RXRDY_FFULLA            0x02
+#define INT_TXRDYA                  0x01
+
+#define STATUS_RECEIVED_BREAK       0x80
+#define STATUS_FRAMING_ERROR        0x40
+#define STATUS_PARITY_ERROR         0x20
+#define STATUS_OVERRUN_ERROR        0x10
+#define STATUS_TRANSMITTER_EMPTY    0x08
+#define STATUS_TRANSMITTER_READY    0x04
+#define STATUS_FIFO_FULL            0x02
+#define STATUS_RECEIVER_READY       0x01
+
+#define MODE_RX_INT_SELECT_BIT      0x40
+#define MODE_BLOCK_ERROR            0x20
+
+#define CHANA_TAG   "cha"
+#define CHANB_TAG   "chb"
+#define CHANC_TAG   "chc"
+#define CHAND_TAG   "chd"
+
+// device type definition
+DEFINE_DEVICE_TYPE(SCN2681, scn2681_device, "scn2681", "SCN2681 DUART")
+DEFINE_DEVICE_TYPE(MC68681, mc68681_device, "mc68681", "MC68681 DUART")
+DEFINE_DEVICE_TYPE(MCF5206E_UART, mcf5206e_uart_device, "mcf5206euart", "MCF5206e UART")
+DEFINE_DEVICE_TYPE(SC28C94, sc28c94_device, "sc28c94", "SC28C94 QUART")
+DEFINE_DEVICE_TYPE(MC68340_DUART, mc68340_duart_device, "mc68340duart", "MC68340 DUART")
+DEFINE_DEVICE_TYPE(XR68C681, xr68c681_device, "xr68c681", "XR68C681 DUART")
+DEFINE_DEVICE_TYPE(DUART_CHANNEL, duart_channel, "duart_channel", "DUART channel")
+
+
+//**************************************************************************
+//  LIVE DEVICE
+//**************************************************************************
+
+duart_base_device::duart_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, type, tag, owner, clock),
+	m_chanA(*this, CHANA_TAG),
+	m_chanB(*this, CHANB_TAG),
+	m_chanC(*this, CHANC_TAG),
+	m_chanD(*this, CHAND_TAG),
+	write_irq(*this),
+	write_a_tx(*this),
+	write_b_tx(*this),
+	write_c_tx(*this),
+	write_d_tx(*this),
+	read_inport(*this, 0),
+	write_outport(*this),
+	ip3clk(0),
+	ip4clk(0),
+	ip5clk(0),
+	ip6clk(0),
+	ACR(0),
+	IP_last_state(0)
+{
+}
+
+scn2681_device::scn2681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, SCN2681, tag, owner, clock)
+{
+}
+
+mc68681_device::mc68681_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+	, m_read_vector(false)
+{
+}
+
+mc68681_device::mc68681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68681_device(mconfig, MC68681, tag, owner, clock)
+{
+}
+
+mcf5206e_uart_device::mcf5206e_uart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+	, m_read_vector(false)
+{
+}
+
+mcf5206e_uart_device::mcf5206e_uart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, MCF5206E_UART, tag, owner, clock)
+{
+}
+
+
+sc28c94_device::sc28c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, SC28C94, tag, owner, clock)
+{
+}
+
+//--------------------------------------------------------------------------------------------------------------------
+// The read and write methods are meant to catch all differences in the register model between 68681 and 68340
+// serial module. Eg some registers are (re)moved into the 68340 like the vector register. There are also no counter
+// in the 68340. The CSR clock register is also different for the external clock modes. The implementation assumes
+// that the code knows all of this and will not warn if those registers are accessed as it could be ported code.
+// TODO: A lot of subtle differences and also detect misuse of unavailable registers as they should be ignored
+//--------------------------------------------------------------------------------------------------------------------
+mc68340_duart_device::mc68340_duart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+{
+}
+
+mc68340_duart_device::mc68340_duart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68340_duart_device(mconfig, MC68340_DUART, tag, owner, clock)
+{
+}
+
+xr68c681_device::xr68c681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68681_device(mconfig, XR68C681, tag, owner, clock)
+	, m_XTXA(false)
+	, m_XRXA(false)
+	, m_XTXB(false)
+	, m_XRXB(false)
+{
+}
+
+//-------------------------------------------------
+//  set_clocks - configuration helper to set
+//  the external clocks
+//-------------------------------------------------
+
+void duart_base_device::set_clocks(int clk3, int clk4, int clk5, int clk6)
+{
+	ip3clk = clk3;
+	ip4clk = clk4;
+	ip5clk = clk5;
+	ip6clk = clk6;
+}
+
+/*-------------------------------------------------
+    device start callback
+-------------------------------------------------*/
+
+void duart_base_device::device_start()
+{
+	duart_timer = timer_alloc(FUNC(duart_base_device::duart_timer_callback), this);
+
+	save_item(NAME(ACR));
+	save_item(NAME(IMR));
+	save_item(NAME(ISR));
+	save_item(NAME(OPCR));
+	save_item(NAME(OPR));
+	save_item(NAME(CTR));
+	save_item(NAME(IPCR));
+	save_item(NAME(IP_last_state));
+	save_item(NAME(half_period));
+	save_item(NAME(m_irq_state));
+}
+
+void mc68681_device::device_start()
+{
+	duart_base_device::device_start();
+
+	save_item(NAME(m_read_vector));
+	save_item(NAME(IVR));
+}
+
+void mcf5206e_uart_device::device_start()
+{
+	duart_base_device::device_start();
+
+	save_item(NAME(m_read_vector));
+	save_item(NAME(IVR));
+	save_item(NAME(UBG));
+}
+
+void xr68c681_device::device_start()
+{
+	mc68681_device::device_start();
+
+	save_item(NAME(m_XTXA));
+	save_item(NAME(m_XRXA));
+	save_item(NAME(m_XTXB));
+	save_item(NAME(m_XRXB));
+}
+
+/*-------------------------------------------------
+    device reset callback
+-------------------------------------------------*/
+
+void duart_base_device::device_reset()
+{
+	ACR = 0;  /* Interrupt Vector Register */
+	IMR = 0;  /* Interrupt Mask Register */
+	ISR = 0;  /* Interrupt Status Register */
+	OPCR = 0; /* Output Port Conf. Register */
+	OPR = 0;  /* Output Port Register */
+	CTR.d = 0;  /* Counter/Timer Preset Value */
+	// "reset clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR) puts OP0-7 in the high state, stops the counter/timer, and puts channels a/b in the inactive state"
+	IPCR = 0;
+
+	m_irq_state = false;
+	write_irq(CLEAR_LINE);
+	write_outport(OPR ^ 0xff);
+}
+
+void mc68681_device::device_reset()
+{
+	duart_base_device::device_reset();
+
+	IVR = 0x0f;  /* Interrupt Vector Register */
+	m_read_vector = false;
+}
+
+void mcf5206e_uart_device::device_reset()
+{
+	duart_base_device::device_reset();
+
+	IVR = 0x0f;  /* Interrupt Vector Register */
+	UBG = 0x00;  /* UART Baud Rate Generator Register */
+	m_read_vector = false;
+}
+
+void xr68c681_device::device_reset()
+{
+	mc68681_device::device_reset();
+
+	m_XTXA = m_XRXA = m_XTXB = m_XRXB = false;
+}
+
+void duart_base_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void sc28c94_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+	DUART_CHANNEL(config, CHANC_TAG);
+	DUART_CHANNEL(config, CHAND_TAG);
+}
+
+void mc68340_duart_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void mcf5206e_uart_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void duart_base_device::update_interrupts()
+{
+	/* update SR state and update interrupt ISR state for the following bits:
+	SRn: bits 7-4: handled elsewhere.
+	SRn: bit 3 (TxEMTn) (we can assume since we're not actually emulating the delay/timing of sending bits, that as long as TxRDYn is set, TxEMTn is also set since the transmit byte has 'already happened', therefore TxEMTn is always 1 assuming tx is enabled on channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined)
+	SRn: bit 2 (TxRDYn) (we COULD assume since we're not emulating delay and timing output, that as long as tx is enabled on channel n, TxRDY is 1 for channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined; however, tx_ready is already nicely handled for us elsewhere, so we can use that instead for now, though we may need to retool that code as well)
+	SRn: bit 1 (FFULLn) (this bit we actually emulate; if the receive fifo for channel n is full, this bit is 1, otherwise it is 0. the receive fifo should be three words long.)
+	SRn: bit 0 (RxRDYn) (this bit we also emulate; the bit is always asserted if the receive fifo is not empty)
+	ISR: bit 7: Input Port change; this should be handled elsewhere, on the input port handler
+	ISR: bit 6: Delta Break B; this should be handled elsewhere, on the data receive handler
+	ISR: bit 5: RxRDYB/FFULLB: this is handled here; depending on whether MSR1B bit 6 is 0 or 1, this bit holds the state of SRB bit 0 or bit 1 respectively
+	ISR: bit 4: TxRDYB: this is handled here; it mirrors SRB bit 2
+	ISR: bit 3: Counter ready; this should be handled by the timer generator
+	ISR: bit 2: Delta Break A; this should be handled elsewhere, on the data receive handler
+	ISR: bit 1: RxRDYA/FFULLA: this is handled here; depending on whether MSR1A bit 6 is 0 or 1, this bit holds the state of SRA bit 0 or bit 1 respectively
+	ISR: bit 0: TxRDYA: this is handled here; it mirrors SRA bit 2
+	*/
+	if ((ISR & IMR) != 0)
+	{
+		if (!m_irq_state)
+		{
+			m_irq_state = true;
+			LOG("Interrupt line active (IMR & ISR = %02X)\n", (ISR & IMR));
+			write_irq(ASSERT_LINE);
+		}
+	}
+	else
+	{
+		if (m_irq_state)
+		{
+			m_irq_state = false;
+			LOG("Interrupt line not active (IMR & ISR = %02X)\n", ISR & IMR);
+			write_irq(CLEAR_LINE);
+		}
+	}
+	if (OPCR & 0xf0)
+	{
+		if (BIT(OPCR, 4))
+		{
+			if (BIT(ISR, 1))
+				OPR |= 0x10;
+			else
+				OPR &= ~0x10;
+		}
+		if (BIT(OPCR, 5))
+		{
+			if (BIT(ISR, 5))
+				OPR |= 0x20;
+			else
+				OPR &= ~0x20;
+		}
+		if (BIT(OPCR, 6))
+		{
+			if (BIT(ISR, 0))
+				OPR |= 0x40;
+			else
+				OPR &= ~0x40;
+		}
+		if (BIT(OPCR, 7))
+		{
+			if (BIT(ISR, 4))
+				OPR |= 0x80;
+			else
+				OPR &= ~0x80;
+		}
+		write_outport(OPR ^ 0xff);
+	}
+}
+
+void mc68681_device::update_interrupts()
+{
+	duart_base_device::update_interrupts();
+
+	if (!irq_pending())
+		m_read_vector = false;  // clear IACK too
+}
+
+uint8_t mc68681_device::get_irq_vector()
+{
+	if (!machine().side_effects_disabled())
+		m_read_vector = true;
+
+	return IVR;
+}
+
+void mcf5206e_uart_device::update_interrupts()
+{
+	duart_base_device::update_interrupts();
+
+	if (!irq_pending())
+		m_read_vector = false;  // clear IACK too
+}
+
+uint8_t mcf5206e_uart_device::get_irq_vector()
+{
+	if (!machine().side_effects_disabled())
+		m_read_vector = true;
+
+	return IVR;
+}
+
+uint32_t duart_base_device::get_ct_rate()
+{
+	uint32_t rate = 0;
+
+	if (ACR & 0x40)
+	{
+		// Timer mode
+		switch ((ACR >> 4) & 3)
+		{
+		case 0: // IP2
+		case 1: // IP2 / 16
+			//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", duart68681->tag(), (duart68681->ACR >> 4) & 3);
+			rate = clock();
+			break;
+		case 2: // X1/CLK
+			rate = clock();
+			break;
+		case 3: // X1/CLK / 16
+			rate = clock() / 16;
+			break;
+		}
+	}
+	else
+	{
+		// Counter mode
+		switch ((ACR >> 4) & 3)
+		{
+		case 0: // IP2
+			//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", device->tag(), (duart68681->ACR >> 4) & 3);
+			rate = clock();
+			break;
+		case 1: // TxCA
+			rate = m_chanA->get_tx_rate();
+			break;
+		case 2: // TxCB
+			rate = m_chanB->get_tx_rate();
+			break;
+		case 3: // X1/CLK / 16
+			rate = clock() / 16;
+			break;
+		}
+	}
+
+	return rate;
+}
+
+uint16_t duart_base_device::get_ct_count()
+{
+	uint32_t clock = get_ct_rate();
+	return duart_timer->remaining().as_ticks(clock);
+}
+
+void duart_base_device::start_ct(int count)
+{
+	uint32_t clock = get_ct_rate();
+	duart_timer->adjust(attotime::from_ticks(count, clock), 0);
+}
+
+TIMER_CALLBACK_MEMBER(duart_base_device::duart_timer_callback)
+{
+	if (ACR & 0x40)
+	{
+		// Timer mode
+		half_period ^= 1;
+
+		// timer output to bit 3?
+		if ((OPCR & 0xc) == 0x4)
+		{
+			OPR ^= 0x8;
+			write_outport(OPR ^ 0xff);
+		}
+
+		// timer driving any serial channels?
+		uint8_t csr = m_chanA->get_chan_CSR();
+
+		if ((csr & 0x0f) == 0x0d)   // tx is timer driven
+		{
+			m_chanA->tx_16x_clock_w(half_period);
+		}
+		if ((csr & 0xf0) == 0xd0)   // rx is timer driven
+		{
+			m_chanA->rx_16x_clock_w(half_period);
+		}
+
+		csr = m_chanB->get_chan_CSR();
+		if ((csr & 0x0f) == 0x0d)   // tx is timer driven
+		{
+			m_chanB->tx_16x_clock_w(half_period);
+		}
+		if ((csr & 0xf0) == 0xd0)   // rx is timer driven
+		{
+			m_chanB->rx_16x_clock_w(half_period);
+		}
+
+		if (!half_period)
+			set_ISR_bits(INT_COUNTER_READY);
+
+		int count = std::max(CTR.w.l, uint16_t(1));
+		start_ct(count);
+	}
+	else
+	{
+		// assert OP3 counter ready
+		if ((OPCR & 0xc) == 0x4)
+			OPR |= 0x8;
+
+		// Counter mode
+		set_ISR_bits(INT_COUNTER_READY);
+		start_ct(0xffff);
+	}
+
+}
+
+uint8_t mc68681_device::read(offs_t offset)
+{
+	if (offset == 0x0c)
+		return IVR;
+
+	uint8_t r = duart_base_device::read(offset);
+
+	if (offset == 0x0d)
+	{
+		// bit 6 is /IACK (note the active-low)
+		if (m_read_vector)
+			r &= ~0x40;
+		else
+			r |= 0x40;
+	}
+
+	return r;
+}
+
+// TODO: move me out of here, it's one channel per UART not 2
+uint8_t mcf5206e_uart_device::read(offs_t offset)
+{
+	uint8_t r = 0xff;
+
+	switch (offset)
+	{
+	case 0x00: /* UMR1/UMR2 */
+	case 0x01: /* USR */
+	case 0x03: /* URBA Receive Buffer Register */
+	case 0x04: /* UIPCR */
+	case 0x05: /* UISR */
+	case 0x0d: /* UIP */
+		r = duart_base_device::read(offset);
+		break;
+
+	case 0x06: /* UBG Baud Generator Prescale MSB */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = (UBG & 0xFF00) >> 8;
+		break;
+	case 0x07: /* UBG Baud Generator Prescale LSB */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = (UBG & 0x00FF);
+		break;
+
+	case 0x0c:  /* UIVR */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = IVR;
+		break;
+
+	default:
+		LOG("Reading unhandled mcf5206e reg %x\n", offset);
+		break;
+	}
+	LOG("returned %02x\n", r);
+
+	return r;
+}
+
+uint8_t mc68340_duart_device::read(offs_t offset)
+{
+	uint8_t r = 0;
+
+	switch (offset)
+	{
+	case 0x00: /* MR1A - does not share register address with MR2A */
+		r = m_chanA->read_MR1();
+		break;
+	case 0x08: /* MR1B - does not share register address with MR2B */
+		r = m_chanB->read_MR1();
+		break;
+	case 0x10: /* MR2A - does not share register address with MR1A */
+		r = m_chanA->read_MR2();
+		break;
+	case 0x11: /* MR2B - does not share register address with MR1B */
+		r = m_chanB->read_MR2();
+		break;
+	default:
+		r = duart_base_device::read(offset);
+	}
+	return r;
+}
+
+uint8_t sc28c94_device::read(offs_t offset)
+{
+	uint8_t r = 0;
+	offset &= 0x1f;
+
+	if (offset < 0x10)
+	{
+		return duart_base_device::read(offset);
+	}
+
+	switch (offset)
+	{
+	case 0x10: /* MR1A/MR2C */
+	case 0x11: /* SRC */
+	case 0x13: /* Rx Holding Register C */
+		r = m_chanC->read_chan_reg(offset & 3);
+		break;
+
+	case 0x18: /* MR1D/MR2D */
+	case 0x19: /* SRD */
+	case 0x1b: /* RHRD */
+		r = m_chanD->read_chan_reg(offset & 3);
+		break;
+	}
+
+	return r;
+}
+
+uint8_t xr68c681_device::read(offs_t offset)
+{
+	if (offset == 0x02)
+	{
+		LOG("Reading XR68C681 (%s) reg 0x02 (MISR)\n", tag());
+		return ISR & IMR;
+	}
+	else
+		return mc68681_device::read(offset);
+}
+
+uint8_t duart_base_device::read(offs_t offset)
+{
+	uint8_t r = 0xff;
+
+	offset &= 0xf;
+
+	LOG("%s: Reading 68681 (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, duart68681_reg_read_names[offset]);
+
+	switch (offset)
+	{
+	case 0x00: /* MR1A/MR2A */
+	case 0x01: /* SRA */
+	case 0x03: /* Rx Holding Register A */
+		r = m_chanA->read_chan_reg(offset & 3);
+		break;
+
+	case 0x04: /* IPCR */
+		r = IPCR;
+
+		// reading this clears all the input change bits
+		IPCR &= 0x0f;
+		clear_ISR_bits(INT_INPUT_PORT_CHANGE);
+		break;
+
+	case 0x05: /* ISR */
+		r = ISR;
+		break;
+
+	case 0x06: /* CUR */
+		r = get_ct_count() >> 8;
+		break;
+
+	case 0x07: /* CLR */
+		r = get_ct_count() & 0xff;
+		break;
+
+	case 0x08: /* MR1B/MR2B */
+	case 0x09: /* SRB */
+	case 0x0b: /* RHRB */
+		r = m_chanB->read_chan_reg(offset & 3);
+		break;
+
+	case 0x0a: /* 1X/16X Test */
+		r = 0x61;   // the old 68681 returned this and it makes Apollo happy
+		break;
+
+	case 0x0d: /* IP */
+		if (!read_inport.isunset())
+		{
+			r = read_inport();  // TODO: go away
+		}
+		else
+		{
+			r = IP_last_state;
+		}
+
+		r |= 0x80;  // bit 7 is always set
+		break;
+
+	case 0x0e: /* Start counter command */
+	{
+		if (ACR & 0x40)
+		{
+			// Reset the timer
+			half_period = 0;
+		}
+
+		int count = std::max(CTR.w.l, uint16_t(1));
+		start_ct(count);
+		break;
+	}
+
+	case 0x0f: /* Stop counter command */
+
+		// Stop the counter only
+		if (!(ACR & 0x40))
+		{
+			duart_timer->enable(false);
+
+			// clear OP3 counter ready
+			if ((OPCR & 0xc) == 0x4)
+				OPR &= ~0x8;
+		}
+
+		clear_ISR_bits(INT_COUNTER_READY);
+		break;
+
+	default:
+		LOG("Reading unhandled 68681 reg %x\n", offset);
+		break;
+	}
+	LOG("returned %02x\n", r);
+
+	return r;
+}
+
+void mc68681_device::write(offs_t offset, uint8_t data)
+{
+	if (offset == 0x0c)
+		IVR = data;
+	else
+		duart_base_device::write(offset, data);
+}
+
+void mcf5206e_uart_device::write(offs_t offset, uint8_t data)
+{
+	switch (offset)
+	{
+	case 0x00: /* UMR */
+	case 0x01: /* UCSR */
+	case 0x03: /* UTB */
+	case 0x04: /* ACR */    // <-- TODO: This needs changing as ACR on ColdFire only handles interrupt enable for CTS
+	case 0x05: /* IMR */
+	case 0x0e: /* Set Output Port (RTS) Bit */
+	case 0x0f: /* Reset Output Port (RTS) Bit */
+		duart_base_device::write(offset, data);
+		break;
+
+	case 0x02: /* UCR */
+		// monomach uses 0x02 0x03 0x01 0x08 0x0c 0x04 at POST
+		// 3 and c are "Do Not Use" according to datasheet
+		// (already a good reason about not deriving from here ...)
+		if (data != 0xc && data != 0x3)
+			duart_base_device::write(offset, data);
+		break;
+
+	case 0x06: /* UBG1 */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		UBG = (UBG & 0x00ff) | (data << 8);
+		break;
+	case 0x07: /* UBG2 */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		UBG = (UBG & 0xff00) | data;
+		m_chanA->baud_updated();
+		m_chanA->update_interrupts();
+		break;
+
+	case 0x0c: /* UIVR */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		IVR = data;
+		break;
+
+	default: break;
+	}
+}
+
+void mc68340_duart_device::write(offs_t offset, uint8_t data)
+{
+	//printf("Duart write %02x -> %02x\n", data, offset);
+
+	switch(offset)
+	{
+	case 0x00: /* MR1A - does not share register address with MR2A */
+		m_chanA->write_MR1(data);
+		break;
+	case 0x08: /* MR1B - does not share register address with MR2B */
+		m_chanB->write_MR1(data);
+		break;
+	case 0x10: /* MR2A - does not share register address with MR1A */
+		m_chanA->write_MR2(data);
+		break;
+	case 0x11: /* MR2B - does not share register address with MR1B */
+		m_chanB->write_MR2(data);
+		break;
+	default:
+		duart_base_device::write(offset, data);
+	}
+}
+
+void sc28c94_device::write(offs_t offset, uint8_t data)
+{
+	offset &= 0x1f;
+
+	if (offset < 0x10)
+	{
+		duart_base_device::write(offset, data);
+	}
+
+	switch (offset)
+	{
+	case 0x10: /* MRC */
+	case 0x11: /* CSRC */
+	case 0x12: /* CRC */
+	case 0x13: /* THRC */
+		m_chanC->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x18: /* MRC */
+	case 0x19: /* CSRC */
+	case 0x1a: /* CRC */
+	case 0x1b: /* THRC */
+		m_chanD->write_chan_reg(offset&3, data);
+		break;
+	}
+}
+
+void xr68c681_device::write(offs_t offset, uint8_t data)
+{
+	if (offset == 0x02) /* CRA */
+		switch (data >> 4)
+		{
+		case 0x08: /* set RX extend bit */
+			m_XRXA = true;
+			m_chanA->baud_updated();
+			data &= 0x0f; /* disable command before we send it off to 68681 */
+			break;
+
+		case 0x09: /* clear RX extend bit */
+			m_XRXA = false;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0a: /* set TX extend bit */
+			m_XTXA = true;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0b: /* clear TX extend bit */
+			m_XTXA = false;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0c: /* enter low power mode TODO: unimplemented */
+		case 0x0d: /* leave low power mode */
+		case 0x0e: /* reserved */
+		case 0x0f: /* reserved */
+			data &= 0x0f;
+			break;
+		}
+
+	else if (offset == 0x0a) /* CRB */
+		switch (data >> 4)
+		{
+		case 0x08: /* set RX extend bit */
+			m_XRXB = true;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x09: /* clear RX extend bit */
+			m_XRXB = false;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0a: /* set TX extend bit */
+			m_XTXB = true;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0b: /* clear TX extend bit */
+			m_XTXB = false;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0c: /* enter low power mode TODO: unimplemented */
+		case 0x0d: /* leave low power mode */
+		case 0x0e: /* reserved */
+		case 0x0f: /* reserved */
+			data &= 0x0f;
+			break;
+		}
+
+	mc68681_device::write(offset, data); /* pass on 68681 command */
+}
+
+void duart_base_device::write(offs_t offset, uint8_t data)
+{
+	offset &= 0x0f;
+	LOG("%s: Writing 68681 (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, duart68681_reg_write_names[offset], data);
+	switch (offset)
+	{
+	case 0x00: /* MRA */
+	case 0x01: /* CSRA */
+	case 0x02: /* CRA */
+	case 0x03: /* THRA */
+		m_chanA->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x04: /* ACR */
+	{
+		uint8_t old_acr = ACR;
+		ACR = data;
+
+		//       bits 6-4: Counter/Timer Mode And Clock Source Select
+		//       bits 3-0: IP3-0 Change-Of-State Interrupt Enable
+		if ((old_acr ^ data) & 0x40)
+		{
+			if (data & 0x40)
+			{
+				// Entering timer mode
+				uint16_t count = std::max(CTR.w.l, uint16_t(1));
+				half_period = 0;
+
+				start_ct(count);
+			}
+			else
+			{
+				// Leaving timer mode (TODO: is this correct?)
+				duart_timer->adjust(attotime::never);
+			}
+		}
+
+		// check for pending input port delta interrupts
+		if ((((IPCR>>4) & data) & 0x0f) != 0)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+
+		m_chanA->baud_updated();
+		m_chanB->baud_updated();
+		m_chanA->update_interrupts();
+		m_chanB->update_interrupts();
+		break;
+	}
+	case 0x05: /* IMR */
+		IMR = data;
+		update_interrupts();
+		break;
+
+	case 0x06: /* CTUR */
+		CTR.b.h = data;
+		break;
+
+	case 0x07: /* CTLR */
+		CTR.b.l = data;
+		break;
+
+	case 0x08: /* MRB */
+	case 0x09: /* CSRB */
+	case 0x0a: /* CRB */
+	case 0x0b: /* THRB */
+		m_chanB->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x0d: /* OPCR */
+		if (((data & 0xf) != 0x00) && ((data & 0xc) != 0x4))
+			logerror("68681 (%s): Unhandled OPCR value: %02x\n", tag(), data);
+		OPCR = data;
+		break;
+
+	case 0x0e: /* Set Output Port Bits */
+		OPR |= data;
+		write_outport(OPR ^ 0xff);
+		break;
+
+	case 0x0f: /* Reset Output Port Bits */
+		OPR &= ~data;
+		write_outport(OPR ^ 0xff);
+		break;
+	}
+}
+
+void duart_base_device::ip0_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x01) | ((state == ASSERT_LINE) ? 1 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x10;
+
+		if (ACR & 1)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip1_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x02) | ((state == ASSERT_LINE) ? 2 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x20;
+
+		if (ACR & 2)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip2_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x04) | ((state == ASSERT_LINE) ? 4 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x40;
+
+		if (ACR & 4)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip3_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x08) | ((state == ASSERT_LINE) ? 8 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x80;
+
+		if (ACR & 8)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip4_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x10) | ((state == ASSERT_LINE) ? 0x10 : 0);
+// TODO: special mode for ip4 (Ch. A Rx clock)
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip5_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x20) | ((state == ASSERT_LINE) ? 0x20 : 0);
+// TODO: special mode for ip5 (Ch. B Tx clock)
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip6_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x40) | ((state == ASSERT_LINE) ? 0x40 : 0);
+// TODO: special mode for ip6 (Ch. B Rx clock)
+	IP_last_state = newIP;
+}
+
+duart_channel *duart_base_device::get_channel(int chan)
+{
+	if (chan == 0)
+	{
+		return m_chanA;
+	}
+
+	return m_chanB;
+}
+
+int duart_base_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+	if (BIT(ACR, 7) == 0)
+	{
+		baud_rate = baud_rate_ACR_0[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+	else
+	{
+		baud_rate = baud_rate_ACR_1[data & 0x0f];
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int mc68340_duart_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+	if (BIT(ACR, 7) == 0)
+	{
+		baud_rate = baud_rate_ACR_0_340[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+	else
+	{
+		baud_rate = baud_rate_ACR_1_340[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int xr68c681_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+
+	baud_rate = baud_rate_ACR_0[data & 0x0f];
+
+	if (ch == 0)
+	{
+		if ((data & 0x0f) == 0x0e)
+			baud_rate = ip3clk/16;
+		else if ((data & 0x0f) == 0x0f)
+			baud_rate = ip3clk;
+		else if ((rx && m_XRXA) || (!rx && m_XTXA)) /* X = 1 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0_X_1[data & 0x0f] : baud_rate_ACR_1_X_1[data & 0x0f];
+		else /* X = 0 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0[data & 0x0f] : baud_rate_ACR_1[data & 0x0f];
+	}
+	else if (ch == 1)
+	{
+		if ((data & 0x0f) == 0x0e)
+			baud_rate = ip5clk/16;
+		else if ((data & 0x0f) == 0x0f)
+			baud_rate = ip5clk;
+		else if ((rx && m_XRXB) || (!rx && m_XTXB)) /* X = 1 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0_X_1[data & 0x0f] : baud_rate_ACR_1_X_1[data & 0x0f];
+		else /* X = 0 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0[data & 0x0f] : baud_rate_ACR_1[data & 0x0f];
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int mcf5206e_uart_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate = 0;
+	u16 ubg_temp = 1;
+
+	if(UBG > 0) ubg_temp = UBG;
+
+	switch (data & 0xf){
+		case 0xe: baud_rate = ip3clk/16; break;
+		case 0xf: baud_rate = ip3clk; break;
+		case 0xd: baud_rate = (this->clock()/32) / ubg_temp; break;
+		default: LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data); break;
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+void duart_base_device::clear_ISR_bits(int mask)
+{
+	if (ISR & mask)
+	{
+		ISR &= ~mask;
+		update_interrupts();
+	}
+}
+
+void duart_base_device::set_ISR_bits(int mask)
+{
+	if (!(ISR & mask))
+	{
+		ISR |= mask;
+		update_interrupts();
+	}
+}
+
+// DUART channel class stuff
+
+duart_channel::duart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: device_t(mconfig, DUART_CHANNEL, tag, owner, clock)
+	, device_serial_interface(mconfig, *this)
+	, MR1(0)
+	, MR2(0)
+	, SR(0)
+	, rx_enabled(0)
+	, rx_fifo_num(0)
+	, m_rx_line(true)
+	, m_tx_data_in_buffer(false)
+	, m_tx_break(false)
+	, m_bits_transmitted(255)
+	, m_tx_enabled(false)
+{
+	std::fill_n(&rx_fifo[0], MC68681_RX_FIFO_SIZE + 1, 0);
+}
+
+void duart_channel::device_start()
+{
+	m_uart = downcast<duart_base_device *>(owner());
+	m_ch = m_uart->get_ch(this);    // get our channel number
+
+	save_item(NAME(CR));
+	save_item(NAME(CSR));
+	save_item(NAME(MR1));
+	save_item(NAME(MR2));
+	save_item(NAME(MR_ptr));
+	save_item(NAME(SR));
+	save_item(NAME(rx_baud_rate));
+	save_item(NAME(tx_baud_rate));
+	save_item(NAME(rx_enabled));
+	save_item(NAME(rx_fifo));
+	save_item(NAME(rx_fifo_read_ptr));
+	save_item(NAME(rx_fifo_write_ptr));
+	save_item(NAME(rx_fifo_num));
+	save_item(NAME(m_tx_data));
+	save_item(NAME(m_tx_data_in_buffer));
+	save_item(NAME(m_tx_break));
+	save_item(NAME(m_bits_transmitted));
+	save_item(NAME(m_tx_enabled));
+	save_item(NAME(m_rx_line));
+}
+
+// VT1200 NOTE (local change, not upstream): the datasheet latches the overrun
+// error "upon receipt of the start bit of the new (overrunning) character",
+// i.e. while the FIFO is full and the previous character is still held in the
+// receive shift register.  MAME's rx_fifo_push() latches it only when that
+// character is fully received, a whole character late.  Watching the RxD line
+// here reproduces the earlier latch time.  Revert: delete this override, delete
+// the m_rx_line member, and restore the device_serial_interface::rx_w calls in
+// mc68681.h's rx_a_w/rx_b_w/rx_c_w/rx_d_w.
+void duart_channel::rx_w(int state)
+{
+	if (state == 0 && m_rx_line && (rx_fifo_num == MC68681_RX_FIFO_SIZE + 1))
+	{
+		SR |= STATUS_OVERRUN_ERROR;
+		update_interrupts();
+	}
+	m_rx_line = (state != 0);
+	device_serial_interface::rx_w(state);
+}
+
+void duart_channel::device_reset()
+{
+	write_CR(0x10); // reset MR
+	write_CR(0x20); // reset Rx
+	write_CR(0x30); // reset Tx
+	write_CR(0x40); // reset errors
+
+	set_data_frame(1, 8, PARITY_NONE, STOP_BITS_1);
+
+	tx_baud_rate = rx_baud_rate = 0;
+	CSR = 0;
+	m_tx_break = false;
+}
+
+// serial device virtual overrides
+void duart_channel::rcv_complete()
+{
+	receive_register_extract();
+
+	//printf("%s ch %d rcv complete\n", tag(), m_ch);
+
+	if (rx_enabled || (MR2 & 0xc0) == 0x80)
+	{
+		uint8_t errors = 0;
+		if (is_receive_framing_error())
+			errors |= STATUS_FRAMING_ERROR;
+		if (is_receive_parity_error())
+			errors |= STATUS_PARITY_ERROR;
+		rx_fifo_push(get_received_char(), errors);
+	}
+}
+
+void duart_channel::rx_fifo_push(uint8_t data, uint8_t errors)
+{
+	if (rx_fifo_num == (MC68681_RX_FIFO_SIZE + 1))
+	{
+		logerror("68681: FIFO overflow\n");
+		SR |= STATUS_OVERRUN_ERROR;
+		// In case of overrun the FIFO tail entry is overwritten
+		// Back rx_fifo_write_ptr up by one position
+		if (rx_fifo_write_ptr)
+			rx_fifo_write_ptr--;
+		else
+			rx_fifo_write_ptr = MC68681_RX_FIFO_SIZE;
+	}
+
+	rx_fifo[rx_fifo_write_ptr++] = data | (errors << 8);
+	if (rx_fifo_write_ptr > MC68681_RX_FIFO_SIZE)
+		rx_fifo_write_ptr = 0;
+
+	if (rx_fifo_num <= MC68681_RX_FIFO_SIZE)
+	{
+		rx_fifo_num++;
+	}
+
+	if (rx_fifo_num == 1)
+	{
+		SR |= STATUS_RECEIVER_READY;
+		if (!(MR1 & MODE_BLOCK_ERROR))
+			SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+		SR |= errors;
+	}
+	if (rx_fifo_num == MC68681_RX_FIFO_SIZE)
+		SR |= STATUS_FIFO_FULL;
+	update_interrupts();
+}
+
+void duart_channel::tra_complete()
+{
+	// The transmit shift register has just emptied.  If another character is
+	// waiting in the THR, transfer it to the shift register and assert TxRDY:
+	// per the datasheet the THR->shift transfer is where the TxRDY conditions
+	// are re-asserted, providing "one full character time of buffering".  If the
+	// THR is empty the transmitter is now idle, so set TxEMT (TxRDY is already
+	// set from the previous transfer).
+	//
+	// Asserting TxRDY here, at the transfer -- rather than in the idle branch --
+	// both prevents the transmitter from deadlocking when TxRDY would otherwise
+	// fail to re-assert on a CPU-write / final-bit-time race, and preserves the
+	// one-character buffering window that firmware polling or pipelining on TxRDY
+	// relies on.
+	if (m_tx_data_in_buffer)
+	{
+		transmit_register_setup(m_tx_data);
+		m_bits_transmitted = 0;
+		m_tx_data_in_buffer = false;
+		SR |= STATUS_TRANSMITTER_READY;
+		update_interrupts();
+	}
+	else
+	{
+		SR |= STATUS_TRANSMITTER_EMPTY;
+		// VT1200 NOTE (local change, not upstream): also assert TxRDY here.  The
+		// VT1200 level-1 host-port test runs an interrupt-driven loopback: the
+		// DUART ISR writes the pattern byte on TxRDYA and, per transmit, reads
+		// SRA and expects the RX FIFO to have filled in step (FFULL before the
+		// 5th byte, OVR after it).  Asserting TxRDY mid-character (see the
+		// removed block in tra_callback below) made the ISR one byte ahead of
+		// the receiver, so the snapshots were FFULL/OVR one index too late and
+		// the test failed.  Asserting TxRDY when the shift register empties
+		// (the THR->TSR transfer point) makes the ISR pace one byte per
+		// character.  Revert: delete the STATUS_TRANSMITTER_READY term below
+		// and restore the removed block in tra_callback.
+		SR |= STATUS_TRANSMITTER_READY;
+		update_interrupts();
+	}
+}
+
+void duart_channel::tra_callback()
+{
+	// don't actually send in loopback mode
+	if ((MR2 & 0xc0) != 0x80)
+	{
+		int bit = transmit_register_get_data_bit();
+		//printf("%s ch %d transmit %d\n", tag(), m_ch, bit);
+		if (m_ch == 0)
+		{
+			m_uart->write_a_tx(bit);
+		}
+		else if (m_ch == 1)
+		{
+			m_uart->write_b_tx(bit);
+		}
+		else if (m_ch == 2)
+		{
+			m_uart->write_c_tx(bit);
+		}
+		else if (m_ch == 3)
+		{
+			m_uart->write_d_tx(bit);
+		}
+	}
+	else
+	{
+		// loop back transmitted bit
+		rx_w(transmit_register_get_data_bit());
+	}
+
+	// VT1200 NOTE (local change, not upstream): the upstream code asserted
+	// TxRDY here ("not until the end of start bit time") when no byte was
+	// buffered.  The datasheet instead asserts TxRDY at the THR->TSR transfer
+	// ("Data is transferred from the holding register to transmit shift
+	// register when it is idle or has completed transmission of the previous
+	// character.  The TxRDY conditions are then asserted again"), which is the
+	// character boundary for a buffered byte -- not mid-character.  Asserting
+	// on the start bit made the VT1200 loopback test's ISR run one byte ahead
+	// of the receiver.  Revert: remove the increment below and restore
+	//   if (m_bits_transmitted++ > 0 && !m_tx_data_in_buffer && m_tx_enabled)
+	//   {
+	//       SR |= STATUS_TRANSMITTER_READY;
+	//       update_interrupts();
+	//   }
+	m_bits_transmitted++;
+}
+
+void duart_channel::update_interrupts()
+{
+	// Handle the TxEMT and TxRDY bits based on mode
+	switch (MR2 & 0xc0) // what mode are we in?
+	{
+	case 0x00: // normal mode
+		break;
+	case 0x40: // automatic echo mode
+		SR &= ~STATUS_TRANSMITTER_READY;
+		break;
+	case 0x80: // local loopback mode
+		break;
+	case 0xc0: // remote loopback mode
+		SR &= ~STATUS_TRANSMITTER_READY;
+		break;
+	}
+
+	// now handle the ISR bits
+	if (SR & STATUS_TRANSMITTER_READY)
+	{
+		if (m_ch == 0)
+			m_uart->set_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->set_ISR_bits(INT_TXRDYB);
+	}
+	else
+	{
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+	}
+	//logerror("DEBUG: 68681 int check: before receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
+	if (MR1 & MODE_RX_INT_SELECT_BIT)
+	{
+		if (SR & STATUS_FIFO_FULL)
+		{
+			m_uart->set_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+		else
+		{
+			m_uart->clear_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+	}
+	else
+	{
+		if (SR & STATUS_RECEIVER_READY)
+		{
+			m_uart->set_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+		else
+		{
+			m_uart->clear_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+	}
+
+	//logerror("DEBUG: 68681 int check: after receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
+}
+
+uint8_t duart_channel::read_rx_fifo()
+{
+	uint8_t rv;
+
+	//printf("read_rx_fifo: rx_fifo_num %d\n", rx_fifo_num);
+
+	if (rx_fifo_num == 0)
+	{
+		LOG("68681 channel: rx fifo underflow\n");
+		update_interrupts();
+		return 0;
+	}
+
+	rv = rx_fifo[rx_fifo_read_ptr++];
+	if (rx_fifo_read_ptr > MC68681_RX_FIFO_SIZE)
+	{
+		rx_fifo_read_ptr = 0;
+	}
+
+	rx_fifo_num--;
+	if (rx_fifo_num == (MC68681_RX_FIFO_SIZE - 1))
+	{
+		SR &= ~STATUS_FIFO_FULL;
+	}
+
+	if (!(MR1 & MODE_BLOCK_ERROR))
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+	if (rx_fifo_num == 0)
+		SR &= ~STATUS_RECEIVER_READY;
+	else
+		SR |= rx_fifo[rx_fifo_read_ptr] >> 8;
+	update_interrupts();
+
+	//printf("Rx read %02x\n", rv);
+
+	return rv;
+}
+
+uint8_t duart_channel::read_chan_reg(int reg)
+{
+	uint8_t rv = 0xff;
+
+	switch (reg)
+	{
+	case 0: // MR1/MR2
+		if (MR_ptr == 0)
+		{
+			rv = MR1;
+			MR_ptr = 1;
+		}
+		else
+		{
+			rv = MR2;
+		}
+		break;
+
+	case 1: // SRA
+		rv = SR;
+		break;
+
+	case 2: // CSRA: reading this is prohibited
+		break;
+
+	case 3: // Rx holding register A
+		rv = read_rx_fifo();
+		break;
+	}
+
+	return rv;
+}
+
+void duart_channel::write_chan_reg(int reg, uint8_t data)
+{
+	switch (reg)
+	{
+	case 0x00: /* MRA */
+		write_MR(data);
+		break;
+
+	case 0x01: /* CSR */
+		CSR = data;
+		tx_baud_rate = m_uart->calc_baud(m_ch, false, data & 0xf);
+		rx_baud_rate = m_uart->calc_baud(m_ch, true, (data>>4) & 0xf);
+		//printf("%s ch %d CSR %02x Tx baud %d Rx baud %d\n", tag(), m_ch, data, tx_baud_rate, rx_baud_rate);
+		set_rcv_rate(rx_baud_rate);
+		set_tra_rate(tx_baud_rate);
+		break;
+
+	case 0x02: /* CR */
+		write_CR(data);
+		break;
+
+	case 0x03: /* THR */
+		write_TX(data);
+		break;
+	}
+}
+
+void duart_channel::write_MR(uint8_t data)
+{
+	if (MR_ptr == 0)
+	{
+		MR1 = data;
+		MR_ptr = 1;
+	}
+	else
+	{
+		MR2 = data;
+	}
+	recalc_framing();
+	update_interrupts();
+}
+
+void duart_channel::recalc_framing()
+{
+	parity_t parity = PARITY_NONE;
+	switch ((MR1 >> 3) & 3)
+	{
+	case 0: // with parity
+		if (MR1 & 4)
+			parity = PARITY_ODD;
+		else
+			parity = PARITY_EVEN;
+		break;
+
+	case 1: // force parity
+		if (MR1 & 4)
+			parity = PARITY_MARK;
+		else
+			parity = PARITY_SPACE;
+		break;
+
+	case 2: // no parity
+		parity = PARITY_NONE;
+		break;
+
+	case 3: // multidrop mode
+		// fatalerror("68681: multidrop parity not supported\n");
+		// Apollo DEX CPU will test this; omit to abort the emulation
+		logerror("68681: multidrop parity not supported\n");
+		break;
+	}
+
+	stop_bits_t stopbits = STOP_BITS_0;
+	switch ((MR2 >> 2) & 3)
+	{
+	case 0:
+	case 1:
+		stopbits = STOP_BITS_1;
+		break;
+
+	case 2: // "1.5 async, 2 sync"
+		stopbits = STOP_BITS_1_5;
+		break;
+
+	case 3:
+		stopbits = STOP_BITS_2;
+		break;
+	}
+
+	//printf("%s ch %d MR1 %02x MR2 %02x => %d bits / char, %d stop bits, parity %d\n", tag(), m_ch, MR1, MR2, (MR1 & 3)+5, stopbits, parity);
+
+	set_data_frame(1, (MR1 & 3) + 5, parity, stopbits);
+}
+
+void duart_channel::write_CR(uint8_t data)
+{
+	switch ((data >> 4) & 0x07)
+	{
+	case 0: /* No command */
+		break;
+	case 1: /* Reset MR pointer. Causes the channel MR pointer to point to MR1 */
+		MR_ptr = 0;
+		break;
+	case 2: /* Reset channel receiver (disable receiver and flush fifo) */
+		rx_enabled = 0;
+		SR &= ~STATUS_RECEIVER_READY;
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+		SR &= ~STATUS_OVERRUN_ERROR; // is this correct?
+		rx_fifo_read_ptr = 0;
+		rx_fifo_write_ptr = 0;
+		rx_fifo_num = 0;
+		receive_register_reset();
+		break;
+	case 3: /* Reset channel transmitter */
+		SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+		if (m_ch == 0)
+		{
+			m_uart->write_a_tx(1);
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		}
+		else
+		{
+			m_uart->write_b_tx(1);
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+		}
+		transmit_register_reset();
+		m_bits_transmitted = 255;
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = false;
+		break;
+	case 4: /* Reset Error Status */
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR | STATUS_OVERRUN_ERROR);
+		break;
+	case 5: /* Reset Channel break change interrupt */
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_DELTA_BREAK_A);
+		else
+			m_uart->clear_ISR_bits(INT_DELTA_BREAK_B);
+		break;
+	case 6: /* Start Tx break */
+		if (!m_tx_break)
+		{
+			m_tx_break = true;
+			if ((MR2 & 0xc0) == 0x80)
+			{
+				// Local loopback mode: set delta break in ISR, simulate break rx
+				if (m_ch == 0)
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_A);
+				else
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_B);
+				rx_fifo_push(0 , STATUS_RECEIVED_BREAK);
+			}
+			// TODO: Actually send break signal
+		}
+		break;
+	case 7: /* Stop tx break */
+		if (m_tx_break)
+		{
+			m_tx_break = false;
+			if ((MR2 & 0xc0) == 0x80)
+			{
+				// Local loopback mode: set delta break in ISR
+				if (m_ch == 0)
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_A);
+				else
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_B);
+			}
+		}
+		break;
+	default:
+		LOG("68681: Unhandled command (%x) in CR%d\n", (data >> 4) & 0x07, m_ch);
+		break;
+	}
+
+	if (BIT(data, 0))
+	{
+		rx_enabled = 1;
+	}
+	if (BIT(data, 1))
+	{
+		rx_enabled = 0;
+		SR &= ~STATUS_RECEIVER_READY;
+	}
+
+	if (!BIT(CR, 2) && BIT(data, 2))
+	{
+		SR |= STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY;
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = true;
+		if (m_ch == 0)
+			m_uart->set_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->set_ISR_bits(INT_TXRDYB);
+	}
+	if (BIT(data, 3))
+	{
+		SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = false;
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+	}
+
+	update_interrupts();
+	CR = data;
+}
+
+void duart_channel::write_TX(uint8_t data)
+{
+	if (!(SR & STATUS_TRANSMITTER_READY))
+	{
+		logerror("write_tx transmitter not ready (data 0x%02x discarded)\n", data);
+		return;
+	}
+
+	SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+	if (!is_transmit_register_empty())
+	{
+		m_tx_data = data;
+		m_tx_data_in_buffer = true;
+	}
+	else
+	{
+		transmit_register_setup(data);
+		m_bits_transmitted = 0;
+	}
+
+	update_interrupts();
+}
+
+void duart_channel::baud_updated()
+{
+	write_chan_reg(1, CSR);
+}
+
+uint8_t duart_channel::get_chan_CSR()
+{
+	return CSR;
+}
+
+void duart_channel::tx_16x_clock_w(bool state)
+{
+	if (state)
+	{
+		m_tx_prescaler--;
+		if (m_tx_prescaler == 8)
+		{
+			tx_clock_w(true);
+		}
+		else if (m_tx_prescaler == 0)
+		{
+			m_tx_prescaler = 16;
+			tx_clock_w(false);
+		}
+	}
+}
+
+void duart_channel::rx_16x_clock_w(bool state)
+{
+	if (!is_receive_register_synchronized())
+	{
+		// Skip over the start bit once synchonization is achieved
+		m_rx_prescaler = 32;
+		rx_clock_w(true);
+	}
+	else if (state)
+	{
+		m_rx_prescaler--;
+		if (m_rx_prescaler == 8)
+		{
+			rx_clock_w(false);
+		}
+		else if (m_rx_prescaler == 0)
+		{
+			m_rx_prescaler = 16;
+			rx_clock_w(true);
+		}
+	}
+}
diff --git a/harness/mame/mame_edits/mc68681.cpp.cfg2 b/harness/mame/mame_edits/mc68681.cpp.cfg2
new file mode 100644
index 0000000..15511cf
--- /dev/null
+++ b/harness/mame/mame_edits/mc68681.cpp.cfg2
@@ -0,0 +1,1927 @@
+// license:BSD-3-Clause
+// copyright-holders:Mariusz Wojcieszek, R. Belmont, Joseph Zatarski
+/*
+    2681 DUART
+    68681 DUART
+    28C94 QUART
+    68340 serial module
+    XR68C681 DUART (backwards compatible with 68681 with some improvements)
+
+    Written by Mariusz Wojcieszek
+    Updated by Jonathan Gevaryahu AKA Lord Nightmare
+    Improved interrupt handling by R. Belmont
+    Rewrite and modernization in progress by R. Belmont
+    Addition of the duart compatible 68340 serial module support by Edstrom
+    Support for the Exar XR68C681 by Joseph Zatarski (July of 2018)
+    Support for Freescale/NXP ColdFire UART module by NaokiS (June 2025)
+
+    The main incompatibility between the 2681 and 68681 (Signetics and Motorola each
+    manufactured both versions of the chip) is that the 68681 has a R/W input and
+    generates a 68000-compatible DTACK signal, instead of using generic RD and WR
+    strobes as the 2681 does. The 68681 also adds a programmable interrupt vector,
+    with an IACK input replacing IP6.
+
+    The command register addresses should never be read from. Doing so may place
+    the baud rate generator into a test mode which drives the parallel outputs with
+    internal counters and causes serial ports to operate at uncontrollable rates.
+
+    Exar XR68C681
+
+    The XR68C681 is an improvement upon the MC68681 which supports more baud
+    rates, adds an additional MISR (masked ISR) register, and adds a low-power
+    standby mode. There may be other differences, but these are the most
+    notable.
+
+    The extra baud rates are implemented by an 'X' bit for each channel. The X
+    bit chooses between two baud rate tables, in addition to the ACR[7] bit.
+    The X bit is changed by additional commands that are written to CRA and CRB.
+
+    The MISR is a read only register that takes the place of the 'BRG Test'
+    register on the MC68681.
+
+    The low power standby mode is entered and left by a command written to CRA
+    or CRB registers. Writing the commands to either register affects the whole
+    DUART, not just one channel. Resetting the DUART also leaves low power mode.
+
+    On the ColdFire MCF5206e, the UART modules are essentially just a pair of
+    MC68681s with only the A port visible and no counter/timer. The ACR on the
+    coldfire uarts shoud be updated to reflect this. Additionally, the
+    Baud Rate Generator prescaler reg should be used to set the baud.
+*/
+
+#include "emu.h"
+#include "mc68681.h"
+
+#include <algorithm>
+
+//#define VERBOSE 1
+//#define LOG_OUTPUT_FUNC printf
+#include "logmacro.h"
+
+
+static const char *const duart68681_reg_read_names[0x10] =
+{
+	"MRA", "SRA", "BRG Test", "RHRA", "IPCR", "ISR", "CTU", "CTL", "MRB", "SRB", "1X/16X Test", "RHRB", "IVR", "Input Ports", "Start Counter", "Stop Counter"
+};
+
+static const char *const duart68681_reg_write_names[0x10] =
+{
+	"MRA", "CSRA", "CRA", "THRA", "ACR", "IMR", "CTUR", "CTLR", "MRB", "CSRB", "CRB", "THRB", "IVR", "OPCR", "Set OP Bits", "Reset OP Bits"
+};
+
+static const char *const mcf5206e_duart_reg_read_names[0x10] =
+{
+	"UMR", "USR", "NO ACCESS", "URB", "UIPCR", "UISR", "UBG1", "UBG2", "NO ACCESS", "NO ACCESS", "NO ACCESS", "NO ACCESS", "UIVR", "UIP Input Ports", "NO ACCESS", "NO ACCESS"
+};
+
+static const char *const mcf5206e_duart_reg_write_names[0x10] =
+{
+	"UMR", "UCSR", "UCRA", "UTB", "UACR", "UIMR", "UBG1", "UBG2", "NO ACCESS", "NO ACCESS", "NO ACCESS", "NO ACCESS", "IVR", "NO ACCESS", "Set OP Bits", "Reset OP Bits"
+};
+
+static const int baud_rate_ACR_0[] =     { 50, 110, 134, 200, 300,  600,   1200,  1050,  2400,   4800, 7200, 9600, 38400, 0, 0, 0 }; /* xr68c681 X=0 */
+static const int baud_rate_ACR_0_X_1[] = { 75, 110, 134, 150, 3600, 14400, 28800, 57600, 115200, 4800, 1800, 9600, 19200, 0, 0, 0 };
+static const int baud_rate_ACR_1[] =     { 75, 110, 134, 150, 300,  600,   1200,  2000,  2400,   4800, 1800, 9600, 19200, 0, 0, 0 }; /* xr68c681 X=0 */
+static const int baud_rate_ACR_1_X_1[] = { 50, 110, 134, 200, 3600, 14400, 28800, 57600, 115200, 4800, 7200, 9600, 38400, 0, 0, 0 };
+
+static const int baud_rate_ACR_0_340[] = { 50, 110, 134, 200, 300,  600,   1200,  1050,  2400,   4800, 7200, 9600, 38400, 76800, 0, 0 }; /* xr68c681 ACR:7=0 */
+static const int baud_rate_ACR_1_340[] = { 75, 110, 134, 150, 300,  600,   1200,  2000,  2400,   4800, 1800, 9600, 19200, 38400, 0, 0 }; /* xr68c681 ACR:7=1 */
+
+#define INT_INPUT_PORT_CHANGE       0x80
+#define INT_DELTA_BREAK_B           0x40
+#define INT_RXRDY_FFULLB            0x20
+#define INT_TXRDYB                  0x10
+#define INT_COUNTER_READY           0x08
+#define INT_DELTA_BREAK_A           0x04
+#define INT_RXRDY_FFULLA            0x02
+#define INT_TXRDYA                  0x01
+
+#define STATUS_RECEIVED_BREAK       0x80
+#define STATUS_FRAMING_ERROR        0x40
+#define STATUS_PARITY_ERROR         0x20
+#define STATUS_OVERRUN_ERROR        0x10
+#define STATUS_TRANSMITTER_EMPTY    0x08
+#define STATUS_TRANSMITTER_READY    0x04
+#define STATUS_FIFO_FULL            0x02
+#define STATUS_RECEIVER_READY       0x01
+
+#define MODE_RX_INT_SELECT_BIT      0x40
+#define MODE_BLOCK_ERROR            0x20
+
+#define CHANA_TAG   "cha"
+#define CHANB_TAG   "chb"
+#define CHANC_TAG   "chc"
+#define CHAND_TAG   "chd"
+
+// device type definition
+DEFINE_DEVICE_TYPE(SCN2681, scn2681_device, "scn2681", "SCN2681 DUART")
+DEFINE_DEVICE_TYPE(MC68681, mc68681_device, "mc68681", "MC68681 DUART")
+DEFINE_DEVICE_TYPE(MCF5206E_UART, mcf5206e_uart_device, "mcf5206euart", "MCF5206e UART")
+DEFINE_DEVICE_TYPE(SC28C94, sc28c94_device, "sc28c94", "SC28C94 QUART")
+DEFINE_DEVICE_TYPE(MC68340_DUART, mc68340_duart_device, "mc68340duart", "MC68340 DUART")
+DEFINE_DEVICE_TYPE(XR68C681, xr68c681_device, "xr68c681", "XR68C681 DUART")
+DEFINE_DEVICE_TYPE(DUART_CHANNEL, duart_channel, "duart_channel", "DUART channel")
+
+
+//**************************************************************************
+//  LIVE DEVICE
+//**************************************************************************
+
+duart_base_device::duart_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, type, tag, owner, clock),
+	m_chanA(*this, CHANA_TAG),
+	m_chanB(*this, CHANB_TAG),
+	m_chanC(*this, CHANC_TAG),
+	m_chanD(*this, CHAND_TAG),
+	write_irq(*this),
+	write_a_tx(*this),
+	write_b_tx(*this),
+	write_c_tx(*this),
+	write_d_tx(*this),
+	read_inport(*this, 0),
+	write_outport(*this),
+	ip3clk(0),
+	ip4clk(0),
+	ip5clk(0),
+	ip6clk(0),
+	ACR(0),
+	IP_last_state(0)
+{
+}
+
+scn2681_device::scn2681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, SCN2681, tag, owner, clock)
+{
+}
+
+mc68681_device::mc68681_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+	, m_read_vector(false)
+{
+}
+
+mc68681_device::mc68681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68681_device(mconfig, MC68681, tag, owner, clock)
+{
+}
+
+mcf5206e_uart_device::mcf5206e_uart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+	, m_read_vector(false)
+{
+}
+
+mcf5206e_uart_device::mcf5206e_uart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, MCF5206E_UART, tag, owner, clock)
+{
+}
+
+
+sc28c94_device::sc28c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, SC28C94, tag, owner, clock)
+{
+}
+
+//--------------------------------------------------------------------------------------------------------------------
+// The read and write methods are meant to catch all differences in the register model between 68681 and 68340
+// serial module. Eg some registers are (re)moved into the 68340 like the vector register. There are also no counter
+// in the 68340. The CSR clock register is also different for the external clock modes. The implementation assumes
+// that the code knows all of this and will not warn if those registers are accessed as it could be ported code.
+// TODO: A lot of subtle differences and also detect misuse of unavailable registers as they should be ignored
+//--------------------------------------------------------------------------------------------------------------------
+mc68340_duart_device::mc68340_duart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+{
+}
+
+mc68340_duart_device::mc68340_duart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68340_duart_device(mconfig, MC68340_DUART, tag, owner, clock)
+{
+}
+
+xr68c681_device::xr68c681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68681_device(mconfig, XR68C681, tag, owner, clock)
+	, m_XTXA(false)
+	, m_XRXA(false)
+	, m_XTXB(false)
+	, m_XRXB(false)
+{
+}
+
+//-------------------------------------------------
+//  set_clocks - configuration helper to set
+//  the external clocks
+//-------------------------------------------------
+
+void duart_base_device::set_clocks(int clk3, int clk4, int clk5, int clk6)
+{
+	ip3clk = clk3;
+	ip4clk = clk4;
+	ip5clk = clk5;
+	ip6clk = clk6;
+}
+
+/*-------------------------------------------------
+    device start callback
+-------------------------------------------------*/
+
+void duart_base_device::device_start()
+{
+	duart_timer = timer_alloc(FUNC(duart_base_device::duart_timer_callback), this);
+
+	save_item(NAME(ACR));
+	save_item(NAME(IMR));
+	save_item(NAME(ISR));
+	save_item(NAME(OPCR));
+	save_item(NAME(OPR));
+	save_item(NAME(CTR));
+	save_item(NAME(IPCR));
+	save_item(NAME(IP_last_state));
+	save_item(NAME(half_period));
+	save_item(NAME(m_irq_state));
+}
+
+void mc68681_device::device_start()
+{
+	duart_base_device::device_start();
+
+	save_item(NAME(m_read_vector));
+	save_item(NAME(IVR));
+}
+
+void mcf5206e_uart_device::device_start()
+{
+	duart_base_device::device_start();
+
+	save_item(NAME(m_read_vector));
+	save_item(NAME(IVR));
+	save_item(NAME(UBG));
+}
+
+void xr68c681_device::device_start()
+{
+	mc68681_device::device_start();
+
+	save_item(NAME(m_XTXA));
+	save_item(NAME(m_XRXA));
+	save_item(NAME(m_XTXB));
+	save_item(NAME(m_XRXB));
+}
+
+/*-------------------------------------------------
+    device reset callback
+-------------------------------------------------*/
+
+void duart_base_device::device_reset()
+{
+	ACR = 0;  /* Interrupt Vector Register */
+	IMR = 0;  /* Interrupt Mask Register */
+	ISR = 0;  /* Interrupt Status Register */
+	OPCR = 0; /* Output Port Conf. Register */
+	OPR = 0;  /* Output Port Register */
+	CTR.d = 0;  /* Counter/Timer Preset Value */
+	// "reset clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR) puts OP0-7 in the high state, stops the counter/timer, and puts channels a/b in the inactive state"
+	IPCR = 0;
+
+	m_irq_state = false;
+	write_irq(CLEAR_LINE);
+	write_outport(OPR ^ 0xff);
+}
+
+void mc68681_device::device_reset()
+{
+	duart_base_device::device_reset();
+
+	IVR = 0x0f;  /* Interrupt Vector Register */
+	m_read_vector = false;
+}
+
+void mcf5206e_uart_device::device_reset()
+{
+	duart_base_device::device_reset();
+
+	IVR = 0x0f;  /* Interrupt Vector Register */
+	UBG = 0x00;  /* UART Baud Rate Generator Register */
+	m_read_vector = false;
+}
+
+void xr68c681_device::device_reset()
+{
+	mc68681_device::device_reset();
+
+	m_XTXA = m_XRXA = m_XTXB = m_XRXB = false;
+}
+
+void duart_base_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void sc28c94_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+	DUART_CHANNEL(config, CHANC_TAG);
+	DUART_CHANNEL(config, CHAND_TAG);
+}
+
+void mc68340_duart_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void mcf5206e_uart_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void duart_base_device::update_interrupts()
+{
+	/* update SR state and update interrupt ISR state for the following bits:
+	SRn: bits 7-4: handled elsewhere.
+	SRn: bit 3 (TxEMTn) (we can assume since we're not actually emulating the delay/timing of sending bits, that as long as TxRDYn is set, TxEMTn is also set since the transmit byte has 'already happened', therefore TxEMTn is always 1 assuming tx is enabled on channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined)
+	SRn: bit 2 (TxRDYn) (we COULD assume since we're not emulating delay and timing output, that as long as tx is enabled on channel n, TxRDY is 1 for channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined; however, tx_ready is already nicely handled for us elsewhere, so we can use that instead for now, though we may need to retool that code as well)
+	SRn: bit 1 (FFULLn) (this bit we actually emulate; if the receive fifo for channel n is full, this bit is 1, otherwise it is 0. the receive fifo should be three words long.)
+	SRn: bit 0 (RxRDYn) (this bit we also emulate; the bit is always asserted if the receive fifo is not empty)
+	ISR: bit 7: Input Port change; this should be handled elsewhere, on the input port handler
+	ISR: bit 6: Delta Break B; this should be handled elsewhere, on the data receive handler
+	ISR: bit 5: RxRDYB/FFULLB: this is handled here; depending on whether MSR1B bit 6 is 0 or 1, this bit holds the state of SRB bit 0 or bit 1 respectively
+	ISR: bit 4: TxRDYB: this is handled here; it mirrors SRB bit 2
+	ISR: bit 3: Counter ready; this should be handled by the timer generator
+	ISR: bit 2: Delta Break A; this should be handled elsewhere, on the data receive handler
+	ISR: bit 1: RxRDYA/FFULLA: this is handled here; depending on whether MSR1A bit 6 is 0 or 1, this bit holds the state of SRA bit 0 or bit 1 respectively
+	ISR: bit 0: TxRDYA: this is handled here; it mirrors SRA bit 2
+	*/
+	if ((ISR & IMR) != 0)
+	{
+		if (!m_irq_state)
+		{
+			m_irq_state = true;
+			LOG("Interrupt line active (IMR & ISR = %02X)\n", (ISR & IMR));
+			write_irq(ASSERT_LINE);
+		}
+	}
+	else
+	{
+		if (m_irq_state)
+		{
+			m_irq_state = false;
+			LOG("Interrupt line not active (IMR & ISR = %02X)\n", ISR & IMR);
+			write_irq(CLEAR_LINE);
+		}
+	}
+	if (OPCR & 0xf0)
+	{
+		if (BIT(OPCR, 4))
+		{
+			if (BIT(ISR, 1))
+				OPR |= 0x10;
+			else
+				OPR &= ~0x10;
+		}
+		if (BIT(OPCR, 5))
+		{
+			if (BIT(ISR, 5))
+				OPR |= 0x20;
+			else
+				OPR &= ~0x20;
+		}
+		if (BIT(OPCR, 6))
+		{
+			if (BIT(ISR, 0))
+				OPR |= 0x40;
+			else
+				OPR &= ~0x40;
+		}
+		if (BIT(OPCR, 7))
+		{
+			if (BIT(ISR, 4))
+				OPR |= 0x80;
+			else
+				OPR &= ~0x80;
+		}
+		write_outport(OPR ^ 0xff);
+	}
+}
+
+void mc68681_device::update_interrupts()
+{
+	duart_base_device::update_interrupts();
+
+	if (!irq_pending())
+		m_read_vector = false;  // clear IACK too
+}
+
+uint8_t mc68681_device::get_irq_vector()
+{
+	if (!machine().side_effects_disabled())
+		m_read_vector = true;
+
+	return IVR;
+}
+
+void mcf5206e_uart_device::update_interrupts()
+{
+	duart_base_device::update_interrupts();
+
+	if (!irq_pending())
+		m_read_vector = false;  // clear IACK too
+}
+
+uint8_t mcf5206e_uart_device::get_irq_vector()
+{
+	if (!machine().side_effects_disabled())
+		m_read_vector = true;
+
+	return IVR;
+}
+
+uint32_t duart_base_device::get_ct_rate()
+{
+	uint32_t rate = 0;
+
+	if (ACR & 0x40)
+	{
+		// Timer mode
+		switch ((ACR >> 4) & 3)
+		{
+		case 0: // IP2
+		case 1: // IP2 / 16
+			//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", duart68681->tag(), (duart68681->ACR >> 4) & 3);
+			rate = clock();
+			break;
+		case 2: // X1/CLK
+			rate = clock();
+			break;
+		case 3: // X1/CLK / 16
+			rate = clock() / 16;
+			break;
+		}
+	}
+	else
+	{
+		// Counter mode
+		switch ((ACR >> 4) & 3)
+		{
+		case 0: // IP2
+			//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", device->tag(), (duart68681->ACR >> 4) & 3);
+			rate = clock();
+			break;
+		case 1: // TxCA
+			rate = m_chanA->get_tx_rate();
+			break;
+		case 2: // TxCB
+			rate = m_chanB->get_tx_rate();
+			break;
+		case 3: // X1/CLK / 16
+			rate = clock() / 16;
+			break;
+		}
+	}
+
+	return rate;
+}
+
+uint16_t duart_base_device::get_ct_count()
+{
+	uint32_t clock = get_ct_rate();
+	return duart_timer->remaining().as_ticks(clock);
+}
+
+void duart_base_device::start_ct(int count)
+{
+	uint32_t clock = get_ct_rate();
+	duart_timer->adjust(attotime::from_ticks(count, clock), 0);
+}
+
+TIMER_CALLBACK_MEMBER(duart_base_device::duart_timer_callback)
+{
+	if (ACR & 0x40)
+	{
+		// Timer mode
+		half_period ^= 1;
+
+		// timer output to bit 3?
+		if ((OPCR & 0xc) == 0x4)
+		{
+			OPR ^= 0x8;
+			write_outport(OPR ^ 0xff);
+		}
+
+		// timer driving any serial channels?
+		uint8_t csr = m_chanA->get_chan_CSR();
+
+		if ((csr & 0x0f) == 0x0d)   // tx is timer driven
+		{
+			m_chanA->tx_16x_clock_w(half_period);
+		}
+		if ((csr & 0xf0) == 0xd0)   // rx is timer driven
+		{
+			m_chanA->rx_16x_clock_w(half_period);
+		}
+
+		csr = m_chanB->get_chan_CSR();
+		if ((csr & 0x0f) == 0x0d)   // tx is timer driven
+		{
+			m_chanB->tx_16x_clock_w(half_period);
+		}
+		if ((csr & 0xf0) == 0xd0)   // rx is timer driven
+		{
+			m_chanB->rx_16x_clock_w(half_period);
+		}
+
+		if (!half_period)
+			set_ISR_bits(INT_COUNTER_READY);
+
+		int count = std::max(CTR.w.l, uint16_t(1));
+		start_ct(count);
+	}
+	else
+	{
+		// assert OP3 counter ready
+		if ((OPCR & 0xc) == 0x4)
+			OPR |= 0x8;
+
+		// Counter mode
+		set_ISR_bits(INT_COUNTER_READY);
+		start_ct(0xffff);
+	}
+
+}
+
+uint8_t mc68681_device::read(offs_t offset)
+{
+	if (offset == 0x0c)
+		return IVR;
+
+	uint8_t r = duart_base_device::read(offset);
+
+	if (offset == 0x0d)
+	{
+		// bit 6 is /IACK (note the active-low)
+		if (m_read_vector)
+			r &= ~0x40;
+		else
+			r |= 0x40;
+	}
+
+	return r;
+}
+
+// TODO: move me out of here, it's one channel per UART not 2
+uint8_t mcf5206e_uart_device::read(offs_t offset)
+{
+	uint8_t r = 0xff;
+
+	switch (offset)
+	{
+	case 0x00: /* UMR1/UMR2 */
+	case 0x01: /* USR */
+	case 0x03: /* URBA Receive Buffer Register */
+	case 0x04: /* UIPCR */
+	case 0x05: /* UISR */
+	case 0x0d: /* UIP */
+		r = duart_base_device::read(offset);
+		break;
+
+	case 0x06: /* UBG Baud Generator Prescale MSB */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = (UBG & 0xFF00) >> 8;
+		break;
+	case 0x07: /* UBG Baud Generator Prescale LSB */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = (UBG & 0x00FF);
+		break;
+
+	case 0x0c:  /* UIVR */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = IVR;
+		break;
+
+	default:
+		LOG("Reading unhandled mcf5206e reg %x\n", offset);
+		break;
+	}
+	LOG("returned %02x\n", r);
+
+	return r;
+}
+
+uint8_t mc68340_duart_device::read(offs_t offset)
+{
+	uint8_t r = 0;
+
+	switch (offset)
+	{
+	case 0x00: /* MR1A - does not share register address with MR2A */
+		r = m_chanA->read_MR1();
+		break;
+	case 0x08: /* MR1B - does not share register address with MR2B */
+		r = m_chanB->read_MR1();
+		break;
+	case 0x10: /* MR2A - does not share register address with MR1A */
+		r = m_chanA->read_MR2();
+		break;
+	case 0x11: /* MR2B - does not share register address with MR1B */
+		r = m_chanB->read_MR2();
+		break;
+	default:
+		r = duart_base_device::read(offset);
+	}
+	return r;
+}
+
+uint8_t sc28c94_device::read(offs_t offset)
+{
+	uint8_t r = 0;
+	offset &= 0x1f;
+
+	if (offset < 0x10)
+	{
+		return duart_base_device::read(offset);
+	}
+
+	switch (offset)
+	{
+	case 0x10: /* MR1A/MR2C */
+	case 0x11: /* SRC */
+	case 0x13: /* Rx Holding Register C */
+		r = m_chanC->read_chan_reg(offset & 3);
+		break;
+
+	case 0x18: /* MR1D/MR2D */
+	case 0x19: /* SRD */
+	case 0x1b: /* RHRD */
+		r = m_chanD->read_chan_reg(offset & 3);
+		break;
+	}
+
+	return r;
+}
+
+uint8_t xr68c681_device::read(offs_t offset)
+{
+	if (offset == 0x02)
+	{
+		LOG("Reading XR68C681 (%s) reg 0x02 (MISR)\n", tag());
+		return ISR & IMR;
+	}
+	else
+		return mc68681_device::read(offset);
+}
+
+uint8_t duart_base_device::read(offs_t offset)
+{
+	uint8_t r = 0xff;
+
+	offset &= 0xf;
+
+	LOG("%s: Reading 68681 (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, duart68681_reg_read_names[offset]);
+
+	switch (offset)
+	{
+	case 0x00: /* MR1A/MR2A */
+	case 0x01: /* SRA */
+	case 0x03: /* Rx Holding Register A */
+		r = m_chanA->read_chan_reg(offset & 3);
+		break;
+
+	case 0x04: /* IPCR */
+		r = IPCR;
+
+		// reading this clears all the input change bits
+		IPCR &= 0x0f;
+		clear_ISR_bits(INT_INPUT_PORT_CHANGE);
+		break;
+
+	case 0x05: /* ISR */
+		r = ISR;
+		break;
+
+	case 0x06: /* CUR */
+		r = get_ct_count() >> 8;
+		break;
+
+	case 0x07: /* CLR */
+		r = get_ct_count() & 0xff;
+		break;
+
+	case 0x08: /* MR1B/MR2B */
+	case 0x09: /* SRB */
+	case 0x0b: /* RHRB */
+		r = m_chanB->read_chan_reg(offset & 3);
+		break;
+
+	case 0x0a: /* 1X/16X Test */
+		r = 0x61;   // the old 68681 returned this and it makes Apollo happy
+		break;
+
+	case 0x0d: /* IP */
+		if (!read_inport.isunset())
+		{
+			r = read_inport();  // TODO: go away
+		}
+		else
+		{
+			r = IP_last_state;
+		}
+
+		r |= 0x80;  // bit 7 is always set
+		break;
+
+	case 0x0e: /* Start counter command */
+	{
+		if (ACR & 0x40)
+		{
+			// Reset the timer
+			half_period = 0;
+		}
+
+		int count = std::max(CTR.w.l, uint16_t(1));
+		start_ct(count);
+		break;
+	}
+
+	case 0x0f: /* Stop counter command */
+
+		// Stop the counter only
+		if (!(ACR & 0x40))
+		{
+			duart_timer->enable(false);
+
+			// clear OP3 counter ready
+			if ((OPCR & 0xc) == 0x4)
+				OPR &= ~0x8;
+		}
+
+		clear_ISR_bits(INT_COUNTER_READY);
+		break;
+
+	default:
+		LOG("Reading unhandled 68681 reg %x\n", offset);
+		break;
+	}
+	LOG("returned %02x\n", r);
+
+	return r;
+}
+
+void mc68681_device::write(offs_t offset, uint8_t data)
+{
+	if (offset == 0x0c)
+		IVR = data;
+	else
+		duart_base_device::write(offset, data);
+}
+
+void mcf5206e_uart_device::write(offs_t offset, uint8_t data)
+{
+	switch (offset)
+	{
+	case 0x00: /* UMR */
+	case 0x01: /* UCSR */
+	case 0x03: /* UTB */
+	case 0x04: /* ACR */    // <-- TODO: This needs changing as ACR on ColdFire only handles interrupt enable for CTS
+	case 0x05: /* IMR */
+	case 0x0e: /* Set Output Port (RTS) Bit */
+	case 0x0f: /* Reset Output Port (RTS) Bit */
+		duart_base_device::write(offset, data);
+		break;
+
+	case 0x02: /* UCR */
+		// monomach uses 0x02 0x03 0x01 0x08 0x0c 0x04 at POST
+		// 3 and c are "Do Not Use" according to datasheet
+		// (already a good reason about not deriving from here ...)
+		if (data != 0xc && data != 0x3)
+			duart_base_device::write(offset, data);
+		break;
+
+	case 0x06: /* UBG1 */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		UBG = (UBG & 0x00ff) | (data << 8);
+		break;
+	case 0x07: /* UBG2 */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		UBG = (UBG & 0xff00) | data;
+		m_chanA->baud_updated();
+		m_chanA->update_interrupts();
+		break;
+
+	case 0x0c: /* UIVR */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		IVR = data;
+		break;
+
+	default: break;
+	}
+}
+
+void mc68340_duart_device::write(offs_t offset, uint8_t data)
+{
+	//printf("Duart write %02x -> %02x\n", data, offset);
+
+	switch(offset)
+	{
+	case 0x00: /* MR1A - does not share register address with MR2A */
+		m_chanA->write_MR1(data);
+		break;
+	case 0x08: /* MR1B - does not share register address with MR2B */
+		m_chanB->write_MR1(data);
+		break;
+	case 0x10: /* MR2A - does not share register address with MR1A */
+		m_chanA->write_MR2(data);
+		break;
+	case 0x11: /* MR2B - does not share register address with MR1B */
+		m_chanB->write_MR2(data);
+		break;
+	default:
+		duart_base_device::write(offset, data);
+	}
+}
+
+void sc28c94_device::write(offs_t offset, uint8_t data)
+{
+	offset &= 0x1f;
+
+	if (offset < 0x10)
+	{
+		duart_base_device::write(offset, data);
+	}
+
+	switch (offset)
+	{
+	case 0x10: /* MRC */
+	case 0x11: /* CSRC */
+	case 0x12: /* CRC */
+	case 0x13: /* THRC */
+		m_chanC->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x18: /* MRC */
+	case 0x19: /* CSRC */
+	case 0x1a: /* CRC */
+	case 0x1b: /* THRC */
+		m_chanD->write_chan_reg(offset&3, data);
+		break;
+	}
+}
+
+void xr68c681_device::write(offs_t offset, uint8_t data)
+{
+	if (offset == 0x02) /* CRA */
+		switch (data >> 4)
+		{
+		case 0x08: /* set RX extend bit */
+			m_XRXA = true;
+			m_chanA->baud_updated();
+			data &= 0x0f; /* disable command before we send it off to 68681 */
+			break;
+
+		case 0x09: /* clear RX extend bit */
+			m_XRXA = false;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0a: /* set TX extend bit */
+			m_XTXA = true;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0b: /* clear TX extend bit */
+			m_XTXA = false;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0c: /* enter low power mode TODO: unimplemented */
+		case 0x0d: /* leave low power mode */
+		case 0x0e: /* reserved */
+		case 0x0f: /* reserved */
+			data &= 0x0f;
+			break;
+		}
+
+	else if (offset == 0x0a) /* CRB */
+		switch (data >> 4)
+		{
+		case 0x08: /* set RX extend bit */
+			m_XRXB = true;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x09: /* clear RX extend bit */
+			m_XRXB = false;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0a: /* set TX extend bit */
+			m_XTXB = true;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0b: /* clear TX extend bit */
+			m_XTXB = false;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0c: /* enter low power mode TODO: unimplemented */
+		case 0x0d: /* leave low power mode */
+		case 0x0e: /* reserved */
+		case 0x0f: /* reserved */
+			data &= 0x0f;
+			break;
+		}
+
+	mc68681_device::write(offset, data); /* pass on 68681 command */
+}
+
+void duart_base_device::write(offs_t offset, uint8_t data)
+{
+	offset &= 0x0f;
+	LOG("%s: Writing 68681 (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, duart68681_reg_write_names[offset], data);
+	switch (offset)
+	{
+	case 0x00: /* MRA */
+	case 0x01: /* CSRA */
+	case 0x02: /* CRA */
+	case 0x03: /* THRA */
+		m_chanA->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x04: /* ACR */
+	{
+		uint8_t old_acr = ACR;
+		ACR = data;
+
+		//       bits 6-4: Counter/Timer Mode And Clock Source Select
+		//       bits 3-0: IP3-0 Change-Of-State Interrupt Enable
+		if ((old_acr ^ data) & 0x40)
+		{
+			if (data & 0x40)
+			{
+				// Entering timer mode
+				uint16_t count = std::max(CTR.w.l, uint16_t(1));
+				half_period = 0;
+
+				start_ct(count);
+			}
+			else
+			{
+				// Leaving timer mode (TODO: is this correct?)
+				duart_timer->adjust(attotime::never);
+			}
+		}
+
+		// check for pending input port delta interrupts
+		if ((((IPCR>>4) & data) & 0x0f) != 0)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+
+		m_chanA->baud_updated();
+		m_chanB->baud_updated();
+		m_chanA->update_interrupts();
+		m_chanB->update_interrupts();
+		break;
+	}
+	case 0x05: /* IMR */
+		IMR = data;
+		update_interrupts();
+		break;
+
+	case 0x06: /* CTUR */
+		CTR.b.h = data;
+		break;
+
+	case 0x07: /* CTLR */
+		CTR.b.l = data;
+		break;
+
+	case 0x08: /* MRB */
+	case 0x09: /* CSRB */
+	case 0x0a: /* CRB */
+	case 0x0b: /* THRB */
+		m_chanB->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x0d: /* OPCR */
+		if (((data & 0xf) != 0x00) && ((data & 0xc) != 0x4))
+			logerror("68681 (%s): Unhandled OPCR value: %02x\n", tag(), data);
+		OPCR = data;
+		break;
+
+	case 0x0e: /* Set Output Port Bits */
+		OPR |= data;
+		write_outport(OPR ^ 0xff);
+		break;
+
+	case 0x0f: /* Reset Output Port Bits */
+		OPR &= ~data;
+		write_outport(OPR ^ 0xff);
+		break;
+	}
+}
+
+void duart_base_device::ip0_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x01) | ((state == ASSERT_LINE) ? 1 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x10;
+
+		if (ACR & 1)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip1_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x02) | ((state == ASSERT_LINE) ? 2 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x20;
+
+		if (ACR & 2)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip2_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x04) | ((state == ASSERT_LINE) ? 4 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x40;
+
+		if (ACR & 4)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip3_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x08) | ((state == ASSERT_LINE) ? 8 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x80;
+
+		if (ACR & 8)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip4_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x10) | ((state == ASSERT_LINE) ? 0x10 : 0);
+// TODO: special mode for ip4 (Ch. A Rx clock)
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip5_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x20) | ((state == ASSERT_LINE) ? 0x20 : 0);
+// TODO: special mode for ip5 (Ch. B Tx clock)
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip6_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x40) | ((state == ASSERT_LINE) ? 0x40 : 0);
+// TODO: special mode for ip6 (Ch. B Rx clock)
+	IP_last_state = newIP;
+}
+
+duart_channel *duart_base_device::get_channel(int chan)
+{
+	if (chan == 0)
+	{
+		return m_chanA;
+	}
+
+	return m_chanB;
+}
+
+int duart_base_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+	if (BIT(ACR, 7) == 0)
+	{
+		baud_rate = baud_rate_ACR_0[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+	else
+	{
+		baud_rate = baud_rate_ACR_1[data & 0x0f];
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int mc68340_duart_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+	if (BIT(ACR, 7) == 0)
+	{
+		baud_rate = baud_rate_ACR_0_340[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+	else
+	{
+		baud_rate = baud_rate_ACR_1_340[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int xr68c681_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+
+	baud_rate = baud_rate_ACR_0[data & 0x0f];
+
+	if (ch == 0)
+	{
+		if ((data & 0x0f) == 0x0e)
+			baud_rate = ip3clk/16;
+		else if ((data & 0x0f) == 0x0f)
+			baud_rate = ip3clk;
+		else if ((rx && m_XRXA) || (!rx && m_XTXA)) /* X = 1 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0_X_1[data & 0x0f] : baud_rate_ACR_1_X_1[data & 0x0f];
+		else /* X = 0 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0[data & 0x0f] : baud_rate_ACR_1[data & 0x0f];
+	}
+	else if (ch == 1)
+	{
+		if ((data & 0x0f) == 0x0e)
+			baud_rate = ip5clk/16;
+		else if ((data & 0x0f) == 0x0f)
+			baud_rate = ip5clk;
+		else if ((rx && m_XRXB) || (!rx && m_XTXB)) /* X = 1 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0_X_1[data & 0x0f] : baud_rate_ACR_1_X_1[data & 0x0f];
+		else /* X = 0 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0[data & 0x0f] : baud_rate_ACR_1[data & 0x0f];
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int mcf5206e_uart_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate = 0;
+	u16 ubg_temp = 1;
+
+	if(UBG > 0) ubg_temp = UBG;
+
+	switch (data & 0xf){
+		case 0xe: baud_rate = ip3clk/16; break;
+		case 0xf: baud_rate = ip3clk; break;
+		case 0xd: baud_rate = (this->clock()/32) / ubg_temp; break;
+		default: LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data); break;
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+void duart_base_device::clear_ISR_bits(int mask)
+{
+	if (ISR & mask)
+	{
+		ISR &= ~mask;
+		update_interrupts();
+	}
+}
+
+void duart_base_device::set_ISR_bits(int mask)
+{
+	if (!(ISR & mask))
+	{
+		ISR |= mask;
+		update_interrupts();
+	}
+}
+
+// DUART channel class stuff
+
+duart_channel::duart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: device_t(mconfig, DUART_CHANNEL, tag, owner, clock)
+	, device_serial_interface(mconfig, *this)
+	, MR1(0)
+	, MR2(0)
+	, SR(0)
+	, rx_enabled(0)
+	, rx_fifo_num(0)
+	, m_rx_line(true)
+	, m_tx_data_in_buffer(false)
+	, m_tx_break(false)
+	, m_bits_transmitted(255)
+	, m_tx_enabled(false)
+{
+	std::fill_n(&rx_fifo[0], MC68681_RX_FIFO_SIZE + 1, 0);
+}
+
+void duart_channel::device_start()
+{
+	m_uart = downcast<duart_base_device *>(owner());
+	m_ch = m_uart->get_ch(this);    // get our channel number
+
+	save_item(NAME(CR));
+	save_item(NAME(CSR));
+	save_item(NAME(MR1));
+	save_item(NAME(MR2));
+	save_item(NAME(MR_ptr));
+	save_item(NAME(SR));
+	save_item(NAME(rx_baud_rate));
+	save_item(NAME(tx_baud_rate));
+	save_item(NAME(rx_enabled));
+	save_item(NAME(rx_fifo));
+	save_item(NAME(rx_fifo_read_ptr));
+	save_item(NAME(rx_fifo_write_ptr));
+	save_item(NAME(rx_fifo_num));
+	save_item(NAME(m_tx_data));
+	save_item(NAME(m_tx_data_in_buffer));
+	save_item(NAME(m_tx_break));
+	save_item(NAME(m_bits_transmitted));
+	save_item(NAME(m_tx_enabled));
+	save_item(NAME(m_rx_line));
+}
+
+// VT1200 NOTE (local change, not upstream): the datasheet latches the overrun
+// error "upon receipt of the start bit of the new (overrunning) character",
+// i.e. while the FIFO is full and the previous character is still held in the
+// receive shift register.  MAME's rx_fifo_push() latches it only when that
+// character is fully received, a whole character late.  Watching the RxD line
+// here reproduces the earlier latch time.  Revert: delete this override, delete
+// the m_rx_line member, and restore the device_serial_interface::rx_w calls in
+// mc68681.h's rx_a_w/rx_b_w/rx_c_w/rx_d_w.
+void duart_channel::rx_w(int state)
+{
+	if (state == 0 && m_rx_line && (rx_fifo_num == MC68681_RX_FIFO_SIZE + 1))
+	{
+		SR |= STATUS_OVERRUN_ERROR;
+		update_interrupts();
+	}
+	m_rx_line = (state != 0);
+	device_serial_interface::rx_w(state);
+}
+
+void duart_channel::device_reset()
+{
+	write_CR(0x10); // reset MR
+	write_CR(0x20); // reset Rx
+	write_CR(0x30); // reset Tx
+	write_CR(0x40); // reset errors
+
+	set_data_frame(1, 8, PARITY_NONE, STOP_BITS_1);
+
+	tx_baud_rate = rx_baud_rate = 0;
+	CSR = 0;
+	m_tx_break = false;
+}
+
+// serial device virtual overrides
+void duart_channel::rcv_complete()
+{
+	receive_register_extract();
+
+	//printf("%s ch %d rcv complete\n", tag(), m_ch);
+
+	if (rx_enabled || (MR2 & 0xc0) == 0x80)
+	{
+		uint8_t errors = 0;
+		if (is_receive_framing_error())
+			errors |= STATUS_FRAMING_ERROR;
+		if (is_receive_parity_error())
+			errors |= STATUS_PARITY_ERROR;
+		rx_fifo_push(get_received_char(), errors);
+	}
+}
+
+void duart_channel::rx_fifo_push(uint8_t data, uint8_t errors)
+{
+	if (rx_fifo_num == (MC68681_RX_FIFO_SIZE + 1))
+	{
+		logerror("68681: FIFO overflow\n");
+		SR |= STATUS_OVERRUN_ERROR;
+		// In case of overrun the FIFO tail entry is overwritten
+		// Back rx_fifo_write_ptr up by one position
+		if (rx_fifo_write_ptr)
+			rx_fifo_write_ptr--;
+		else
+			rx_fifo_write_ptr = MC68681_RX_FIFO_SIZE;
+	}
+
+	rx_fifo[rx_fifo_write_ptr++] = data | (errors << 8);
+	if (rx_fifo_write_ptr > MC68681_RX_FIFO_SIZE)
+		rx_fifo_write_ptr = 0;
+
+	if (rx_fifo_num <= MC68681_RX_FIFO_SIZE)
+	{
+		rx_fifo_num++;
+	}
+
+	if (rx_fifo_num == 1)
+	{
+		SR |= STATUS_RECEIVER_READY;
+		if (!(MR1 & MODE_BLOCK_ERROR))
+			SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+		SR |= errors;
+	}
+	if (rx_fifo_num == MC68681_RX_FIFO_SIZE)
+		SR |= STATUS_FIFO_FULL;
+	update_interrupts();
+}
+
+void duart_channel::tra_complete()
+{
+	// The transmit shift register has just emptied.  If another character is
+	// waiting in the THR, transfer it to the shift register and assert TxRDY:
+	// per the datasheet the THR->shift transfer is where the TxRDY conditions
+	// are re-asserted, providing "one full character time of buffering".  If the
+	// THR is empty the transmitter is now idle, so set TxEMT (TxRDY is already
+	// set from the previous transfer).
+	//
+	// Asserting TxRDY here, at the transfer -- rather than in the idle branch --
+	// both prevents the transmitter from deadlocking when TxRDY would otherwise
+	// fail to re-assert on a CPU-write / final-bit-time race, and preserves the
+	// one-character buffering window that firmware polling or pipelining on TxRDY
+	// relies on.
+	if (m_tx_data_in_buffer)
+	{
+		transmit_register_setup(m_tx_data);
+		m_bits_transmitted = 0;
+		m_tx_data_in_buffer = false;
+		SR |= STATUS_TRANSMITTER_READY;
+		update_interrupts();
+	}
+	else
+	{
+		SR |= STATUS_TRANSMITTER_EMPTY;
+		update_interrupts();
+	}
+}
+
+void duart_channel::tra_callback()
+{
+	// don't actually send in loopback mode
+	if ((MR2 & 0xc0) != 0x80)
+	{
+		int bit = transmit_register_get_data_bit();
+		//printf("%s ch %d transmit %d\n", tag(), m_ch, bit);
+		if (m_ch == 0)
+		{
+			m_uart->write_a_tx(bit);
+		}
+		else if (m_ch == 1)
+		{
+			m_uart->write_b_tx(bit);
+		}
+		else if (m_ch == 2)
+		{
+			m_uart->write_c_tx(bit);
+		}
+		else if (m_ch == 3)
+		{
+			m_uart->write_d_tx(bit);
+		}
+	}
+	else
+	{
+		// loop back transmitted bit
+		rx_w(transmit_register_get_data_bit());
+	}
+
+	// TxRDY is not set until the end of start bit time
+	if (++m_bits_transmitted > 1 && !m_tx_data_in_buffer && m_tx_enabled)
+	{
+		SR |= STATUS_TRANSMITTER_READY;
+		update_interrupts();
+	}
+}
+
+void duart_channel::update_interrupts()
+{
+	// Handle the TxEMT and TxRDY bits based on mode
+	switch (MR2 & 0xc0) // what mode are we in?
+	{
+	case 0x00: // normal mode
+		break;
+	case 0x40: // automatic echo mode
+		SR &= ~STATUS_TRANSMITTER_READY;
+		break;
+	case 0x80: // local loopback mode
+		break;
+	case 0xc0: // remote loopback mode
+		SR &= ~STATUS_TRANSMITTER_READY;
+		break;
+	}
+
+	// now handle the ISR bits
+	if (SR & STATUS_TRANSMITTER_READY)
+	{
+		if (m_ch == 0)
+			m_uart->set_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->set_ISR_bits(INT_TXRDYB);
+	}
+	else
+	{
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+	}
+	//logerror("DEBUG: 68681 int check: before receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
+	if (MR1 & MODE_RX_INT_SELECT_BIT)
+	{
+		if (SR & STATUS_FIFO_FULL)
+		{
+			m_uart->set_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+		else
+		{
+			m_uart->clear_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+	}
+	else
+	{
+		if (SR & STATUS_RECEIVER_READY)
+		{
+			m_uart->set_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+		else
+		{
+			m_uart->clear_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+	}
+
+	//logerror("DEBUG: 68681 int check: after receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
+}
+
+uint8_t duart_channel::read_rx_fifo()
+{
+	uint8_t rv;
+
+	//printf("read_rx_fifo: rx_fifo_num %d\n", rx_fifo_num);
+
+	if (rx_fifo_num == 0)
+	{
+		LOG("68681 channel: rx fifo underflow\n");
+		update_interrupts();
+		return 0;
+	}
+
+	rv = rx_fifo[rx_fifo_read_ptr++];
+	if (rx_fifo_read_ptr > MC68681_RX_FIFO_SIZE)
+	{
+		rx_fifo_read_ptr = 0;
+	}
+
+	rx_fifo_num--;
+	if (rx_fifo_num == (MC68681_RX_FIFO_SIZE - 1))
+	{
+		SR &= ~STATUS_FIFO_FULL;
+	}
+
+	if (!(MR1 & MODE_BLOCK_ERROR))
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+	if (rx_fifo_num == 0)
+		SR &= ~STATUS_RECEIVER_READY;
+	else
+		SR |= rx_fifo[rx_fifo_read_ptr] >> 8;
+	update_interrupts();
+
+	//printf("Rx read %02x\n", rv);
+
+	return rv;
+}
+
+uint8_t duart_channel::read_chan_reg(int reg)
+{
+	uint8_t rv = 0xff;
+
+	switch (reg)
+	{
+	case 0: // MR1/MR2
+		if (MR_ptr == 0)
+		{
+			rv = MR1;
+			MR_ptr = 1;
+		}
+		else
+		{
+			rv = MR2;
+		}
+		break;
+
+	case 1: // SRA
+		rv = SR;
+		break;
+
+	case 2: // CSRA: reading this is prohibited
+		break;
+
+	case 3: // Rx holding register A
+		rv = read_rx_fifo();
+		break;
+	}
+
+	return rv;
+}
+
+void duart_channel::write_chan_reg(int reg, uint8_t data)
+{
+	switch (reg)
+	{
+	case 0x00: /* MRA */
+		write_MR(data);
+		break;
+
+	case 0x01: /* CSR */
+		CSR = data;
+		tx_baud_rate = m_uart->calc_baud(m_ch, false, data & 0xf);
+		rx_baud_rate = m_uart->calc_baud(m_ch, true, (data>>4) & 0xf);
+		//printf("%s ch %d CSR %02x Tx baud %d Rx baud %d\n", tag(), m_ch, data, tx_baud_rate, rx_baud_rate);
+		set_rcv_rate(rx_baud_rate);
+		set_tra_rate(tx_baud_rate);
+		break;
+
+	case 0x02: /* CR */
+		write_CR(data);
+		break;
+
+	case 0x03: /* THR */
+		write_TX(data);
+		break;
+	}
+}
+
+void duart_channel::write_MR(uint8_t data)
+{
+	if (MR_ptr == 0)
+	{
+		MR1 = data;
+		MR_ptr = 1;
+	}
+	else
+	{
+		MR2 = data;
+	}
+	recalc_framing();
+	update_interrupts();
+}
+
+void duart_channel::recalc_framing()
+{
+	parity_t parity = PARITY_NONE;
+	switch ((MR1 >> 3) & 3)
+	{
+	case 0: // with parity
+		if (MR1 & 4)
+			parity = PARITY_ODD;
+		else
+			parity = PARITY_EVEN;
+		break;
+
+	case 1: // force parity
+		if (MR1 & 4)
+			parity = PARITY_MARK;
+		else
+			parity = PARITY_SPACE;
+		break;
+
+	case 2: // no parity
+		parity = PARITY_NONE;
+		break;
+
+	case 3: // multidrop mode
+		// fatalerror("68681: multidrop parity not supported\n");
+		// Apollo DEX CPU will test this; omit to abort the emulation
+		logerror("68681: multidrop parity not supported\n");
+		break;
+	}
+
+	stop_bits_t stopbits = STOP_BITS_0;
+	switch ((MR2 >> 2) & 3)
+	{
+	case 0:
+	case 1:
+		stopbits = STOP_BITS_1;
+		break;
+
+	case 2: // "1.5 async, 2 sync"
+		stopbits = STOP_BITS_1_5;
+		break;
+
+	case 3:
+		stopbits = STOP_BITS_2;
+		break;
+	}
+
+	//printf("%s ch %d MR1 %02x MR2 %02x => %d bits / char, %d stop bits, parity %d\n", tag(), m_ch, MR1, MR2, (MR1 & 3)+5, stopbits, parity);
+
+	set_data_frame(1, (MR1 & 3) + 5, parity, stopbits);
+}
+
+void duart_channel::write_CR(uint8_t data)
+{
+	switch ((data >> 4) & 0x07)
+	{
+	case 0: /* No command */
+		break;
+	case 1: /* Reset MR pointer. Causes the channel MR pointer to point to MR1 */
+		MR_ptr = 0;
+		break;
+	case 2: /* Reset channel receiver (disable receiver and flush fifo) */
+		rx_enabled = 0;
+		SR &= ~STATUS_RECEIVER_READY;
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+		SR &= ~STATUS_OVERRUN_ERROR; // is this correct?
+		rx_fifo_read_ptr = 0;
+		rx_fifo_write_ptr = 0;
+		rx_fifo_num = 0;
+		receive_register_reset();
+		break;
+	case 3: /* Reset channel transmitter */
+		SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+		if (m_ch == 0)
+		{
+			m_uart->write_a_tx(1);
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		}
+		else
+		{
+			m_uart->write_b_tx(1);
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+		}
+		transmit_register_reset();
+		m_bits_transmitted = 255;
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = false;
+		break;
+	case 4: /* Reset Error Status */
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR | STATUS_OVERRUN_ERROR);
+		break;
+	case 5: /* Reset Channel break change interrupt */
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_DELTA_BREAK_A);
+		else
+			m_uart->clear_ISR_bits(INT_DELTA_BREAK_B);
+		break;
+	case 6: /* Start Tx break */
+		if (!m_tx_break)
+		{
+			m_tx_break = true;
+			if ((MR2 & 0xc0) == 0x80)
+			{
+				// Local loopback mode: set delta break in ISR, simulate break rx
+				if (m_ch == 0)
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_A);
+				else
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_B);
+				rx_fifo_push(0 , STATUS_RECEIVED_BREAK);
+			}
+			// TODO: Actually send break signal
+		}
+		break;
+	case 7: /* Stop tx break */
+		if (m_tx_break)
+		{
+			m_tx_break = false;
+			if ((MR2 & 0xc0) == 0x80)
+			{
+				// Local loopback mode: set delta break in ISR
+				if (m_ch == 0)
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_A);
+				else
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_B);
+			}
+		}
+		break;
+	default:
+		LOG("68681: Unhandled command (%x) in CR%d\n", (data >> 4) & 0x07, m_ch);
+		break;
+	}
+
+	if (BIT(data, 0))
+	{
+		rx_enabled = 1;
+	}
+	if (BIT(data, 1))
+	{
+		rx_enabled = 0;
+		SR &= ~STATUS_RECEIVER_READY;
+	}
+
+	if (!BIT(CR, 2) && BIT(data, 2))
+	{
+		SR |= STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY;
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = true;
+		if (m_ch == 0)
+			m_uart->set_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->set_ISR_bits(INT_TXRDYB);
+	}
+	if (BIT(data, 3))
+	{
+		SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = false;
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+	}
+
+	update_interrupts();
+	CR = data;
+}
+
+void duart_channel::write_TX(uint8_t data)
+{
+	if (!(SR & STATUS_TRANSMITTER_READY))
+	{
+		logerror("write_tx transmitter not ready (data 0x%02x discarded)\n", data);
+		return;
+	}
+
+	SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+	if (!is_transmit_register_empty())
+	{
+		m_tx_data = data;
+		m_tx_data_in_buffer = true;
+	}
+	else
+	{
+		transmit_register_setup(data);
+		m_bits_transmitted = 0;
+	}
+
+	update_interrupts();
+}
+
+void duart_channel::baud_updated()
+{
+	write_chan_reg(1, CSR);
+}
+
+uint8_t duart_channel::get_chan_CSR()
+{
+	return CSR;
+}
+
+void duart_channel::tx_16x_clock_w(bool state)
+{
+	if (state)
+	{
+		m_tx_prescaler--;
+		if (m_tx_prescaler == 8)
+		{
+			tx_clock_w(true);
+		}
+		else if (m_tx_prescaler == 0)
+		{
+			m_tx_prescaler = 16;
+			tx_clock_w(false);
+		}
+	}
+}
+
+void duart_channel::rx_16x_clock_w(bool state)
+{
+	if (!is_receive_register_synchronized())
+	{
+		// Skip over the start bit once synchonization is achieved
+		m_rx_prescaler = 32;
+		rx_clock_w(true);
+	}
+	else if (state)
+	{
+		m_rx_prescaler--;
+		if (m_rx_prescaler == 8)
+		{
+			rx_clock_w(false);
+		}
+		else if (m_rx_prescaler == 0)
+		{
+			m_rx_prescaler = 16;
+			rx_clock_w(true);
+		}
+	}
+}
diff --git a/harness/mame/mame_edits/mc68681.cpp.cfg3 b/harness/mame/mame_edits/mc68681.cpp.cfg3
new file mode 100644
index 0000000..59a4bcb
--- /dev/null
+++ b/harness/mame/mame_edits/mc68681.cpp.cfg3
@@ -0,0 +1,1928 @@
+// license:BSD-3-Clause
+// copyright-holders:Mariusz Wojcieszek, R. Belmont, Joseph Zatarski
+/*
+    2681 DUART
+    68681 DUART
+    28C94 QUART
+    68340 serial module
+    XR68C681 DUART (backwards compatible with 68681 with some improvements)
+
+    Written by Mariusz Wojcieszek
+    Updated by Jonathan Gevaryahu AKA Lord Nightmare
+    Improved interrupt handling by R. Belmont
+    Rewrite and modernization in progress by R. Belmont
+    Addition of the duart compatible 68340 serial module support by Edstrom
+    Support for the Exar XR68C681 by Joseph Zatarski (July of 2018)
+    Support for Freescale/NXP ColdFire UART module by NaokiS (June 2025)
+
+    The main incompatibility between the 2681 and 68681 (Signetics and Motorola each
+    manufactured both versions of the chip) is that the 68681 has a R/W input and
+    generates a 68000-compatible DTACK signal, instead of using generic RD and WR
+    strobes as the 2681 does. The 68681 also adds a programmable interrupt vector,
+    with an IACK input replacing IP6.
+
+    The command register addresses should never be read from. Doing so may place
+    the baud rate generator into a test mode which drives the parallel outputs with
+    internal counters and causes serial ports to operate at uncontrollable rates.
+
+    Exar XR68C681
+
+    The XR68C681 is an improvement upon the MC68681 which supports more baud
+    rates, adds an additional MISR (masked ISR) register, and adds a low-power
+    standby mode. There may be other differences, but these are the most
+    notable.
+
+    The extra baud rates are implemented by an 'X' bit for each channel. The X
+    bit chooses between two baud rate tables, in addition to the ACR[7] bit.
+    The X bit is changed by additional commands that are written to CRA and CRB.
+
+    The MISR is a read only register that takes the place of the 'BRG Test'
+    register on the MC68681.
+
+    The low power standby mode is entered and left by a command written to CRA
+    or CRB registers. Writing the commands to either register affects the whole
+    DUART, not just one channel. Resetting the DUART also leaves low power mode.
+
+    On the ColdFire MCF5206e, the UART modules are essentially just a pair of
+    MC68681s with only the A port visible and no counter/timer. The ACR on the
+    coldfire uarts shoud be updated to reflect this. Additionally, the
+    Baud Rate Generator prescaler reg should be used to set the baud.
+*/
+
+#include "emu.h"
+#include "mc68681.h"
+
+#include <algorithm>
+
+//#define VERBOSE 1
+//#define LOG_OUTPUT_FUNC printf
+#include "logmacro.h"
+
+
+static const char *const duart68681_reg_read_names[0x10] =
+{
+	"MRA", "SRA", "BRG Test", "RHRA", "IPCR", "ISR", "CTU", "CTL", "MRB", "SRB", "1X/16X Test", "RHRB", "IVR", "Input Ports", "Start Counter", "Stop Counter"
+};
+
+static const char *const duart68681_reg_write_names[0x10] =
+{
+	"MRA", "CSRA", "CRA", "THRA", "ACR", "IMR", "CTUR", "CTLR", "MRB", "CSRB", "CRB", "THRB", "IVR", "OPCR", "Set OP Bits", "Reset OP Bits"
+};
+
+static const char *const mcf5206e_duart_reg_read_names[0x10] =
+{
+	"UMR", "USR", "NO ACCESS", "URB", "UIPCR", "UISR", "UBG1", "UBG2", "NO ACCESS", "NO ACCESS", "NO ACCESS", "NO ACCESS", "UIVR", "UIP Input Ports", "NO ACCESS", "NO ACCESS"
+};
+
+static const char *const mcf5206e_duart_reg_write_names[0x10] =
+{
+	"UMR", "UCSR", "UCRA", "UTB", "UACR", "UIMR", "UBG1", "UBG2", "NO ACCESS", "NO ACCESS", "NO ACCESS", "NO ACCESS", "IVR", "NO ACCESS", "Set OP Bits", "Reset OP Bits"
+};
+
+static const int baud_rate_ACR_0[] =     { 50, 110, 134, 200, 300,  600,   1200,  1050,  2400,   4800, 7200, 9600, 38400, 0, 0, 0 }; /* xr68c681 X=0 */
+static const int baud_rate_ACR_0_X_1[] = { 75, 110, 134, 150, 3600, 14400, 28800, 57600, 115200, 4800, 1800, 9600, 19200, 0, 0, 0 };
+static const int baud_rate_ACR_1[] =     { 75, 110, 134, 150, 300,  600,   1200,  2000,  2400,   4800, 1800, 9600, 19200, 0, 0, 0 }; /* xr68c681 X=0 */
+static const int baud_rate_ACR_1_X_1[] = { 50, 110, 134, 200, 3600, 14400, 28800, 57600, 115200, 4800, 7200, 9600, 38400, 0, 0, 0 };
+
+static const int baud_rate_ACR_0_340[] = { 50, 110, 134, 200, 300,  600,   1200,  1050,  2400,   4800, 7200, 9600, 38400, 76800, 0, 0 }; /* xr68c681 ACR:7=0 */
+static const int baud_rate_ACR_1_340[] = { 75, 110, 134, 150, 300,  600,   1200,  2000,  2400,   4800, 1800, 9600, 19200, 38400, 0, 0 }; /* xr68c681 ACR:7=1 */
+
+#define INT_INPUT_PORT_CHANGE       0x80
+#define INT_DELTA_BREAK_B           0x40
+#define INT_RXRDY_FFULLB            0x20
+#define INT_TXRDYB                  0x10
+#define INT_COUNTER_READY           0x08
+#define INT_DELTA_BREAK_A           0x04
+#define INT_RXRDY_FFULLA            0x02
+#define INT_TXRDYA                  0x01
+
+#define STATUS_RECEIVED_BREAK       0x80
+#define STATUS_FRAMING_ERROR        0x40
+#define STATUS_PARITY_ERROR         0x20
+#define STATUS_OVERRUN_ERROR        0x10
+#define STATUS_TRANSMITTER_EMPTY    0x08
+#define STATUS_TRANSMITTER_READY    0x04
+#define STATUS_FIFO_FULL            0x02
+#define STATUS_RECEIVER_READY       0x01
+
+#define MODE_RX_INT_SELECT_BIT      0x40
+#define MODE_BLOCK_ERROR            0x20
+
+#define CHANA_TAG   "cha"
+#define CHANB_TAG   "chb"
+#define CHANC_TAG   "chc"
+#define CHAND_TAG   "chd"
+
+// device type definition
+DEFINE_DEVICE_TYPE(SCN2681, scn2681_device, "scn2681", "SCN2681 DUART")
+DEFINE_DEVICE_TYPE(MC68681, mc68681_device, "mc68681", "MC68681 DUART")
+DEFINE_DEVICE_TYPE(MCF5206E_UART, mcf5206e_uart_device, "mcf5206euart", "MCF5206e UART")
+DEFINE_DEVICE_TYPE(SC28C94, sc28c94_device, "sc28c94", "SC28C94 QUART")
+DEFINE_DEVICE_TYPE(MC68340_DUART, mc68340_duart_device, "mc68340duart", "MC68340 DUART")
+DEFINE_DEVICE_TYPE(XR68C681, xr68c681_device, "xr68c681", "XR68C681 DUART")
+DEFINE_DEVICE_TYPE(DUART_CHANNEL, duart_channel, "duart_channel", "DUART channel")
+
+
+//**************************************************************************
+//  LIVE DEVICE
+//**************************************************************************
+
+duart_base_device::duart_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, type, tag, owner, clock),
+	m_chanA(*this, CHANA_TAG),
+	m_chanB(*this, CHANB_TAG),
+	m_chanC(*this, CHANC_TAG),
+	m_chanD(*this, CHAND_TAG),
+	write_irq(*this),
+	write_a_tx(*this),
+	write_b_tx(*this),
+	write_c_tx(*this),
+	write_d_tx(*this),
+	read_inport(*this, 0),
+	write_outport(*this),
+	ip3clk(0),
+	ip4clk(0),
+	ip5clk(0),
+	ip6clk(0),
+	ACR(0),
+	IP_last_state(0)
+{
+}
+
+scn2681_device::scn2681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, SCN2681, tag, owner, clock)
+{
+}
+
+mc68681_device::mc68681_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+	, m_read_vector(false)
+{
+}
+
+mc68681_device::mc68681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68681_device(mconfig, MC68681, tag, owner, clock)
+{
+}
+
+mcf5206e_uart_device::mcf5206e_uart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+	, m_read_vector(false)
+{
+}
+
+mcf5206e_uart_device::mcf5206e_uart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, MCF5206E_UART, tag, owner, clock)
+{
+}
+
+
+sc28c94_device::sc28c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, SC28C94, tag, owner, clock)
+{
+}
+
+//--------------------------------------------------------------------------------------------------------------------
+// The read and write methods are meant to catch all differences in the register model between 68681 and 68340
+// serial module. Eg some registers are (re)moved into the 68340 like the vector register. There are also no counter
+// in the 68340. The CSR clock register is also different for the external clock modes. The implementation assumes
+// that the code knows all of this and will not warn if those registers are accessed as it could be ported code.
+// TODO: A lot of subtle differences and also detect misuse of unavailable registers as they should be ignored
+//--------------------------------------------------------------------------------------------------------------------
+mc68340_duart_device::mc68340_duart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+{
+}
+
+mc68340_duart_device::mc68340_duart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68340_duart_device(mconfig, MC68340_DUART, tag, owner, clock)
+{
+}
+
+xr68c681_device::xr68c681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68681_device(mconfig, XR68C681, tag, owner, clock)
+	, m_XTXA(false)
+	, m_XRXA(false)
+	, m_XTXB(false)
+	, m_XRXB(false)
+{
+}
+
+//-------------------------------------------------
+//  set_clocks - configuration helper to set
+//  the external clocks
+//-------------------------------------------------
+
+void duart_base_device::set_clocks(int clk3, int clk4, int clk5, int clk6)
+{
+	ip3clk = clk3;
+	ip4clk = clk4;
+	ip5clk = clk5;
+	ip6clk = clk6;
+}
+
+/*-------------------------------------------------
+    device start callback
+-------------------------------------------------*/
+
+void duart_base_device::device_start()
+{
+	duart_timer = timer_alloc(FUNC(duart_base_device::duart_timer_callback), this);
+
+	save_item(NAME(ACR));
+	save_item(NAME(IMR));
+	save_item(NAME(ISR));
+	save_item(NAME(OPCR));
+	save_item(NAME(OPR));
+	save_item(NAME(CTR));
+	save_item(NAME(IPCR));
+	save_item(NAME(IP_last_state));
+	save_item(NAME(half_period));
+	save_item(NAME(m_irq_state));
+}
+
+void mc68681_device::device_start()
+{
+	duart_base_device::device_start();
+
+	save_item(NAME(m_read_vector));
+	save_item(NAME(IVR));
+}
+
+void mcf5206e_uart_device::device_start()
+{
+	duart_base_device::device_start();
+
+	save_item(NAME(m_read_vector));
+	save_item(NAME(IVR));
+	save_item(NAME(UBG));
+}
+
+void xr68c681_device::device_start()
+{
+	mc68681_device::device_start();
+
+	save_item(NAME(m_XTXA));
+	save_item(NAME(m_XRXA));
+	save_item(NAME(m_XTXB));
+	save_item(NAME(m_XRXB));
+}
+
+/*-------------------------------------------------
+    device reset callback
+-------------------------------------------------*/
+
+void duart_base_device::device_reset()
+{
+	ACR = 0;  /* Interrupt Vector Register */
+	IMR = 0;  /* Interrupt Mask Register */
+	ISR = 0;  /* Interrupt Status Register */
+	OPCR = 0; /* Output Port Conf. Register */
+	OPR = 0;  /* Output Port Register */
+	CTR.d = 0;  /* Counter/Timer Preset Value */
+	// "reset clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR) puts OP0-7 in the high state, stops the counter/timer, and puts channels a/b in the inactive state"
+	IPCR = 0;
+
+	m_irq_state = false;
+	write_irq(CLEAR_LINE);
+	write_outport(OPR ^ 0xff);
+}
+
+void mc68681_device::device_reset()
+{
+	duart_base_device::device_reset();
+
+	IVR = 0x0f;  /* Interrupt Vector Register */
+	m_read_vector = false;
+}
+
+void mcf5206e_uart_device::device_reset()
+{
+	duart_base_device::device_reset();
+
+	IVR = 0x0f;  /* Interrupt Vector Register */
+	UBG = 0x00;  /* UART Baud Rate Generator Register */
+	m_read_vector = false;
+}
+
+void xr68c681_device::device_reset()
+{
+	mc68681_device::device_reset();
+
+	m_XTXA = m_XRXA = m_XTXB = m_XRXB = false;
+}
+
+void duart_base_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void sc28c94_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+	DUART_CHANNEL(config, CHANC_TAG);
+	DUART_CHANNEL(config, CHAND_TAG);
+}
+
+void mc68340_duart_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void mcf5206e_uart_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void duart_base_device::update_interrupts()
+{
+	/* update SR state and update interrupt ISR state for the following bits:
+	SRn: bits 7-4: handled elsewhere.
+	SRn: bit 3 (TxEMTn) (we can assume since we're not actually emulating the delay/timing of sending bits, that as long as TxRDYn is set, TxEMTn is also set since the transmit byte has 'already happened', therefore TxEMTn is always 1 assuming tx is enabled on channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined)
+	SRn: bit 2 (TxRDYn) (we COULD assume since we're not emulating delay and timing output, that as long as tx is enabled on channel n, TxRDY is 1 for channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined; however, tx_ready is already nicely handled for us elsewhere, so we can use that instead for now, though we may need to retool that code as well)
+	SRn: bit 1 (FFULLn) (this bit we actually emulate; if the receive fifo for channel n is full, this bit is 1, otherwise it is 0. the receive fifo should be three words long.)
+	SRn: bit 0 (RxRDYn) (this bit we also emulate; the bit is always asserted if the receive fifo is not empty)
+	ISR: bit 7: Input Port change; this should be handled elsewhere, on the input port handler
+	ISR: bit 6: Delta Break B; this should be handled elsewhere, on the data receive handler
+	ISR: bit 5: RxRDYB/FFULLB: this is handled here; depending on whether MSR1B bit 6 is 0 or 1, this bit holds the state of SRB bit 0 or bit 1 respectively
+	ISR: bit 4: TxRDYB: this is handled here; it mirrors SRB bit 2
+	ISR: bit 3: Counter ready; this should be handled by the timer generator
+	ISR: bit 2: Delta Break A; this should be handled elsewhere, on the data receive handler
+	ISR: bit 1: RxRDYA/FFULLA: this is handled here; depending on whether MSR1A bit 6 is 0 or 1, this bit holds the state of SRA bit 0 or bit 1 respectively
+	ISR: bit 0: TxRDYA: this is handled here; it mirrors SRA bit 2
+	*/
+	if ((ISR & IMR) != 0)
+	{
+		if (!m_irq_state)
+		{
+			m_irq_state = true;
+			LOG("Interrupt line active (IMR & ISR = %02X)\n", (ISR & IMR));
+			write_irq(ASSERT_LINE);
+		}
+	}
+	else
+	{
+		if (m_irq_state)
+		{
+			m_irq_state = false;
+			LOG("Interrupt line not active (IMR & ISR = %02X)\n", ISR & IMR);
+			write_irq(CLEAR_LINE);
+		}
+	}
+	if (OPCR & 0xf0)
+	{
+		if (BIT(OPCR, 4))
+		{
+			if (BIT(ISR, 1))
+				OPR |= 0x10;
+			else
+				OPR &= ~0x10;
+		}
+		if (BIT(OPCR, 5))
+		{
+			if (BIT(ISR, 5))
+				OPR |= 0x20;
+			else
+				OPR &= ~0x20;
+		}
+		if (BIT(OPCR, 6))
+		{
+			if (BIT(ISR, 0))
+				OPR |= 0x40;
+			else
+				OPR &= ~0x40;
+		}
+		if (BIT(OPCR, 7))
+		{
+			if (BIT(ISR, 4))
+				OPR |= 0x80;
+			else
+				OPR &= ~0x80;
+		}
+		write_outport(OPR ^ 0xff);
+	}
+}
+
+void mc68681_device::update_interrupts()
+{
+	duart_base_device::update_interrupts();
+
+	if (!irq_pending())
+		m_read_vector = false;  // clear IACK too
+}
+
+uint8_t mc68681_device::get_irq_vector()
+{
+	if (!machine().side_effects_disabled())
+		m_read_vector = true;
+
+	return IVR;
+}
+
+void mcf5206e_uart_device::update_interrupts()
+{
+	duart_base_device::update_interrupts();
+
+	if (!irq_pending())
+		m_read_vector = false;  // clear IACK too
+}
+
+uint8_t mcf5206e_uart_device::get_irq_vector()
+{
+	if (!machine().side_effects_disabled())
+		m_read_vector = true;
+
+	return IVR;
+}
+
+uint32_t duart_base_device::get_ct_rate()
+{
+	uint32_t rate = 0;
+
+	if (ACR & 0x40)
+	{
+		// Timer mode
+		switch ((ACR >> 4) & 3)
+		{
+		case 0: // IP2
+		case 1: // IP2 / 16
+			//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", duart68681->tag(), (duart68681->ACR >> 4) & 3);
+			rate = clock();
+			break;
+		case 2: // X1/CLK
+			rate = clock();
+			break;
+		case 3: // X1/CLK / 16
+			rate = clock() / 16;
+			break;
+		}
+	}
+	else
+	{
+		// Counter mode
+		switch ((ACR >> 4) & 3)
+		{
+		case 0: // IP2
+			//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", device->tag(), (duart68681->ACR >> 4) & 3);
+			rate = clock();
+			break;
+		case 1: // TxCA
+			rate = m_chanA->get_tx_rate();
+			break;
+		case 2: // TxCB
+			rate = m_chanB->get_tx_rate();
+			break;
+		case 3: // X1/CLK / 16
+			rate = clock() / 16;
+			break;
+		}
+	}
+
+	return rate;
+}
+
+uint16_t duart_base_device::get_ct_count()
+{
+	uint32_t clock = get_ct_rate();
+	return duart_timer->remaining().as_ticks(clock);
+}
+
+void duart_base_device::start_ct(int count)
+{
+	uint32_t clock = get_ct_rate();
+	duart_timer->adjust(attotime::from_ticks(count, clock), 0);
+}
+
+TIMER_CALLBACK_MEMBER(duart_base_device::duart_timer_callback)
+{
+	if (ACR & 0x40)
+	{
+		// Timer mode
+		half_period ^= 1;
+
+		// timer output to bit 3?
+		if ((OPCR & 0xc) == 0x4)
+		{
+			OPR ^= 0x8;
+			write_outport(OPR ^ 0xff);
+		}
+
+		// timer driving any serial channels?
+		uint8_t csr = m_chanA->get_chan_CSR();
+
+		if ((csr & 0x0f) == 0x0d)   // tx is timer driven
+		{
+			m_chanA->tx_16x_clock_w(half_period);
+		}
+		if ((csr & 0xf0) == 0xd0)   // rx is timer driven
+		{
+			m_chanA->rx_16x_clock_w(half_period);
+		}
+
+		csr = m_chanB->get_chan_CSR();
+		if ((csr & 0x0f) == 0x0d)   // tx is timer driven
+		{
+			m_chanB->tx_16x_clock_w(half_period);
+		}
+		if ((csr & 0xf0) == 0xd0)   // rx is timer driven
+		{
+			m_chanB->rx_16x_clock_w(half_period);
+		}
+
+		if (!half_period)
+			set_ISR_bits(INT_COUNTER_READY);
+
+		int count = std::max(CTR.w.l, uint16_t(1));
+		start_ct(count);
+	}
+	else
+	{
+		// assert OP3 counter ready
+		if ((OPCR & 0xc) == 0x4)
+			OPR |= 0x8;
+
+		// Counter mode
+		set_ISR_bits(INT_COUNTER_READY);
+		start_ct(0xffff);
+	}
+
+}
+
+uint8_t mc68681_device::read(offs_t offset)
+{
+	if (offset == 0x0c)
+		return IVR;
+
+	uint8_t r = duart_base_device::read(offset);
+
+	if (offset == 0x0d)
+	{
+		// bit 6 is /IACK (note the active-low)
+		if (m_read_vector)
+			r &= ~0x40;
+		else
+			r |= 0x40;
+	}
+
+	return r;
+}
+
+// TODO: move me out of here, it's one channel per UART not 2
+uint8_t mcf5206e_uart_device::read(offs_t offset)
+{
+	uint8_t r = 0xff;
+
+	switch (offset)
+	{
+	case 0x00: /* UMR1/UMR2 */
+	case 0x01: /* USR */
+	case 0x03: /* URBA Receive Buffer Register */
+	case 0x04: /* UIPCR */
+	case 0x05: /* UISR */
+	case 0x0d: /* UIP */
+		r = duart_base_device::read(offset);
+		break;
+
+	case 0x06: /* UBG Baud Generator Prescale MSB */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = (UBG & 0xFF00) >> 8;
+		break;
+	case 0x07: /* UBG Baud Generator Prescale LSB */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = (UBG & 0x00FF);
+		break;
+
+	case 0x0c:  /* UIVR */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = IVR;
+		break;
+
+	default:
+		LOG("Reading unhandled mcf5206e reg %x\n", offset);
+		break;
+	}
+	LOG("returned %02x\n", r);
+
+	return r;
+}
+
+uint8_t mc68340_duart_device::read(offs_t offset)
+{
+	uint8_t r = 0;
+
+	switch (offset)
+	{
+	case 0x00: /* MR1A - does not share register address with MR2A */
+		r = m_chanA->read_MR1();
+		break;
+	case 0x08: /* MR1B - does not share register address with MR2B */
+		r = m_chanB->read_MR1();
+		break;
+	case 0x10: /* MR2A - does not share register address with MR1A */
+		r = m_chanA->read_MR2();
+		break;
+	case 0x11: /* MR2B - does not share register address with MR1B */
+		r = m_chanB->read_MR2();
+		break;
+	default:
+		r = duart_base_device::read(offset);
+	}
+	return r;
+}
+
+uint8_t sc28c94_device::read(offs_t offset)
+{
+	uint8_t r = 0;
+	offset &= 0x1f;
+
+	if (offset < 0x10)
+	{
+		return duart_base_device::read(offset);
+	}
+
+	switch (offset)
+	{
+	case 0x10: /* MR1A/MR2C */
+	case 0x11: /* SRC */
+	case 0x13: /* Rx Holding Register C */
+		r = m_chanC->read_chan_reg(offset & 3);
+		break;
+
+	case 0x18: /* MR1D/MR2D */
+	case 0x19: /* SRD */
+	case 0x1b: /* RHRD */
+		r = m_chanD->read_chan_reg(offset & 3);
+		break;
+	}
+
+	return r;
+}
+
+uint8_t xr68c681_device::read(offs_t offset)
+{
+	if (offset == 0x02)
+	{
+		LOG("Reading XR68C681 (%s) reg 0x02 (MISR)\n", tag());
+		return ISR & IMR;
+	}
+	else
+		return mc68681_device::read(offset);
+}
+
+uint8_t duart_base_device::read(offs_t offset)
+{
+	uint8_t r = 0xff;
+
+	offset &= 0xf;
+
+	LOG("%s: Reading 68681 (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, duart68681_reg_read_names[offset]);
+
+	switch (offset)
+	{
+	case 0x00: /* MR1A/MR2A */
+	case 0x01: /* SRA */
+	case 0x03: /* Rx Holding Register A */
+		r = m_chanA->read_chan_reg(offset & 3);
+		break;
+
+	case 0x04: /* IPCR */
+		r = IPCR;
+
+		// reading this clears all the input change bits
+		IPCR &= 0x0f;
+		clear_ISR_bits(INT_INPUT_PORT_CHANGE);
+		break;
+
+	case 0x05: /* ISR */
+		r = ISR;
+		break;
+
+	case 0x06: /* CUR */
+		r = get_ct_count() >> 8;
+		break;
+
+	case 0x07: /* CLR */
+		r = get_ct_count() & 0xff;
+		break;
+
+	case 0x08: /* MR1B/MR2B */
+	case 0x09: /* SRB */
+	case 0x0b: /* RHRB */
+		r = m_chanB->read_chan_reg(offset & 3);
+		break;
+
+	case 0x0a: /* 1X/16X Test */
+		r = 0x61;   // the old 68681 returned this and it makes Apollo happy
+		break;
+
+	case 0x0d: /* IP */
+		if (!read_inport.isunset())
+		{
+			r = read_inport();  // TODO: go away
+		}
+		else
+		{
+			r = IP_last_state;
+		}
+
+		r |= 0x80;  // bit 7 is always set
+		break;
+
+	case 0x0e: /* Start counter command */
+	{
+		if (ACR & 0x40)
+		{
+			// Reset the timer
+			half_period = 0;
+		}
+
+		int count = std::max(CTR.w.l, uint16_t(1));
+		start_ct(count);
+		break;
+	}
+
+	case 0x0f: /* Stop counter command */
+
+		// Stop the counter only
+		if (!(ACR & 0x40))
+		{
+			duart_timer->enable(false);
+
+			// clear OP3 counter ready
+			if ((OPCR & 0xc) == 0x4)
+				OPR &= ~0x8;
+		}
+
+		clear_ISR_bits(INT_COUNTER_READY);
+		break;
+
+	default:
+		LOG("Reading unhandled 68681 reg %x\n", offset);
+		break;
+	}
+	LOG("returned %02x\n", r);
+
+	return r;
+}
+
+void mc68681_device::write(offs_t offset, uint8_t data)
+{
+	if (offset == 0x0c)
+		IVR = data;
+	else
+		duart_base_device::write(offset, data);
+}
+
+void mcf5206e_uart_device::write(offs_t offset, uint8_t data)
+{
+	switch (offset)
+	{
+	case 0x00: /* UMR */
+	case 0x01: /* UCSR */
+	case 0x03: /* UTB */
+	case 0x04: /* ACR */    // <-- TODO: This needs changing as ACR on ColdFire only handles interrupt enable for CTS
+	case 0x05: /* IMR */
+	case 0x0e: /* Set Output Port (RTS) Bit */
+	case 0x0f: /* Reset Output Port (RTS) Bit */
+		duart_base_device::write(offset, data);
+		break;
+
+	case 0x02: /* UCR */
+		// monomach uses 0x02 0x03 0x01 0x08 0x0c 0x04 at POST
+		// 3 and c are "Do Not Use" according to datasheet
+		// (already a good reason about not deriving from here ...)
+		if (data != 0xc && data != 0x3)
+			duart_base_device::write(offset, data);
+		break;
+
+	case 0x06: /* UBG1 */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		UBG = (UBG & 0x00ff) | (data << 8);
+		break;
+	case 0x07: /* UBG2 */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		UBG = (UBG & 0xff00) | data;
+		m_chanA->baud_updated();
+		m_chanA->update_interrupts();
+		break;
+
+	case 0x0c: /* UIVR */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		IVR = data;
+		break;
+
+	default: break;
+	}
+}
+
+void mc68340_duart_device::write(offs_t offset, uint8_t data)
+{
+	//printf("Duart write %02x -> %02x\n", data, offset);
+
+	switch(offset)
+	{
+	case 0x00: /* MR1A - does not share register address with MR2A */
+		m_chanA->write_MR1(data);
+		break;
+	case 0x08: /* MR1B - does not share register address with MR2B */
+		m_chanB->write_MR1(data);
+		break;
+	case 0x10: /* MR2A - does not share register address with MR1A */
+		m_chanA->write_MR2(data);
+		break;
+	case 0x11: /* MR2B - does not share register address with MR1B */
+		m_chanB->write_MR2(data);
+		break;
+	default:
+		duart_base_device::write(offset, data);
+	}
+}
+
+void sc28c94_device::write(offs_t offset, uint8_t data)
+{
+	offset &= 0x1f;
+
+	if (offset < 0x10)
+	{
+		duart_base_device::write(offset, data);
+	}
+
+	switch (offset)
+	{
+	case 0x10: /* MRC */
+	case 0x11: /* CSRC */
+	case 0x12: /* CRC */
+	case 0x13: /* THRC */
+		m_chanC->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x18: /* MRC */
+	case 0x19: /* CSRC */
+	case 0x1a: /* CRC */
+	case 0x1b: /* THRC */
+		m_chanD->write_chan_reg(offset&3, data);
+		break;
+	}
+}
+
+void xr68c681_device::write(offs_t offset, uint8_t data)
+{
+	if (offset == 0x02) /* CRA */
+		switch (data >> 4)
+		{
+		case 0x08: /* set RX extend bit */
+			m_XRXA = true;
+			m_chanA->baud_updated();
+			data &= 0x0f; /* disable command before we send it off to 68681 */
+			break;
+
+		case 0x09: /* clear RX extend bit */
+			m_XRXA = false;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0a: /* set TX extend bit */
+			m_XTXA = true;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0b: /* clear TX extend bit */
+			m_XTXA = false;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0c: /* enter low power mode TODO: unimplemented */
+		case 0x0d: /* leave low power mode */
+		case 0x0e: /* reserved */
+		case 0x0f: /* reserved */
+			data &= 0x0f;
+			break;
+		}
+
+	else if (offset == 0x0a) /* CRB */
+		switch (data >> 4)
+		{
+		case 0x08: /* set RX extend bit */
+			m_XRXB = true;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x09: /* clear RX extend bit */
+			m_XRXB = false;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0a: /* set TX extend bit */
+			m_XTXB = true;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0b: /* clear TX extend bit */
+			m_XTXB = false;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0c: /* enter low power mode TODO: unimplemented */
+		case 0x0d: /* leave low power mode */
+		case 0x0e: /* reserved */
+		case 0x0f: /* reserved */
+			data &= 0x0f;
+			break;
+		}
+
+	mc68681_device::write(offset, data); /* pass on 68681 command */
+}
+
+void duart_base_device::write(offs_t offset, uint8_t data)
+{
+	offset &= 0x0f;
+	LOG("%s: Writing 68681 (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, duart68681_reg_write_names[offset], data);
+	switch (offset)
+	{
+	case 0x00: /* MRA */
+	case 0x01: /* CSRA */
+	case 0x02: /* CRA */
+	case 0x03: /* THRA */
+		m_chanA->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x04: /* ACR */
+	{
+		uint8_t old_acr = ACR;
+		ACR = data;
+
+		//       bits 6-4: Counter/Timer Mode And Clock Source Select
+		//       bits 3-0: IP3-0 Change-Of-State Interrupt Enable
+		if ((old_acr ^ data) & 0x40)
+		{
+			if (data & 0x40)
+			{
+				// Entering timer mode
+				uint16_t count = std::max(CTR.w.l, uint16_t(1));
+				half_period = 0;
+
+				start_ct(count);
+			}
+			else
+			{
+				// Leaving timer mode (TODO: is this correct?)
+				duart_timer->adjust(attotime::never);
+			}
+		}
+
+		// check for pending input port delta interrupts
+		if ((((IPCR>>4) & data) & 0x0f) != 0)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+
+		m_chanA->baud_updated();
+		m_chanB->baud_updated();
+		m_chanA->update_interrupts();
+		m_chanB->update_interrupts();
+		break;
+	}
+	case 0x05: /* IMR */
+		IMR = data;
+		update_interrupts();
+		break;
+
+	case 0x06: /* CTUR */
+		CTR.b.h = data;
+		break;
+
+	case 0x07: /* CTLR */
+		CTR.b.l = data;
+		break;
+
+	case 0x08: /* MRB */
+	case 0x09: /* CSRB */
+	case 0x0a: /* CRB */
+	case 0x0b: /* THRB */
+		m_chanB->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x0d: /* OPCR */
+		if (((data & 0xf) != 0x00) && ((data & 0xc) != 0x4))
+			logerror("68681 (%s): Unhandled OPCR value: %02x\n", tag(), data);
+		OPCR = data;
+		break;
+
+	case 0x0e: /* Set Output Port Bits */
+		OPR |= data;
+		write_outport(OPR ^ 0xff);
+		break;
+
+	case 0x0f: /* Reset Output Port Bits */
+		OPR &= ~data;
+		write_outport(OPR ^ 0xff);
+		break;
+	}
+}
+
+void duart_base_device::ip0_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x01) | ((state == ASSERT_LINE) ? 1 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x10;
+
+		if (ACR & 1)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip1_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x02) | ((state == ASSERT_LINE) ? 2 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x20;
+
+		if (ACR & 2)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip2_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x04) | ((state == ASSERT_LINE) ? 4 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x40;
+
+		if (ACR & 4)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip3_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x08) | ((state == ASSERT_LINE) ? 8 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x80;
+
+		if (ACR & 8)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip4_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x10) | ((state == ASSERT_LINE) ? 0x10 : 0);
+// TODO: special mode for ip4 (Ch. A Rx clock)
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip5_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x20) | ((state == ASSERT_LINE) ? 0x20 : 0);
+// TODO: special mode for ip5 (Ch. B Tx clock)
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip6_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x40) | ((state == ASSERT_LINE) ? 0x40 : 0);
+// TODO: special mode for ip6 (Ch. B Rx clock)
+	IP_last_state = newIP;
+}
+
+duart_channel *duart_base_device::get_channel(int chan)
+{
+	if (chan == 0)
+	{
+		return m_chanA;
+	}
+
+	return m_chanB;
+}
+
+int duart_base_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+	if (BIT(ACR, 7) == 0)
+	{
+		baud_rate = baud_rate_ACR_0[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+	else
+	{
+		baud_rate = baud_rate_ACR_1[data & 0x0f];
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int mc68340_duart_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+	if (BIT(ACR, 7) == 0)
+	{
+		baud_rate = baud_rate_ACR_0_340[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+	else
+	{
+		baud_rate = baud_rate_ACR_1_340[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int xr68c681_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+
+	baud_rate = baud_rate_ACR_0[data & 0x0f];
+
+	if (ch == 0)
+	{
+		if ((data & 0x0f) == 0x0e)
+			baud_rate = ip3clk/16;
+		else if ((data & 0x0f) == 0x0f)
+			baud_rate = ip3clk;
+		else if ((rx && m_XRXA) || (!rx && m_XTXA)) /* X = 1 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0_X_1[data & 0x0f] : baud_rate_ACR_1_X_1[data & 0x0f];
+		else /* X = 0 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0[data & 0x0f] : baud_rate_ACR_1[data & 0x0f];
+	}
+	else if (ch == 1)
+	{
+		if ((data & 0x0f) == 0x0e)
+			baud_rate = ip5clk/16;
+		else if ((data & 0x0f) == 0x0f)
+			baud_rate = ip5clk;
+		else if ((rx && m_XRXB) || (!rx && m_XTXB)) /* X = 1 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0_X_1[data & 0x0f] : baud_rate_ACR_1_X_1[data & 0x0f];
+		else /* X = 0 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0[data & 0x0f] : baud_rate_ACR_1[data & 0x0f];
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int mcf5206e_uart_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate = 0;
+	u16 ubg_temp = 1;
+
+	if(UBG > 0) ubg_temp = UBG;
+
+	switch (data & 0xf){
+		case 0xe: baud_rate = ip3clk/16; break;
+		case 0xf: baud_rate = ip3clk; break;
+		case 0xd: baud_rate = (this->clock()/32) / ubg_temp; break;
+		default: LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data); break;
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+void duart_base_device::clear_ISR_bits(int mask)
+{
+	if (ISR & mask)
+	{
+		ISR &= ~mask;
+		update_interrupts();
+	}
+}
+
+void duart_base_device::set_ISR_bits(int mask)
+{
+	if (!(ISR & mask))
+	{
+		ISR |= mask;
+		update_interrupts();
+	}
+}
+
+// DUART channel class stuff
+
+duart_channel::duart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: device_t(mconfig, DUART_CHANNEL, tag, owner, clock)
+	, device_serial_interface(mconfig, *this)
+	, MR1(0)
+	, MR2(0)
+	, SR(0)
+	, rx_enabled(0)
+	, rx_fifo_num(0)
+	, m_tx_data_in_buffer(false)
+	, m_tx_break(false)
+	, m_bits_transmitted(255)
+	, m_tx_enabled(false)
+{
+	std::fill_n(&rx_fifo[0], MC68681_RX_FIFO_SIZE + 1, 0);
+}
+
+void duart_channel::device_start()
+{
+	m_uart = downcast<duart_base_device *>(owner());
+	m_ch = m_uart->get_ch(this);    // get our channel number
+
+	save_item(NAME(CR));
+	save_item(NAME(CSR));
+	save_item(NAME(MR1));
+	save_item(NAME(MR2));
+	save_item(NAME(MR_ptr));
+	save_item(NAME(SR));
+	save_item(NAME(rx_baud_rate));
+	save_item(NAME(tx_baud_rate));
+	save_item(NAME(rx_enabled));
+	save_item(NAME(rx_fifo));
+	save_item(NAME(rx_fifo_read_ptr));
+	save_item(NAME(rx_fifo_write_ptr));
+	save_item(NAME(rx_fifo_num));
+	save_item(NAME(m_tx_data));
+	save_item(NAME(m_tx_data_in_buffer));
+	save_item(NAME(m_tx_break));
+	save_item(NAME(m_bits_transmitted));
+	save_item(NAME(m_tx_enabled));
+}
+
+
+void duart_channel::device_reset()
+{
+	write_CR(0x10); // reset MR
+	write_CR(0x20); // reset Rx
+	write_CR(0x30); // reset Tx
+	write_CR(0x40); // reset errors
+
+	set_data_frame(1, 8, PARITY_NONE, STOP_BITS_1);
+
+	tx_baud_rate = rx_baud_rate = 0;
+	CSR = 0;
+	m_tx_break = false;
+}
+
+// serial device virtual overrides
+void duart_channel::rcv_complete()
+{
+	receive_register_extract();
+
+	//printf("%s ch %d rcv complete\n", tag(), m_ch);
+
+	if (rx_enabled || (MR2 & 0xc0) == 0x80)
+	{
+		uint8_t errors = 0;
+		if (is_receive_framing_error())
+			errors |= STATUS_FRAMING_ERROR;
+		if (is_receive_parity_error())
+			errors |= STATUS_PARITY_ERROR;
+		rx_fifo_push(get_received_char(), errors);
+	}
+}
+
+void duart_channel::rx_fifo_push(uint8_t data, uint8_t errors)
+{
+	if (rx_fifo_num == (MC68681_RX_FIFO_SIZE + 1))
+	{
+		logerror("68681: FIFO overflow\n");
+		SR |= STATUS_OVERRUN_ERROR;
+		// In case of overrun the FIFO tail entry is overwritten
+		// Back rx_fifo_write_ptr up by one position
+		if (rx_fifo_write_ptr)
+			rx_fifo_write_ptr--;
+		else
+			rx_fifo_write_ptr = MC68681_RX_FIFO_SIZE;
+	}
+
+	rx_fifo[rx_fifo_write_ptr++] = data | (errors << 8);
+	if (rx_fifo_write_ptr > MC68681_RX_FIFO_SIZE)
+		rx_fifo_write_ptr = 0;
+
+	if (rx_fifo_num <= MC68681_RX_FIFO_SIZE)
+	{
+		rx_fifo_num++;
+	}
+
+	if (rx_fifo_num == 1)
+	{
+		SR |= STATUS_RECEIVER_READY;
+		if (!(MR1 & MODE_BLOCK_ERROR))
+			SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+		SR |= errors;
+	}
+	if (rx_fifo_num == MC68681_RX_FIFO_SIZE)
+		SR |= STATUS_FIFO_FULL;
+	update_interrupts();
+}
+
+void duart_channel::tra_complete()
+{
+	// The transmit shift register has just emptied.  If another character is
+	// waiting in the THR, transfer it to the shift register and assert TxRDY:
+	// per the datasheet the THR->shift transfer is where the TxRDY conditions
+	// are re-asserted, providing "one full character time of buffering".  If the
+	// THR is empty the transmitter is now idle, so set TxEMT (TxRDY is already
+	// set from the previous transfer).
+	//
+	// Asserting TxRDY here, at the transfer -- rather than in the idle branch --
+	// both prevents the transmitter from deadlocking when TxRDY would otherwise
+	// fail to re-assert on a CPU-write / final-bit-time race, and preserves the
+	// one-character buffering window that firmware polling or pipelining on TxRDY
+	// relies on.
+	if (m_tx_data_in_buffer)
+	{
+		transmit_register_setup(m_tx_data);
+		m_bits_transmitted = 0;
+		m_tx_data_in_buffer = false;
+		SR |= STATUS_TRANSMITTER_READY;
+		update_interrupts();
+	}
+	else
+	{
+		SR |= STATUS_TRANSMITTER_EMPTY;
+		// VT1200 NOTE (local change, not upstream): also assert TxRDY here.  The
+		// VT1200 level-1 host-port test runs an interrupt-driven loopback: the
+		// DUART ISR writes the pattern byte on TxRDYA and, per transmit, reads
+		// SRA and expects the RX FIFO to have filled in step (FFULL before the
+		// 5th byte, OVR after it).  Asserting TxRDY mid-character (see the
+		// removed block in tra_callback below) made the ISR one byte ahead of
+		// the receiver, so the snapshots were FFULL/OVR one index too late and
+		// the test failed.  Asserting TxRDY when the shift register empties
+		// (the THR->TSR transfer point) makes the ISR pace one byte per
+		// character.  Revert: delete the STATUS_TRANSMITTER_READY term below
+		// and restore the removed block in tra_callback.
+		SR |= STATUS_TRANSMITTER_READY;
+		update_interrupts();
+	}
+}
+
+void duart_channel::tra_callback()
+{
+	// don't actually send in loopback mode
+	if ((MR2 & 0xc0) != 0x80)
+	{
+		int bit = transmit_register_get_data_bit();
+		//printf("%s ch %d transmit %d\n", tag(), m_ch, bit);
+		if (m_ch == 0)
+		{
+			m_uart->write_a_tx(bit);
+		}
+		else if (m_ch == 1)
+		{
+			m_uart->write_b_tx(bit);
+		}
+		else if (m_ch == 2)
+		{
+			m_uart->write_c_tx(bit);
+		}
+		else if (m_ch == 3)
+		{
+			m_uart->write_d_tx(bit);
+		}
+	}
+	else
+	{
+		// loop back transmitted bit
+		rx_w(transmit_register_get_data_bit());
+	}
+
+	// VT1200 NOTE (local change, not upstream): the upstream code asserted
+	// TxRDY here ("not until the end of start bit time") when no byte was
+	// buffered.  The datasheet instead asserts TxRDY at the THR->TSR transfer
+	// ("Data is transferred from the holding register to transmit shift
+	// register when it is idle or has completed transmission of the previous
+	// character.  The TxRDY conditions are then asserted again"), which is the
+	// character boundary for a buffered byte -- not mid-character.  Asserting
+	// on the start bit made the VT1200 loopback test's ISR run one byte ahead
+	// of the receiver.  Revert: remove the increment below and restore
+	//   if (m_bits_transmitted++ > 0 && !m_tx_data_in_buffer && m_tx_enabled)
+	//   {
+	//       SR |= STATUS_TRANSMITTER_READY;
+	//       update_interrupts();
+	//   }
+	m_bits_transmitted++;
+}
+
+void duart_channel::update_interrupts()
+{
+	// Handle the TxEMT and TxRDY bits based on mode
+	switch (MR2 & 0xc0) // what mode are we in?
+	{
+	case 0x00: // normal mode
+		break;
+	case 0x40: // automatic echo mode
+		SR &= ~STATUS_TRANSMITTER_READY;
+		break;
+	case 0x80: // local loopback mode
+		break;
+	case 0xc0: // remote loopback mode
+		SR &= ~STATUS_TRANSMITTER_READY;
+		break;
+	}
+
+	// now handle the ISR bits
+	if (SR & STATUS_TRANSMITTER_READY)
+	{
+		if (m_ch == 0)
+			m_uart->set_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->set_ISR_bits(INT_TXRDYB);
+	}
+	else
+	{
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+	}
+	//logerror("DEBUG: 68681 int check: before receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
+	if (MR1 & MODE_RX_INT_SELECT_BIT)
+	{
+		if (SR & STATUS_FIFO_FULL)
+		{
+			m_uart->set_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+		else
+		{
+			m_uart->clear_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+	}
+	else
+	{
+		if (SR & STATUS_RECEIVER_READY)
+		{
+			m_uart->set_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+		else
+		{
+			m_uart->clear_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+	}
+
+	//logerror("DEBUG: 68681 int check: after receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
+}
+
+uint8_t duart_channel::read_rx_fifo()
+{
+	uint8_t rv;
+
+	//printf("read_rx_fifo: rx_fifo_num %d\n", rx_fifo_num);
+
+	if (rx_fifo_num == 0)
+	{
+		LOG("68681 channel: rx fifo underflow\n");
+		update_interrupts();
+		return 0;
+	}
+
+	rv = rx_fifo[rx_fifo_read_ptr++];
+	if (rx_fifo_read_ptr > MC68681_RX_FIFO_SIZE)
+	{
+		rx_fifo_read_ptr = 0;
+	}
+
+	rx_fifo_num--;
+	if (rx_fifo_num == (MC68681_RX_FIFO_SIZE - 1))
+	{
+		SR &= ~STATUS_FIFO_FULL;
+	}
+
+	if (!(MR1 & MODE_BLOCK_ERROR))
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+	if (rx_fifo_num == 0)
+		SR &= ~STATUS_RECEIVER_READY;
+	else
+		SR |= rx_fifo[rx_fifo_read_ptr] >> 8;
+	update_interrupts();
+
+	//printf("Rx read %02x\n", rv);
+
+	return rv;
+}
+
+uint8_t duart_channel::read_chan_reg(int reg)
+{
+	uint8_t rv = 0xff;
+
+	switch (reg)
+	{
+	case 0: // MR1/MR2
+		if (MR_ptr == 0)
+		{
+			rv = MR1;
+			MR_ptr = 1;
+		}
+		else
+		{
+			rv = MR2;
+		}
+		break;
+
+	case 1: // SRA
+		rv = SR;
+		break;
+
+	case 2: // CSRA: reading this is prohibited
+		break;
+
+	case 3: // Rx holding register A
+		rv = read_rx_fifo();
+		break;
+	}
+
+	return rv;
+}
+
+void duart_channel::write_chan_reg(int reg, uint8_t data)
+{
+	switch (reg)
+	{
+	case 0x00: /* MRA */
+		write_MR(data);
+		break;
+
+	case 0x01: /* CSR */
+		CSR = data;
+		tx_baud_rate = m_uart->calc_baud(m_ch, false, data & 0xf);
+		rx_baud_rate = m_uart->calc_baud(m_ch, true, (data>>4) & 0xf);
+		//printf("%s ch %d CSR %02x Tx baud %d Rx baud %d\n", tag(), m_ch, data, tx_baud_rate, rx_baud_rate);
+		set_rcv_rate(rx_baud_rate);
+		set_tra_rate(tx_baud_rate);
+		break;
+
+	case 0x02: /* CR */
+		write_CR(data);
+		break;
+
+	case 0x03: /* THR */
+		write_TX(data);
+		break;
+	}
+}
+
+void duart_channel::write_MR(uint8_t data)
+{
+	if (MR_ptr == 0)
+	{
+		MR1 = data;
+		MR_ptr = 1;
+	}
+	else
+	{
+		MR2 = data;
+	}
+	recalc_framing();
+	update_interrupts();
+}
+
+void duart_channel::recalc_framing()
+{
+	parity_t parity = PARITY_NONE;
+	switch ((MR1 >> 3) & 3)
+	{
+	case 0: // with parity
+		if (MR1 & 4)
+			parity = PARITY_ODD;
+		else
+			parity = PARITY_EVEN;
+		break;
+
+	case 1: // force parity
+		if (MR1 & 4)
+			parity = PARITY_MARK;
+		else
+			parity = PARITY_SPACE;
+		break;
+
+	case 2: // no parity
+		parity = PARITY_NONE;
+		break;
+
+	case 3: // multidrop mode
+		// fatalerror("68681: multidrop parity not supported\n");
+		// Apollo DEX CPU will test this; omit to abort the emulation
+		logerror("68681: multidrop parity not supported\n");
+		break;
+	}
+
+	stop_bits_t stopbits = STOP_BITS_0;
+	switch ((MR2 >> 2) & 3)
+	{
+	case 0:
+	case 1:
+		stopbits = STOP_BITS_1;
+		break;
+
+	case 2: // "1.5 async, 2 sync"
+		stopbits = STOP_BITS_1_5;
+		break;
+
+	case 3:
+		stopbits = STOP_BITS_2;
+		break;
+	}
+
+	//printf("%s ch %d MR1 %02x MR2 %02x => %d bits / char, %d stop bits, parity %d\n", tag(), m_ch, MR1, MR2, (MR1 & 3)+5, stopbits, parity);
+
+	set_data_frame(1, (MR1 & 3) + 5, parity, stopbits);
+}
+
+void duart_channel::write_CR(uint8_t data)
+{
+	switch ((data >> 4) & 0x07)
+	{
+	case 0: /* No command */
+		break;
+	case 1: /* Reset MR pointer. Causes the channel MR pointer to point to MR1 */
+		MR_ptr = 0;
+		break;
+	case 2: /* Reset channel receiver (disable receiver and flush fifo) */
+		rx_enabled = 0;
+		SR &= ~STATUS_RECEIVER_READY;
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+		SR &= ~STATUS_OVERRUN_ERROR; // is this correct?
+		rx_fifo_read_ptr = 0;
+		rx_fifo_write_ptr = 0;
+		rx_fifo_num = 0;
+		receive_register_reset();
+		break;
+	case 3: /* Reset channel transmitter */
+		SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+		if (m_ch == 0)
+		{
+			m_uart->write_a_tx(1);
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		}
+		else
+		{
+			m_uart->write_b_tx(1);
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+		}
+		transmit_register_reset();
+		m_bits_transmitted = 255;
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = false;
+		break;
+	case 4: /* Reset Error Status */
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR | STATUS_OVERRUN_ERROR);
+		break;
+	case 5: /* Reset Channel break change interrupt */
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_DELTA_BREAK_A);
+		else
+			m_uart->clear_ISR_bits(INT_DELTA_BREAK_B);
+		break;
+	case 6: /* Start Tx break */
+		if (!m_tx_break)
+		{
+			m_tx_break = true;
+			if ((MR2 & 0xc0) == 0x80)
+			{
+				// Local loopback mode: set delta break in ISR, simulate break rx
+				if (m_ch == 0)
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_A);
+				else
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_B);
+				rx_fifo_push(0 , STATUS_RECEIVED_BREAK);
+			}
+			// TODO: Actually send break signal
+		}
+		break;
+	case 7: /* Stop tx break */
+		if (m_tx_break)
+		{
+			m_tx_break = false;
+			if ((MR2 & 0xc0) == 0x80)
+			{
+				// Local loopback mode: set delta break in ISR
+				if (m_ch == 0)
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_A);
+				else
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_B);
+			}
+		}
+		break;
+	default:
+		LOG("68681: Unhandled command (%x) in CR%d\n", (data >> 4) & 0x07, m_ch);
+		break;
+	}
+
+	if (BIT(data, 0))
+	{
+		rx_enabled = 1;
+	}
+	if (BIT(data, 1))
+	{
+		rx_enabled = 0;
+		SR &= ~STATUS_RECEIVER_READY;
+	}
+
+	if (!BIT(CR, 2) && BIT(data, 2))
+	{
+		SR |= STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY;
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = true;
+		if (m_ch == 0)
+			m_uart->set_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->set_ISR_bits(INT_TXRDYB);
+	}
+	if (BIT(data, 3))
+	{
+		SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = false;
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+	}
+
+	update_interrupts();
+	CR = data;
+}
+
+void duart_channel::write_TX(uint8_t data)
+{
+	if (!(SR & STATUS_TRANSMITTER_READY))
+	{
+		logerror("write_tx transmitter not ready (data 0x%02x discarded)\n", data);
+		return;
+	}
+
+	SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+	if (!is_transmit_register_empty())
+	{
+		m_tx_data = data;
+		m_tx_data_in_buffer = true;
+	}
+	else
+	{
+		transmit_register_setup(data);
+		m_bits_transmitted = 0;
+	}
+
+	update_interrupts();
+}
+
+void duart_channel::baud_updated()
+{
+	write_chan_reg(1, CSR);
+}
+
+uint8_t duart_channel::get_chan_CSR()
+{
+	return CSR;
+}
+
+void duart_channel::tx_16x_clock_w(bool state)
+{
+	if (state)
+	{
+		m_tx_prescaler--;
+		if (m_tx_prescaler == 8)
+		{
+			tx_clock_w(true);
+		}
+		else if (m_tx_prescaler == 0)
+		{
+			m_tx_prescaler = 16;
+			tx_clock_w(false);
+		}
+	}
+}
+
+void duart_channel::rx_16x_clock_w(bool state)
+{
+	if (!is_receive_register_synchronized())
+	{
+		// Skip over the start bit once synchonization is achieved
+		m_rx_prescaler = 32;
+		rx_clock_w(true);
+	}
+	else if (state)
+	{
+		m_rx_prescaler--;
+		if (m_rx_prescaler == 8)
+		{
+			rx_clock_w(false);
+		}
+		else if (m_rx_prescaler == 0)
+		{
+			m_rx_prescaler = 16;
+			rx_clock_w(true);
+		}
+	}
+}
diff --git a/harness/mame/mame_edits/mc68681.cpp.upstream b/harness/mame/mame_edits/mc68681.cpp.upstream
new file mode 100644
index 0000000..70d3cfd
--- /dev/null
+++ b/harness/mame/mame_edits/mc68681.cpp.upstream
@@ -0,0 +1,1906 @@
+// license:BSD-3-Clause
+// copyright-holders:Mariusz Wojcieszek, R. Belmont, Joseph Zatarski
+/*
+    2681 DUART
+    68681 DUART
+    28C94 QUART
+    68340 serial module
+    XR68C681 DUART (backwards compatible with 68681 with some improvements)
+
+    Written by Mariusz Wojcieszek
+    Updated by Jonathan Gevaryahu AKA Lord Nightmare
+    Improved interrupt handling by R. Belmont
+    Rewrite and modernization in progress by R. Belmont
+    Addition of the duart compatible 68340 serial module support by Edstrom
+    Support for the Exar XR68C681 by Joseph Zatarski (July of 2018)
+    Support for Freescale/NXP ColdFire UART module by NaokiS (June 2025)
+
+    The main incompatibility between the 2681 and 68681 (Signetics and Motorola each
+    manufactured both versions of the chip) is that the 68681 has a R/W input and
+    generates a 68000-compatible DTACK signal, instead of using generic RD and WR
+    strobes as the 2681 does. The 68681 also adds a programmable interrupt vector,
+    with an IACK input replacing IP6.
+
+    The command register addresses should never be read from. Doing so may place
+    the baud rate generator into a test mode which drives the parallel outputs with
+    internal counters and causes serial ports to operate at uncontrollable rates.
+
+    Exar XR68C681
+
+    The XR68C681 is an improvement upon the MC68681 which supports more baud
+    rates, adds an additional MISR (masked ISR) register, and adds a low-power
+    standby mode. There may be other differences, but these are the most
+    notable.
+
+    The extra baud rates are implemented by an 'X' bit for each channel. The X
+    bit chooses between two baud rate tables, in addition to the ACR[7] bit.
+    The X bit is changed by additional commands that are written to CRA and CRB.
+
+    The MISR is a read only register that takes the place of the 'BRG Test'
+    register on the MC68681.
+
+    The low power standby mode is entered and left by a command written to CRA
+    or CRB registers. Writing the commands to either register affects the whole
+    DUART, not just one channel. Resetting the DUART also leaves low power mode.
+
+    On the ColdFire MCF5206e, the UART modules are essentially just a pair of
+    MC68681s with only the A port visible and no counter/timer. The ACR on the
+    coldfire uarts shoud be updated to reflect this. Additionally, the
+    Baud Rate Generator prescaler reg should be used to set the baud.
+*/
+
+#include "emu.h"
+#include "mc68681.h"
+
+#include <algorithm>
+
+//#define VERBOSE 1
+//#define LOG_OUTPUT_FUNC printf
+#include "logmacro.h"
+
+
+static const char *const duart68681_reg_read_names[0x10] =
+{
+	"MRA", "SRA", "BRG Test", "RHRA", "IPCR", "ISR", "CTU", "CTL", "MRB", "SRB", "1X/16X Test", "RHRB", "IVR", "Input Ports", "Start Counter", "Stop Counter"
+};
+
+static const char *const duart68681_reg_write_names[0x10] =
+{
+	"MRA", "CSRA", "CRA", "THRA", "ACR", "IMR", "CTUR", "CTLR", "MRB", "CSRB", "CRB", "THRB", "IVR", "OPCR", "Set OP Bits", "Reset OP Bits"
+};
+
+static const char *const mcf5206e_duart_reg_read_names[0x10] =
+{
+	"UMR", "USR", "NO ACCESS", "URB", "UIPCR", "UISR", "UBG1", "UBG2", "NO ACCESS", "NO ACCESS", "NO ACCESS", "NO ACCESS", "UIVR", "UIP Input Ports", "NO ACCESS", "NO ACCESS"
+};
+
+static const char *const mcf5206e_duart_reg_write_names[0x10] =
+{
+	"UMR", "UCSR", "UCRA", "UTB", "UACR", "UIMR", "UBG1", "UBG2", "NO ACCESS", "NO ACCESS", "NO ACCESS", "NO ACCESS", "IVR", "NO ACCESS", "Set OP Bits", "Reset OP Bits"
+};
+
+static const int baud_rate_ACR_0[] =     { 50, 110, 134, 200, 300,  600,   1200,  1050,  2400,   4800, 7200, 9600, 38400, 0, 0, 0 }; /* xr68c681 X=0 */
+static const int baud_rate_ACR_0_X_1[] = { 75, 110, 134, 150, 3600, 14400, 28800, 57600, 115200, 4800, 1800, 9600, 19200, 0, 0, 0 };
+static const int baud_rate_ACR_1[] =     { 75, 110, 134, 150, 300,  600,   1200,  2000,  2400,   4800, 1800, 9600, 19200, 0, 0, 0 }; /* xr68c681 X=0 */
+static const int baud_rate_ACR_1_X_1[] = { 50, 110, 134, 200, 3600, 14400, 28800, 57600, 115200, 4800, 7200, 9600, 38400, 0, 0, 0 };
+
+static const int baud_rate_ACR_0_340[] = { 50, 110, 134, 200, 300,  600,   1200,  1050,  2400,   4800, 7200, 9600, 38400, 76800, 0, 0 }; /* xr68c681 ACR:7=0 */
+static const int baud_rate_ACR_1_340[] = { 75, 110, 134, 150, 300,  600,   1200,  2000,  2400,   4800, 1800, 9600, 19200, 38400, 0, 0 }; /* xr68c681 ACR:7=1 */
+
+#define INT_INPUT_PORT_CHANGE       0x80
+#define INT_DELTA_BREAK_B           0x40
+#define INT_RXRDY_FFULLB            0x20
+#define INT_TXRDYB                  0x10
+#define INT_COUNTER_READY           0x08
+#define INT_DELTA_BREAK_A           0x04
+#define INT_RXRDY_FFULLA            0x02
+#define INT_TXRDYA                  0x01
+
+#define STATUS_RECEIVED_BREAK       0x80
+#define STATUS_FRAMING_ERROR        0x40
+#define STATUS_PARITY_ERROR         0x20
+#define STATUS_OVERRUN_ERROR        0x10
+#define STATUS_TRANSMITTER_EMPTY    0x08
+#define STATUS_TRANSMITTER_READY    0x04
+#define STATUS_FIFO_FULL            0x02
+#define STATUS_RECEIVER_READY       0x01
+
+#define MODE_RX_INT_SELECT_BIT      0x40
+#define MODE_BLOCK_ERROR            0x20
+
+#define CHANA_TAG   "cha"
+#define CHANB_TAG   "chb"
+#define CHANC_TAG   "chc"
+#define CHAND_TAG   "chd"
+
+// device type definition
+DEFINE_DEVICE_TYPE(SCN2681, scn2681_device, "scn2681", "SCN2681 DUART")
+DEFINE_DEVICE_TYPE(MC68681, mc68681_device, "mc68681", "MC68681 DUART")
+DEFINE_DEVICE_TYPE(MCF5206E_UART, mcf5206e_uart_device, "mcf5206euart", "MCF5206e UART")
+DEFINE_DEVICE_TYPE(SC28C94, sc28c94_device, "sc28c94", "SC28C94 QUART")
+DEFINE_DEVICE_TYPE(MC68340_DUART, mc68340_duart_device, "mc68340duart", "MC68340 DUART")
+DEFINE_DEVICE_TYPE(XR68C681, xr68c681_device, "xr68c681", "XR68C681 DUART")
+DEFINE_DEVICE_TYPE(DUART_CHANNEL, duart_channel, "duart_channel", "DUART channel")
+
+
+//**************************************************************************
+//  LIVE DEVICE
+//**************************************************************************
+
+duart_base_device::duart_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, type, tag, owner, clock),
+	m_chanA(*this, CHANA_TAG),
+	m_chanB(*this, CHANB_TAG),
+	m_chanC(*this, CHANC_TAG),
+	m_chanD(*this, CHAND_TAG),
+	write_irq(*this),
+	write_a_tx(*this),
+	write_b_tx(*this),
+	write_c_tx(*this),
+	write_d_tx(*this),
+	read_inport(*this, 0),
+	write_outport(*this),
+	ip3clk(0),
+	ip4clk(0),
+	ip5clk(0),
+	ip6clk(0),
+	ACR(0),
+	IP_last_state(0)
+{
+}
+
+scn2681_device::scn2681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, SCN2681, tag, owner, clock)
+{
+}
+
+mc68681_device::mc68681_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+	, m_read_vector(false)
+{
+}
+
+mc68681_device::mc68681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68681_device(mconfig, MC68681, tag, owner, clock)
+{
+}
+
+mcf5206e_uart_device::mcf5206e_uart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+	, m_read_vector(false)
+{
+}
+
+mcf5206e_uart_device::mcf5206e_uart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, MCF5206E_UART, tag, owner, clock)
+{
+}
+
+
+sc28c94_device::sc28c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, SC28C94, tag, owner, clock)
+{
+}
+
+//--------------------------------------------------------------------------------------------------------------------
+// The read and write methods are meant to catch all differences in the register model between 68681 and 68340
+// serial module. Eg some registers are (re)moved into the 68340 like the vector register. There are also no counter
+// in the 68340. The CSR clock register is also different for the external clock modes. The implementation assumes
+// that the code knows all of this and will not warn if those registers are accessed as it could be ported code.
+// TODO: A lot of subtle differences and also detect misuse of unavailable registers as they should be ignored
+//--------------------------------------------------------------------------------------------------------------------
+mc68340_duart_device::mc68340_duart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+	: duart_base_device(mconfig, type, tag, owner, clock)
+{
+}
+
+mc68340_duart_device::mc68340_duart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68340_duart_device(mconfig, MC68340_DUART, tag, owner, clock)
+{
+}
+
+xr68c681_device::xr68c681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: mc68681_device(mconfig, XR68C681, tag, owner, clock)
+	, m_XTXA(false)
+	, m_XRXA(false)
+	, m_XTXB(false)
+	, m_XRXB(false)
+{
+}
+
+//-------------------------------------------------
+//  set_clocks - configuration helper to set
+//  the external clocks
+//-------------------------------------------------
+
+void duart_base_device::set_clocks(int clk3, int clk4, int clk5, int clk6)
+{
+	ip3clk = clk3;
+	ip4clk = clk4;
+	ip5clk = clk5;
+	ip6clk = clk6;
+}
+
+/*-------------------------------------------------
+    device start callback
+-------------------------------------------------*/
+
+void duart_base_device::device_start()
+{
+	duart_timer = timer_alloc(FUNC(duart_base_device::duart_timer_callback), this);
+
+	save_item(NAME(ACR));
+	save_item(NAME(IMR));
+	save_item(NAME(ISR));
+	save_item(NAME(OPCR));
+	save_item(NAME(OPR));
+	save_item(NAME(CTR));
+	save_item(NAME(IPCR));
+	save_item(NAME(IP_last_state));
+	save_item(NAME(half_period));
+	save_item(NAME(m_irq_state));
+}
+
+void mc68681_device::device_start()
+{
+	duart_base_device::device_start();
+
+	save_item(NAME(m_read_vector));
+	save_item(NAME(IVR));
+}
+
+void mcf5206e_uart_device::device_start()
+{
+	duart_base_device::device_start();
+
+	save_item(NAME(m_read_vector));
+	save_item(NAME(IVR));
+	save_item(NAME(UBG));
+}
+
+void xr68c681_device::device_start()
+{
+	mc68681_device::device_start();
+
+	save_item(NAME(m_XTXA));
+	save_item(NAME(m_XRXA));
+	save_item(NAME(m_XTXB));
+	save_item(NAME(m_XRXB));
+}
+
+/*-------------------------------------------------
+    device reset callback
+-------------------------------------------------*/
+
+void duart_base_device::device_reset()
+{
+	ACR = 0;  /* Interrupt Vector Register */
+	IMR = 0;  /* Interrupt Mask Register */
+	ISR = 0;  /* Interrupt Status Register */
+	OPCR = 0; /* Output Port Conf. Register */
+	OPR = 0;  /* Output Port Register */
+	CTR.d = 0;  /* Counter/Timer Preset Value */
+	// "reset clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR) puts OP0-7 in the high state, stops the counter/timer, and puts channels a/b in the inactive state"
+	IPCR = 0;
+
+	m_irq_state = false;
+	write_irq(CLEAR_LINE);
+	write_outport(OPR ^ 0xff);
+}
+
+void mc68681_device::device_reset()
+{
+	duart_base_device::device_reset();
+
+	IVR = 0x0f;  /* Interrupt Vector Register */
+	m_read_vector = false;
+}
+
+void mcf5206e_uart_device::device_reset()
+{
+	duart_base_device::device_reset();
+
+	IVR = 0x0f;  /* Interrupt Vector Register */
+	UBG = 0x00;  /* UART Baud Rate Generator Register */
+	m_read_vector = false;
+}
+
+void xr68c681_device::device_reset()
+{
+	mc68681_device::device_reset();
+
+	m_XTXA = m_XRXA = m_XTXB = m_XRXB = false;
+}
+
+void duart_base_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void sc28c94_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+	DUART_CHANNEL(config, CHANC_TAG);
+	DUART_CHANNEL(config, CHAND_TAG);
+}
+
+void mc68340_duart_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void mcf5206e_uart_device::device_add_mconfig(machine_config &config)
+{
+	DUART_CHANNEL(config, CHANA_TAG);
+	DUART_CHANNEL(config, CHANB_TAG);
+}
+
+void duart_base_device::update_interrupts()
+{
+	/* update SR state and update interrupt ISR state for the following bits:
+	SRn: bits 7-4: handled elsewhere.
+	SRn: bit 3 (TxEMTn) (we can assume since we're not actually emulating the delay/timing of sending bits, that as long as TxRDYn is set, TxEMTn is also set since the transmit byte has 'already happened', therefore TxEMTn is always 1 assuming tx is enabled on channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined)
+	SRn: bit 2 (TxRDYn) (we COULD assume since we're not emulating delay and timing output, that as long as tx is enabled on channel n, TxRDY is 1 for channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined; however, tx_ready is already nicely handled for us elsewhere, so we can use that instead for now, though we may need to retool that code as well)
+	SRn: bit 1 (FFULLn) (this bit we actually emulate; if the receive fifo for channel n is full, this bit is 1, otherwise it is 0. the receive fifo should be three words long.)
+	SRn: bit 0 (RxRDYn) (this bit we also emulate; the bit is always asserted if the receive fifo is not empty)
+	ISR: bit 7: Input Port change; this should be handled elsewhere, on the input port handler
+	ISR: bit 6: Delta Break B; this should be handled elsewhere, on the data receive handler
+	ISR: bit 5: RxRDYB/FFULLB: this is handled here; depending on whether MSR1B bit 6 is 0 or 1, this bit holds the state of SRB bit 0 or bit 1 respectively
+	ISR: bit 4: TxRDYB: this is handled here; it mirrors SRB bit 2
+	ISR: bit 3: Counter ready; this should be handled by the timer generator
+	ISR: bit 2: Delta Break A; this should be handled elsewhere, on the data receive handler
+	ISR: bit 1: RxRDYA/FFULLA: this is handled here; depending on whether MSR1A bit 6 is 0 or 1, this bit holds the state of SRA bit 0 or bit 1 respectively
+	ISR: bit 0: TxRDYA: this is handled here; it mirrors SRA bit 2
+	*/
+	if ((ISR & IMR) != 0)
+	{
+		if (!m_irq_state)
+		{
+			m_irq_state = true;
+			LOG("Interrupt line active (IMR & ISR = %02X)\n", (ISR & IMR));
+			write_irq(ASSERT_LINE);
+		}
+	}
+	else
+	{
+		if (m_irq_state)
+		{
+			m_irq_state = false;
+			LOG("Interrupt line not active (IMR & ISR = %02X)\n", ISR & IMR);
+			write_irq(CLEAR_LINE);
+		}
+	}
+	if (OPCR & 0xf0)
+	{
+		if (BIT(OPCR, 4))
+		{
+			if (BIT(ISR, 1))
+				OPR |= 0x10;
+			else
+				OPR &= ~0x10;
+		}
+		if (BIT(OPCR, 5))
+		{
+			if (BIT(ISR, 5))
+				OPR |= 0x20;
+			else
+				OPR &= ~0x20;
+		}
+		if (BIT(OPCR, 6))
+		{
+			if (BIT(ISR, 0))
+				OPR |= 0x40;
+			else
+				OPR &= ~0x40;
+		}
+		if (BIT(OPCR, 7))
+		{
+			if (BIT(ISR, 4))
+				OPR |= 0x80;
+			else
+				OPR &= ~0x80;
+		}
+		write_outport(OPR ^ 0xff);
+	}
+}
+
+void mc68681_device::update_interrupts()
+{
+	duart_base_device::update_interrupts();
+
+	if (!irq_pending())
+		m_read_vector = false;  // clear IACK too
+}
+
+uint8_t mc68681_device::get_irq_vector()
+{
+	if (!machine().side_effects_disabled())
+		m_read_vector = true;
+
+	return IVR;
+}
+
+void mcf5206e_uart_device::update_interrupts()
+{
+	duart_base_device::update_interrupts();
+
+	if (!irq_pending())
+		m_read_vector = false;  // clear IACK too
+}
+
+uint8_t mcf5206e_uart_device::get_irq_vector()
+{
+	if (!machine().side_effects_disabled())
+		m_read_vector = true;
+
+	return IVR;
+}
+
+uint32_t duart_base_device::get_ct_rate()
+{
+	uint32_t rate = 0;
+
+	if (ACR & 0x40)
+	{
+		// Timer mode
+		switch ((ACR >> 4) & 3)
+		{
+		case 0: // IP2
+		case 1: // IP2 / 16
+			//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", duart68681->tag(), (duart68681->ACR >> 4) & 3);
+			rate = clock();
+			break;
+		case 2: // X1/CLK
+			rate = clock();
+			break;
+		case 3: // X1/CLK / 16
+			rate = clock() / 16;
+			break;
+		}
+	}
+	else
+	{
+		// Counter mode
+		switch ((ACR >> 4) & 3)
+		{
+		case 0: // IP2
+			//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", device->tag(), (duart68681->ACR >> 4) & 3);
+			rate = clock();
+			break;
+		case 1: // TxCA
+			rate = m_chanA->get_tx_rate();
+			break;
+		case 2: // TxCB
+			rate = m_chanB->get_tx_rate();
+			break;
+		case 3: // X1/CLK / 16
+			rate = clock() / 16;
+			break;
+		}
+	}
+
+	return rate;
+}
+
+uint16_t duart_base_device::get_ct_count()
+{
+	uint32_t clock = get_ct_rate();
+	return duart_timer->remaining().as_ticks(clock);
+}
+
+void duart_base_device::start_ct(int count)
+{
+	uint32_t clock = get_ct_rate();
+	duart_timer->adjust(attotime::from_ticks(count, clock), 0);
+}
+
+TIMER_CALLBACK_MEMBER(duart_base_device::duart_timer_callback)
+{
+	if (ACR & 0x40)
+	{
+		// Timer mode
+		half_period ^= 1;
+
+		// timer output to bit 3?
+		if ((OPCR & 0xc) == 0x4)
+		{
+			OPR ^= 0x8;
+			write_outport(OPR ^ 0xff);
+		}
+
+		// timer driving any serial channels?
+		uint8_t csr = m_chanA->get_chan_CSR();
+
+		if ((csr & 0x0f) == 0x0d)   // tx is timer driven
+		{
+			m_chanA->tx_16x_clock_w(half_period);
+		}
+		if ((csr & 0xf0) == 0xd0)   // rx is timer driven
+		{
+			m_chanA->rx_16x_clock_w(half_period);
+		}
+
+		csr = m_chanB->get_chan_CSR();
+		if ((csr & 0x0f) == 0x0d)   // tx is timer driven
+		{
+			m_chanB->tx_16x_clock_w(half_period);
+		}
+		if ((csr & 0xf0) == 0xd0)   // rx is timer driven
+		{
+			m_chanB->rx_16x_clock_w(half_period);
+		}
+
+		if (!half_period)
+			set_ISR_bits(INT_COUNTER_READY);
+
+		int count = std::max(CTR.w.l, uint16_t(1));
+		start_ct(count);
+	}
+	else
+	{
+		// assert OP3 counter ready
+		if ((OPCR & 0xc) == 0x4)
+			OPR |= 0x8;
+
+		// Counter mode
+		set_ISR_bits(INT_COUNTER_READY);
+		start_ct(0xffff);
+	}
+
+}
+
+uint8_t mc68681_device::read(offs_t offset)
+{
+	if (offset == 0x0c)
+		return IVR;
+
+	uint8_t r = duart_base_device::read(offset);
+
+	if (offset == 0x0d)
+	{
+		// bit 6 is /IACK (note the active-low)
+		if (m_read_vector)
+			r &= ~0x40;
+		else
+			r |= 0x40;
+	}
+
+	return r;
+}
+
+// TODO: move me out of here, it's one channel per UART not 2
+uint8_t mcf5206e_uart_device::read(offs_t offset)
+{
+	uint8_t r = 0xff;
+
+	switch (offset)
+	{
+	case 0x00: /* UMR1/UMR2 */
+	case 0x01: /* USR */
+	case 0x03: /* URBA Receive Buffer Register */
+	case 0x04: /* UIPCR */
+	case 0x05: /* UISR */
+	case 0x0d: /* UIP */
+		r = duart_base_device::read(offset);
+		break;
+
+	case 0x06: /* UBG Baud Generator Prescale MSB */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = (UBG & 0xFF00) >> 8;
+		break;
+	case 0x07: /* UBG Baud Generator Prescale LSB */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = (UBG & 0x00FF);
+		break;
+
+	case 0x0c:  /* UIVR */
+	LOG("%s: Reading mcf5206e (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_read_names[offset]);
+		r = IVR;
+		break;
+
+	default:
+		LOG("Reading unhandled mcf5206e reg %x\n", offset);
+		break;
+	}
+	LOG("returned %02x\n", r);
+
+	return r;
+}
+
+uint8_t mc68340_duart_device::read(offs_t offset)
+{
+	uint8_t r = 0;
+
+	switch (offset)
+	{
+	case 0x00: /* MR1A - does not share register address with MR2A */
+		r = m_chanA->read_MR1();
+		break;
+	case 0x08: /* MR1B - does not share register address with MR2B */
+		r = m_chanB->read_MR1();
+		break;
+	case 0x10: /* MR2A - does not share register address with MR1A */
+		r = m_chanA->read_MR2();
+		break;
+	case 0x11: /* MR2B - does not share register address with MR1B */
+		r = m_chanB->read_MR2();
+		break;
+	default:
+		r = duart_base_device::read(offset);
+	}
+	return r;
+}
+
+uint8_t sc28c94_device::read(offs_t offset)
+{
+	uint8_t r = 0;
+	offset &= 0x1f;
+
+	if (offset < 0x10)
+	{
+		return duart_base_device::read(offset);
+	}
+
+	switch (offset)
+	{
+	case 0x10: /* MR1A/MR2C */
+	case 0x11: /* SRC */
+	case 0x13: /* Rx Holding Register C */
+		r = m_chanC->read_chan_reg(offset & 3);
+		break;
+
+	case 0x18: /* MR1D/MR2D */
+	case 0x19: /* SRD */
+	case 0x1b: /* RHRD */
+		r = m_chanD->read_chan_reg(offset & 3);
+		break;
+	}
+
+	return r;
+}
+
+uint8_t xr68c681_device::read(offs_t offset)
+{
+	if (offset == 0x02)
+	{
+		LOG("Reading XR68C681 (%s) reg 0x02 (MISR)\n", tag());
+		return ISR & IMR;
+	}
+	else
+		return mc68681_device::read(offset);
+}
+
+uint8_t duart_base_device::read(offs_t offset)
+{
+	uint8_t r = 0xff;
+
+	offset &= 0xf;
+
+	LOG("%s: Reading 68681 (%s) reg %x (%s)\n", this->machine().describe_context(), tag(), offset, duart68681_reg_read_names[offset]);
+
+	switch (offset)
+	{
+	case 0x00: /* MR1A/MR2A */
+	case 0x01: /* SRA */
+	case 0x03: /* Rx Holding Register A */
+		r = m_chanA->read_chan_reg(offset & 3);
+		break;
+
+	case 0x04: /* IPCR */
+		r = IPCR;
+
+		// reading this clears all the input change bits
+		IPCR &= 0x0f;
+		clear_ISR_bits(INT_INPUT_PORT_CHANGE);
+		break;
+
+	case 0x05: /* ISR */
+		r = ISR;
+		break;
+
+	case 0x06: /* CUR */
+		r = get_ct_count() >> 8;
+		break;
+
+	case 0x07: /* CLR */
+		r = get_ct_count() & 0xff;
+		break;
+
+	case 0x08: /* MR1B/MR2B */
+	case 0x09: /* SRB */
+	case 0x0b: /* RHRB */
+		r = m_chanB->read_chan_reg(offset & 3);
+		break;
+
+	case 0x0a: /* 1X/16X Test */
+		r = 0x61;   // the old 68681 returned this and it makes Apollo happy
+		break;
+
+	case 0x0d: /* IP */
+		if (!read_inport.isunset())
+		{
+			r = read_inport();  // TODO: go away
+		}
+		else
+		{
+			r = IP_last_state;
+		}
+
+		r |= 0x80;  // bit 7 is always set
+		break;
+
+	case 0x0e: /* Start counter command */
+	{
+		if (ACR & 0x40)
+		{
+			// Reset the timer
+			half_period = 0;
+		}
+
+		int count = std::max(CTR.w.l, uint16_t(1));
+		start_ct(count);
+		break;
+	}
+
+	case 0x0f: /* Stop counter command */
+
+		// Stop the counter only
+		if (!(ACR & 0x40))
+		{
+			duart_timer->enable(false);
+
+			// clear OP3 counter ready
+			if ((OPCR & 0xc) == 0x4)
+				OPR &= ~0x8;
+		}
+
+		clear_ISR_bits(INT_COUNTER_READY);
+		break;
+
+	default:
+		LOG("Reading unhandled 68681 reg %x\n", offset);
+		break;
+	}
+	LOG("returned %02x\n", r);
+
+	return r;
+}
+
+void mc68681_device::write(offs_t offset, uint8_t data)
+{
+	if (offset == 0x0c)
+		IVR = data;
+	else
+		duart_base_device::write(offset, data);
+}
+
+void mcf5206e_uart_device::write(offs_t offset, uint8_t data)
+{
+	switch (offset)
+	{
+	case 0x00: /* UMR */
+	case 0x01: /* UCSR */
+	case 0x03: /* UTB */
+	case 0x04: /* ACR */    // <-- TODO: This needs changing as ACR on ColdFire only handles interrupt enable for CTS
+	case 0x05: /* IMR */
+	case 0x0e: /* Set Output Port (RTS) Bit */
+	case 0x0f: /* Reset Output Port (RTS) Bit */
+		duart_base_device::write(offset, data);
+		break;
+
+	case 0x02: /* UCR */
+		// monomach uses 0x02 0x03 0x01 0x08 0x0c 0x04 at POST
+		// 3 and c are "Do Not Use" according to datasheet
+		// (already a good reason about not deriving from here ...)
+		if (data != 0xc && data != 0x3)
+			duart_base_device::write(offset, data);
+		break;
+
+	case 0x06: /* UBG1 */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		UBG = (UBG & 0x00ff) | (data << 8);
+		break;
+	case 0x07: /* UBG2 */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		UBG = (UBG & 0xff00) | data;
+		m_chanA->baud_updated();
+		m_chanA->update_interrupts();
+		break;
+
+	case 0x0c: /* UIVR */
+	LOG("%s: Writing mcf5206e (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, mcf5206e_duart_reg_write_names[offset], data);
+		IVR = data;
+		break;
+
+	default: break;
+	}
+}
+
+void mc68340_duart_device::write(offs_t offset, uint8_t data)
+{
+	//printf("Duart write %02x -> %02x\n", data, offset);
+
+	switch(offset)
+	{
+	case 0x00: /* MR1A - does not share register address with MR2A */
+		m_chanA->write_MR1(data);
+		break;
+	case 0x08: /* MR1B - does not share register address with MR2B */
+		m_chanB->write_MR1(data);
+		break;
+	case 0x10: /* MR2A - does not share register address with MR1A */
+		m_chanA->write_MR2(data);
+		break;
+	case 0x11: /* MR2B - does not share register address with MR1B */
+		m_chanB->write_MR2(data);
+		break;
+	default:
+		duart_base_device::write(offset, data);
+	}
+}
+
+void sc28c94_device::write(offs_t offset, uint8_t data)
+{
+	offset &= 0x1f;
+
+	if (offset < 0x10)
+	{
+		duart_base_device::write(offset, data);
+	}
+
+	switch (offset)
+	{
+	case 0x10: /* MRC */
+	case 0x11: /* CSRC */
+	case 0x12: /* CRC */
+	case 0x13: /* THRC */
+		m_chanC->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x18: /* MRC */
+	case 0x19: /* CSRC */
+	case 0x1a: /* CRC */
+	case 0x1b: /* THRC */
+		m_chanD->write_chan_reg(offset&3, data);
+		break;
+	}
+}
+
+void xr68c681_device::write(offs_t offset, uint8_t data)
+{
+	if (offset == 0x02) /* CRA */
+		switch (data >> 4)
+		{
+		case 0x08: /* set RX extend bit */
+			m_XRXA = true;
+			m_chanA->baud_updated();
+			data &= 0x0f; /* disable command before we send it off to 68681 */
+			break;
+
+		case 0x09: /* clear RX extend bit */
+			m_XRXA = false;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0a: /* set TX extend bit */
+			m_XTXA = true;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0b: /* clear TX extend bit */
+			m_XTXA = false;
+			m_chanA->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0c: /* enter low power mode TODO: unimplemented */
+		case 0x0d: /* leave low power mode */
+		case 0x0e: /* reserved */
+		case 0x0f: /* reserved */
+			data &= 0x0f;
+			break;
+		}
+
+	else if (offset == 0x0a) /* CRB */
+		switch (data >> 4)
+		{
+		case 0x08: /* set RX extend bit */
+			m_XRXB = true;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x09: /* clear RX extend bit */
+			m_XRXB = false;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0a: /* set TX extend bit */
+			m_XTXB = true;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0b: /* clear TX extend bit */
+			m_XTXB = false;
+			m_chanB->baud_updated();
+			data &= 0x0f;
+			break;
+
+		case 0x0c: /* enter low power mode TODO: unimplemented */
+		case 0x0d: /* leave low power mode */
+		case 0x0e: /* reserved */
+		case 0x0f: /* reserved */
+			data &= 0x0f;
+			break;
+		}
+
+	mc68681_device::write(offset, data); /* pass on 68681 command */
+}
+
+void duart_base_device::write(offs_t offset, uint8_t data)
+{
+	offset &= 0x0f;
+	LOG("%s: Writing 68681 (%s) reg %x (%s) with %02x\n", this->machine().describe_context(), tag(), offset, duart68681_reg_write_names[offset], data);
+	switch (offset)
+	{
+	case 0x00: /* MRA */
+	case 0x01: /* CSRA */
+	case 0x02: /* CRA */
+	case 0x03: /* THRA */
+		m_chanA->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x04: /* ACR */
+	{
+		uint8_t old_acr = ACR;
+		ACR = data;
+
+		//       bits 6-4: Counter/Timer Mode And Clock Source Select
+		//       bits 3-0: IP3-0 Change-Of-State Interrupt Enable
+		if ((old_acr ^ data) & 0x40)
+		{
+			if (data & 0x40)
+			{
+				// Entering timer mode
+				uint16_t count = std::max(CTR.w.l, uint16_t(1));
+				half_period = 0;
+
+				start_ct(count);
+			}
+			else
+			{
+				// Leaving timer mode (TODO: is this correct?)
+				duart_timer->adjust(attotime::never);
+			}
+		}
+
+		// check for pending input port delta interrupts
+		if ((((IPCR>>4) & data) & 0x0f) != 0)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+
+		m_chanA->baud_updated();
+		m_chanB->baud_updated();
+		m_chanA->update_interrupts();
+		m_chanB->update_interrupts();
+		break;
+	}
+	case 0x05: /* IMR */
+		IMR = data;
+		update_interrupts();
+		break;
+
+	case 0x06: /* CTUR */
+		CTR.b.h = data;
+		break;
+
+	case 0x07: /* CTLR */
+		CTR.b.l = data;
+		break;
+
+	case 0x08: /* MRB */
+	case 0x09: /* CSRB */
+	case 0x0a: /* CRB */
+	case 0x0b: /* THRB */
+		m_chanB->write_chan_reg(offset&3, data);
+		break;
+
+	case 0x0d: /* OPCR */
+		if (((data & 0xf) != 0x00) && ((data & 0xc) != 0x4))
+			logerror("68681 (%s): Unhandled OPCR value: %02x\n", tag(), data);
+		OPCR = data;
+		break;
+
+	case 0x0e: /* Set Output Port Bits */
+		OPR |= data;
+		write_outport(OPR ^ 0xff);
+		break;
+
+	case 0x0f: /* Reset Output Port Bits */
+		OPR &= ~data;
+		write_outport(OPR ^ 0xff);
+		break;
+	}
+}
+
+void duart_base_device::ip0_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x01) | ((state == ASSERT_LINE) ? 1 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x10;
+
+		if (ACR & 1)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip1_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x02) | ((state == ASSERT_LINE) ? 2 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x20;
+
+		if (ACR & 2)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip2_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x04) | ((state == ASSERT_LINE) ? 4 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x40;
+
+		if (ACR & 4)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip3_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x08) | ((state == ASSERT_LINE) ? 8 : 0);
+
+	if (newIP != IP_last_state)
+	{
+		IPCR &= ~0x0f;
+		IPCR |= (newIP & 0x0f);
+		IPCR |= 0x80;
+
+		if (ACR & 8)
+			set_ISR_bits(INT_INPUT_PORT_CHANGE);
+	}
+
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip4_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x10) | ((state == ASSERT_LINE) ? 0x10 : 0);
+// TODO: special mode for ip4 (Ch. A Rx clock)
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip5_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x20) | ((state == ASSERT_LINE) ? 0x20 : 0);
+// TODO: special mode for ip5 (Ch. B Tx clock)
+	IP_last_state = newIP;
+}
+
+void duart_base_device::ip6_w(int state)
+{
+	uint8_t newIP = (IP_last_state & ~0x40) | ((state == ASSERT_LINE) ? 0x40 : 0);
+// TODO: special mode for ip6 (Ch. B Rx clock)
+	IP_last_state = newIP;
+}
+
+duart_channel *duart_base_device::get_channel(int chan)
+{
+	if (chan == 0)
+	{
+		return m_chanA;
+	}
+
+	return m_chanB;
+}
+
+int duart_base_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+	if (BIT(ACR, 7) == 0)
+	{
+		baud_rate = baud_rate_ACR_0[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+	else
+	{
+		baud_rate = baud_rate_ACR_1[data & 0x0f];
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int mc68340_duart_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+	if (BIT(ACR, 7) == 0)
+	{
+		baud_rate = baud_rate_ACR_0_340[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+	else
+	{
+		baud_rate = baud_rate_ACR_1_340[data & 0x0f];
+
+		if (ch == 0)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip3clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip3clk;
+			}
+		}
+		else if (ch == 1)
+		{
+			if ((data & 0xf) == 0xe)
+			{
+				baud_rate = ip5clk/16;
+			}
+			else if ((data & 0xf) == 0xf)
+			{
+				baud_rate = ip5clk;
+			}
+		}
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int xr68c681_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate;
+
+
+	baud_rate = baud_rate_ACR_0[data & 0x0f];
+
+	if (ch == 0)
+	{
+		if ((data & 0x0f) == 0x0e)
+			baud_rate = ip3clk/16;
+		else if ((data & 0x0f) == 0x0f)
+			baud_rate = ip3clk;
+		else if ((rx && m_XRXA) || (!rx && m_XTXA)) /* X = 1 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0_X_1[data & 0x0f] : baud_rate_ACR_1_X_1[data & 0x0f];
+		else /* X = 0 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0[data & 0x0f] : baud_rate_ACR_1[data & 0x0f];
+	}
+	else if (ch == 1)
+	{
+		if ((data & 0x0f) == 0x0e)
+			baud_rate = ip5clk/16;
+		else if ((data & 0x0f) == 0x0f)
+			baud_rate = ip5clk;
+		else if ((rx && m_XRXB) || (!rx && m_XTXB)) /* X = 1 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0_X_1[data & 0x0f] : baud_rate_ACR_1_X_1[data & 0x0f];
+		else /* X = 0 */
+			baud_rate = BIT(ACR, 7) == 0 ? baud_rate_ACR_0[data & 0x0f] : baud_rate_ACR_1[data & 0x0f];
+	}
+
+	if ((baud_rate == 0) && ((data & 0xf) != 0xd))
+	{
+		LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data);
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+int mcf5206e_uart_device::calc_baud(int ch, bool rx, uint8_t data)
+{
+	int baud_rate = 0;
+	u16 ubg_temp = 1;
+
+	if(UBG > 0) ubg_temp = UBG;
+
+	switch (data & 0xf){
+		case 0xe: baud_rate = ip3clk/16; break;
+		case 0xf: baud_rate = ip3clk; break;
+		case 0xd: baud_rate = (this->clock()/32) / ubg_temp; break;
+		default: LOG("Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data); break;
+	}
+
+	//printf("%s ch %d setting baud to %d\n", tag(), ch, baud_rate);
+	return baud_rate;
+}
+
+void duart_base_device::clear_ISR_bits(int mask)
+{
+	if (ISR & mask)
+	{
+		ISR &= ~mask;
+		update_interrupts();
+	}
+}
+
+void duart_base_device::set_ISR_bits(int mask)
+{
+	if (!(ISR & mask))
+	{
+		ISR |= mask;
+		update_interrupts();
+	}
+}
+
+// DUART channel class stuff
+
+duart_channel::duart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: device_t(mconfig, DUART_CHANNEL, tag, owner, clock)
+	, device_serial_interface(mconfig, *this)
+	, MR1(0)
+	, MR2(0)
+	, SR(0)
+	, rx_enabled(0)
+	, rx_fifo_num(0)
+	, m_tx_data_in_buffer(false)
+	, m_tx_break(false)
+	, m_bits_transmitted(255)
+	, m_tx_enabled(false)
+{
+	std::fill_n(&rx_fifo[0], MC68681_RX_FIFO_SIZE + 1, 0);
+}
+
+void duart_channel::device_start()
+{
+	m_uart = downcast<duart_base_device *>(owner());
+	m_ch = m_uart->get_ch(this);    // get our channel number
+
+	save_item(NAME(CR));
+	save_item(NAME(CSR));
+	save_item(NAME(MR1));
+	save_item(NAME(MR2));
+	save_item(NAME(MR_ptr));
+	save_item(NAME(SR));
+	save_item(NAME(rx_baud_rate));
+	save_item(NAME(tx_baud_rate));
+	save_item(NAME(rx_enabled));
+	save_item(NAME(rx_fifo));
+	save_item(NAME(rx_fifo_read_ptr));
+	save_item(NAME(rx_fifo_write_ptr));
+	save_item(NAME(rx_fifo_num));
+	save_item(NAME(m_tx_data));
+	save_item(NAME(m_tx_data_in_buffer));
+	save_item(NAME(m_tx_break));
+	save_item(NAME(m_bits_transmitted));
+	save_item(NAME(m_tx_enabled));
+}
+
+void duart_channel::device_reset()
+{
+	write_CR(0x10); // reset MR
+	write_CR(0x20); // reset Rx
+	write_CR(0x30); // reset Tx
+	write_CR(0x40); // reset errors
+
+	set_data_frame(1, 8, PARITY_NONE, STOP_BITS_1);
+
+	tx_baud_rate = rx_baud_rate = 0;
+	CSR = 0;
+	m_tx_break = false;
+}
+
+// serial device virtual overrides
+void duart_channel::rcv_complete()
+{
+	receive_register_extract();
+
+	//printf("%s ch %d rcv complete\n", tag(), m_ch);
+
+	if (rx_enabled || (MR2 & 0xc0) == 0x80)
+	{
+		uint8_t errors = 0;
+		if (is_receive_framing_error())
+			errors |= STATUS_FRAMING_ERROR;
+		if (is_receive_parity_error())
+			errors |= STATUS_PARITY_ERROR;
+		rx_fifo_push(get_received_char(), errors);
+	}
+}
+
+void duart_channel::rx_fifo_push(uint8_t data, uint8_t errors)
+{
+	if (rx_fifo_num == (MC68681_RX_FIFO_SIZE + 1))
+	{
+		logerror("68681: FIFO overflow\n");
+		SR |= STATUS_OVERRUN_ERROR;
+		// In case of overrun the FIFO tail entry is overwritten
+		// Back rx_fifo_write_ptr up by one position
+		if (rx_fifo_write_ptr)
+			rx_fifo_write_ptr--;
+		else
+			rx_fifo_write_ptr = MC68681_RX_FIFO_SIZE;
+	}
+
+	rx_fifo[rx_fifo_write_ptr++] = data | (errors << 8);
+	if (rx_fifo_write_ptr > MC68681_RX_FIFO_SIZE)
+		rx_fifo_write_ptr = 0;
+
+	if (rx_fifo_num <= MC68681_RX_FIFO_SIZE)
+	{
+		rx_fifo_num++;
+	}
+
+	if (rx_fifo_num == 1)
+	{
+		SR |= STATUS_RECEIVER_READY;
+		if (!(MR1 & MODE_BLOCK_ERROR))
+			SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+		SR |= errors;
+	}
+	if (rx_fifo_num == MC68681_RX_FIFO_SIZE)
+		SR |= STATUS_FIFO_FULL;
+	update_interrupts();
+}
+
+void duart_channel::tra_complete()
+{
+	// The transmit shift register has just emptied.  If another character is
+	// waiting in the THR, transfer it to the shift register and assert TxRDY:
+	// per the datasheet the THR->shift transfer is where the TxRDY conditions
+	// are re-asserted, providing "one full character time of buffering".  If the
+	// THR is empty the transmitter is now idle, so set TxEMT (TxRDY is already
+	// set from the previous transfer).
+	//
+	// Asserting TxRDY here, at the transfer -- rather than in the idle branch --
+	// both prevents the transmitter from deadlocking when TxRDY would otherwise
+	// fail to re-assert on a CPU-write / final-bit-time race, and preserves the
+	// one-character buffering window that firmware polling or pipelining on TxRDY
+	// relies on.
+	if (m_tx_data_in_buffer)
+	{
+		transmit_register_setup(m_tx_data);
+		m_bits_transmitted = 0;
+		m_tx_data_in_buffer = false;
+		SR |= STATUS_TRANSMITTER_READY;
+		update_interrupts();
+	}
+	else
+	{
+		SR |= STATUS_TRANSMITTER_EMPTY;
+		update_interrupts();
+	}
+}
+
+void duart_channel::tra_callback()
+{
+	// don't actually send in loopback mode
+	if ((MR2 & 0xc0) != 0x80)
+	{
+		int bit = transmit_register_get_data_bit();
+		//printf("%s ch %d transmit %d\n", tag(), m_ch, bit);
+		if (m_ch == 0)
+		{
+			m_uart->write_a_tx(bit);
+		}
+		else if (m_ch == 1)
+		{
+			m_uart->write_b_tx(bit);
+		}
+		else if (m_ch == 2)
+		{
+			m_uart->write_c_tx(bit);
+		}
+		else if (m_ch == 3)
+		{
+			m_uart->write_d_tx(bit);
+		}
+	}
+	else
+	{
+		// loop back transmitted bit
+		rx_w(transmit_register_get_data_bit());
+	}
+
+	// TxRDY is not set until the end of start bit time
+	if (++m_bits_transmitted > 1 && !m_tx_data_in_buffer && m_tx_enabled)
+	{
+		SR |= STATUS_TRANSMITTER_READY;
+		update_interrupts();
+	}
+}
+
+void duart_channel::update_interrupts()
+{
+	// Handle the TxEMT and TxRDY bits based on mode
+	switch (MR2 & 0xc0) // what mode are we in?
+	{
+	case 0x00: // normal mode
+		break;
+	case 0x40: // automatic echo mode
+		SR &= ~STATUS_TRANSMITTER_READY;
+		break;
+	case 0x80: // local loopback mode
+		break;
+	case 0xc0: // remote loopback mode
+		SR &= ~STATUS_TRANSMITTER_READY;
+		break;
+	}
+
+	// now handle the ISR bits
+	if (SR & STATUS_TRANSMITTER_READY)
+	{
+		if (m_ch == 0)
+			m_uart->set_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->set_ISR_bits(INT_TXRDYB);
+	}
+	else
+	{
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+	}
+	//logerror("DEBUG: 68681 int check: before receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
+	if (MR1 & MODE_RX_INT_SELECT_BIT)
+	{
+		if (SR & STATUS_FIFO_FULL)
+		{
+			m_uart->set_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+		else
+		{
+			m_uart->clear_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+	}
+	else
+	{
+		if (SR & STATUS_RECEIVER_READY)
+		{
+			m_uart->set_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+		else
+		{
+			m_uart->clear_ISR_bits((m_ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
+		}
+	}
+
+	//logerror("DEBUG: 68681 int check: after receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
+}
+
+uint8_t duart_channel::read_rx_fifo()
+{
+	uint8_t rv;
+
+	//printf("read_rx_fifo: rx_fifo_num %d\n", rx_fifo_num);
+
+	if (rx_fifo_num == 0)
+	{
+		LOG("68681 channel: rx fifo underflow\n");
+		update_interrupts();
+		return 0;
+	}
+
+	rv = rx_fifo[rx_fifo_read_ptr++];
+	if (rx_fifo_read_ptr > MC68681_RX_FIFO_SIZE)
+	{
+		rx_fifo_read_ptr = 0;
+	}
+
+	rx_fifo_num--;
+	if (rx_fifo_num == (MC68681_RX_FIFO_SIZE - 1))
+	{
+		SR &= ~STATUS_FIFO_FULL;
+	}
+
+	if (!(MR1 & MODE_BLOCK_ERROR))
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+	if (rx_fifo_num == 0)
+		SR &= ~STATUS_RECEIVER_READY;
+	else
+		SR |= rx_fifo[rx_fifo_read_ptr] >> 8;
+	update_interrupts();
+
+	//printf("Rx read %02x\n", rv);
+
+	return rv;
+}
+
+uint8_t duart_channel::read_chan_reg(int reg)
+{
+	uint8_t rv = 0xff;
+
+	switch (reg)
+	{
+	case 0: // MR1/MR2
+		if (MR_ptr == 0)
+		{
+			rv = MR1;
+			MR_ptr = 1;
+		}
+		else
+		{
+			rv = MR2;
+		}
+		break;
+
+	case 1: // SRA
+		rv = SR;
+		break;
+
+	case 2: // CSRA: reading this is prohibited
+		break;
+
+	case 3: // Rx holding register A
+		rv = read_rx_fifo();
+		break;
+	}
+
+	return rv;
+}
+
+void duart_channel::write_chan_reg(int reg, uint8_t data)
+{
+	switch (reg)
+	{
+	case 0x00: /* MRA */
+		write_MR(data);
+		break;
+
+	case 0x01: /* CSR */
+		CSR = data;
+		tx_baud_rate = m_uart->calc_baud(m_ch, false, data & 0xf);
+		rx_baud_rate = m_uart->calc_baud(m_ch, true, (data>>4) & 0xf);
+		//printf("%s ch %d CSR %02x Tx baud %d Rx baud %d\n", tag(), m_ch, data, tx_baud_rate, rx_baud_rate);
+		set_rcv_rate(rx_baud_rate);
+		set_tra_rate(tx_baud_rate);
+		break;
+
+	case 0x02: /* CR */
+		write_CR(data);
+		break;
+
+	case 0x03: /* THR */
+		write_TX(data);
+		break;
+	}
+}
+
+void duart_channel::write_MR(uint8_t data)
+{
+	if (MR_ptr == 0)
+	{
+		MR1 = data;
+		MR_ptr = 1;
+	}
+	else
+	{
+		MR2 = data;
+	}
+	recalc_framing();
+	update_interrupts();
+}
+
+void duart_channel::recalc_framing()
+{
+	parity_t parity = PARITY_NONE;
+	switch ((MR1 >> 3) & 3)
+	{
+	case 0: // with parity
+		if (MR1 & 4)
+			parity = PARITY_ODD;
+		else
+			parity = PARITY_EVEN;
+		break;
+
+	case 1: // force parity
+		if (MR1 & 4)
+			parity = PARITY_MARK;
+		else
+			parity = PARITY_SPACE;
+		break;
+
+	case 2: // no parity
+		parity = PARITY_NONE;
+		break;
+
+	case 3: // multidrop mode
+		// fatalerror("68681: multidrop parity not supported\n");
+		// Apollo DEX CPU will test this; omit to abort the emulation
+		logerror("68681: multidrop parity not supported\n");
+		break;
+	}
+
+	stop_bits_t stopbits = STOP_BITS_0;
+	switch ((MR2 >> 2) & 3)
+	{
+	case 0:
+	case 1:
+		stopbits = STOP_BITS_1;
+		break;
+
+	case 2: // "1.5 async, 2 sync"
+		stopbits = STOP_BITS_1_5;
+		break;
+
+	case 3:
+		stopbits = STOP_BITS_2;
+		break;
+	}
+
+	//printf("%s ch %d MR1 %02x MR2 %02x => %d bits / char, %d stop bits, parity %d\n", tag(), m_ch, MR1, MR2, (MR1 & 3)+5, stopbits, parity);
+
+	set_data_frame(1, (MR1 & 3) + 5, parity, stopbits);
+}
+
+void duart_channel::write_CR(uint8_t data)
+{
+	switch ((data >> 4) & 0x07)
+	{
+	case 0: /* No command */
+		break;
+	case 1: /* Reset MR pointer. Causes the channel MR pointer to point to MR1 */
+		MR_ptr = 0;
+		break;
+	case 2: /* Reset channel receiver (disable receiver and flush fifo) */
+		rx_enabled = 0;
+		SR &= ~STATUS_RECEIVER_READY;
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR);
+		SR &= ~STATUS_OVERRUN_ERROR; // is this correct?
+		rx_fifo_read_ptr = 0;
+		rx_fifo_write_ptr = 0;
+		rx_fifo_num = 0;
+		receive_register_reset();
+		break;
+	case 3: /* Reset channel transmitter */
+		SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+		if (m_ch == 0)
+		{
+			m_uart->write_a_tx(1);
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		}
+		else
+		{
+			m_uart->write_b_tx(1);
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+		}
+		transmit_register_reset();
+		m_bits_transmitted = 255;
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = false;
+		break;
+	case 4: /* Reset Error Status */
+		SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR | STATUS_OVERRUN_ERROR);
+		break;
+	case 5: /* Reset Channel break change interrupt */
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_DELTA_BREAK_A);
+		else
+			m_uart->clear_ISR_bits(INT_DELTA_BREAK_B);
+		break;
+	case 6: /* Start Tx break */
+		if (!m_tx_break)
+		{
+			m_tx_break = true;
+			if ((MR2 & 0xc0) == 0x80)
+			{
+				// Local loopback mode: set delta break in ISR, simulate break rx
+				if (m_ch == 0)
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_A);
+				else
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_B);
+				rx_fifo_push(0 , STATUS_RECEIVED_BREAK);
+			}
+			// TODO: Actually send break signal
+		}
+		break;
+	case 7: /* Stop tx break */
+		if (m_tx_break)
+		{
+			m_tx_break = false;
+			if ((MR2 & 0xc0) == 0x80)
+			{
+				// Local loopback mode: set delta break in ISR
+				if (m_ch == 0)
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_A);
+				else
+					m_uart->set_ISR_bits(INT_DELTA_BREAK_B);
+			}
+		}
+		break;
+	default:
+		LOG("68681: Unhandled command (%x) in CR%d\n", (data >> 4) & 0x07, m_ch);
+		break;
+	}
+
+	if (BIT(data, 0))
+	{
+		rx_enabled = 1;
+	}
+	if (BIT(data, 1))
+	{
+		rx_enabled = 0;
+		SR &= ~STATUS_RECEIVER_READY;
+	}
+
+	if (!BIT(CR, 2) && BIT(data, 2))
+	{
+		SR |= STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY;
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = true;
+		if (m_ch == 0)
+			m_uart->set_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->set_ISR_bits(INT_TXRDYB);
+	}
+	if (BIT(data, 3))
+	{
+		SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+		m_tx_data_in_buffer = false;
+		m_tx_enabled = false;
+		if (m_ch == 0)
+			m_uart->clear_ISR_bits(INT_TXRDYA);
+		else
+			m_uart->clear_ISR_bits(INT_TXRDYB);
+	}
+
+	update_interrupts();
+	CR = data;
+}
+
+void duart_channel::write_TX(uint8_t data)
+{
+	if (!(SR & STATUS_TRANSMITTER_READY))
+	{
+		logerror("write_tx transmitter not ready (data 0x%02x discarded)\n", data);
+		return;
+	}
+
+	SR &= ~(STATUS_TRANSMITTER_READY | STATUS_TRANSMITTER_EMPTY);
+	if (!is_transmit_register_empty())
+	{
+		m_tx_data = data;
+		m_tx_data_in_buffer = true;
+	}
+	else
+	{
+		transmit_register_setup(data);
+		m_bits_transmitted = 0;
+	}
+
+	update_interrupts();
+}
+
+void duart_channel::baud_updated()
+{
+	write_chan_reg(1, CSR);
+}
+
+uint8_t duart_channel::get_chan_CSR()
+{
+	return CSR;
+}
+
+void duart_channel::tx_16x_clock_w(bool state)
+{
+	if (state)
+	{
+		m_tx_prescaler--;
+		if (m_tx_prescaler == 8)
+		{
+			tx_clock_w(true);
+		}
+		else if (m_tx_prescaler == 0)
+		{
+			m_tx_prescaler = 16;
+			tx_clock_w(false);
+		}
+	}
+}
+
+void duart_channel::rx_16x_clock_w(bool state)
+{
+	if (!is_receive_register_synchronized())
+	{
+		// Skip over the start bit once synchonization is achieved
+		m_rx_prescaler = 32;
+		rx_clock_w(true);
+	}
+	else if (state)
+	{
+		m_rx_prescaler--;
+		if (m_rx_prescaler == 8)
+		{
+			rx_clock_w(false);
+		}
+		else if (m_rx_prescaler == 0)
+		{
+			m_rx_prescaler = 16;
+			rx_clock_w(true);
+		}
+	}
+}
diff --git a/harness/mame/mame_edits/mc68681.h.cfg1 b/harness/mame/mame_edits/mc68681.h.cfg1
new file mode 100644
index 0000000..c1e09db
--- /dev/null
+++ b/harness/mame/mame_edits/mc68681.h.cfg1
@@ -0,0 +1,334 @@
+// license:BSD-3-Clause
+// copyright-holders:Mariusz Wojcieszek, R. Belmont
+#ifndef MAME_MACHINE_MC68681_H
+#define MAME_MACHINE_MC68681_H
+
+#pragma once
+
+#include "diserial.h"
+
+#define MC68681_RX_FIFO_SIZE                3
+
+// forward declaration
+class duart_base_device;
+
+// duart_channel class
+class duart_channel : public device_t, public device_serial_interface
+{
+public:
+	duart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
+
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+	// device_serial overrides
+	virtual void rcv_complete() override;    // Rx completed receiving byte
+	virtual void tra_complete() override;    // Tx completed sending byte
+	virtual void tra_callback() override;    // Tx send bit
+
+	uint8_t read_chan_reg(int reg);
+	void write_chan_reg(int reg, uint8_t data);
+	void update_interrupts();
+
+	// VT1200 NOTE (local change, not upstream): saw the RxD line so the overrun
+	// error can be latched on the start bit of the overrunning character (the
+	// datasheet's timing), rather than at its completion in rx_fifo_push().
+	void rx_w(int state);
+
+	void rx_fifo_push(uint8_t data, uint8_t errors);
+	uint8_t read_rx_fifo();
+
+	void baud_updated();
+
+	uint8_t get_chan_CSR();
+
+	// Access methods needed for 68340 serial module register model
+	uint8_t read_MR1(){ return MR1; }
+	uint8_t read_MR2(){ return MR2; }
+	void write_MR1(uint8_t data){ MR1 = data; }
+	void write_MR2(uint8_t data){ MR2 = data; }
+
+	void tx_16x_clock_w(bool state);
+	void rx_16x_clock_w(bool state);
+
+	int get_tx_rate() const { return tx_baud_rate; }
+
+private:
+	/* Registers */
+	uint8_t CR;  /* Command register */
+	uint8_t CSR; /* Clock select register */
+	uint8_t MR1; /* Mode register 1 */
+	uint8_t MR2; /* Mode register 2 */
+	uint8_t MR_ptr; /* Mode register pointer */
+	uint8_t SR;  /* Status register */
+
+	/* State */
+	int tx_baud_rate, rx_baud_rate;
+
+	/* Receiver */
+	uint8_t rx_enabled;
+	uint16_t rx_fifo[MC68681_RX_FIFO_SIZE + 1];
+	int   rx_fifo_read_ptr;
+	int   rx_fifo_write_ptr;
+	int   rx_fifo_num;
+	bool  m_rx_line;   // VT1200 NOTE (local): previous RxD line state
+
+	int m_ch;
+
+	/* Transmitter */
+	uint8_t m_tx_data;
+	bool m_tx_data_in_buffer;
+	bool m_tx_break;
+	uint8_t m_bits_transmitted;
+	bool m_tx_enabled;
+
+	/* Rx/Tx clocking */
+	uint8_t m_rx_prescaler , m_tx_prescaler;
+
+	duart_base_device *m_uart;
+
+	void write_MR(uint8_t data);
+	void write_CR(uint8_t data);
+	void write_TX(uint8_t data);
+	void recalc_framing();
+};
+
+class duart_base_device : public device_t
+{
+	friend class duart_channel;
+
+public:
+	required_device<duart_channel> m_chanA;
+	required_device<duart_channel> m_chanB;
+	optional_device<duart_channel> m_chanC;
+	optional_device<duart_channel> m_chanD;
+
+	// inline configuration helpers
+	void set_clocks(int clk3, int clk4, int clk5, int clk6);
+	void set_clocks(const XTAL &clk3, const XTAL &clk4, const XTAL &clk5, const XTAL &clk6) {
+		set_clocks(clk3.value(), clk4.value(), clk5.value(), clk6.value());
+	}
+
+	// API
+	virtual uint8_t read(offs_t offset);
+	virtual void write(offs_t offset, uint8_t data);
+
+	void rx_a_w(int state) { m_chanA->rx_w((uint8_t)state); }
+	void rx_b_w(int state) { m_chanB->rx_w((uint8_t)state); }
+
+	auto irq_cb() { return write_irq.bind(); }
+	auto a_tx_cb() { return write_a_tx.bind(); }
+	auto b_tx_cb() { return write_b_tx.bind(); }
+	auto inport_cb() { return read_inport.bind(); } // deprecated: use ipX_w() instead
+	auto outport_cb() { return write_outport.bind(); }
+
+	// new-style push handlers for input port bits
+	virtual void ip0_w(int state);
+	virtual void ip1_w(int state);
+	virtual void ip2_w(int state);
+	virtual void ip3_w(int state);
+	virtual void ip4_w(int state);
+	virtual void ip5_w(int state);
+	virtual void ip6_w(int state);
+
+	bool irq_pending() const { return (ISR & IMR) != 0; }
+
+protected:
+	duart_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+	devcb_write_line write_irq, write_a_tx, write_b_tx, write_c_tx, write_d_tx;
+	devcb_read8 read_inport;
+	devcb_write8 write_outport;
+	int32_t ip3clk, ip4clk, ip5clk, ip6clk;
+
+protected:
+	virtual void update_interrupts();
+
+private:
+	TIMER_CALLBACK_MEMBER(duart_timer_callback);
+
+protected:
+	/* registers */
+	uint8_t ACR;  /* Auxiliary Control Register */
+	uint8_t IMR;  /* Interrupt Mask Register */
+	uint8_t ISR;  /* Interrupt Status Register */
+
+private:
+	uint8_t OPCR; /* Output Port Conf. Register */
+	uint8_t OPR;  /* Output Port Register */
+	PAIR  CTR;  /* Counter/Timer Preset Value */
+	uint8_t IPCR; /* Input Port Control Register */
+
+	/* state */
+	uint8_t IP_last_state; /* last state of IP bits */
+
+	/* timer */
+	uint8_t half_period;
+	emu_timer *duart_timer;
+
+	bool m_irq_state;
+
+	uint32_t get_ct_rate();
+	uint16_t get_ct_count();
+	void start_ct(int count);
+	virtual int calc_baud(int ch, bool rx, uint8_t data);
+	void clear_ISR_bits(int mask);
+	void set_ISR_bits(int mask);
+
+	int get_ch(duart_channel *ch)
+	{
+		if (ch == m_chanA)
+		{
+			return 0;
+		}
+		else if (ch == m_chanB)
+		{
+			return 1;
+		}
+		else if (ch == m_chanC)
+		{
+			return 2;
+		}
+
+		return 3;
+	}
+
+	duart_channel *get_channel(int chan);
+};
+
+class scn2681_device : public duart_base_device
+{
+public:
+	scn2681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+};
+
+class mc68681_device : public duart_base_device
+{
+public:
+	mc68681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+	uint8_t get_irq_vector();
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void update_interrupts() override;
+	mc68681_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
+
+	uint8_t IVR;  /* Interrupt Vector Register */
+};
+
+/**************************
+ * ColdFire MCF5206e UART
+ **************************/
+class mcf5206e_uart_device : public duart_base_device
+{
+public:
+	mcf5206e_uart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+	uint8_t get_irq_vector();
+
+	// There is no GPIO on the coldfire UART module
+	void cts_w(int state) { duart_base_device::ip0_w(state); }
+
+	virtual void ip1_w(int state) override {}
+	virtual void ip2_w(int state) override {}
+	virtual void ip3_w(int state) override {}
+	virtual void ip4_w(int state) override {}
+	virtual void ip5_w(int state) override {}
+	virtual void ip6_w(int state) override {}
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void update_interrupts() override;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+	mcf5206e_uart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+
+	bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
+
+	// ColdFire UART module is essentially two 68681 a-channels with a slighty different register map and no counter
+	uint8_t IVR;  /* Interrupt Vector Register */
+	uint16_t UBG;  /* Baud Rate Generator Prescale Register - Manual erronuosly calls this the timer preload register */
+
+};
+
+class sc28c94_device : public duart_base_device
+{
+public:
+	sc28c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	auto c_tx_cb() { return write_c_tx.bind(); }
+	auto d_tx_cb() { return write_d_tx.bind(); }
+
+	void rx_c_w(int state) { m_chanC->device_serial_interface::rx_w((uint8_t)state); }
+	void rx_d_w(int state) { m_chanD->device_serial_interface::rx_w((uint8_t)state); }
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+private:
+};
+
+class mc68340_duart_device : public duart_base_device
+{
+public:
+	mc68340_duart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+	mc68340_duart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+};
+
+class xr68c681_device : public mc68681_device
+{
+public:
+	xr68c681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+
+	bool m_XTXA,m_XRXA,m_XTXB,m_XRXB; /* X bits for the BRG (selects between 2 BRG tables) */
+};
+
+DECLARE_DEVICE_TYPE(SCN2681, scn2681_device)
+DECLARE_DEVICE_TYPE(MC68681, mc68681_device)
+DECLARE_DEVICE_TYPE(SC28C94, sc28c94_device)
+DECLARE_DEVICE_TYPE(MC68340_DUART, mc68340_duart_device)
+DECLARE_DEVICE_TYPE(MCF5206E_UART, mcf5206e_uart_device)
+DECLARE_DEVICE_TYPE(XR68C681, xr68c681_device)
+DECLARE_DEVICE_TYPE(DUART_CHANNEL, duart_channel)
+
+#endif // MAME_MACHINE_MC68681_H
diff --git a/harness/mame/mame_edits/mc68681.h.cfg2 b/harness/mame/mame_edits/mc68681.h.cfg2
new file mode 100644
index 0000000..c1e09db
--- /dev/null
+++ b/harness/mame/mame_edits/mc68681.h.cfg2
@@ -0,0 +1,334 @@
+// license:BSD-3-Clause
+// copyright-holders:Mariusz Wojcieszek, R. Belmont
+#ifndef MAME_MACHINE_MC68681_H
+#define MAME_MACHINE_MC68681_H
+
+#pragma once
+
+#include "diserial.h"
+
+#define MC68681_RX_FIFO_SIZE                3
+
+// forward declaration
+class duart_base_device;
+
+// duart_channel class
+class duart_channel : public device_t, public device_serial_interface
+{
+public:
+	duart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
+
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+	// device_serial overrides
+	virtual void rcv_complete() override;    // Rx completed receiving byte
+	virtual void tra_complete() override;    // Tx completed sending byte
+	virtual void tra_callback() override;    // Tx send bit
+
+	uint8_t read_chan_reg(int reg);
+	void write_chan_reg(int reg, uint8_t data);
+	void update_interrupts();
+
+	// VT1200 NOTE (local change, not upstream): saw the RxD line so the overrun
+	// error can be latched on the start bit of the overrunning character (the
+	// datasheet's timing), rather than at its completion in rx_fifo_push().
+	void rx_w(int state);
+
+	void rx_fifo_push(uint8_t data, uint8_t errors);
+	uint8_t read_rx_fifo();
+
+	void baud_updated();
+
+	uint8_t get_chan_CSR();
+
+	// Access methods needed for 68340 serial module register model
+	uint8_t read_MR1(){ return MR1; }
+	uint8_t read_MR2(){ return MR2; }
+	void write_MR1(uint8_t data){ MR1 = data; }
+	void write_MR2(uint8_t data){ MR2 = data; }
+
+	void tx_16x_clock_w(bool state);
+	void rx_16x_clock_w(bool state);
+
+	int get_tx_rate() const { return tx_baud_rate; }
+
+private:
+	/* Registers */
+	uint8_t CR;  /* Command register */
+	uint8_t CSR; /* Clock select register */
+	uint8_t MR1; /* Mode register 1 */
+	uint8_t MR2; /* Mode register 2 */
+	uint8_t MR_ptr; /* Mode register pointer */
+	uint8_t SR;  /* Status register */
+
+	/* State */
+	int tx_baud_rate, rx_baud_rate;
+
+	/* Receiver */
+	uint8_t rx_enabled;
+	uint16_t rx_fifo[MC68681_RX_FIFO_SIZE + 1];
+	int   rx_fifo_read_ptr;
+	int   rx_fifo_write_ptr;
+	int   rx_fifo_num;
+	bool  m_rx_line;   // VT1200 NOTE (local): previous RxD line state
+
+	int m_ch;
+
+	/* Transmitter */
+	uint8_t m_tx_data;
+	bool m_tx_data_in_buffer;
+	bool m_tx_break;
+	uint8_t m_bits_transmitted;
+	bool m_tx_enabled;
+
+	/* Rx/Tx clocking */
+	uint8_t m_rx_prescaler , m_tx_prescaler;
+
+	duart_base_device *m_uart;
+
+	void write_MR(uint8_t data);
+	void write_CR(uint8_t data);
+	void write_TX(uint8_t data);
+	void recalc_framing();
+};
+
+class duart_base_device : public device_t
+{
+	friend class duart_channel;
+
+public:
+	required_device<duart_channel> m_chanA;
+	required_device<duart_channel> m_chanB;
+	optional_device<duart_channel> m_chanC;
+	optional_device<duart_channel> m_chanD;
+
+	// inline configuration helpers
+	void set_clocks(int clk3, int clk4, int clk5, int clk6);
+	void set_clocks(const XTAL &clk3, const XTAL &clk4, const XTAL &clk5, const XTAL &clk6) {
+		set_clocks(clk3.value(), clk4.value(), clk5.value(), clk6.value());
+	}
+
+	// API
+	virtual uint8_t read(offs_t offset);
+	virtual void write(offs_t offset, uint8_t data);
+
+	void rx_a_w(int state) { m_chanA->rx_w((uint8_t)state); }
+	void rx_b_w(int state) { m_chanB->rx_w((uint8_t)state); }
+
+	auto irq_cb() { return write_irq.bind(); }
+	auto a_tx_cb() { return write_a_tx.bind(); }
+	auto b_tx_cb() { return write_b_tx.bind(); }
+	auto inport_cb() { return read_inport.bind(); } // deprecated: use ipX_w() instead
+	auto outport_cb() { return write_outport.bind(); }
+
+	// new-style push handlers for input port bits
+	virtual void ip0_w(int state);
+	virtual void ip1_w(int state);
+	virtual void ip2_w(int state);
+	virtual void ip3_w(int state);
+	virtual void ip4_w(int state);
+	virtual void ip5_w(int state);
+	virtual void ip6_w(int state);
+
+	bool irq_pending() const { return (ISR & IMR) != 0; }
+
+protected:
+	duart_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+	devcb_write_line write_irq, write_a_tx, write_b_tx, write_c_tx, write_d_tx;
+	devcb_read8 read_inport;
+	devcb_write8 write_outport;
+	int32_t ip3clk, ip4clk, ip5clk, ip6clk;
+
+protected:
+	virtual void update_interrupts();
+
+private:
+	TIMER_CALLBACK_MEMBER(duart_timer_callback);
+
+protected:
+	/* registers */
+	uint8_t ACR;  /* Auxiliary Control Register */
+	uint8_t IMR;  /* Interrupt Mask Register */
+	uint8_t ISR;  /* Interrupt Status Register */
+
+private:
+	uint8_t OPCR; /* Output Port Conf. Register */
+	uint8_t OPR;  /* Output Port Register */
+	PAIR  CTR;  /* Counter/Timer Preset Value */
+	uint8_t IPCR; /* Input Port Control Register */
+
+	/* state */
+	uint8_t IP_last_state; /* last state of IP bits */
+
+	/* timer */
+	uint8_t half_period;
+	emu_timer *duart_timer;
+
+	bool m_irq_state;
+
+	uint32_t get_ct_rate();
+	uint16_t get_ct_count();
+	void start_ct(int count);
+	virtual int calc_baud(int ch, bool rx, uint8_t data);
+	void clear_ISR_bits(int mask);
+	void set_ISR_bits(int mask);
+
+	int get_ch(duart_channel *ch)
+	{
+		if (ch == m_chanA)
+		{
+			return 0;
+		}
+		else if (ch == m_chanB)
+		{
+			return 1;
+		}
+		else if (ch == m_chanC)
+		{
+			return 2;
+		}
+
+		return 3;
+	}
+
+	duart_channel *get_channel(int chan);
+};
+
+class scn2681_device : public duart_base_device
+{
+public:
+	scn2681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+};
+
+class mc68681_device : public duart_base_device
+{
+public:
+	mc68681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+	uint8_t get_irq_vector();
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void update_interrupts() override;
+	mc68681_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
+
+	uint8_t IVR;  /* Interrupt Vector Register */
+};
+
+/**************************
+ * ColdFire MCF5206e UART
+ **************************/
+class mcf5206e_uart_device : public duart_base_device
+{
+public:
+	mcf5206e_uart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+	uint8_t get_irq_vector();
+
+	// There is no GPIO on the coldfire UART module
+	void cts_w(int state) { duart_base_device::ip0_w(state); }
+
+	virtual void ip1_w(int state) override {}
+	virtual void ip2_w(int state) override {}
+	virtual void ip3_w(int state) override {}
+	virtual void ip4_w(int state) override {}
+	virtual void ip5_w(int state) override {}
+	virtual void ip6_w(int state) override {}
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void update_interrupts() override;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+	mcf5206e_uart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+
+	bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
+
+	// ColdFire UART module is essentially two 68681 a-channels with a slighty different register map and no counter
+	uint8_t IVR;  /* Interrupt Vector Register */
+	uint16_t UBG;  /* Baud Rate Generator Prescale Register - Manual erronuosly calls this the timer preload register */
+
+};
+
+class sc28c94_device : public duart_base_device
+{
+public:
+	sc28c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	auto c_tx_cb() { return write_c_tx.bind(); }
+	auto d_tx_cb() { return write_d_tx.bind(); }
+
+	void rx_c_w(int state) { m_chanC->device_serial_interface::rx_w((uint8_t)state); }
+	void rx_d_w(int state) { m_chanD->device_serial_interface::rx_w((uint8_t)state); }
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+private:
+};
+
+class mc68340_duart_device : public duart_base_device
+{
+public:
+	mc68340_duart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+	mc68340_duart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+};
+
+class xr68c681_device : public mc68681_device
+{
+public:
+	xr68c681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+
+	bool m_XTXA,m_XRXA,m_XTXB,m_XRXB; /* X bits for the BRG (selects between 2 BRG tables) */
+};
+
+DECLARE_DEVICE_TYPE(SCN2681, scn2681_device)
+DECLARE_DEVICE_TYPE(MC68681, mc68681_device)
+DECLARE_DEVICE_TYPE(SC28C94, sc28c94_device)
+DECLARE_DEVICE_TYPE(MC68340_DUART, mc68340_duart_device)
+DECLARE_DEVICE_TYPE(MCF5206E_UART, mcf5206e_uart_device)
+DECLARE_DEVICE_TYPE(XR68C681, xr68c681_device)
+DECLARE_DEVICE_TYPE(DUART_CHANNEL, duart_channel)
+
+#endif // MAME_MACHINE_MC68681_H
diff --git a/harness/mame/mame_edits/mc68681.h.cfg3 b/harness/mame/mame_edits/mc68681.h.cfg3
new file mode 100644
index 0000000..d5476e8
--- /dev/null
+++ b/harness/mame/mame_edits/mc68681.h.cfg3
@@ -0,0 +1,328 @@
+// license:BSD-3-Clause
+// copyright-holders:Mariusz Wojcieszek, R. Belmont
+#ifndef MAME_MACHINE_MC68681_H
+#define MAME_MACHINE_MC68681_H
+
+#pragma once
+
+#include "diserial.h"
+
+#define MC68681_RX_FIFO_SIZE                3
+
+// forward declaration
+class duart_base_device;
+
+// duart_channel class
+class duart_channel : public device_t, public device_serial_interface
+{
+public:
+	duart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
+
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+	// device_serial overrides
+	virtual void rcv_complete() override;    // Rx completed receiving byte
+	virtual void tra_complete() override;    // Tx completed sending byte
+	virtual void tra_callback() override;    // Tx send bit
+
+	uint8_t read_chan_reg(int reg);
+	void write_chan_reg(int reg, uint8_t data);
+	void update_interrupts();
+
+	void rx_fifo_push(uint8_t data, uint8_t errors);
+	uint8_t read_rx_fifo();
+
+	void baud_updated();
+
+	uint8_t get_chan_CSR();
+
+	// Access methods needed for 68340 serial module register model
+	uint8_t read_MR1(){ return MR1; }
+	uint8_t read_MR2(){ return MR2; }
+	void write_MR1(uint8_t data){ MR1 = data; }
+	void write_MR2(uint8_t data){ MR2 = data; }
+
+	void tx_16x_clock_w(bool state);
+	void rx_16x_clock_w(bool state);
+
+	int get_tx_rate() const { return tx_baud_rate; }
+
+private:
+	/* Registers */
+	uint8_t CR;  /* Command register */
+	uint8_t CSR; /* Clock select register */
+	uint8_t MR1; /* Mode register 1 */
+	uint8_t MR2; /* Mode register 2 */
+	uint8_t MR_ptr; /* Mode register pointer */
+	uint8_t SR;  /* Status register */
+
+	/* State */
+	int tx_baud_rate, rx_baud_rate;
+
+	/* Receiver */
+	uint8_t rx_enabled;
+	uint16_t rx_fifo[MC68681_RX_FIFO_SIZE + 1];
+	int   rx_fifo_read_ptr;
+	int   rx_fifo_write_ptr;
+	int   rx_fifo_num;
+
+	int m_ch;
+
+	/* Transmitter */
+	uint8_t m_tx_data;
+	bool m_tx_data_in_buffer;
+	bool m_tx_break;
+	uint8_t m_bits_transmitted;
+	bool m_tx_enabled;
+
+	/* Rx/Tx clocking */
+	uint8_t m_rx_prescaler , m_tx_prescaler;
+
+	duart_base_device *m_uart;
+
+	void write_MR(uint8_t data);
+	void write_CR(uint8_t data);
+	void write_TX(uint8_t data);
+	void recalc_framing();
+};
+
+class duart_base_device : public device_t
+{
+	friend class duart_channel;
+
+public:
+	required_device<duart_channel> m_chanA;
+	required_device<duart_channel> m_chanB;
+	optional_device<duart_channel> m_chanC;
+	optional_device<duart_channel> m_chanD;
+
+	// inline configuration helpers
+	void set_clocks(int clk3, int clk4, int clk5, int clk6);
+	void set_clocks(const XTAL &clk3, const XTAL &clk4, const XTAL &clk5, const XTAL &clk6) {
+		set_clocks(clk3.value(), clk4.value(), clk5.value(), clk6.value());
+	}
+
+	// API
+	virtual uint8_t read(offs_t offset);
+	virtual void write(offs_t offset, uint8_t data);
+
+	void rx_a_w(int state) { m_chanA->device_serial_interface::rx_w((uint8_t)state); }
+	void rx_b_w(int state) { m_chanB->device_serial_interface::rx_w((uint8_t)state); }
+
+	auto irq_cb() { return write_irq.bind(); }
+	auto a_tx_cb() { return write_a_tx.bind(); }
+	auto b_tx_cb() { return write_b_tx.bind(); }
+	auto inport_cb() { return read_inport.bind(); } // deprecated: use ipX_w() instead
+	auto outport_cb() { return write_outport.bind(); }
+
+	// new-style push handlers for input port bits
+	virtual void ip0_w(int state);
+	virtual void ip1_w(int state);
+	virtual void ip2_w(int state);
+	virtual void ip3_w(int state);
+	virtual void ip4_w(int state);
+	virtual void ip5_w(int state);
+	virtual void ip6_w(int state);
+
+	bool irq_pending() const { return (ISR & IMR) != 0; }
+
+protected:
+	duart_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+	devcb_write_line write_irq, write_a_tx, write_b_tx, write_c_tx, write_d_tx;
+	devcb_read8 read_inport;
+	devcb_write8 write_outport;
+	int32_t ip3clk, ip4clk, ip5clk, ip6clk;
+
+protected:
+	virtual void update_interrupts();
+
+private:
+	TIMER_CALLBACK_MEMBER(duart_timer_callback);
+
+protected:
+	/* registers */
+	uint8_t ACR;  /* Auxiliary Control Register */
+	uint8_t IMR;  /* Interrupt Mask Register */
+	uint8_t ISR;  /* Interrupt Status Register */
+
+private:
+	uint8_t OPCR; /* Output Port Conf. Register */
+	uint8_t OPR;  /* Output Port Register */
+	PAIR  CTR;  /* Counter/Timer Preset Value */
+	uint8_t IPCR; /* Input Port Control Register */
+
+	/* state */
+	uint8_t IP_last_state; /* last state of IP bits */
+
+	/* timer */
+	uint8_t half_period;
+	emu_timer *duart_timer;
+
+	bool m_irq_state;
+
+	uint32_t get_ct_rate();
+	uint16_t get_ct_count();
+	void start_ct(int count);
+	virtual int calc_baud(int ch, bool rx, uint8_t data);
+	void clear_ISR_bits(int mask);
+	void set_ISR_bits(int mask);
+
+	int get_ch(duart_channel *ch)
+	{
+		if (ch == m_chanA)
+		{
+			return 0;
+		}
+		else if (ch == m_chanB)
+		{
+			return 1;
+		}
+		else if (ch == m_chanC)
+		{
+			return 2;
+		}
+
+		return 3;
+	}
+
+	duart_channel *get_channel(int chan);
+};
+
+class scn2681_device : public duart_base_device
+{
+public:
+	scn2681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+};
+
+class mc68681_device : public duart_base_device
+{
+public:
+	mc68681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+	uint8_t get_irq_vector();
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void update_interrupts() override;
+	mc68681_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
+
+	uint8_t IVR;  /* Interrupt Vector Register */
+};
+
+/**************************
+ * ColdFire MCF5206e UART
+ **************************/
+class mcf5206e_uart_device : public duart_base_device
+{
+public:
+	mcf5206e_uart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+	uint8_t get_irq_vector();
+
+	// There is no GPIO on the coldfire UART module
+	void cts_w(int state) { duart_base_device::ip0_w(state); }
+
+	virtual void ip1_w(int state) override {}
+	virtual void ip2_w(int state) override {}
+	virtual void ip3_w(int state) override {}
+	virtual void ip4_w(int state) override {}
+	virtual void ip5_w(int state) override {}
+	virtual void ip6_w(int state) override {}
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void update_interrupts() override;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+	mcf5206e_uart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+
+	bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
+
+	// ColdFire UART module is essentially two 68681 a-channels with a slighty different register map and no counter
+	uint8_t IVR;  /* Interrupt Vector Register */
+	uint16_t UBG;  /* Baud Rate Generator Prescale Register - Manual erronuosly calls this the timer preload register */
+
+};
+
+class sc28c94_device : public duart_base_device
+{
+public:
+	sc28c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	auto c_tx_cb() { return write_c_tx.bind(); }
+	auto d_tx_cb() { return write_d_tx.bind(); }
+
+	void rx_c_w(int state) { m_chanC->device_serial_interface::rx_w((uint8_t)state); }
+	void rx_d_w(int state) { m_chanD->device_serial_interface::rx_w((uint8_t)state); }
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+private:
+};
+
+class mc68340_duart_device : public duart_base_device
+{
+public:
+	mc68340_duart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+	mc68340_duart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+};
+
+class xr68c681_device : public mc68681_device
+{
+public:
+	xr68c681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+
+	bool m_XTXA,m_XRXA,m_XTXB,m_XRXB; /* X bits for the BRG (selects between 2 BRG tables) */
+};
+
+DECLARE_DEVICE_TYPE(SCN2681, scn2681_device)
+DECLARE_DEVICE_TYPE(MC68681, mc68681_device)
+DECLARE_DEVICE_TYPE(SC28C94, sc28c94_device)
+DECLARE_DEVICE_TYPE(MC68340_DUART, mc68340_duart_device)
+DECLARE_DEVICE_TYPE(MCF5206E_UART, mcf5206e_uart_device)
+DECLARE_DEVICE_TYPE(XR68C681, xr68c681_device)
+DECLARE_DEVICE_TYPE(DUART_CHANNEL, duart_channel)
+
+#endif // MAME_MACHINE_MC68681_H
diff --git a/harness/mame/mame_edits/mc68681.h.upstream b/harness/mame/mame_edits/mc68681.h.upstream
new file mode 100644
index 0000000..d5476e8
--- /dev/null
+++ b/harness/mame/mame_edits/mc68681.h.upstream
@@ -0,0 +1,328 @@
+// license:BSD-3-Clause
+// copyright-holders:Mariusz Wojcieszek, R. Belmont
+#ifndef MAME_MACHINE_MC68681_H
+#define MAME_MACHINE_MC68681_H
+
+#pragma once
+
+#include "diserial.h"
+
+#define MC68681_RX_FIFO_SIZE                3
+
+// forward declaration
+class duart_base_device;
+
+// duart_channel class
+class duart_channel : public device_t, public device_serial_interface
+{
+public:
+	duart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
+
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+	// device_serial overrides
+	virtual void rcv_complete() override;    // Rx completed receiving byte
+	virtual void tra_complete() override;    // Tx completed sending byte
+	virtual void tra_callback() override;    // Tx send bit
+
+	uint8_t read_chan_reg(int reg);
+	void write_chan_reg(int reg, uint8_t data);
+	void update_interrupts();
+
+	void rx_fifo_push(uint8_t data, uint8_t errors);
+	uint8_t read_rx_fifo();
+
+	void baud_updated();
+
+	uint8_t get_chan_CSR();
+
+	// Access methods needed for 68340 serial module register model
+	uint8_t read_MR1(){ return MR1; }
+	uint8_t read_MR2(){ return MR2; }
+	void write_MR1(uint8_t data){ MR1 = data; }
+	void write_MR2(uint8_t data){ MR2 = data; }
+
+	void tx_16x_clock_w(bool state);
+	void rx_16x_clock_w(bool state);
+
+	int get_tx_rate() const { return tx_baud_rate; }
+
+private:
+	/* Registers */
+	uint8_t CR;  /* Command register */
+	uint8_t CSR; /* Clock select register */
+	uint8_t MR1; /* Mode register 1 */
+	uint8_t MR2; /* Mode register 2 */
+	uint8_t MR_ptr; /* Mode register pointer */
+	uint8_t SR;  /* Status register */
+
+	/* State */
+	int tx_baud_rate, rx_baud_rate;
+
+	/* Receiver */
+	uint8_t rx_enabled;
+	uint16_t rx_fifo[MC68681_RX_FIFO_SIZE + 1];
+	int   rx_fifo_read_ptr;
+	int   rx_fifo_write_ptr;
+	int   rx_fifo_num;
+
+	int m_ch;
+
+	/* Transmitter */
+	uint8_t m_tx_data;
+	bool m_tx_data_in_buffer;
+	bool m_tx_break;
+	uint8_t m_bits_transmitted;
+	bool m_tx_enabled;
+
+	/* Rx/Tx clocking */
+	uint8_t m_rx_prescaler , m_tx_prescaler;
+
+	duart_base_device *m_uart;
+
+	void write_MR(uint8_t data);
+	void write_CR(uint8_t data);
+	void write_TX(uint8_t data);
+	void recalc_framing();
+};
+
+class duart_base_device : public device_t
+{
+	friend class duart_channel;
+
+public:
+	required_device<duart_channel> m_chanA;
+	required_device<duart_channel> m_chanB;
+	optional_device<duart_channel> m_chanC;
+	optional_device<duart_channel> m_chanD;
+
+	// inline configuration helpers
+	void set_clocks(int clk3, int clk4, int clk5, int clk6);
+	void set_clocks(const XTAL &clk3, const XTAL &clk4, const XTAL &clk5, const XTAL &clk6) {
+		set_clocks(clk3.value(), clk4.value(), clk5.value(), clk6.value());
+	}
+
+	// API
+	virtual uint8_t read(offs_t offset);
+	virtual void write(offs_t offset, uint8_t data);
+
+	void rx_a_w(int state) { m_chanA->device_serial_interface::rx_w((uint8_t)state); }
+	void rx_b_w(int state) { m_chanB->device_serial_interface::rx_w((uint8_t)state); }
+
+	auto irq_cb() { return write_irq.bind(); }
+	auto a_tx_cb() { return write_a_tx.bind(); }
+	auto b_tx_cb() { return write_b_tx.bind(); }
+	auto inport_cb() { return read_inport.bind(); } // deprecated: use ipX_w() instead
+	auto outport_cb() { return write_outport.bind(); }
+
+	// new-style push handlers for input port bits
+	virtual void ip0_w(int state);
+	virtual void ip1_w(int state);
+	virtual void ip2_w(int state);
+	virtual void ip3_w(int state);
+	virtual void ip4_w(int state);
+	virtual void ip5_w(int state);
+	virtual void ip6_w(int state);
+
+	bool irq_pending() const { return (ISR & IMR) != 0; }
+
+protected:
+	duart_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+	devcb_write_line write_irq, write_a_tx, write_b_tx, write_c_tx, write_d_tx;
+	devcb_read8 read_inport;
+	devcb_write8 write_outport;
+	int32_t ip3clk, ip4clk, ip5clk, ip6clk;
+
+protected:
+	virtual void update_interrupts();
+
+private:
+	TIMER_CALLBACK_MEMBER(duart_timer_callback);
+
+protected:
+	/* registers */
+	uint8_t ACR;  /* Auxiliary Control Register */
+	uint8_t IMR;  /* Interrupt Mask Register */
+	uint8_t ISR;  /* Interrupt Status Register */
+
+private:
+	uint8_t OPCR; /* Output Port Conf. Register */
+	uint8_t OPR;  /* Output Port Register */
+	PAIR  CTR;  /* Counter/Timer Preset Value */
+	uint8_t IPCR; /* Input Port Control Register */
+
+	/* state */
+	uint8_t IP_last_state; /* last state of IP bits */
+
+	/* timer */
+	uint8_t half_period;
+	emu_timer *duart_timer;
+
+	bool m_irq_state;
+
+	uint32_t get_ct_rate();
+	uint16_t get_ct_count();
+	void start_ct(int count);
+	virtual int calc_baud(int ch, bool rx, uint8_t data);
+	void clear_ISR_bits(int mask);
+	void set_ISR_bits(int mask);
+
+	int get_ch(duart_channel *ch)
+	{
+		if (ch == m_chanA)
+		{
+			return 0;
+		}
+		else if (ch == m_chanB)
+		{
+			return 1;
+		}
+		else if (ch == m_chanC)
+		{
+			return 2;
+		}
+
+		return 3;
+	}
+
+	duart_channel *get_channel(int chan);
+};
+
+class scn2681_device : public duart_base_device
+{
+public:
+	scn2681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+};
+
+class mc68681_device : public duart_base_device
+{
+public:
+	mc68681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+	uint8_t get_irq_vector();
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void update_interrupts() override;
+	mc68681_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
+
+	uint8_t IVR;  /* Interrupt Vector Register */
+};
+
+/**************************
+ * ColdFire MCF5206e UART
+ **************************/
+class mcf5206e_uart_device : public duart_base_device
+{
+public:
+	mcf5206e_uart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+	uint8_t get_irq_vector();
+
+	// There is no GPIO on the coldfire UART module
+	void cts_w(int state) { duart_base_device::ip0_w(state); }
+
+	virtual void ip1_w(int state) override {}
+	virtual void ip2_w(int state) override {}
+	virtual void ip3_w(int state) override {}
+	virtual void ip4_w(int state) override {}
+	virtual void ip5_w(int state) override {}
+	virtual void ip6_w(int state) override {}
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void update_interrupts() override;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+	mcf5206e_uart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+
+	bool m_read_vector; // if this is read and IRQ is active, it counts as pulling IACK
+
+	// ColdFire UART module is essentially two 68681 a-channels with a slighty different register map and no counter
+	uint8_t IVR;  /* Interrupt Vector Register */
+	uint16_t UBG;  /* Baud Rate Generator Prescale Register - Manual erronuosly calls this the timer preload register */
+
+};
+
+class sc28c94_device : public duart_base_device
+{
+public:
+	sc28c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	auto c_tx_cb() { return write_c_tx.bind(); }
+	auto d_tx_cb() { return write_d_tx.bind(); }
+
+	void rx_c_w(int state) { m_chanC->device_serial_interface::rx_w((uint8_t)state); }
+	void rx_d_w(int state) { m_chanD->device_serial_interface::rx_w((uint8_t)state); }
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+private:
+};
+
+class mc68340_duart_device : public duart_base_device
+{
+public:
+	mc68340_duart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+	mc68340_duart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+};
+
+class xr68c681_device : public mc68681_device
+{
+public:
+	xr68c681_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	virtual uint8_t read(offs_t offset) override;
+	virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+private:
+	virtual int calc_baud(int ch, bool rx, uint8_t data) override;
+
+	bool m_XTXA,m_XRXA,m_XTXB,m_XRXB; /* X bits for the BRG (selects between 2 BRG tables) */
+};
+
+DECLARE_DEVICE_TYPE(SCN2681, scn2681_device)
+DECLARE_DEVICE_TYPE(MC68681, mc68681_device)
+DECLARE_DEVICE_TYPE(SC28C94, sc28c94_device)
+DECLARE_DEVICE_TYPE(MC68340_DUART, mc68340_duart_device)
+DECLARE_DEVICE_TYPE(MCF5206E_UART, mcf5206e_uart_device)
+DECLARE_DEVICE_TYPE(XR68C681, xr68c681_device)
+DECLARE_DEVICE_TYPE(DUART_CHANNEL, duart_channel)
+
+#endif // MAME_MACHINE_MC68681_H