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~TEXAS
INSTRUMENTS
TItfS34010
1988 Graphics Products
TMS34010 User's Guide
."
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to discontinue
any semiconductor product or service identified in this publication without
notice. TI advises its customers to obtain the latest version of the relevant in-
formation to verify, before placing orders, that the information being relied
upon is current.
TI warrants performance of its semiconductor products to current specifica-
tions in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this
warranty. Unless mandated by government requirements, specific testing of
all parameters of each device is not necessarily performed.
TI assumes no liability for TI applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
Nor does TI warrant or represent that license, either express or implied, is
granted under any patent right, copyright, mask work right, or other intellec-
tual property right of TI covering or relating to any combination, machine, or
process in which such semiconductor products or services might be or are
used.
Copyright © 1988, Texas Instruments Incorporated
Contents
Section Page
1 Introduction 1-1
1.1 TMS34010 Overview . . . . . 1-2
1 .2 Key Features 1-3
1.3 Architectural Overview 1-4
1.3.1 TMS34010 Block Diagram 1-5
1.3.2 Other Special Processing Hardware 1-7
1.4 Typical Applications ........ . 1-8
1.5 Manual Organization . . . . . . . . . 1-9
1 .6 Related Documentation, References, and Suggested Reading 1 -11
2 Pin Functions 2-1
2.1 Pinout and Pin Descriptions 2-2
2.2 Host Interface Bus Signals 2-5
2.3 Local Memory Interface Signals 2-7
2.4 Video Timing Signals . . . . . . . 2-9
2.5 Hold and Emulator Interface Signals 2-10
2.6 Power, Ground, and Reset Signals 2-11
3 Memory Organization 3-1
3.1 Memory Addressing 3-2
3.2 Memory Map 3-4
3.3 Stacks . . . . . . . 3-6
3.3.1 System Stack 3-6
3.3.2 Auxiliary Stacks 3-9
4 Hardware-Supported Data Structures 4-1
4.1 Fields . . . . . . . . . 4-2
4.2 Pixels . . . . . . . . . 4-6
4.2.1 Pixels in Memory 4-6
4.2.2 Pixels on the Screen 4-7
4.2.3 Display Pitch 4-10
4.3 XY Addressing . . 4-11
4.3.1 XY -to- Linear Conversion 4-12
4.4 Pixel Arrays . . . . . . . . . 4-15
5 CPU Registers and Instruction Cache 5-1
5.1 General-Purpose Registers 5-2
5.1.1 Register File A ..... . 5-2
5.1.2 Register File B ..... . 5-3
5.1.3 Stack Pointer ..... . 5-4
5.1.4 Implied Graphics Operands 5-5
5.2 Status Register 5-18
5.3 Program Counter . . . . . . . 5-19
5.4 Instruction Cache . . . . . . . 5-20
5.4.1 Cache Hardware .... . 5-20
5.4.2 Cache Replacement Algorithm 5-21
5.4.3 Cache Operation ...... . 5-22
iii
5.4.4 Self-Modifying Code . . . . . . . . . . . . . . . . . . . 5-23
5.4.5 Flushing the Cache .................. . 5-23
5.4.6 Cache Disable . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.4.7 Performance with Cache Enabled versus Cache Disabled 5-24
5.5 Internal Parallelism . . . . . . . . . . . . . . . . . . . . . . 5-25
6 I/O Registers 6-1
6.1 I/O Register Addressing ..... 6-2
6.2 Latency of Writes to I/O Registers 6-4
6.3 I/O Registers Summary . . . . . . 6-5
6.3.1 Host Interface Registers 6-7
6.3.2 Local Memory Interface Registers 6-8
6.3.3 Interrupt Interface Registers 6-8
6.3.4 Video Timing and Screen Refresh Registers 6-9
6.4 Alphabetical Listing of I/O Registers .. . . . 6-10
7 Graphics Operations 7-1
7.1 Graphics Operations Overview 7-2
7.2 Pixel Block Transfers . . . . . 7-4
7.2.1 Color- Expand Operation 7-5
7.2.2 Starting Corner Selection . 7-7
7.2.3 Interrupting PixBlts and Fills 7-8
7.3 Pixel Transfers ....... . 7-10
7.4 Incremental Algorithm Support 7-10
7.5 Transparency . . . . . . . . 7 -11
7.6 Plane Masking ....... . 7-12
7.7 Pixel Processing ...... . 7-15
7.8 Boolean Processing Examples .. 7-17
7.8.1 Replace Destination with Source 7-18
7.8.2 Logical OR of Source with Destination 7-18
7.8.3 Logical AND of NOT Source with Destination 7-18
7.8.4 Exclusive OR of Source with Destination 7-18
7.9 Multiple-Bit Pixel Operations ......... . 7-19
7.9.1 Examples of Boolean and Arithmetic Operations 7-19
7.9.2 Operations on Pixel Intensity . . . . . 7-22
7.10 Window Checking ........... . 7-25
7.10.1 W=1 Mode - Window Hit Detection . 7-26
7.10.2 W=2 Mode - Window Miss Detection • 7-27
7.10.3 W=3 Mode - Window Clipping 7-27
7.10.4 Specifying Window Limits 7-28
7.10.5 Window Violation Interrupt 7-29
7.10.6 Line Clipping . . . . . . . 7-29
8 Interrupts, Traps, and Reset 8-1
8.1 Interrupt Priorities and Vector Addresses 8-2
8.2 Interrupt Interface Registers 8-3
8.3 External Interrupts 8-3
8.4 Internal Interrupts .. 8-5
8.5 Interrupt Processing 8-6
8.5.1 Interrupt Latency 8-7
8.6 Traps ....... . 8-9
8.7 Illegal Opcode Interrupts 8-9
8.8 Reset . . . . . . . . . . 8-10
8.8.1 Asserting Reset 8-10
8.8.2 Suspension of DRAM-Refresh Cycles During Reset 8-11
iv
8.8.3 State of VCLK During Reset 8-11
8.8.4 Initial State Following Reset 8-11
8.8.5 Activity Following Reset 8-12
9 Screen Refresh and Video Timing 9-1
9.1 Screen Sizes ........................ . 9-2
9.2 Video Timing Signals . . . . . . . . . . . . . . . . . . . . . 9-3
9.3 Video Timing Registers . . . . . . . . . . . . . . . . . . . . 9-4
9.4 Relationship Between Horizontal and Vertical Timing Signals 9-5
9.5 Horizontal Video Timing 9-6
9.6 Vertical Video Timing . . . . . 9-8
9.6.1 Noninterlaced Video Timing 9-9
9.7 Display Interrupt 9-13
9.8 Dot Rate ......... . 9-14
9.9 External Sync Mode 9-15
9.9.1 A Two-GSP System I •• 9-15
9.9.2 External Interlaced Video 9-17
9.10 Video RAM Control . . . . . 9-18
9.10.1 Screen Refresh ..... 9-18
9.10.2 Video Memory Bulk Initialization 9-26
10 Host Interface Bus 10-1
10.1 Host Interface Bus Pins 10-2
10.2 Host Interface Registers 10-2
10.3 Host Register Reads and Writes 10-4
10.3.1 Functional Timing Examples 10-5
10.3.2 Ready Signal to Host . . . 10-8
10.3.3 Indirect Accesses of Local Memory 10-11
10.3.4 Halt Latency ........... . 10-19
10.3.5 Accommodating Host Byte-Addressing Conventions 10-20
10.4 Bandwidth 10-22
10.5 Worst-Case Delay 10-23
11 local Memory Interface 11-1
11.1 Local Memory Interface Pins 11-2
11.2 Local Memory Interface Registers 11-3
11.3 Memory Bus Request Priorities . 11-4
11.4 Local Memory Interface Timing 11-5
11.4.1 Local Memory Write Cycle Timing 11-7
11.4.2 Local Memory Read Cycle Timing 11-8
11.4.3 Local Register-to- Memory Cycle Timing 11 -9
11.4.4 Local Memory-to-Register Cycle Timing 11 -10
11.4.5 Local Memory RAS-Only DRAM Refresh Cycle Timing 11 -11
11.4.6 Local Memory CAS-before-RAS DRAM Refresh Cycle Timing 11 -12
11.4.7 Local Memory Internal Cycles 11 -13
11.4.8 I/O Register Access Cycles .. 11 -13
11.4'.9 Read-Modify-Write Operations .. 11 -15
11.4.10 Local Memory Wait States 11 -16
11.4.11 Hold Interface Timing . . . . . . . 11 -18
11.4.12 Local Bus Timing Following Reset 11 -22
11.5 Addressing Mechanisms . . . . . . . 11-23
11.5.1 Display Memory Hardware Requirements 11-24
11.5.2 Memory Organization and Bank Selecting 11-25
11.5.3 Dynamic RAM Refresh Addresses 11-25
11.5.4 An Example - Memory Organization and Decoding 11-28
v
12 TMS34010 Instruction Set 12-1
12.1 Style and Symbol Conventions .. . . . 12-2
12.2 Addressing Modes and Operand Formats 12-4
12.2.1 Immediate Values and Constants 12-4
12.2.2 Absolute Addresses . . . . . 12-5
12.2.3 Register- Direct Operands . . . . . . 12-6
12.2.4 Register-Indirect Operands . . . . . 12-7
12.2.5 Register-Indirect with Offset 12-8
12.2.6 Register-Indirect with Postincrement 12-9
12.2.7 Register-Indirect with Predecrement 12-10
12.2.8 Register-Indirect in XY Mode 12-11
12.3 Instruction Set Summary Table . . . . . 12-12
12.4 Arithmetic, Logical, and Compare Instructions 12-19
12.5 Move Instructions Summary 12-20
12.5.1 Register-to- Register Moves 12-20
12.5.2 Value-to-Register Moves 12-20
12.5.3 XY Moves . . . . . . . . 12-20
12.5.4 Multiple-Register Moves 12-21
12.5.5 Byte Moves . . . . . . . 12-21
12.5.6 Field Moves . . . . . . . 12-22
12.S Graphics Instructions Summary 12-26
12.S.1 Comparing a Point to a Window 12-26
12.S.2 Converting an XY Address to a Linear Address 12-26
12.6.3 Drawing a Pixel and Advancing to the Next Pixel Address 12-26
1 2.S.4 Draw a Line . . . . . . . . . . . . . . . . . 12-26
12.S.5 Filling a Pixel Block . . . . . . . . . . . . . 12-26
12.S.6 Moving a Single Pixel .......... . 12-27
12.6.7 Moving a Two- Dimensional Block of Pixels 12-27
12.6.8 Implied Operands . . . . . . . . . . . . . . 12-28
12.7 Program Control and Context Switching Instructions 12-29
12.7.1 Subroutine Calls and Returns ......... . 12-29
12.7.2 Interrupt Handling ............... . 12-29
12.7.3 Setting, Saving, and Restoring Status Information 12-29
12.7.4 Jump Instructions ....... . 12-30
12.8 Shift Instructions . . . . . . . . . . . 12-32
12.9 XY Instructions . . . . . . . . . . . . 12-33
12.10 Alphabetical Reference of Instructions 12-34
13 Instruction Timings 13-1
13.1 General Instructions .............. . 13-2
13.1.1 Best Case Timing - Considering Hidden States 13-2
13.1 .2 Other Effects on Instruction Timing 13-3
13.2 MOVE and MOVB Instructions . . . . . . 13-4
13.2.1 Moves Between Registers and Memory 13-5
13.2.2 Memory-to- Memory Moves 13-S
13.2.3 MOVE Timing Example 13-8
13.3 FILL Instructions 13-10
13.3.1 FILL Setup Time 13-10
13.3.2 FI LL Transfer Timing 13-11
13.3.3 FILL Timing Examples 13-14
13.3.4 Interrupt Effects on FILL Timing 13-17
13.4 PIXBLT Instructions 13-18
13.4.1 PIXBLT Setup Time .. 13-18
13.4.2 PIXBLT Transfer Timing 13-20
vi
13.4.3 PIXBLT Timing Examples . . . . . . . . . . . . 13-26
13.4.4 The Effect of Interrupts on PIXBLT Instructions 13-30
13.5 PIXBLT Expand Instructions 13-31
13.5.1 PIXBLT Setup Time . . . 13-31
13.5.2 PIXBLT Transfer Timing 13-32
13.5.3 PIXBLT Timing Examples 13-37
13.5.4 The Effect of Interrupts 13-40
A TMS34010 Data Sheet A-1
B System Design Considerations B-1
C Software Compatibility with Future GSPs C-1
o Glossary 0-1
vii
Illustrations
Figure Page
1 -1 System Block Diagram ....................................... . 1-4
1-2 Internal Architecture Block Diagram ............................. . 1-5
2-1 TMS34010 Pinout (Top View) " ............................... . 2-2
2-2 TMS34010 Major Interfaces ................................... . 2-3
3-1 Logical Memory Address Space ................................ . 3-2
3-2 Physical Memory Addressing .................................. . 3-3
3-3 TMS34010 Memory Map ..................................... . 3-4
3-4 System Stack ............................................... . 3-7
3-5 Stack Operations ............................................ . 3-8
3-6 An Auxiliary Stack that Grows Toward Lower Addresses ............. . 3-10
3-7 An Auxiliary Stack that Grows Toward Higher Addresses ............ . 3-11
4-1 Field Storage in External Memory ............................... . 4-2
4-2 Field Alignment in Memory .................................... . 4-3
4-3 Field Insertion .............................................. . 4-5
4-4 Pixel Storage in External Memory ............................... . 4-7
4-5 Mapping of Pixels to Monitor Screen ............................ . 4-7
4-6 Configurable Screen Origin .................................... . 4-8
4-7 Display Memory Dimensions ................................... . 4-9
4-8 Display Memory Coordinates .................................. . 4-9
4-9 Pixel Addressing in Terms of XY Coordinates ...................... . 4-11
4-10 Concatenation of XY Coordinates in Address ...................... . 4-12
4-11 Conversion from XY Coordinates to Memory Address ............... . 4-13
4-12 Pixel Array ................................................. . 4-15
5-1 Register File A .............................................. . 5-2
5-2 Register File B .............................................. . 5-3
5-3 Stack Pointer Register ........................................ . 5-4
5-4 Status Register ............................................. . 5-18
5-5 Program Counter ............................................ . 5-19
5-6 TMS34010 Instruction Cache .................................. . 5-20
5-7 Segment Start Address ....................................... . 5-21
5-8 Internal Data Paths .......................................... . 5-25
5-9 Parallel Operation of Cache, Execution Unit, and Memory Interface 5-26
6-1 I/O Register Memory Map .................................... . 6-2
6-2 Correlation Between SRFADR and Logical Address Bits ............. . 6-18
6-3 Correlation Between DPYADR Bits and Row/Column Addresses ...... . 6-18
7 -1 Color- Expand Operation ...................................... . 7-6
7-2 Starting Corner Selection ..................................... . 7-7
7-3 Transparency ............................................... . 7 -11
7-4 Read Cycle With Plane Masking ................................ . 7-13
7-5 Write Cycle With Transparency and Plane Masking ................. . 7-14
7-6 Graphics Operations Interaction ................................ . 7 -16
7-7 Examples of Operations on Single- Bit Pixels ...................... . 7 -17
7-8 Examples of Boolean and Arithmetic Operations ................... . 7-19
7-9 Examples of Operations on Pixel Intensity ........................ . 7-22
7-10 Specifying Window Limits .................................... . 7-28
7 -11 Outcodes for Line Endpoints ................................... . 7-30
7-12 Midpoint Subdivision Method ................................. . 7-31
8-1 Vector Address Map ......................................... . 8-2
9-1 Horizontal and Vertical Timing Relationship ....................... . 9-5
viii
9-2 Horizontal Timing ........................................... . 9-6
9-3 Horizontal Timing Logic - Equivalent Circuit ...................... . 9-7
9-4 Example of Horizontal Signal Generation ......................... . 9-7
9-5 Vertical Timing for Noninterlaced Display ......................... . 9-8
9-6 Vertical Timing Logic - Equivalent Circuit ......................... . 9-9
9-7 Electron Beam Pattern for Noninterlaced Video .................... . 9-9
9-8 Noninterlaced Video Timing Waveform Example .................... . 9-10
9-9 Electron Beam Pattern for Interlaced Video ........................ . 9-11
9-10 Interlaced Video Timing Waveform Example ....................... . 9-12
9-11 External Sync Timing - Two GSP Chips .......................... . 9-16
9-12 Screen-Refresh Address Registers ............................... . 9-19
9-13 Logical Pixel Address ........................................ . -9-21
9-14 Screen-Refresh Address Generation ............................. . 9-22
10-1 Equivalent Circuit of Host Interlace Control Signals ................. . 10-4
10-2 Host 8- Bit Write with HCS Used as Strobe ....................... . 10-5
10-3 Host 8- Bit Read with HCS Used as Strobe ....................... . 10-6
10-4 Host 16- Bit Read with FfREAi) Used as Strobe .................... . 10-6
10-5 Host 16-Bit Write with HWRITE Used as Strobe ................... . 10-7
10-6 Host 16-Bit Write with HLDS, HUDS Used as Strobes .............. . 10-7
10-7 Host 16-Bit Read with HLDS, HUDS Used as Strobes .............. . 10-8
10-8 Host Interface Timing - Write Cycle With Wait ..................... . 10-10
10-9 Host Interface Timing - Read Cycle With Wait ..................... . 10-10
10-10 Host Indirect Read from Local Memory (INCR=1) .................. . 10-13
10-11 Host Indirect Write to Local Memory (INCW=1) ................... . 10-15
10-12 Indirect Write Followed by Two Indirect Reads (INCW=1, INCR=O) 10-16
10-13 Calculation of Worst-Case Host Interface Delay .................... . 10-23
11-1 Triple Multiplexing of Addresses and Data ., ...................... . 11-5
11 -2 Rowand Column Address Phases of Memory Cycle ................ . 11-6
11 -3 Local Bus Write Cycle Timing .................................. . 11-7
11 -4 Local Bus Read Cycle Timing .................................. . 11-8
11 -5 Local Bus Register-to- Memory Cycle Timing ...................... . 11-9
11 -6 Local Bus Memory-to- Register Cycle Timing ...................... . 11 -10
11-7 Local Bus RAS-Only DRAM-Refresh Cycle Timing ................. . 11 -11
11-8 Local Bus CAS-before-RAS DRAM-Refresh Cycle Timing ........... . 11 -12
11 -9 Local Bus Internal Cycles Back to Back .......................... . 11 -13
11 -10 I/O Register Read Cycle Timing ................................ . 11-14
11 -11 I/O Register Write Cycle Timing ................................ . 11 -15
11 -12 Local Bus Read Cycle with One Wait State ....................... . 11 -16
11-13 Local Bus Write Cycle with One Wait State ....................... . 11 -17
11 -14 Local Bus Register-to- Memory Cycle with One Wait State ........... . 11 -18
11 -15 TMS34010 Releases Control of Local Bus ........................ . 11-19
11 -16 TMS34010 Resumes Control of Local Bus ........................ . 11 -21
11 -17 Local Bus Timing Following Reset .............................. . 11-22
11 -18 External Address Format ...................................... . 11-23
11-19 Row Address for DRAM-Refresh Cycle .......................... . 11-27
11 -20 Address Decode for Example System ............................ . 11-28
11 -21 Display Memory Dimensions for the Example ...................... . 11-29
12-1 An Example of Immediate Addressing ............................ . 12-4
12-2 An Example of Absolute Addressing ............................. . 12-5
12-3 An Example of Register- Direct Addressing ........................ . 12-6
12-4 An Example of Register-Indirect Addressing ....................... . 12-7
12-5 An Example of Register-Indirect with Offset Addressing ............. . 12-8
12-6 An Example of Register-Indirect with Postincrement Addressing ....... . 12-9
12-7 An Example of Register-Indirect with Predecrement Addressing ....... . 12-10
12-8 Register-to- Memory Moves ................................... . 12-23
12-9 Memory-to- Register Moves ................................... . 12-24
ix
12-10 Memory-to-Memory Moves .................................... 12-25
12-11 Implied Operand Setup for LINE Timing Example .................... 12-10
12-12 LINE Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-10
12-13 LINE Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-10
13-1 Field Alignments in Memory .................................... 13-4
13-2 Source Data, Alignment G ...................................... 13-8
13-3 Destination Location, Alignment E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-8
13-4 Pixel Block Alignment in X .................................... , 13-11
13-5 Pixel Block Alignments ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-12
13-6 Implied Operand Setup for FILL Example ................ . . . . . . . . .. 13-14
13-7 FILL XY Timing Example ....................................... 13-15
13-8 Pixel Block Alignment in X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-21
13-9 Pixel Block Alignments ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-22
13-10 Source to Destination Alignments ................................ 13-23
13-11 Implied Operand Setup for PIXBLT Timing Examples ................. 13-26
13-12 PIXBLT XY,L Timing Example ................................... 13-27
13-13 Pixel Block Alignment in X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-33
13-14 Pixel Block Row Alignments .................................... 13-34
13-15 Implied Operand Setup for PIXBLT - Expand Examples ... . . . . . . . . . . . .. 13-37
13-16 PIXBLT B,XY Timing Example ................................... 13-38
Tables
Table Page
1 -1 Typical Applications of the TMS3401 0 ........................... . 1-8
2-1 Pin Descriptions ............................................ . 2-3
2-2 Host Interface Signals ........................................ . 2-5
2-3 Local Bus Interface Signals .................................... . 2-7
2-4 Video Timing Signals ........................................ . 2-9
2-5 Hold and Emulator Interface Signals ............................. . 2-10
2-6 Power, Ground, and Reset Signals .............................. . 2-11
5-1 B-File Registers Summary ..................................... . 5-5
5-2 Definition of Bits in Status Register ............................. . 5-18
5-3 Decoding of Field-Size Bits in Status Register ..................... . 5-19
5-4 Instruction Effects on the PC .................................. . 5-19
6-1 I/O Registers Summary ....................................... . 6-5
7-1 Boolean Pixel Processing Options .............................. . 7-15
7-2 Arithmetic (or Color) Pixel Processing Options .................... . 7-15
8-1 Interrupt Priorities ........................................... . 8-2
8-2 External Interrupt Vectors ..................................... . 8-4
8-3 Interrupts Associated with Internal Events ........................ . 8-5
8-4 Six Sources of Interrupt Delay ................................. . 8-8
8-5 Sample Instruction Completion Times ............................ . 8-8
8-6 Illegal Opcodes Ranges ....................................... . 8-9
8-7 State of Pins During a Reset ................................... . 8-11
9-1 Programming GSP #2 For External Sync Mode .................... . 9-16
9-2 Screen - Refresh Latency ...................................... . 9-25
10-1 Host Interface Register Selection ............................... . 10-2
10-2 Five Sources of Halt Delay .................................... . 10-20
10-3 Sample Instruction Completion Times ............................ . 10-20
10-4 Host Interface Estimated Bandwidth ............................. . 10-22
11 -1 Priorities for Memory Cycle Requests ............................ . 11-4
x
12-1 Instruction Set Symbol and Abbreviation Definitions ............... .. 12-2
12-2 Summary of Move Instructions ................................ .. 12-20
12-3 Summary of Operand Formats for the MOVB Instruction .. . . . . . . . . . . .. 12-21
12-4 Summary of Operand Formats for the MOVE Instruction . . . . . . . . . . . . .. 12-22
12-5 Summary of Operand Formats for the PIXT Instruction . . . . . . . . . . . . . .. 12-27
12-6 Summary of Array Types for the PIXBLT Instruction . . . . . . . . . . . . . . . .. 12-27
12-7 Implied Operands Used by Graphics Instructions .................... 12-28
12-8 Condition Codes for J Rcc and JAcc Instructions .................... 12-31
12-9 Summary of XY Instructions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-33
12-10 LINE Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-10
12-11 Per-Word Timing Values for Pixel Processing (P) . . . . . . . . . . . . . . . . . .. 12-10
13-1 MOVE and MOVB Memory-to-Register Timings . . . . . . . . . . . . . . . . . . .. 13-5
13-2 MOVE and MOVB Register-to-Memory Timings . . . . . . . . . . . . . . . . . . .. 13-6
13-3 Alignment Indices for Memory-to-Memory Moves ................... 13-6
13-4 MOVE Memory-to-Memory Timings .............................. 13-7
13-5 FILL Setup Time . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-10
13-6 FILL Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-11
13-7 Timing Values per Word for Graphics Operations (G) . . . . . . . . . . . . . . .. 13-13
13-8 PIXBLT Setup Time ........................................... 13-18
13-9 PIXBLT Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-20
13-10 Timing Values per Word for Graphics Operations (G) . . . . . . . . . . . . . . .. 13-24
13-11 PIXBLT Expand Setup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-32
13-12 PIXBLT Expand Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-32
13-13 Timing Values per Word for Graphics Operations (G) . . . . . . . . . . . . . . .. 13-36
B-1 Loading .................................................. .. B-2
xi
xii
Section 1
Introduction
The TMS34010 Graphics System Processor (GSP) is an advanced 32-bit
microprocessor, optimized for graphics systems. The TMS3401 0 is a member
of the TMS340 family of computer graphics products from Texas Instruments.
A single TMS3401 0 provides a cost-effective solution in applications that re-
quire efficient data manipulation. The TMS3401 0 can be configured to serve
in either a host-based or a stand-alone environment. Systems based on mul-
tiple TMS34010 devices are implemented using special features of the
TMS34010's local and host interfaces.
The TMS3401 0 is well supported by a full set of hardware and software de-
velopment tools, including a full-speed emulator, a software simulator, an
IBM-PC development board, a C compiler, predeveloped software libraries,
and assembly language tools.
Topics covered in this introductory section include:
Section Page
1.1 TMS34010 Overview ................................................................................ 1 -2
1.2 Key Features ............................................................................................... 1 -3
1.3 Architectural Overview .............................................................................. 1 -4
1.4 Typical Applications .................................................................................. 1 -8
1.5 Manual Organization ................................................................................. 1 -9
1.6 Related Documentation, References, and Suggested Reading ......... 1 -11
1 -1
Introduction - TMS3401 0 Overview
1.1 TMS34010 Overview
The TMS3401 0 combines the best features of general-purpose processors and
graphics controllers to create a powerful and flexible Graphics System Pro-
cessor. Key features of the TMS34010 are its speed, high degree of pro-
grammability, and efficient manipulation of hardware-supported data types
such as pixels and two-dimensional pixel arrays.
The TMS34010's unique memory interface reduces the time needed to per-
form tasks such as bit alignment and masking. The 32-bit architecture sup-
plies the large blocks of continuously-addressable memory that are necessary
in graphics applications. TMS34010 system designs can take advantage of
video RAM (such as the TMS4461 ) technology to facilitate applications such
as high-bandwidth frame buffers; this circumvents the bottleneck often en-
countered when using conventional D RAMs in graphics systems.
The TMS3401 0 instruction set includes a full complement of general-purpose
instructions, as well as graphics functions, from which you can construct ef-
ficient high-level functions. The instructions support arithmetic and Boolean
operations, data moves, conditional jumps, and subroutine calls and returns.
The TMS34010 architecture supports a variety of pixel sizes, frame buffer
sizes, and screen sizes. On-chip functions have been carefully selected so that
no functions tie the TMS3401 0 to a particular display resolution. This en-
hances the portability of graphics software, and allows the TMS34010 to
adapt to graphics standards such as MIT's X, CGljCGM, GKS, NAPLPS,
PHIGS, and evolving industry and display management standards.
1-2
Introduction - Key Features
1.2 Key Features
• Fully programmable 32-bit general-purpose processor
• 128-megabyte address range
• Instruction cycle times:
132 ns (TMS34010-60)
160 ns (TMS34010-50)
200 ns (TMS34010-40)
• On-chip peripheral functions include:
Programmable CRT control (horizontal sync, vertical sync, and
blanking)
Direct interfacing to conventional DRAMs and multiport video
RAMs
Automatic CRT display refresh
Direct communications with an external (host) processor
• Instruction set includes special graphics functions such as pixel
processing, XY addressing, and window clip/hit
• Programmable 1, 2, 4, 8, or 16-bit pixel size with 16 Boolean and
6 arithmetic pixel-processing options
• 30 general-purpose 32-bit registers
• 256-byte on-chip instruction cache
• Dedicated 8/16-bit host-processor interface and HOLD/HLDA interface
• 32-bit and 64-bit integer arithmetic
• High-level language support
• Full line of hardware and software development tools including:
C compiler
Macro assembler
Linker
Archiver
Software application libraries
XDS (Extended Development Support) in-circuit emulator
Software development board (SDB)
ROM utility
Simulator
Symbolic debugger
• 68-pin PLCC package
• 5-V CMOS technology
1-3
Introduction - Architectural Overview
1.3 Architectural Overview
Figure 1 -1 illustrates the TMS34010's major internal functions and its inter-
faces to external devices. The on-chip processor executes both graphics in-
structions and general-purpose instructions. The TMS3401 0 is a true 32-bit
processor, with 32-bit internal data paths, a 32-bit ALU, and a large address
space. Thirty 32-bit general-purpose registers, a 32-bit stack pointer, and a
256-byte instruction cache increase performance. Nonprocessor functions
included on the chip include CRT timing, screen refresh, and DRAM refresh.
Separate physical interfaces are provided for communicating with a host pro-
cessor, for providing the video timing signals necessary to control a CRT
monitor, and for connecting directly to dynamic RAMs (like the TMS4256 or
TMS4C1024) and video RAMs (such as the TMS4461).
Host
~
Prooeaeor
{
I
~_~_~~..c:~_~~
.:.:.: Host Bus :.:.:. Holt-Graphics
Interfaoe
pGroraphoa~r
v.vv
___LI
I.
I
I ,f c-r
Conventional
DRAMa
il~
~:::::::::::::::,:::::::::::::::::::::::::::::::,,::}:::: eraphlOl
l
:!i!!!
Memory BU8 ;:;;;:;:;:;;::;;;;;:;:::::;;;;;:;:;:;:;:::;:,:;:::;:;:;;;;;:;;;})
II ::~t~ :~ r---"----. . .
i I::::::
I .~(..I.
Frame BUffer
.~ ~ Lo.
,..
ORAM-
Refresh
Control
____________________ ~~-_-_J________~__~
5,; ~ J5~ lie = ~;~>=or
...
Figure 1-1. System Block Diagram
1-4
Introduction - Architectural Overview
1.3.1 TMS34010 Block Diagram
Figure 1 -2 illustrates the internal architecture of the TMS3401 0; the following
subsections describe the individual blocks shown in Figure 1 -2.
Ir----------------------------------,
VO Register.
External Instruction Instruction
Interrupt Interrupt Cache Decode
Requests Registers
Reset
Host Host
Interface Interface
Bus Registers
---::'I
Program
Counter
Sync and Video Timing
Blanking Registers
status Register
Mlorocontrol
ALU ROM
8arrel Shifter
Register File A
Local Memory
Control Register File 8
Registers
stack Pointer
Clock
Outputs
Internal Clock
Clroultry Clock
Inputs
Local Memory
Interface Bus
Figure 1-2. Internal Architecture Block Diagram
1.3.1.1 CPU Internal Functions
The center portion of Figure 1-2 highlights the main internal functions of the
TMS34010:
• The 32-bit program counter (PC) points to the next instruction word
to be fetched. The PC's four LSBs are always O. Section 5.3 (page
5-18) discusses the program counter.
• The 32-bit status register (ST) specifies the status of the TMS3401 0
processor. It contains the sign, carry, zero, overflow, interrupt enable,
and PixBlt execution status bits. It also specifies the lengths and field
extension modes of fields 0 and 1. Section 5.2 (page 5-17) discusses
the status register.
1-5
Introduction - Architectural Overview
• Register files A and B each contain 15 general-purpose registers,
Ao-A14 and Bo-B14, respectively. The B-file registers are also used as
implied operands for the graphics instructions. Section 5.1 (page 5-2)
discusses the register files.
The general-purpose register files are dual ported to support parallel data
movement. Two separate internal buses route data from the registers to
the ALU, and a third bus routes results back to the registers.
• The stack pointer, or SP, is available to instructions that operate on
either reg ister fi Ie.
• The 32-bit barrel shifter shifts or rotates 32-bit operands from 1 to
32 bit positions in a single machine state.
• The 32-bit ALU is connected to the other CPU components by 32-bit
data paths. This allows most register-to-register operations to be per-
formed in a single machine state. (Accessing external memory requires
a minimum of two states.) The following actions occur in parallel during
a single state:
1) Two operands are transferred from the selected general-purpose
register file to the ALU.
2) The ALU performs the specified operation on the operands.
3) The result is routed back to the general-purpose register file.
1.3.1.2 Instruction Cache
The TMS3401 0 contains a 256-byte instruction cache that can contain up to
128 instruction words (an instruction word may be an entire single-word in-
struction or 16 bits of a multiple-word instruction). Section 5.4 (page 5-19)
describes instruction cache operation.
1.3.1.3 I/O Registers
Twenty-eight 16-bit, on-chip I/O registers are dedicated to peripheral control
functions. The I/O registers are divided into four categories:
• Seven local memory interface registers are dedicated to memory
interface control and configure the memory controller.
• Fourteen video timing and screen refresh registers generate the
sync and blanking signals used to drive a CRT, and schedule screen-
refresh cycles.
• Five host interface registers are accessible to external host process-
ors as well as to the TMS3401 O. Status information can be communi-
cated directly through these registers. Large blocks of data in
TMS34010 memory can be accessed indirectly through pointer registers.
• Two interrupt control registers provide status information about
interrupt requests.
Section 6 provides individual descriptions of each I/O register.
1-6
Introduction - Architectural Overview
1.3.1.4 Microcontrol ROM
The TMS34010 transfers decoded instructions to the microcontrol ROM for
interpretation. The microcontrol ROM has 166 control outputs and 808 mic-
rostates.
1.3.1.5 Clock Timing Logic
The clock timing logic converts the clock input signals to internal timing sig-
nals and generates the clock output signals, LCLK1 and LCLK2, used by ex-
ternal devices. The machine state is a fundamental time unit of the graphics
processor in the TMS3401 0; it is the time interval during which the processor
is in a particular microinstruction state. The instruction timing for each as-
sembly language instruction is specified in multiples of machine states. The
TMS34010's machine state is a single local clock period (the time from one
LCLK1 low-to-high transition to the next) in duration.
1.3.2 Other Special Processing Hardware
The TMS3401 0 CPU also supports the following special processing functions
in hardware:
• Detecting whether a pixel lies within a specified display window
• Detecting the leftmost one in a 32-bit register
• Expanding a black-and-white pattern to a variable pixel-depth pattern
1-7
Introduction - Typical Applications
1.4 Typical Applications
The TMS34010's 32-bit processing power and its ability to handle complex
data structures make it well suited for a variety of applications. These include
display systems, imaging systems, mass storage, communications, high-speed
controllers, and peripheral processing. The TMS3401 O's efficient bit manip-
ulation facilitates demanding tasks such as high-quality, proportionally-
spaced text; this capability makes it especially useful in applications such as
desktop publishing. In graphics display systems, the TMS34010 provides
cost-effective performance for color or black-and-white bit-mapped displays.
Table 1-1 lists typical end uses of the TMS3401 O.
Table 1-1. Typical Applications of the TMS3401 0
Computers Industrial Control
- Terminals and CRTs - Robotics
- Windowing systems - Process control
- Electronic publishing - Instrumentation
- Laser printers - Motor control
- Personal computers - Navigation
- Printers and plotters
- Engineering workstations
- Copiers Telecommunications
- Document readers
- FAX - Video phones
- Imaging - PBX
- Data processing
Consumer Electronics
- Automotive displays
- Information terminals
- Cable TV
- Home control
- Video games
1-8
Introduction - Manual Organization
1.5 Manual Organization
The TMS34010 User's Guide describes TMS3401 0 operation, focusing on the
TMS34010's role in applications that involve CRT -based, bit-mapped, graph-
ics systems. The user's guide is divided into four major sections:
1) General information (Section 1 )
2) Architecture (Sections 2-8)
3) Timing (Sections 9-11 )
4) Instruction set (Sections 7, 12, and 13)
A glossary, an index, and a reference card are also provided.
Section 1 Introduction
Provides an overview of the TMS3401 0 and TMS3401 0 architecture, includ-
ing key features, a block diagram, and typical applications. Discusses manual
organization and lists suggested reading.
Section 2 Pin Functions
Illustrates the TMS3401 0 pinout and contains general pin descriptions. Also
describes specific pin functions regarding the host interface, the local bus in-
terface, video timing signals, hold and emulator interface pins, and power,
ground, and reset pins.
Section 3 Memory Organization
Discusses 32-bit addressing methods, the TMS3401 0 memory map, and the
stack.
Section 4 Hardware-Supported Data Structures
Discusses hardware-supported data structures (such as fields and pixels) and
XY addressing.
Section 5 CPU Registers and Instruction Cache
Describes general-purpose register files A and B (including a reference of the
B registers' graphics functions), the status register, the program counter, and
the instruction cache.
Section 6 I/O Registers
Provides a detailed discussion of host interface registers, memory-interface
control registers, video timing and screen refresh registers, interrupt interface
registers, and I/O register addressing. Includes an alphabetical reference of
the I/O registers.
Section 7 Graphics Operations
Discusses graphics instructions such as PixBlts, PIXTs, and related topics such
as 2-dimensional arrays of pixels, window checking, XY -to-linear conversion,
and plane masking.
Section 8 Interrupts, Traps, and Reset
Describes external and internal interrupts, interrupt processing, and reset.
1-9
Introduction - Manual Organization
Section 9 Screen Refresh and Video Timing
Describes the horizontal sync, vertical sync, and blanking signals, horizontal
and vertical timing, and video RAM control.
Section 10 Host Interface Bus
Discusses host interface pins, registers, and timing.
Section 11 Local Memory Interface Bus
Discusses local memory interface timing, addressing mechanisms, and data
manipulation at the local memory interface.
Section 12 Assembly Language Instruction Set
Discusses addressing modes, summarizes MOVE, PIXBLT, and PIXT in-
struction variations, and presents the entire TMS34010 assembly language
instruction set in alphabetical order.
Section 13 Instruction Timings
Contains an overview of timing for general instructions, and specific timing
information for move and graphics instructions.
Appendix A TMS34010 Data Sheet
Appendix B Emulation Guidelines for Prototyping
Appendix C Software Compatibility with Future GSPs
Appendix D Glossary
1-10
Introduction - Related Documentation, References, and Suggested Reading
1.6 Related Documentation, References, and Suggested Reading
The following books and articles provide further background in graphics and
system concepts associated with graphics.
Artwick, Bruce A. Applied Concepts in Microcomputer Graphics. Englewood
Cliffs, New Jersey: Prentice- Hall, 1984.
Asal, Short, Preston, Simpson, Roskell, and Guttag. "The Texas Instruments
34010 Graphics System Processor." IEEE Computer Graphics and Appli-
cations voL6 no.10, pp. 24-39.
Bresenham, J.E. "Algorithm for Computer Control of a Digital Plotter." IBM
Systems Journal 4 No.1 (1965): 25-30.
Bresenham, J.E. "A Linear Algorithm for Incremental Display of Digital Arcs."
Communications of the ACM 20 (Feb. 1977): 100-106.
Cody, William J. Jr., and William Waite. Software Manual for the Elementary
Functions. Englewood Cliffs, New Jersey: Prentice- Hall, 1980.
Foley, James, and Andries van Dam. Fundamentals of Interactive Computer
Graphics. Reading, Massachussetts: Addison-Wesley, 1982.
Gupta, Satish. "Architectures and Algorithms for Parallel Updates of Raster
Scan Displays." Tech. Report CMU-CS-82-111, Computer Science Dept.,
Carnegie Mellon University, 1981.
Ingalls, D.H. "The Smalltalk Graphics KerneL" Spec:al issue on Smalltalk,
Byte, August 1981, pp. 168-194.
Kernighan, B., and D. Ritchie The "c" Programming Language. Englewood
Cliffs, New Jersey: Prentice- Hall, 1978.
Killebrew, C.R. Jr., "The TMS3401 0 Graphics System Processor." BYTE, De-
cember 1986, pp. 193-204.
Kochan, Stephen G. Programming in C. Hasbrouck Heights, New Jersey:
Hayden Book Company, 1983.
Newman, W.M., and R.F. Sproull. Principles of Interactive Computer
Graphics. 2nd ed. New York: McGraw-Hili, 1979.
Pike, Rob. "Graphics in Overlapping Bitmap Layers." ACM Transactions On
Graphics 2 (April 1983): 135-160.
Pinkham, R., M. Novak, and K. Guttag. "Video RAM Excels at Fast Graphics."
Electronic Design, August 18, 1983, pp. 161-168.
Pitteway, M.L.V. "Algorithm for Drawing Ellipses or Hyperbolae with a Digital
Plotter." Computer Journal 1 0 (November 1967): 24-35.
Porter, T. and T. Duff. "Composing Digital Images." Computer Graphics, July
1984, pp. 253-259.
Sproull, R.F. and I.E. Sutherland. "A Clipping Divider." Fall Joint Computer
Conference Washington, DC: Thompson Books, 1968.
1-11
Introduction - Related Documentation, References, and Suggested Reading
Van Aken, Jerry R. "An Efficient Ellipse-Drawing Algorithm." IEEE Computer
Graphics & Applications 4 (Sept. 1984): 24-35.
Wientjes, Guttag, and Roskell. "First Graphics Processor Takes Complex Or-
ders to Run Bit-Mapped Displays." Electronic Design Vol. 34, No.2
(January 23, 1986): 73-80.
The following TMS34010 documents are available from Texas Instruments.
To obtain a copy of any of the TI documents listed below, please call the Texas
Instruments Customer Response Center (CRC) at 1 -800-232-3200.
• The TMS34010 Application Guide (literature number SPVA007) is a
collection of individual application reports. Each application report dis-
cusses a specific TMS34010 application; for example, using a
TMS34010 in a 512 x 512-pixel minimum-chip system, designing
TMS34010-based systems that are compatible with various graphics
standards, and interfacing the TMS3401 0 to a variety of host processors.
• The TMS34010 Assembly Language Tools User's Guide (literature
number SPVU004) tells you how to use the TMS34010 assembler,
linker, archiver, object format converter, and simulator.
• The TMS34010 C Compiler User's Guide (literature number
SPVU005) tells you how to use the TMS34010 C compiler. This C
compiler accepts standard Kernighan and Ritchie C source code and
produces TMS3401 0 assembly language source code. We suggest that
you use The C Programming Language (written by Brian W. Kernighan
and Dennis M. Ritchie, published by Prentice- Hall) as a companion to
the TMS34010 C Compiler User's Guide.
• The TMS34010 Math/Graphics Function Library User's Guide
(literature number SPVS006) describes a collection of mathematics and
graphics functions that can be called from C programs.
• The TMS34010 Software Development Board User's Guide (lit-
erature number SPVU002) describes using the TMS3401 0 software de-
velopment board (a high-performance, PC-based graphics card) for
testing and developing TMS3401 O-based graphics systems.
• The TMS34010 Software Development Board Schematics (liter-
ature number SPVU003) is a companion to the TMS34010 Software
Development Board User's Guide.
• The TMS34010 Font Library User's Guide (literature number
SPVU007) describes a set of fonts that are available for use in a
TMS3401 O-based graphics system.
1 -12
Section 2
Pin Functions
This section discusses the TMS3401 0 pin functions. Section 2.1 contains a
TMS34010 pinout, summarizes the pin functions, and categorizes the signals
by function; Section 2.2 through Section 2.6 describe the functional catego-
ries.
Topics in this section include:
Section Page
2.1 Pinout and Pin Descriptions .................................................................... 2-2
2.2 Host Interface Bus Signals ....................................................................... 2-5
2.3 Local Memory Interface Signals .............................................................. 2-7
2.4 Video Timing Signals ................................................................................ 2-9
2.5 Hold and Emulator Interface Signals .................................................... 2-10
2.6 Power, Ground, and Reset Signals ....................................................... 2-11
2-1
Pin Functions - Pinout and Pin Descriptions
2.1 Pinout and Pin Descriptions
The TMS3401 0 is packaged as a 68-pin plastic leaded chip carrier (PLCC).
Figure 2-1 shows a pinout of the TMS3401 0 processor, and Table 2-1 sum-
marizes the pin functions at each interface. Appendix A contains mechanical
information.
9 8 7 6 5 4 3 2 1 6867666564 63 6261
LAD1
LAD11
LAD12
44
27 28 29 3031 32 33 34 35 36 37 38 394041 42 43
U. . N lUlU I~ I<t: 1. .1 V) ~ IZ IV) IV) I~ IWI~
u~~zzz~<t:V)~w<t:<t: ozo>-
> d d >- >- <t: ~ ...J > 0 Cl a: U Iii I a:
...J...I~~ffi~ g ~ I
I<t:
I~
Figure 2-1. TMS34010 Pinout (Top View)
As Figure 2-2 shows, the TMS3401 O's 68 pins are divided among several in-
terfaces:
Host interface 25 pins
Local memory interface 29 pins
Video timing interface 4 pins
Hold and emulator interfaces 3 pins
Power and reset 7 pins
Total: 68 pins
2-2
Pin Functions - Pinout and Pin Descriptions
Host Interface ---
+-----tmIt
..
( x l a . a HDO-HD15
':x,' ,.; ;•..:,";?;"""; HF8O-HFS1
- - -.... RCDS
- - -.... ~y
LADO-LAD15 ~LZim~
t)ER 1-----+
DDO~I--_ _'"
~I-----+
~I------'"
'mIcI
t----+ r
Looal Memory
Interface
LRDYM----
Video TIming
{ -----MVCLK
a UN'f1-L1Nf21(1_ _
LCLK1t---.......
LCLK2t---.......
w ibidi2iXfT@ VCC INCLKM----
Power, Ground
{ ~-±l,':ii~';V88
and Reset ~M----} Hold and
RUNJ§.ID Emulator
- - -.... mET ~ Interfaoes
Figure 2-2. TMS34010 Major Interfaces
Table 2-1. Pin Descriptions
Host Interface Bus Pins
Name Pin I/O Description
'RCS 66 I Host chip select
HDo-HD15 44-51,53-60 I/O Host bidirectional data bus
HFSO,HFS1 67,68 I Host function select
'FITNT 42 0 Host interrupt request
FITI5'S" 63 I Host lower data select
~ 62 I Host upper data select
HRDY 43 0 Host ready
'Rlm\l') 64 I Host read strobe
HWm'IT 65 I Host write strobe
2-3
Pin Functions - Pinout and Pin Descriptions
Table 2-1. Pin Descriptions (Concluded)
Locsllnterfsce Bus Pins
Name Pin I/O Description
~ 38 0 Local row-address strobe
~ 39 0 Local column-address strobe
DDOUT 36 0 Local data direction out
lrEN 37 0 Local data enable
LADo-LAD15 10-17,19-26 I/O Local address/data bus
IA[ 34 0 Local address latched
LCLK1,LCLK2 28,29 0 Local output clocks
'[I'NT1 ,Lfl\JT2 6,7 I Local interrupt request pins
LRDY 9 I Local ready
TR/M 41 0 Local shift-register transfer or output enable
W 40 0 Local write strobe
INCLK 5 I Input clock
Hold snd Emulation
Name Pin I/O Description
HOll) 8 I Hold request
RUN/E'M'U 2 I Run/Emulate
H'D5A/mTI'A 33 0 Hold acknowledge or emulate acknowledge
Video Timing Signals
Name Pin I/O Description
lITANl( 32 0 Blanking
~ 30 I/O Horizontal sync
VCLK 4 I Video clock
~ 31 I/O Vertical sync
Power, Ground, snd Reset Signals
Name Pin I/O Description
~ 3 I Device reset
Vee 27,61 I Nominal 5-volt power supply
VSS 1,18,35,52 I Ground
2-4
Pin Functions - Host Interface Bus Signals
2.2 Host Interface Bus Signals
The host interface pins are used for communication between the TMS3401 0
and a host processor. Signals output on these pins are assumed to be asyn-
chronous with respect to local clocks LCLK1 and LCLK2. To software running
on a host processor, the TMS34010's host interface appears as a peripheral
device containing a block of four 16-bit registers. Table 2-2 describes the
host interface pins. Section 6 describes the host interface registers, and Sec-
tion 10 discusses host interface operation.
Table 2-2. Host Interface Signals
Signal I/O Description
HCS I Host Chip Select. HCS is driven active low to enable access to the 16-bit host
interface register that is selected by H FSO and H FS1. During the low-to-high
transition of RESET, the level on the HCS input determines whether the
TMS34010 is halted (if ReS is high), or begins immediately executing its reset
service routine (if ReS is low). In the second case, the ReS and RESE'i" pins
may be tied directly together.
HFSO, HFS1 I Host Function Select. HFSO and HFS1 determine which of the four 16-bit
host interface registers is selected during a read or write cycle that is initiated
by the host processor.
HFS1 HFSO Register Description
0 0 HSTADRL LSBs of pointer address
0 1 HSTADRH MSBs of pointer address
1 0 HSTDATA Data buffer register
1 1 HSTCTL Control register
HREAD I Host Read Strobe. HREAD is driven active low during a read cycle that is
initiated by the host processor. This enables the contents of the selected host
interface register to be output on H Do-H 015. 'R'RtAD should not be active low
at the same time that HWRITE is active low.
HWRITE I Host Write Strobe. HWRITE is driven active low during a write cycle that is
initiated by the host processor. This enables the contents of HDo-HD15 to be
written to the selected host interface register. HWRITE should not be active low
at the same time that HREAD is active low.
HLDS I Host Lower Data Select. H LDS is driven active low during a read or write
cycle that is initiated by the host. This enables the lower byte (bits 0-7) of the
selected host interface register to be accessed.
'RUiJS I Host Upper Data Select. 'RUiJS is driven active low during a read or write
cycle that is initiated by the host processor. This enables the upper byte (bits
8-15) of the selected host interface register to be accessed.
t In systems that do not use the host interface, it may be desirable to pull these inputs up to the +Vcc
level.
2-5
Pin Functions - Host Interface Bus Signals
Table 2-2. Host Interface Signals (Concluded)
Signal I/O Description
HROY 0 Host Ready. HROY indicates when the TMS3401 0 is ready to complete a read
or write cycle that is initiated by the host. Except during an access of a host
interface register, HROY is always high. H ROY is driven low if the host pro-
cessor attempts to initiate an access of a host interface register before the
TMS34010 has had sufficient time to complete all processing resulting from an
access initiated previously by the host. H RDY always goes low briefly at the
start of a HSTCTL register access. When HRDY is driven low, the host must
wait to complete the access until HRDY is again driven high. While'RCS is high,
H RDY is driven high.
HiNT 0 Host Interrupt Request. HINT follows the INTOUT bit in the HSTCTL reg-
ister; it is typically used to transmit interrupt requests from the TMS3401 0 to the
host processor. When INTOUT is set to 1 by the TMS34010, 'RTNT is driven
active low. HiNT remains active low until the host writes a 0 to INTOUT, at
which time 'RTNT becomes inactive high.
HOQ-H015 I/O Host Bidirectional Data Bus. The host data pins, HDQ-HD15, form a bidi-
rectional 16-bit bus which is used to transfer data between the selected 16-bit
host interface register and the host processor. H DO is the LS Band H 015 is the
MSB.
2-6
Pin Functions - Local Memory Interface Signals
2.3 Local Memory Interface Signals
The TMS3401 0 uses the local bus interface pins to communicate with external
memory and with memory-mapped I/O devices. The signals at this interface
are used directly to control DRAMs (dynamic RAMs) and VRAMs (video
RAMs). Section 11 discusses local memory interface operation.
Table 2-3. Local Bus Interface Signals
Signal I/O Description
DEN 0 Local Data Enable. DEN is an active-low output; it drives the active-low
output-enable inputs on the bidirectional transceivers (such as the
74ALS245) which are used to buffer data input and output on the
LADo-LAD15 pins. External buffering may be required on the LADo-LAD15
pins when the TMS34010 is interfaced to a large number of local memory
devices.
DDOUT 0 Local Data Direction Out. DDOUT drives the direction control inputs on
the bidirectional transceivers (such as the 74ALS245) which are used to buf-
fer data input and output on the LADo-LAD15 pins. External buffering may
be required on the LADo-LAD15 pins when the TMS3401 0 is interfaced to a
large number of local memory devices. During write cycles, DDOUT is driven
high to enable data to be output from the LADo-LAD15 pins while DEN is
driven active low. During read cycles, DDOUT goes low to enable data to be
input to the LADo-LAD15 pins while DEN is driven active low. At all other
times, DDOUT remains driven to the default high level.
LAL 0 Local Address Latched. An external latch can use the high-to-Iow transi-
tion of LA[ to capture the column address from the LADo-LAD15 pins. When
a transparent latch such as a 74ALS373 is used, the address remains latched
as long as LAL remains active low.
RAS 0 Local Row Address Strobe. The RAS output drives the RAS inputs of
DRAMs and VRAMs.
~ 0 Local Column Address Strobe. The Ct\S output drives the Ct\S inputs of
DRAMs and VRAMs.
W 0 Local Write Strobe. The active-low W output drives the W inputs of
DRAMs and VRAMs. W can also be used as the active-low write enable to
static memories and other devices connected to the TMS3401 0 local interface.
During a local memory read cycle, W remains inactive high while CA:S is
strobed active low. During a local memory write cycle, W is strobed active low
while Ct\S is low. During shift-register-transfer cycles, the state of W indicates
whether the transfer is from shift register to memory (W is low) or memory to
shift register (W is high). At all other times, W is driven to the default high
level.
TR/ITE 0 Local Shift Register Transfer or Output Enable. This pin connects di-
rectly to a VRAM's TR/OE (or DT/Ot) pin. During local memory read cycles,
the TR/ITE pin functions as an active-low output enable to gate data from
memory to the LADo-LAD15 pins. During VRAM shift-register-transfer cy-
cles, TR/M is driven active low during the high-to-Iow transition of RAS.
INCLK I Input Clock. I NCLK is the input clock used to generate the LCLK1 and
LCLK2 outputs, to which all processor functions in the TMS3401 0 are syn-
chronous. A separate input clock, VCLK, controls the video timing registers.
2-7
Pin Functions - Local Memory Interface Signals
Table 2-3. Local Bus Interface Signals (Concluded)
Signal I/O Description
LCLK1,LCLK2 0 Local Output Clocks. These two output clocks, 90 degrees out of phase with
each other, provide convenient synchronous control of external circuitry to the
TMS34010's internal timing. All clocked signals output from the TMS34010,
with the exception of the CRT timing signals, are synchronous to these clocks.
LRDY I Local Ready. LRDY is driven low by external circuitry to inhibit the
TMS34010 from completing a local memory cycle it has initiated. While LRDY
remains low, the TMS34010 continues to wait. When LRDY is again driven
high, the TMS3401 0 completes the cycle. While LRDY is low, the TMS3401 0
generates internal wait states in increments of one full LCLK1 cycle in duration.
LRDY can be driven low to extend local memory read and write cycles, shift-
register-transfer cycles, and DRAM refresh cycles. During internal cycles, the
TMS34010 ignores LRDY.
"[ff\ff1,iJNi2 I Local Interrupt Request Pins. Interrupt requests from external devices are
transmitted to the TMS3401 0 on the 1:TN'F1 and LlNT2 pins. Each pin activates
the request for one of two external interrupt request levels. An external device
generates an interrupt request by driving the appropriate interrupt request pin
to its active-low state. The pin should remain active low until the TMS34010
has recognized the request.
Transitions on the two interrupt request pins are assumed to be asynchronous
with respect to local clocks LCLK1 and LCLK2; the signals on these pins are
synchronized internally before being used internally.
LADo-LAD15 I/O Local Address/Data Bus. LADo-LAD15 form the local multiplexed
address/data bus. At the start of a memory cycle, two addresses (row and col-
umn) are output on LADo-LAD15. During a read cycle, data are input on
LADo-LAD15 during the latter part of the cycle. During a write cycle, data are
output on LADo-LAD15 during the latter part of the cycle. LADO is the LSB,
and LAD15 is the MSB. During the time the row address is output on
LADo-LAD14, status bit RF is output on LAD15. RF is active low at the start
of a DRAM-refresh cycle (either 'liAS-only or CAS-before-RAS"). During the time
that the column address is output on LADo-LAD13, status bits TR and lAO are
output on LAD15 and LAD14, respectively. lAO is active high during a read
cycle in which the TMS3401 0 fetches an instruction word from the local me-
mory. During all other cycles, lAO is inactive low. TR is active low during
shift-register-transfer cycles. (The level output on LAD14 during the high-
to-low transition of CAS is always the same as the level output on TR/GE during
the high-to-Iow transition of'R'AS.)
Notes: 1) The system designer must ensure that LRDY is not held low for so long that the TMS3401 0
is prevented from performing the necessary number of DRAM refresh cycles or is prevented
from refreshing the display by performing a VRAM memory-to-shift-register cycle during
horizontal retrace.
2) The operation of LlNT1 and LlNT2 is affected by the RUN/EMU pin. Make sure this pin is in
the proper state.
2-8
Pin Functions - Video Timing Signals
2.4 Video Timing Signals
The video timing signals (BLANK, HSYNC, and VSYNC) control the horizontal
and vertical sweep rates of the video monitor. They also synchronize the dis-
play on the monitor to video data that is output from the VRAMs. Section 9
discusses video timing and screen refresh operations.
Table 2-4. Video Timing Signals
Signal I/O Description
~ I/O Horizontal Sync. 'RSY"NC is the horizontal sync Signal used to control external
video circuitry. It is programmed as either an input or an output by means of
two control bits in the DPYCTL register. When configured as an output, the
active-low horizontal sync signal is generated by the TMS3401 O's on-chip vi-
deo timers. When configured as an input, the TMS3401 0 synchronizes its video
timers to externally-generated horizontal sync pulses. Immediately following
reset, ~ is configured as an input.
\7'SVNC I/O Vertical Sync. \7'SVNC is the vertical sync signal used to control external video
circuitry. It is programmed as either an input or an output by means of a control
bit in the DPYCTL register. When configured as an output, the active-low ver-
tical sync signal is generated by the TMS3401 O's on-chip video timers. When
configured as an input, the TMS34010 synchronizes its video timers to exter-
nally-generated vertical sync pulses. Immediately following reset, VSYNC is
configured as an input.
BLANK 0 Blanking. BLANK is a composite blanking signal used to turn off the electron
beam of a CRT during both horizontal and vertical retrace intervals. This signal
may also be used to control the starting and stopping of the VRAM shift regis-
ters.
VCLK I Video Clock. VCLK is derived from the dot clock of the external video system
and is used internally to drive the TMS3401 O's video timing logic. The signals
output at the BLANK, ~, and VSYNC pins are synchronous to VCLK. VCLK
is not required to have any timing relationship with respect to I NCLK; that is,
VCLK and I NCLK can be asynchronous. In order to read HCOUNT and
VCOUNT registers reliably, VCLK should be held high during the read. In sys-
tems which do not use the video timing registers or require automatic screen
refreshing, VCLK can be strapped high.
Note: The operation of HSYNC and - -- - - pin. Make sure this pin is in the
VSYNC is affected by the RUN/EMU
proper state.
2-9
Pin Functions - Hold and Emulator Interface Signals
2.5 Hold and Emulator Interface Signals
The TMS3401 0 hold interface permits other devices to request and be granted
control of the local interface bus.
The emulator interface is used to control the TMS34010 when it is used for
emulation. The RUN/EMU pin may remain unconnected in nonemulation ap-
plications.
Table 2-5. Hold and Emulator Interface Signals
Signal I/O Description
I Hold Request. The HOLD pin is driven active low by an external device to
signal a request that the TMS3401 0 release ownership of the local memory bus.
Once the TMS3401 0 has acknowledged the hold request via a hold acknowl-
edge signal, the external device assumes ownership of the bus. The device must
continue to assert its hold request until it has released the bus.
o Hold Acknowledge and Emulate Acknowledge. The HLDA/E1iii'OA pin is
multiplexed between two functions: (1) acknowledgment of hold requests and
(2) acknowledgment of emulation requests.
The hold acknowledge signal (FITI5A) is output during phases 03 and 04 of the
local clock cycle. The emulate acknowledge signal (rnoA) is output during
phases 01 and 02. HLDA is driven active low in response to a hold request from
an external device. but not until the TMS3401 0 has released the bus to the re-
questing device. The device must delay taking possession of the bus until it
has received an active HLDA signal. Once an active-low hold acknowledge
signal has been transmitted during 03-04. it will continue to be transmitted
during 03-04 of each local clock period until the external device ceases to as-
sert its hold request.
EMUA is driven active low to indicate to external circuitry that the TMS34010
has halted in response to an EMU command input on the RUN/EMU pin.
HLDA/EMUA is also driven low when an EMU opcode is executed by the
TMS34010. but only during phases 01 and 02 of a single LCLK1 cycle. Exe-
cution of an EMU opcode causes an active-low signal to be output at the
HLDA/EMUA pin during phases 01 and 02. so external devices that generate
hold requests should avoid interpreting these signals as hold acknowledgment.
RUN/EMU Run/Emulate. This pin is defined as a no-connect during normal system op-
eration. The RUN/EMU pin should not be pulled low except during factor
testing or chip emulation. An internal pull-up load permits RUN/EMU to remain
unconnected during normal use.
If RUN/EMU is pulled low. RESET. LlNT1. LlNT2. 'R"'S'Y"NC. and \lS'YNC are recon-
figured to perform special functions used only during emulation and factory
testing.
2-10
Pin Functions - Power, Ground, and Reset Signals
2.6 Power, Ground, and Reset Signals
Six TMS34010 pins are dedicated to ground and power supply. Section 8
provides more details about RESET.
Table 2-6. Power, Ground, and Reset Signals
Signal I/O Description
Vee I Vee (2 pins). Two +5-volt power supply inputs.
VSS I VSS (4 pins). Four electrical ground inputs.
RESET I Reset. RESET is pulled low to reset the device during normal operation.
While RESET is asserted low, the internal registers of the TMS3401 0 are set
to an initial known state, and all output and bidirectional pins are driven ei-
ther to inactive levels or to high impedance. The behavior of the TMS3401 0
chip following reset depends on the level of the HCS input just prior to the
low-to-high transition of RESET. If HCS is low, the TMS3401 0 begins exe-
cuting the instructions pointed to by the reset vector. If HCS is high, the
TMS34010 is halted until a host processor writes a 0 to the H LT bit in the
HSTCTL register.
Transitions on the RES"ET pin are assumed to be asynchronous with respect
to local clocks LCLK1 and LCLK2; the signal input on this pin is synchro-
nized internally before it is used internally.
2-11
Pin Functions
2-12
Section 3
Memory Organization
This section presents details of physical and logical addresses, illustrates the
TMS34010 memory map, and describes stack operation.
Section Page
3.1 Memory Addressing .................................................................................. 3-2
3.2 Memory Map .............................................................................................. 3-4
3.3 Stacks .......................................................................................................... 3-6
3-1
Memory Organization - Memory Addressing
3.1 Memory Addressing
The TMS3401 0 is a bit-addressable machine with a 32-bit internal memory
address. The total memory capacity is four gigabits (or 512 megabytes); the
TMS34010 supports external addressing of 128 megabytes.
Memory is accessed as a continuously addressable string of bits. Each 32-bit
address points to an individual bit within memory. Groups of adjacent bits
form data structures called fields. A field is specified by its starting bit ad-
dress and its length. The TMS3401 0 supports field lengths from 1 to 32 bits.
Bit addresses range from OOOOOOOOh to OFFFFFFFFh.
Figure 3-1 illustrates the logical memory structure.
32-B1t
Logical Addreas
N
Figure 3-1. Logical Memory Address Space
Figure 3-2 illustrates physical memory organization. The TMS34010 com-
municates with memory over a 16-bit data bus, and always reads or writes a
complete 16-bit word from or to memory. A word accessed during a memory
cycle always begins on an even 16-bit boundary; thus, the four LSBs of the
32-bit starting address of the word are Os. Bits within a word are numbered
from 0 to 15; bit 15 is the MSB and bit 0 is the LSB. A word is identified by
the address of its LSB. In this document, the LSB of a memory word is de-
picted as the rightmost bit in the word.
3-2
Memory Organization - Memory Addressing
32-B1t Logical Addre88
2 ~
MSBs J 26-BIt J LSBs r
"I' Phyaloal Addreaa T
31 30129 N ~13 0
~
~
Externally
I Select BIt Boundary
WIthin Word
!
Memory /1 Word N+1 I Word N I Word N-1 l/
15 14 13 12 11 10 Q Q 7 e 5 j; 3 2 1
I I I I I I I I I I I I I I I I I
f
T
MSB LSB
Figure 3-2. Physical Memory Addressing
The four LSBs of the 32-bit logical address in Figure 3-2 do not appear on the
local memory bus. When the TMS3401 0 extracts a data structure that does
not begin and end on even word boundaries, these four LSBs are used inter-
nally to indicate a bit boundary within an accessed word. Control logic at the
local memory interface automatically performs the bit alignment and masking
necessary to extract a data structure from physical memory; this is completely
transparent to software. If the data structure being extracted straddles word
boundaries, multiple read cycles are required. Similarly, inserting a data
structure into memory may require a series of read and write cycles, accom-
panied by the internal masking and shifting of data to properly align the data
structure within memory. The memory-control logic performs these tasks au-
tomatically.
The two MSBs of the 32-bit logical address are not output. The TMS3401 0
supports an external address range of 128 megabytes of physical memory.
3-3
Memory Organization - Memory Map
3.2 Memory Map
Figure 3-3 illustrates the TMS34010 memory map. Memory is logically or-
ganized as four gigabits, but is physically accessed 16 bits at a time. Locations
are shown as 16-bit words, identified by 32-bit addresses whose four LSBs
are Os. Word addresses range from OOOOOOOOh to FFFFFFFOh (bit address
OOOOOOOOh is the rightmost bit in the word at the bottom of Figure 3-3, and
bit address FFFFFFFFh is the leftmost bit in the word at the top.) Reading
or writing to an address in the range COOOOOOOh to C00001 FOh accesses an
internal I/O register. Reading or writing to any address outside this range
accesses off-chip memory (or a memory-mapped device) external to the
TMS34010.
Address
FFFF FFFO
FFFF FCOO
FFFF FBFO P"I,-+..,..,...,.....,....,....,...,.....,.~,-t
FFFF EOOO
FFFF DFFO I"-"'-+-~""'""'--'-"--"""t
C0002000
COOO 1 FFO ~..-+..,....,...,.....,..,...,.....,.....,....,...,....
COOO0200
COOO 01 FO 1-"-"-4'--""""-"","",--~"'-'~
COOO 0000 1---+---------10..--1
BFFF FFFO
3 X 2 26 words
0000 0000 ~.....&.._ _ _ _ _ _............
Bit 0
l---16 bits~ (first bit in memory)
Figure 3-3. TMS34010 Memory Map
As Figure 3-3 shows, memory is divided into several regions:
• General use
Addresses ranges Oh-BFFFFFFOh and C0002000h-FFFFDFFOh are for
general use (executable code, data tables, etc.).
• I/O registers
Addresses COOOOOOOh-COOOO1 FOh are reserved for the 16-bit I/O reg-
isters. Section 6 discusses the I/O registers; it contains a map of this
3-4
Memory Organization - Memory Map
memory area which associates each I/O register with the appropriate
address.
• Interrupt, Reset, and Trap Vectors
Addresses FFFFFCOOh-FFFFFFEOh are reserved for 32 interrupt, reset,
and trap vectors. A vector is a 32-bit address that points to the starting
location in memory of the appropriate interrupt, reset, or trap service
routine. Each address is stored in physical memory as two consecutive
16-bit words, with the 16 LSBs at the lower address. Section 8 contains
more information about interrupts and traps.
• Reserved memory
Addresses C0000200h-C0001 FFOh are reserved for future expansion of
the I/O registers.
Addresses FFFFEOOOh-FFFFFBFOh are reserved for future expansion of
the interrupt vectors.
3-5
Memory Organization - Stacks
3.3 Stacks
The TMS3401 O's system stack is implemented in local memory and managed
in hardware. The stack is used to store return addresses and processor status
information during interrupts, traps, and subroutine calls. The contents of
general-purpose registers can be pushed onto the stack and popped off the
stack. The system stack can also be used for dynamically allocated data stor-
age.
The stack is accessed through a dedicated 32-bit internal register, called the
stack pointer, or SP. The SP points to the top of the system stack; it can be
accessed as register 15 in either register file.
In addition to the system stack, you can define your own auxiliary stacks. The
system stack always grows toward lower memory addresses; an auxiliary stack
can be defined to grow toward either lower or higher addresses. The MOVE
and MOVB instructions, combined with the automatic predecrement and
postincrement addressing modes, facilitate pushing and popping auxiliary
stack data. One or more registers in the A or B files can be used by software
as auxiliary stack pointers and frame pointers. The indexed addressing modes
can be used in conjunction with a frame pointer to access variables embedded
within the stack.
3.3.1 System Stack
Figure 3-4 shows the structure of the system stack, which grows in the di-
rection of lower memory addresses.
The SP points to the top of the stack; it contains the 32-bit address of the LSB
(bit 0) of the value on top of the stack. The SP can contain any 32-bit ad-
dress; however, stack operations execute more efficiently when the four LSBs
of the SP are Os. This aligns the SP to word boundaries in memory, reducing
the number of memory cycles necessary to push values onto the stack or pop
values off the stack.
Any instruction that manipulates general-purpose registers (Ao-A14 or
Bo-B14) can also be used to manipulate the SP. The SP can be specified as
the source or destination operand in any instruction that operates on the
general-purpose registers. Instructions that manipulate the SP include:
Instructions that Push Instructions that Pop
Values on the Stack Values from the Stack
MMTM SP, register list M M FM S P, register list
CALL Rs RETI
CALLA absolute address RETS
CALLR relative address POPST
TRAP number MOVE *SP+, Rd
PUSHST
MOVE Rs, -*SP
3-6
Memory Organization - Stacks
Memory
,,---..1"'---'""1,
~16~
Highest Address
Stack Bottom
System
Stack
Area
}
SP
Lowest Address
Figure 3-4. System Stack
3.3.1.1 Saving Registers on the System Stack
Register information can be stored on the stack during an interrupt or a sub-
routine call. This frees up the register for use by an interrupt routine or a su-
broutine, and allows you to restore the original register values from the stack
when the routine finishes executing.
During an interrupt, the contents of the PC and ST are automatically saved
on the stack; if you want to save values that are in general-purpose registers,
you can use the MMTM and MMFM instructions. MMTM pushes multiple
general-purpose registers onto the stack, and MMFM pops multiple gener-
al-purpose registers from the stack.
When the contents of a 32-bit register are pushed onto the stack, they are
stored in two consecutive 16-bit words. The 16 MSBs are stored at the higher
memory address, and the 16 LSBs are stored at the lower address. This is
shown in Figure 3-5, which demonstrates the effects of the following in-
struction sequence:
MMTM SP, AO Push register AO onto stack
MMFM SP, Al Pop stack into register Al
3-7
Memory Organization - Stacks
• Figure 3-5 a shows the original state of the stack and registers.
• Figure 3-5 b illustrates the state after AO is pushed onto the stack.
• Figure 3-5 c shows the result of popping the top of the stack into A1.
(a)
................
................
Stack Bottom ................
................
................
................
Stack
--OFE2h-- N
...................
SP N
: .. : ....:::::::::.
................
................
Lowest Address .:::::::::: ........ :.
................................. 0
Memory
~
(b)
1'--16---1
................
................
AO
A11-~~~-i
................
................
................
................
Stack Bottom
Stack
--oFr~-- N
--O'i23h-- N-16
.:.:.~~~::. N-32
................
(c)
................
................
Stack Bottom ................
0°:::::::::::::::
................
................
Stack
SP '--__N"--~ --OFEih-- N
,,"11""'""'"
, •• , •• " , , " , • • 11
................
""""","1'"
"","111"'"1"
• f",""" ••• , ••••
Lowest Address --~--_...'.;..'.;.'.....'_''_'_"_"_'"","
Figure 3-5. Stack Operations
The TMS3401 0 performs two steps to push the contents of a 32-bit register
onto the top of the stack:
1) Decrement the PC by 32.
2) Push the register contents onto the stack.
The TMS3401 0 performs two steps to pop the top of stack into a 32-bit reg-
ister:
1) Pop the 32 bits at the top of the stack into the register,
2) Increment the SP by 32.
3-8
Memory Organization - Stacks
3.3.1.2 Saving Information On the System Stack During an Interrupt
During an interrupt, the TMS3401 0 pushes the PC and ST onto the stack; this
allows the interrupted routine to resume execution when the interrupt proc-
essing is completed. An interrupt routine performs the following actions:
1) Decrement the SP by 32.
2) Push the PC onto the stack.
3) Decrement the SP again by 32.
4) Push the ST onto the stack.
During a return from an interrupt:
1) Pop the 32 bits at the top of the stack into the ST.
2) Increment the SP by 32.
3) Pop the 32 bits at the top of the stack into the PC.
4) Increment the SP again by 32.
3.3.1.3 Saving Information On the System Stack During a Subroutine Call
A subroutine call saves the state of the calling routine on the stack; this allows
the routine to resume execution when the subroutine completes. A subroutine
call performs the following actions:
1) Decrement the SP by 32.
2) Push the PC onto the stack.
During a return from a subroutine:
1) Pop the 32 bits at the top of the stack into the PC.
2) Increment the SP by 32.
3.3.2 Auxiliary Stacks
Auxiliary stacks can be managed in software. Any A- or B-file register, except
the SP, can be used as the auxiliary stack pointer. Auxiliary stacks are typically
used to contain dynamically allocated data storage.
In the following discussion, STK represents the auxiliary stack pointer. STK
is a symbol that must be equated to one of the general-purpose registers; for
example:
STK .set AO
The STK may contain any 32-bit value; however, stack operations execute
more efficiently when the four LSBs of the STK are Os. This aligns the STK
to word boundaries in memory, reducing the number of memory cycles nec-
essary to push values onto the stack or pop values off the stack.
As Figure 3-6 and Figure 3-7 show, the auxiliary stack can be configured to
grow in either direction in memory. The memory is shown in these figures as
a string of continuously addressable bits.
3-9
Memory Organization - Stacks
3.3.2.1 An Auxiliary Stack that Grows Toward Lower Addresses
Figure 3-6 shows a stack that grows toward lower memory addresses:
• Figure 3-6 a shows the original stack.
• In Figure 3-6 b, a field of arbitrary size is pushed onto the stack with this
instruction:
MOVE Rs, * -STK
(Rs and STK represent general-purpose registers.)
• In Figure 3-6 c, the field is popped off the stack with this instruction:
MOVE *STK-, Rd
(Rd and STK represent general-purpose registers.)
Between instructions, the STK always points to the lowest bit address in the
stack - th is corresponds to the very top of the stack. You can use the M MTM
STK,register list instruction to save mUltiple registers on the stack in Figure
3-6. Later, you can restore the registers to their former values with an
MMFM STK,register list instruction.
stack
, A ,
(a)
+-HIQh Low
s
Addreaa Addreaa-+
ST!(
(b) Field i s
T
ST!(
Staok
A
(0)
s
t
ST!(
Figure 3-6. An Auxiliary Stack that Grows Toward Lower
Addresses
3-10
Memory Organization - Stacks
3.3.2.2 An Auxiliary Stack that Grows Toward Higher Addresses
Figure 3-7 shows a stack that grows toward higher memory addresses:
• Figure 3-7 a shows the original stack.
• In Figure 3-7 b, a field of arbitrary size is pushed onto the stack using
the following instruction:
MOVE Rs, * STK+
• In Figure 3-7 c, the field is popped off the stack with this instruction:
MOVE * -STK, Rd
Between instructions, the STK always points to one plus the highest bit ad-
dress in the stack - this location is one bit beyond the very top of the stack.
Staok
A
I ,
(a) sHigh
+- Addresses T Addr~: ---+
STK
(b) s Reid
T
STK
Stack
A
(0) s
t
STK
Figure 3-7. An Auxiliary Stack that Grows Toward Higher
Addresses
3-11
Memory Organization
3-12
Section 4
Hardware-Supported Data Structures
The TMS3401 0 supports several data structures at the machine level:
• Fields are configurable data structures whose length can be defined
within the range 1 to 32 bits. Two field sizes can be defined simul-
taneously. A field can begin and end at arbitrary bit addresses.
• Bytes are a special case of field in which the field length is fixed at eight
bits and is sign extended. Bytes can begin on any bit boundary within
a word.
• Pixels are configurable data structures; pixel length can be programmed
to be 1, 2, 4, 8, or 16 bits (always a power of two). Pixels are aligned
so that they do not cross word boundaries in memory.
• Two-dimensional pixel arrays, or pixel blocks, are rectangular groups
of pixels that are manipulated using the PIXBLT (pixel block transfer)
and FILL (pixel block fill) instructions. A pixel array can be moved from
one area of memory to another in a single PixBlt operation. It can be
combined with another array of the same size by performing Boolean or
arithmetic operations on the corresponding pixels of the two arrays.
The number of bits in a pixel, field, or array is programmable, but byte length
is fixed. Two field sizes and one pixel size can be specified simultaneously.
The size and starting addresses of the pixel arrays that are manipulated during
a PixBlt operation are specified by the values loaded into dedicated hardware
registers.
Topics in this section include:
Section Page
4.1 Fields ........................................................................................................... 4-2
4.2 Pixels ........................................................................................................... 4-6
4.3 XY Addressing ......................................................................................... 4-11
4.4 Pixel Arrays ............................................................................................... 4-15
4-1
Hardware-Supported Data Structures - Fields
4.1 Fields
The TMS3401 0 supports two software-configurable field types, field 0 and
field 1. A field in memory is defined by two parameters:
• Starting address and
• Field size (1 to 32 bits)
A field's starting address is the address of the field's LSB. A field can begin
at an arbitrary bit address in memory. When a field is moved from memory to
a general-purpose register, the field is right justified within the register; that
is, the field's LSB coincides with the register's rightmost bit (bit 0). The reg-
ister bits to the left of the field are all 1 s or all Os, depending on the values of
both the appropriate FE (field extension) bit in the status register, and the sign
bit (MSB) of the field. If FE=1, the field is sign extended; if FE=O, the field
is zero extended.
Field size can range from 1 to 32 bits. The lengths of fields 0 and 1 are defined
by two 5-bit fields in the status register, FSO and FS1.
Figure 4-1 illustrates a field in memory. In this example, the field straddles the
boundary between words Nand N+ 1 in memory. Field extraction and in-
sertion is performed by on -chip hardware:
• To move the field to a general-purpose register, the TMS3401 0 extracts
the field from memory by reading word N and word N+ 1 in separate
cycles.
• To move the field from a general-purpose register, the TMS3401 0 inserts
the field into memory by reading and writing word N, and reading and
writing word N+ 1.
The memory operations necessary to insert or extract a field are performed
automatically by special hardware, and are transparent to software.
I f - - - - - - - - - 32-B1t Logical Address ------~
28-B1t
Physloal Address
Memory
L
r-- Slze----'.1
Reid
Figure 4-1. Field Storage in External Memory
4-2
Hardware-Supported Data Structures - Fields
In Figure 4-1, word N is pointed to by a 26-bit physical address output by the
TMS34010 to memory. This 26-bit address corresponds to bits 4-29 of the
field's 32-bit logical address. The four LSBs of the logical address point to the
beginning of the field within word N.
The number of memory cycles required to extract or insert a field depends on
how the field is aligned in memory. Field manipulation is more rapid when
fields are stored in memory so that they do not cross word boundaries. Figure
4-2 illustrates various cases of alignment and nonalignment of fields to word
boundaries in memory. Given a field starting address and field length, the
memory controller will recognize the specified field alignment as one of the
seven cases in Figure 4-2. Field extraction and field insertion are performed
in a manner that requires the minimum number of memory cycles.
Case A
CaseB
CaseC , Word N+1 I Word N
~,
- 32-BIt Reid
Case 0 [±i N+1 ;r;:;zord N
Reid
Case E Word N+i:=[ wor!:![;j
Reid
Case F Word N+1 I Word N
it===- Reid ::::::::::;j
Case G Word N+2 Word N+1 Word N
k Reid ~I
Figure 4-2. Field Alignment in Memory
Case A A 16-bit field is aligned on word boundaries. Field extraction requires a single
read cycle, and field insertion requires a single write cycle.
Cases
81-83 The field length is less than 1 6 bits.
• In Case 81, the field starting address is not aligned to a word bou ndary,
although the end of the field coincides with the end of the word.
• In Case 82, the field starting address is aligned to a word boundary, but
the end of the field does not coincide with the end of the word.
• In Case 83, the field length is 14 bits or less, and neither the start nor the
end of the field is aligned to a word boundary.
4-3
Hardware-Supported Data Structures - Fields
For Cases 81-83, a field extraction requires a single read cycle. A field in-
sertion requires the following sequence of memory cycles:
1) Read word N
2) Write word N
Case C A 32-bit field is aligned on word boundaries. A field extraction requires the
following sequence of memory cycles:
1) Read word N
2) Read word N+ 1
A field insertion requires the following sequence of memory cycles:
1 ) Write word N
2) Write word N+ 1
Case 0 The field size is greater than 16 bits. The field starting address is not aligned
to a word boundary, but the end of the field coincides with the end of the
word. A field extraction requires the following sequence of memory cycles:
1) Read word N
2) Read word N+ 1
A field insertion requires the following sequence of memory cycles:
1) Read word N
2) Write word N
3) Write word N+ 1
Case E The field size is greater than 16 bits. The field starting address is aligned to a
word boundary, but the end of the field does not coincide with the end of the
word. A field extraction requires the following sequence of memory cycles:
1) Read word N
2) Read word N+ 1
A field insertion requires the following sequence of memory cycles:
1 ) Write word N
2) Read word. N+ 1
3) Write word N+ 1
Case F The field straddles the boundary between two words. Neither the start nor the
end of the field is aligned to a word boundary. A field extraction requires the
following sequence of memory cycles:
1) Read word N
2) Read word N+ 1
A field insertion requires the following sequence of memory cycles:
1) Read word N
2) Write word N
3) Read word N+ 1
4) Write word N+ 1
Case G The field size ranges from 18 to 32 bits, and the field straddles two word
boundaries. Neither the start nor the end of the field is aligned to a word
boundary. A field extraction requires the following sequence of memory cy-
cles:
1) Read word N
2) Read word N+ 1
3) Read word N+2
4-4
Hardware-Supported Data Structures - Fields
A field insertion requires the following sequence of memory cycles:
1) Read word N
2) Write word N
3) Write word N+ 1
4) Read word N+2
5) Write word N+2
A field insertion modifies only the portion of a word that lies within a field.
The TMS34010 memory controller must perform a read-modify-write opera-
tion when a field that does not begin and end on even 16-bit word boundaries
is to be written to memory. This occurs when the four LSBs of the address
are not 0, or when the specified field size is a value other than 16 or 32. The
memory controller uses these two parameters (address LSBs and field size) to
produce a mask that identifies the bits in the word corresponding to the field.
Hardware uses the mask to perform the read-modify-write cycle. The
TMS34010's local memory control logic automatically generates the mask and
executes the read-modify-write operation; this is transparent to software.
Figure 4-3 shows an example of inserting a 5-bit field stored in a register to
logical address OOOOOOOBh.
• In Figure 4-3 a, the field to be inserted is shown right-justified in the
16 LSBs of the designated general-purpose register.
• In b, memory controller hardware has rotated the field to align it with the
destination in memory.
• In c, the TMS3401 0 reads the original word from the destination in me-
mory.
• In d, the mask is generated to designate the bits to be modified.
• In e, the field is inserted into the word from memory, and the result is
written back to the destination address in memory.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
(a) Field to be Inserted X X X X X X X X X X X F F F F F
(b) Rotate to align to bit 8 X X X F F F F F X X X X X X X X
(0) Initial destination data A A A A A A A A A A A A A A A A
(d) Mask generated 0 0 0 0 0 0 0 0 0 0 0
(e) Final destination data A A A F F F F F A A A A A A A A
Figure 4-3. Field Insertion
In the more complex case in which a field straddles one or two word bound-
aries in memory, the portion of the field lying within each word is inserted into
that word using the methods described above.
4-5
Hardware-Supported Data Structures - Pixels
4.2 Pixels
The term pixel has two meanings in the context of a TMS34010-based
graphics system. Outside the TMS34010, a pixel is a picture element on a
display surface. Inside the TMS34010, a logical pixel is a software-
configurable data structure supported by the TMS3401 0 instruction set. The
logical pixel data structure in TMS34010 memory contains the information
needed to specify the attributes of a picture element visible on a screen. The
information for a horizontal line of pixels on the screen is usually stored in
consecutive words in memory.
4.2.1 Pixels in Memory
Within TMS3401 0 memory, the pixel data structure is defined by two param-
eters:
• Starting address and
• Pixel size
A pixel's starting address is the address of the LSB of the pixel.
Pixel size (the number of bits per pixel) is defined in the PSIZE register. A
pixel can be 1, 2, 4, 8, or 16 bits long. The TMS3401 0 treats pixels as a spe-
cial case of a field in which the field size is constrained to be a power of two.
However, pixels do not cross word boundaries within memory; they are
aligned within memory so that an integral number of pixels is contained within
the boundaries of a memory word. For example, a 2-bit pixel should begin at
an even bit address whose LSB is 0, a 4-bit pixel should begin at a bit address
whose two LSBs are Os, and so forth.
When a pixel is moved from memory to a general-purpose register, the pixel
is right justified within the register. That is, the LSB of the pixel coincides
with the rightmost bit (bit 0) of the register. Register bits to the left of the
pixel are loaded with Os.
Figure 4-4 illustrates pixel storage in memory. The pixel is located within the
word pointed to by the 26-bit physical address corresponding to bits 4-29 of
the 32-bit logical address of the pixel. The four LSBs of the logical address
specify the displacement of the pixel within the word. When the pixel length
is less than 16, each word contains two or more pixels.
Pixel extraction and insertion is performed by on-chip hardware in a manner
that requires the minimum number of memory cycles. (The operations are
transparent to the programmer.) In the worst case, two memory cycles (a read
followed by a write) are required to insert a pixel of less than 16 bits. Inserting
a 16-bit pixel requires a single write cycle, and extracting a pixel (1 to 16 bits)
requires a single read cycle.
4-6
Hardware-Supported Data Structures - Pixels
It--------- 32-BIt Logical Address -------~
2
MSBs 28-BIt
Physical Address
Memory
Pixel Size
~---Word -----.,~I
Figure 4-4. Pixel Storage in External Memory
4.2.2 Pixels on the Screen
Figure 4-5 illustrates the mapping of pixels from memory to a display screen.
The screen refresh function outputs pixels in the sequence of ascending pixel
addresses. However, the electron beam sweeps from the left edge of the
screen to the right edge during each horizontal scan interval, so pixels appear
on the screen in the opposite order of their representation in memory. That is,
the least significant pixel (in terms of bit address) appears on the left, and the
most significant pixel appears on the right.
Video Monitor Screen
Word Word Word
N-1 N N+1
i====r:f==i
L
r--
'--
I IPixel Pixel Pixel PixelI I
I I I I I I I I I
Memory I I I I I I I I I
I I I I I I I I I
4N+34N+2 4N+1 4N
~wordN+1 ~I. Word N + Word N-1----..j
Figure 4-5. Mapping of Pixels to Monitor Screen
4-7
Hardware-Supported Data Structures - Pixels
The TMS3401 0 allows a pixel to be identified either in terms of its XY coor-
dinates on the screen, or in terms of the address of. the logical pixel in memory.
These two methods are called XV addressing and linear addressing, re-
spectively.
When XY addressing is used, the origin can be selected to lie in either the
upper left or lower left corner of the screen. The position of the origin is
controlled by the ORG bit in the DPYCTL register. Figure 4-6 a illustrates the
default coordinate system (ORG=O), in which the origin of the two coordinate
axes is located in the upper left corner of the screen. Figure 4-6 b shows the
alternate coordinate system (ORG =1) in which the origin is located in the
lower left corner of the screen.
x
(a) Monitor
~Default Soreen
y
Soreen
Origin
I
(b)
y
Alternate
Screen
V Origin
L.-.----+X
Figure 4-6. Configurable Screen Origin
Using the default screen origin, Figure 4-7 illustrates the mapping of pixels
from memory to the screen. In Figure 4-7, horizontal movement represents
travel in the X direction on the screen. Vertical movement represents travel in
the Y direction. The depth of the buffer represents the pixel size. The "on-
screen memory" contains the pixels that appear on the screen.
The display memory shown in Figure 4-7 is shown in terms of a "screen for-
mat" rather than the "memory format" used in the memory map shown in
Figure 3-3 on page 3-4. The screen format places the lowest pixel address
at the upper left corner of the memory map. This is the same relative orien-
tation in which pixels appear on the screen. Compare this to the memory
format shown in Figure 3-3, which places the lowest bit address at the lower
right corner of the memory map. This convention is frequently used in in-
dustry to represent the relative location of addresses in memory. In this doc-
ument, assume the standard memory format is used unless the screen format
is indicated.
Figure 4-8 illustrates the mapping of XY coordinates to the on-screen memory.
For simplicity, assume that the screen origin coincides with the upper left
4-8
Hardware-Supported Data Structures - Pixels
corner of the display memory. P represents the X extent of the display memory
and N represents the Y extent. Each box represents a pixel within the memory.
The number within the box represents the pixel's memory location, relative to
the beginning of the on-screen memory. The number in the box is multiplied
by the number of bits per pixel to produce the address offset of the pixel from
the start of the display memory. Since the pixel size is constrained to be a
power of two, the multiply can be replaced by a simple shift operation.
Display Memory
r-------+X I
./
,----------,
, ,
, ,
Y I
,
On-8oreen
Memory
I
,
,I
L. _ _ _ _ _ _ _ _ _ _ ,
,,
Figure 4-7. Display Memory Dimensions
~ Inore,rng
1
Inoreaslng
. x=o
0
X=1
1
X=2
2
X=3
3 I
X=P-2
P-2
X=P-1
P-1
Y Y=O
Y=1 P P+1 P+2 P+3 \ 2P-2 2P-1
Y=2 2P 2P+1 2P+2 2P+3 11 3P-2 3P-1
, Display Memory
=
P X Extent
=
N Y Extent
(N:~)P (N-1}P
-1
l NP-2 NP-1
Each box oontalns a pixel.
The number Inside the box
Is the pixel's XV address.
Display Pitch (X extent) x (pixel size)
Differences in 32-bit memory addresses
of two vertically adjacent pixels
Figure 4-8. Display Memory Coordinates
4-9
Hardware-Supported Data Structures - Pixels
4.2.3 Display Pitch
The term display pitch refers to the difference in memory addresses between
two pixels that appear in vertically adjacent positions (one directly above the
other) on the screen. In Figure 4-8, the pitch is calculated as P times the pixel
size, where P is the X extent of the display memory.
The display pitch must be a power of two in order to support XY addressing
of pixels on the screen. Linear addressing of pixels on the screen imposes
fewer restrictions. In particular, the display pitch for linear addressing may be
any value that is a multiple of 16; that is, the four LSBs of the address must
be Os. Features such as automatic window checking are available with XY
addressing, but are not available with linear addressing.
The pitch of a pixel array is the difference in memory addresses of two verti-
cally adjacent pixels in the array. If the array occupies a rectangular area of the
screen, the array pitch is the same as the display pitch.
During a pixel operation such as a PixBlt, the source and destination array
pitches are specified in separate dedicated hardware registers. This facilitates
the transfer of pixel arrays between on-screen and off-screen memory, which
may have different pitches.
A sample display pitch calculation is shown below. In this example, the pixel
size is four bits and the X extent of the pixel display is 640 pixels. However,
since XY addressing and windowing are to be used, the physical memory is
organized so that there are 1024 pixels between successive scan lines. Thus,
the X extent of physical display memory is 1024, and the display pitch is:
Display Pitch (1024 pixels/line) x (4 bits/pixel)
= 4096 (which is 212)
4-10
Hardware-Supported Data Structures - XV Addressing
4.3 XV Addressing
The TMS34010 allows pixel addresses to be specified in terms of two-
dimensional XY coordinates that correspond to locations on the screen. This
is referred to as XY addressing. XY addressing has several benefits:
• TMS34010 software can be easily ported from one display configuration
to another. System-dependent details such as the number of bits per
pixel and the X extent of the display memory are transparent to the
software, but are used by the machine to automatically convert the XY
coordinates to the address of a pixel in memory.
• XY addressing allows you to think in terms of the high-level concept of
XY coordinates rather than in terms of the machine-level mapping of
pixels into memory.
• XY addressing facilitates such functions as window clipping.
Figure 4-9 illustrates XY addressing format. The XY address is stored in a
32-bit general-purpose register. The X and Y components are each treated
as 16-bit signed integers. The X component resides in the 16 LSBs of the
register, and is right justified to bit 0 of the register. The Y component occu-
pies the 16 MS Bs of the register, and is right justified to bit 16 of the register.
XY coordinates in the range (-32768,-32768) to (+32767,+32767) can be
represented. The clipping window, which identifies the pixels that can be al-
tered during drawing operations, is restricted to positive X and Y coordinate
values, (0,0) to (+32767, +32767). Thus, pixels identified by negative X or
Y coordinates must always lie outside the window.
~ ----.J
j.--S24 18
r-- MSBs
18
LSBs~
I----~~------~--.X
B..ATIVE I
ORIGIN I
'---_.... ______ ...+--PIX8.. AT
(X,V)
y
Figure 4-9. Pixel Addressing in Terms of XV Coordinates
4-11
Hardware-Supported Data Structures - XV Addressing
4.3.1 XV-to-Linear Conversion
The TMS3401 0 automatically converts a pixel's XY address to a 32-bit logical
address (linear address) for all instructions that use XY addressing. Three
parameters are used to perform XY -to-linear conversion:
• The logical pixel size (stored in the PSIZE register)
• A pitch conversion factor (stored in the CONVSP or CONVDP registers)
• An offset defining the XY origin (stored in the OFFSET register)
The TMS3401 0 uses the following formula to calculate the physical address
associated with the XY address:
Address = [(V x display pitch) OR (X x pixel size)] + offset
Since the display pitch and pixel size are both powers of two, the calculation
is performed using only shift, OR, and add operations. Window clipping may
be used to detect out-of-bounds (negative) X or Y values before this calcu-
lation is performed.
Linear addresses are formed from XY addresses by simply concatenating the
binary numbers that represent the X and Y coordinate values, as shown in
Figure 4-10. The number of Os to the right of the X component of the address
depends on the number of bits per pixel, and equals 1092(pixel size). The
displacement of the Y component within the 32-bit logical address in Figure
4-10 is equal to 1092(display pitch). Finally, a 32-bit offset is added to the
address in Figure 4-10 to calculate the address in memory of the pixel at co-
ordinates (X,Y). The offset corresponds to the linear address in memory of the
pixel at (0,0).
o 0 ... 0 o 0 ... 0
y X
MSBs are 08 Component Component LSBs are Os
Note: The shift value for the Y component is contained in
CONVSP or CONVDP register, depending on the in-
struction being executed.
Figure 4-10. Concatenation of XV Coordinates in Address
The TMS34010 uses the pitch conversion factors CONVSP and CONVDP
to compute the displacement of the Y component within the address, as
shown in Figure 4-10. The Y component is displaced from bit 0 of the address
by an amount equal to 1092(pitch), which the hardware obtains by inverting
the five LSBs of the appropriate CONVSP or CONVDP register. These values
must be loaded through software before executing an instruction that uses
XY addressing. CONVSP (source address pitch) is used if the XY address
points to a source pixel or pixel array; CONVDP (destination address pitch) is
used if the XY address points to a destination pixel or pixel array. The pixel
size stored in the PSIZE register is used similarly to determine the displace-
ment of the X component, as shown in Figure 4-10.
4-12
Hardware-Supported Data Structures - XV Addressing
The OFFSET register contains the linear memory address of the pixel located
at coordinates (0,0) on the monitor screen. The OFFSET register is used in
translating XV coordinates into linear addresses, but does not control which
region of the display memory is output to refresh the video screen. It is a vir-
tual screen origin. It allows the coordinate axes of the XV address to be
translated to an arbitrary position in memory. The OFFSET register supports
the use of "window relative" addressing in which the X and V coordinates are
specified relative to coordinate offsets in the display memory. The position
and size of a window can be specified arbitrarily. A new offset specified in
terms of XV coordinates can be converted to a linear address using the CVXVL
instruction. CVXVL converts an XV address to a linear address for the purpose
of absolute memory addressing, or to use special features available to in-
structions that use linear addressing. Figure 4-11 illustrates the XV -to-linear
conversion process.
31 16 15 0
(a) Original XV address
(b) Extract 16 LSBs and
I V 10000001 X
extend with Os 100000000000000000000001 X
(c) Rotate X left by
1092 (pixel size) 100000000000000000000 I X
1
00
(d) Extract 16 MSBs from
original XV address V 10000000000000000
I:~g~ 1
(e) Rotate V left by
16 + 1092 (vertical pitch)
V 1000000000000
(f) Bitwise logical-OR together I I
sign
shifted X and V components of y
V X 00 I I
(g) Add offset from B4 to ~--~----------~------------~--~
displacement above to Memory Address
get final memory address
Figure 4-11. Conversion from XV Coordinates to Memory Address
• Step a shows the original XV address.
• The X component is extracted in step b.
• In step c, the X component is shifted left by 1092(pixel size). The result
of step c represents the product of the X component and the pixel size.
• The Y component is extracted in step d.
• In step e, the V component is rotated left by 16+1092(display pitCh).
The result of step e is V multiplied by the display pitch.
• In step f, the results of steps c and e are bitwise-ORed to form the dis-
placement in memory of the pixel at (X,V) from the pixel at the origin.
• In step G, the offset is added to produce the final memory address.
The example of Figure 4-11 corresponds to a pixel size of four bits and a pitch
of 4,096. The six MSBs of the X half of the XV address (bits 10-15) in Figure
4-11 must be Os to produce a valid memory address. For this example, the
4-13
Hardware-Supported Data Structures - XV Addressing
clipping window should be set to disable writes to pixels having X coordinate
values outside the range 0 to +1023.
Generally, given a display with a pitch of 2n, a valid memory address is pro-
duced by the XY translation process shown in Figure 4-11 when only the n
LSBs of the X half of the XY address are nonzero (that is, when the 16-n
MSBs are 0). X values may be in the range -32768 to +32767 before clip-
ping. However, after clipping, the X value should be a positive number in the
range 0 to (Xextent -1), where Xextent = pitch/pixel size. The TMS34010's
automatic window clipping can be configured to clip pixels lying outside the
window; hence, no software overhead is incurred in clipping. Y values lying
outside the window are clipped in a similar fashion.
4-14
Graphics Operations - Pixel Arrays
4.4 Pixel Arrays
A rectangular area of the screen that is DX pixels wide and DY pixels high is
an example of a data structure called a two-dimensional pixel array. The
array contains DX x DY pixels, but can be manipulated by the TMS3401 0 as
one structure. The TMS34010's instruction set includes a powerful set of
raster operations, called PixBlts, that manipulate pixel arrays on the screen and
elsewhere in memory.
Figure 4-12 shows a pixel array occupying a rectangular region in display
memory. The DX pixels in each row of the array are packed together into ad-
jacent cells in the display memory. Rows do not generally occupy adjacent
areas of memory, but are separated from each other by a constant displace-
ment called the array pitch. The array pitch is the difference in memory ad-
dresses between the start of one row and the start of the row directly beneath
it. In the Figure 4-12 example, the array pitch is equal to the display pitch.
The product of the array width DX and the pixel size must be less than or equal
to the pitch.
Display Memory
r-------+x
Default
starting 2-D1mensionaJ
Address Pixel Array
,
L-.' "
Y
I l:l.Y
1
l:l.X = Pixels per row of array
l:l.Y = Pixels per oolumn of array
Figure 4-12. Pixel Array
A pixel array is specified in terms of its width, height, pitch, and starting ad-
dress. The starting address is the address of the first pixel to be moved during
a PixBlt. The default starting address is simply the base address of the array;
that is, the address of the pixel that has the lowest address in the array.
In Figure 4-12, the XY origin is located in its default position at the upper left
corner of the screen. The default starting address is the address of the pixel
located in the upper left corner of the array. When a PixBlt operation moves
the pixels from a source pixel array to a destination array, the pixels in each
row are moved in sequence from left to right, and the rows are moved in se-
quence from top to bottom.
4-15
Graphics Operations - Pixel Arrays
Certain PixBlt operations allow the starting pixel to be specified as one of the
pixels in the other three corners of the array. This feature is provided so that
when the source and destination arrays overlap, the appropriate starting corner
can be selected to ensure that no data is lost by being overwritten during
PixBlt execution. The order in which pixels in the array are moved can be al-
tered to be from right to left or from bottom to top as appropriate to accom-
modate the change in starting corner.
The starting address of a pixel array can be specified either in terms of the XY
coordinates of the starting pixel (XY address), or the memory address of the
starting pixel (linear address):
• An array whose starting location is specified as an XY address is referred
to as an XY array. In this format, the starting location of the array is
identified by the XY coordinates of the first pixel in the array.
• A pixel array whose starting location is specified as a memory address
is referred to as a linear array. In this format, the location of the array is
identified by the memory address of the first pixel (the pixel that has the
lowest bit address) in the array.
The XY array format has two advantages. First, the starting location of the
array is specified in system-independent Cartesian coordinates rather than as
a system-dependent memory address. Second, the TMS34010's window
checking (which allows it to automatically detect an attempt to write a pixel
inside or outside a specified window) can only be used in conjunction with
XY addressing.
The linear format's main advantage is that the array pitch does not have to be
a power of two. This supports a wider variety of memory organizations. Using
XY format, the array pitch is constrained to be a power of two.
The general rules governing array pitch are as follows. When an array is spe-
cified in XY format, the pitch must be a power of two. The pitch for an array
specified in linear format may be any multiple of 16; that is, the four lSBs of
the pitch must be Os. There are a few important exceptions to the second rule
which are discussed below.
For the special case of a PIXBlT B,XY or PIXBlT B,l instruction, the source
pitch may be any value. This feature supports efficient use of memory by al-
lowing adjacent rows of the source array to be packed together with no in-
tervening gaps. The destination pitch must still be a multiple of 16.
Under certain conditions the linear source array specified for a PIXBlT l,XY
or PIXBlT B,XY must have a pitch that is a power of two. This is necessary
when the linear start address for the array has to be adjusted in the Y direction
due to one of the following conditions:
• The source array is automatically preclipped to lie within a rectangular
window.
• One of the lower two corners of the source array (refer to Figure 4-12)
is sele::;ted to be the start address.
4-16
Graphics Operations - Pixel Arrays
In either case, the start addresses specified for both the source and destination
arrays are automatically adjusted, and for this purpose the conversion factors
specified in the CONVSP and CONVDP registers must be valid.
While PixBlts are useful for moving arrays from one area of the screen to an-
other, they can also be used to move arrays to the screen from other parts of
memory, and vice versa. The pitch for the off-screen pixel array can be spec-
ified independently of the pitch for the on-screen array. This permits off-
screen data to make efficient use of storage, regardless of the display pitch.
On-screen objects may be defined as XV arrays but may be more efficiently
stored as linear arrays in off-screen memory. The PIXBLT instructions support
the transfer of a linear array to an XV array, and vice versa. PIXBLT in-
structions can also be used to rapidly move blocks of non-pixel data (ASCII
characters, for example) from one location in memory to another.
4-17
Hardware-Supported Data Structures
4-18
Section 5
CPU Registers and Instruction Cache
The TMS3401 0 has two on-chip general-purpose register files, file A and file
B. Each register file contains 15 32-bit registers. The two files share a 32-bit
hardware stack pointer (SP) that automatically manages the system stack
during interrupts and subroutine calls. The TMS3401 0 also has two dedicated
32-bit registers - a program counter and a status register. An on-chip cache
holds up to 128 instruction words, and is transparent to software. The CPU
registers and instruction cache are discussed in the following sections:
Section Page
5.1 General-Purpose Registers ....................................................................... 5-2
5.2 Status Register ......................................................................................... 5-18
5.3 Program Counter ..................................................................................... 5-19
5.4 Instruction Cache .................................................................................... 5-20
5.5 Internal Parallelism .................................................................................. 5-25
In addition to the CPU registers, the TMS3401 0 contains 28 memory-mapped
registers that are dedicated to I/O functions; Section 6 discusses the I/O reg-
isters.
5-1
CPU Registers and Instruction Cache - General-Purpose Registers
5.1 General-Purpose Registers
The TMS3401 0 has 30 32-bit general-purpose registers, divided into register
files A and B. In addition, a single stack pointer (SP) is common to both regis-
ter files.
The multiple internal data paths that link the ALU and general-purpose regis-
ters provide single machine state execution of most register-to-register in-
structions. Single-state instructions include add, subtract, Boolean
operations, and shifts (1 to 32 bits). During a single-state instruction, the
following actions occur:
1) Two 32-bit operands are read in parallel from the general-purpose
registers.
2} The ALU performs the specified operation.
3) The 32-bit result is stored in the specified general-purpose register.
The general-purpose registers are dual-ported to permit operands to be read
from two independent registers at the same time.
5.1.1 Register File A
Fifteen of the 30 general-purpose registers, Ao-A14, form register file A.
These registers can be used for data storage and manipulation. No hard-
ware-dedicated functions are associated with these general-purpose registers.
All register-to-register instructions (except MOVE Rs, Rd) require both regis-
ters to be in the same file. Instructions that manipulate registers AO-A14 can
also manipulate the stack pointer. The SP can be specified in place of an A-
file register in any of these instructions. Figure 5-1 illustrates register file A.
MSB LSB
bit 31 bit 0
AO
A1
A2
A3
A4
A5
AS
A7
AS
A9
A10
A1"
A12
A13
A14
SP Stack Pointer
Figure 5-1. Register File A
5-2
CPU Registers and Instruction Cache - General-Purpose Registers
5.1.2 Register File B
Register file B consists of 15 general-purpose registers, BO-B14. All regis-
ter-to-register instructions (except MOVE Rs,Rd) require both registers to be
in the same file. Instructions that manipulate registers Bo-B14 can also ma-
nipulate the stack pointer. The SP can be specified in place of a B-file register
in any of these instructions.
Registers Bo-B14 can be used for general-purpose functions such as data
storage and manipulation. During PixBlt and other pixel operations, however,
these registers are assigned hardware-dedicated functions.
MSB LSB
bit 31 bit 0
BO SADDR Source address
B1 SPTCH Source pitch
B2 DADDR Destination address
B3 DPTCH Destination pitch
B4 OFFSET Offset
B5 WSTART Window start address
B6 WEND Window end address
B7 DYDX Delta Y /Delta X
B8 COLORa Color 0
B9 COLOR1 Color 1
B10 TEMP or COUNT
B11 TEMP or INC1
B12 TEMP or INC2
B13 TEMP or PATTRN
B14 TEMP
SP Stack Pointer
Figure 5-2. Register File B
As Figure 5-2 shows, registers Bo-B9 are used as special-purpose registers
during pixel operations. These registers must be loaded with specific param-
eters before execution of pixel operations. Registers B1 o-B14 are used as
special-purpose registers for the LINE instruction. During pixel operations,
registers B1 0-B14 are used for temporary storage; their previous contents are
destroyed. Register functions may vary for individual instructions.
Section 5.1.4 describes the B-file registers in detail.
5-3
CPU Registers and Instruction Cache - General-Purpose Registers
5.1.3 Stack Pointer
The stack pointer (SP) is a 32-bit register that contains the bit address of the
top of the system stack. The TMS34010 contains only a single SP. However,
this SP can be addressed as a member of either register file, as register A15
or register B15. Any instruction that uses a general-purpose register as an
operand can also use the SP as an operand.
Figure 5-3 illustrates the stack pointer; Section 3.3 (page 3-6) describes stack
operation in detail.
31 43 o
I Word Address I Bit Addr I
~14- - - 28 bits ----t.IiI4- 4 blts-+l
Figure 5-3. Stack Pointer Register
The system stack grows in the direction of smaller addresses. During an in-
terrupt, the PC and ST are pushed onto the stack to permit the interrupted
routine to resume execution when interrupt processing is completed. A sub-
routine call saves the PC on the stack to allow the calling routine to resume
execution when subroutine execution is completed.
The stack pointer always points to the value at the top of the stack. Specif-
ically, the SP contains the 32-bit address of the LSB of that value. While the
four LSBs of the SP may be set to an arbitrary value, stack operations execute
more efficiently when the four LSBs are Os. Setting these bits to Os aligns the
stack pointer to 16-bit word boundaries in memory, reducing to two the
number of memory cycles necessary to push or pop the contents of a 32-bit
register.
The SP can be specified as the source or destination operand in any in-
struction that operates on the general-purpose registers. The SP can be ac-
cessed as register 15 in file A or B. Refer to the descriptions of the specific
instructions for details.
5-4
CPU Registers and Instruction Cache - General-Purpose Registers
5.1.4 Implied Graphics Operands
Table 5-1 summarizes the B-file register functions during graphics operations.
These registers are referred to as implied graphics operands. Several I/O reg-
isters, described in Section 6, are also implied graphics operands.
Table 5-1. B-File Registers Summary
Reg. Function Description
BO SADDR Source Address. Address of the upper left corner of the source pixel array
(lowest pixel address in the array). SADDR is a linear or XY address, depend-
ing on the instruction which uses it.
B1 SPTCH Source Pitch. Difference in linear start addresses between adjacent rows of
a source pixel array.
B2 DADDR Destination Address. Address of the upper left corner of the destination
pixel array (lowest pixel address in the array). DADDR is a linear or XY ad-
dress, depending on the instruction which uses it.
B3 DPTCH Destination Pitch. Difference in linear start addresses between adjacent
rows of a destination pixel array.
B4 OFFSET Offset. Linear bit address corresponding to XV-coordinate origin (X=O, Y=O).
B5 WSTART Window Start Address. XY address of the upper left corner of the window
(smallest X and Y coordinate values in the array).
B6 WEND Window End Address. XY address of the lower right corner of the window
(largest X and Y coordinate values in the array).
B7 DYDX Delta YjDelta X. The 16 LSBs of this register specify the width (X dimen-
sion) of the destination array. The 16 MSBs specify the height (Y dimension)
of the destination array. If either DY = a or DX = 0, then nothing is moved.
B8 COLORa Pixel value corresponding to "color 0". COLORa contains the source
background color to be used during a color-expand operation (PIXBLT B,XY
or PIXBLT B,L). The pixel value should be replicated throughout the 16 LSBs
of register B8 (see note below). Non-replicated patterns may be entered for
dithering effects. The 16 MSBs are ignored during the expand operation. For
example, at four bits per pixel, COLORa contains four identical pixel values,
as shown below.
B9 COLOR1 Pixel value corresponding to "color 1 It. COLOR1 contains the source
foreground color to be used during a color-expand, fill, or draw-and-advance
operation. The pixel value should be replicated throughout the 16 LSBs of
register B9 (see note below). Nonreplicated patterns may be entered for dith-
ering effects. The 16 MSBs are ignored during the expand operation. For ex-
ample, at four bits per pixel, COLOR1 contains four identical pixel values, as
shown below.
B10-814 Pix Bit temporary registers. PixBlt instructions use these registers for
storing temporary values and context information necessary to resume exe-
cution of a partially-completed PixBlt operation in the event of an interrupt.
SP SP Stack pointer. SP contains the bit address of the top of the stack.
Notes: To provide upward compatibility with future versions of the GSP, replicate the pixel value
throughout all 32 bits of COLORa or COLOR1, as shown.
5-5
80 Source Address Register
Format 31 16 15 o
Y x
or
31 o
Linear Bit Address
Description SADDR contains the source array address for PIXBLTs. Generally, SADDR
points to the pixel with the lowest address in the source array. When the
selected starting corner is not the upper left corner, the TMS3401 0 auto-
matically adjusts SADDR to point to the selected starting corner of the
source array. (For PIXBLT L,L, however, you must manually adjust SADDR
to point to the starting corner. This feature allows you to use PIXBLT L,L
for manipulating pixel arrays with pitches that are not powers of two.)
SADDR is in either XY or linear format. If the first operand of a PIXBLT
instruction is an L (such as PIXBLT L,XY), then SADDR is in linear format.
If the first operand of a PIXBLT instruction is an XY (such as PIXBLT XY,L),
then SADDR is in XY format.
During PIXBLT operations, SADDR is used in linear format. When the
PIXBLT is completed, SADDR points to the starting location of the row that
follows the last row in the array. If a PIXBLT is interrupted, SADDR points
to the next word of pixels to be read.
During LINE operation, SADDR contains the current decision variable va-
lue.
The following instructions use SADDR as an implied operand:
Instruction SADDR Format and Function
LINE Contains d=2b-a, used for the line draw.
PIXBLT B,L Linear address; points to the beginning of a binary source
array (a bit map).
PIXBLT B,XY Linear address; points to the beginning of a binary source
array (a bit map).
PIXBLT L,L Linear address with special requirements when PBH = 1
or PBV = 1. Refer to the PIXB LT L,L for a description of
its unique requirements.
PIXBLT L,XY Linear address; points to the beginning of a source array.
PIXBLT XY,L XY address; points to the beginning of a source array.
PIXBLT XY,XY XY address; points to the beginning of a source array.
Example SADDR .set BO
MOVI 00080015h, SADDR Move XY value 15h,8h
into BO
MOVI OOOlOAFCh, SADDR Move linear value
lOAFCh into BO
5-6
Source Pitch Register B1
Format 31 o
Linear Bit Address
Description SPTCH specifies the linear difference in the start addresses of adjacent rows
of the source array for PIXBLT and FILL instructions. The TMS3401 0 uses
the value in SPTCH to move from row to row through the source array.
SPTCH must be an integer multiple of 16 (except for the special cases of
PIXBLT B,L and PIXBLT B,XY). SPTCH is constrained in some cases to
be a power of two; this allows XY addressing and allows SADDR to be
automatically adjusted to point to an alternate starting corner.
The following instructions use SPTCH as an implied operand.
Instruction SPTCH Format and Function
PIXBLT B,L Linear; any value.
PIXBLT B,XY Linear; power of two for windowing, any value otherwise.
PIXBLT L,L Linear; multiple of 16.
PIXBLT L,XY Linear; power of two ~ 16 for windowing or PBV = 1,
multiple of 16 otherwise.
PIXBLT XY,L Linear; power of two ~ 16.
PIXBLT XY,XY Linear; power of two ~ 16.
Example SPTCH .set Bl
MOVI OOOOlOOOh, SPTCH Power of two for
PIXBLT XY,L
MOVI OOOlOAFCh, SPTCH Any value for
PIXBLT B,L
5-7
82 Destination Address Register
Format 31 16 15 o
Y x
or
31 o
Linear Bit Address
Description DADDR contains the destination array address for PIXBLTs. Generally,
DADDR points to the pixel with the lowest address in the destination array.
When the selected starting corner is not the upper left corner, the
TMS34010 automatically adjusts DADDR to point to the selected starting
corner of the destination array. (For PIXBLT L,L, however, you must man-
ually adjust DADDR to point to the starting corner. This feature allows you
to use PIXBLT L,L for manipulating pixel arrays with pitches that are not
powers of two.)
DADDR is also used in conjunction with DYDX to perform a common rec-
tangle function for some instructions (FILL XV, PIXBLT B,XY, PIXBLT
L,XY, and PIXBLT XY,XY, with window option 1). In these cases, DADDR
is set to the starting XY address of the common rectangle that represents
the intersection of the original destination array and the clipping window
indicated by WSTART and WEN D. No drawing is performed. If the array
and the window do not intersect, the V bit is not set and the contents of
DADDR are undefined.
DADDR is in either XY or linear format. If the second operand of the
PIXBLT instruction is an L (such as PIXBLT XY,L), then DADDR is in linear
format. If the second operand of the PIXBLT instruction is an XY (such as
PIXBLT XY,XY), then DADDR is in XY format.
If DADDR is specified in XY format, the PIXBLT converts it to the corre-
sponding linear address prior to the start of the pixel array transfer. During
PIXBLT operation, DADDR is maintained in linear format. When the
PIXBLT completes, DADDR points to the linear starting address of the row
following the last row in the array. If a PIXBLT is interrupted, DADDR
points to the next word of pixels to be read.
For the LINE instruction, DADDR contains the XY address of the next point
on the line.
The following instructions use DADDR as an implied operand.
Instruction DADDR Format and Function
FILL L Linear; points to the beginning of the destination array.
FILL XY XV; points to the beginning of the destination array.
LINE XV; points to the current pixel.
PIXBLT B,L Linear; points to the beginning of the destination array.
PIXBLT B,XY XV; points to the beginning of the destination array.
PIXBLT L,L Linear with special requirements when PBH=1 or PBV=1.
Refer to the PIXBLT L,L for a description of its unique re-
quirements.
PIXBLT L,XY XV; points to the beginning of the destination array.
PIXBLT XY,L Linear; points to the beginning of the destination array.
PIXBLT XY,XY XV; points to the beginning of the destination array.
5-8
Destination Address Register 82
Example DADDR .set B2
MOVI 00080015h, DADDR Move XY value 15h,8h
into B2
MOVI OOOlOAFCh, DADDR Move linear value
lOAFCh into B2
5-9
83 Destination Pitch Register
Format 31 o
Linear Bit Address
Description DPTCH specifies the linear difference in the starting memory addresses of
adjacent rows of the destination array for PIXBLT and FILL instructions.
The TMS3401 0 uses the value in DPTCH to move from row to row through
the destination array. DPTCH must be an integer multiple of 16 (except
for FILL L when DX=1). DPTCH is also constrained in some cases to be
a power of two; this allows XV addressing and allows DADDR to be auto-
matically adjusted to point to an alternate starting corner.
The following instructions use DPTCH as an implied operand.
Instruction DPTCH Format and Function
FILL L Linear; unused when DY=1.
FILL XV Linear; power of two ~ 16.
PIXBLT B,L Linear; multiple of 16.
PIXBLT B,XY Linear; power of two ~ 16 for windowing, multiple of 16
otherwise.
PIXBLT L,L Linear; multiple of 16.
PIXBLT L,XY Linear; power of two ~ 16.
PIXBLT XY,L Linear; power of two us.> 16 for PBV = 1, multiple of 16
otherwise.
PIXBLT XY,XY Linear; power of two ~ 16.
Example DPTCH .set B3
MOVI OOOOlOOOh, DPTCH Power of two for
PIXBLT XY,L
MOVI OOOlOAFCh, DPTCH Any value for
PIXBLT L,L
5-10
XV Addressing Offset Register 84
Format 31 o
Linear Bit Address
Description OFFSET contains the linear address of the first pixel in the XY coordinate
space for instructions using XY addressing. This corresponds to the linear
address of the XY origin (X=O,Y=O). This value is used as the memory base
for performing XY to linear address conversions.
OFFSET is always in linear format. It may be placed at any position in the
TMS34010 linear address space and should contain a pixel-aligned value
for proper XY address conversions, transparency, pixel processing, and
plane masking. Instructions that use OFFSET as an implied operand do not
modify the contents of OFFSET.
The following instructions use OFFSET as an implied operand.
Instruction OFFSET Format and Function
CVXYL Rs,Rd Linear address of XY origin
DRAV Rs,Rd Linear address of XY origin
FILL XY Linear address of XY origin
LINE Linear address of XY origin
PIXBLT B,XY Linear address of XY origin
PIXBLT L,XY Linear address of XY origin
PIXBLT XY,L Linear address of XY origin
PIXBLT XY,XY Linear address of XY origin
PIXT Rs,Rd.XY Linear address of XY origin
PIXT Rs.XY,Rd Linear address of XY origin
PIXT Rs.XY,Rd.XY Linear address of XY origin
Example OFFSET .set B4
MOVI 00042000h, OFFSET Linear value on
pixel boundary
5-11
85 Window Start Address Register
Format 31 16 15 o
Window start Y Window start X
Description WSTART specifies the XY address of the least significant pixel contained
in the rectangular destination clipping window. WSTART must be valid for
instructions that use an XY destination address and a window option. The
least significant pixel is the pixel with the lowest address in the array. For
a screen with the ORG bit of the DPYCTL register set to 0, this corresponds
to the pixel in the upper left corner of the pixel array.
WSTART may be placed at any position in the positive quadrant of the XY
address space. It describes an inclusive pixel; that is, the pixel at the XY
location contained in WSTART is included in the window. The value in
WSTART is used with WEND, DADDR, and DYDX to preclip pixels, lines,
and pixel arrays. WSTART is not modified by instruction execution.
The following instructions use WSTART as an implied operand.
Instruction WSTART Format and Function
CPW Rs,Rd XY value of least significant window corner
DRAV Rs,Rd XY value of least significant window corner
FILL XY XY value of least significant window corner
LINE XY value of least significant window corner
PIXBLT B,XY XY value of least significant window corner
PIXBLT L,XY XY value of least significant window corner
PIXBLT XY,XY XY value of least significant window corner
PIXT Rs,Rd.XY XY value of least significant window corner
PIXT Rs.XY,Rd.XY XY value of least significant window corner
Example WSTART .set B5
MOVI 00400100h, WSTART XY value (256,64)
stored in WSTART
5-12
Window End Address Register 86
Format 31 16 15 o
Window end Y Window end X
Description WEN D specifies the XY address of the most significant pixel contained in
the rectangular destination clipping window. WEND must be valid for in-
structions that use an XY destination address and a window option. The
most significant pixel is the pixel with the highest address in the array. For
a screen with the ORG bit of the DPYCTL register set to 0, this corresponds
to the pixel in the lower right corner of the pixel array.
WEN D may be placed at any position in the positive quadrant of the XY
address space. It describes an inclusive pixel; that is, the pixel at the XY
location contained in WEN D is included in the window. The value in
WEND is used with WSTART, DADDR, and DYDX to preclip pixels, lines,
and pixel arrays. WEND is not modified by instruction execution.
The following instructions use WEN D as an implied operand.
Instruction WEND Format and Function
CPW Rs,Rd XY value of most significant window corner
DRAV Rs,Rd XY value of most significant window corner
FILL XY XY value of most significant window corner
LINE XY value of most significant window corner
PIXBLT B,XY XY value of most significant window corner
PIXBLT L,XY XY value of most significant window corner
PIXBLT XY,XY XY value of most significant window corner
PIXT Rs,Rd.XY XY value of most significant window corner
PIXT Rs.XY,Rd.XY XY value of most significant window corner
Example WEND .set B6
MOVI 00400100h, WEND XY value (256,64) stored
in WEND
5-13
B7 Delta Y /Delta X Register
Format 31 16 15 o
Delta Y Delta X
Description DYDX specifies the X and Y dimensions of the rectangular destination array
for PIXBLT and FILL instructions. Both the X and Y dimensions are in
pixels; that is, the DX value is number of pixels in width of the array, and
DY is the number of rows of pixels in the destination array.
When the window clipping option is selected, the pixel block dimensions
for the transfer are determined by the relationships between WSTART,
WEND, DADDR, and DYDX. If either the X or Y dimension is 0, then the
block is interpreted as having a dimension of 0; no transfer is performed.
The values for DY and DX may range up to the coordinate extent of the
display (up to 65,535, depending on the display pitch and pixel size se-
lected). For window operations, the relationship between DYDX,
WSTART, and WEN D is such that DY = Yend - Ystart + 1 and DX = Xend
- Xstart + 1. The value in DYDX is used with WSTART, DADDR, and DYDX
to preclip pixels, lines, and pixel arrays.
Most graphics instructions do not modify the contents of DYDX. For FI LL
XV, PIXBLT B,XY, PIXBLT L,XY, and PIXBLT XY,XY, with window option
1, however, DYDX is used with DADDR to perform a common rectangle
function. In this case, the instruction sets DYDX to the dimensions of the
common pixel block described by the intersection of the original destination
array and the window identified by WSTART and WEND. No drawing is
performed. If there is no common rectangle, the V bit is not set and the
value of DYDX is indeterminate. See these instructions for further infor-
mation.
The following instructions use DYDX as an implied operand.
Instruction DYDX Format and Function
FILL L Array dimensions in XY format.
FILL XY Array dimensions in XY format; special results when W=1
is selected, as previously noted.
LINE Dimensions of the rectangle described by the line to be
drawn.
PIXBLT B,L Array dimensions in XY format
PIXBLT B,XY Array dimensions in XY format; special results when pick
is selected, as previously noted.
PIXBLT L,L Array dimensions in XY format.
PIXBLT L,XY Array dimensions in XY format; special results when pick
is selected, as previously noted.
PIXBLT XY,L Array dimensions in XY format.
PIXBLT XY,XY Array dimensions in XY format; special results when pick
is selected, as previously noted.
Example This example illustrates the relationship of DYDX to WSTART and WEN D.
WSTART .set B5
WEND .set B6
DYDX .set B7
MOVE WEND, DYDX Put WEND into DYDX
SUBXY WSTART, DYDX Generate (WEND - WSTART)
ADDI lOOOlh, DYDX Increment by 1 in each
dimension
5-14
Background Color Register B8
Format 31 o
Replicated Pixel Value
Description COLORO specifies the replacement color for 0 bits in the source array for
PIXBLT B,L and PIXBLT B,XY instructions. These two instructions trans-
form binary pixel array information to multiple bits per pixel arrays using the
color information in COLOR1 and COLORO. The lower 16 bits of COLORO
are used for the 0 or background color. There is a direct correspondence
between the alignment of pixels within the COLORO register and pixels
within memory words to be altered. That is, individual pixels within
COLORO are used as they align with destination pixels in the destination
word.
Execution of graphics instructions does not modify COLORO.
To provide upward compatibility with future versions of the GSP, the plane
mask should be replicated through all 32 bits of COLORO.
The following instructions use COLORO as an implied operand.
Instruction CO LO RO Contents
PIXBLT B,L Background pixel color for color-expanded array
PIXBLT B,XY Background pixel color for color-expanded array
Example This example is for 4-bit pixels. A pixel value of 5 is replicated throughout
the register.
COLORO .set B8
MOV! 55555555h, COLORO store uniform pixel
value in COLORO
5-15
89 Foreground Color Register
Format 31 o
Replicated Pixel Value
Description COLOR1 specifies the replacement color for pixels to be altered at the des-
tination pixel or pixel block for FILL, DRAV and LINE instructions.
For PIXBLT B,L and PIXBLT B,XY instructions, COLOR1 specifies the re-
placement color for 1 bits in the source array. These two instructions
transform binary pixel array information to multiple-plane pixel arrays using
color information in COLOR1 and COLORO. There is a direct correspond-
ence between the alignment of pixels within the COLOR1 register and pix-
els within memory words to be altered. That is, individual pixels within
COLOR1 are used as they align with destination pixels in the destination
word.
Execution of graphics instructions does not modify COLOR1.
To provide upward compatibility with future versions of the GSP, the plane
mask should be replicated through all 32 bits of COLOR1.
The following instructions use COLOR1 as an implied operand.
Instruction CO LO R1 Contents
DRAV Rs,Rd Pixel color for pixel draw
FILL L Pixel color for filled array
FILL XY Pixel color for filled array
LINE Pixel color for line draw
PIXBLT B/L Foreground pixel color for color-expanded array
PIXBLT B,XY Foreground pixel color for color-expanded array
Example This example is for 4-bit pixels. A pixel value of 3 is replicated throughout
the register.
COLOR! .set B9
MOVI 33333333h, COLOR! Store uniform pixel
value in COLORl
5-16
Reserved Registers 810-814
Format 31 o
Various Formats
Description The functions of these registers depend on which instruction uses them:
• PIXBLT and FI LL instructions use registers B10 through B14 as tem-
porary registers that hold intermediate values.
• The LINE instruction uses these registers as implied operands with the
following functions:
B11 is the INC1 register; it specifies the X and Y increments for
a diagonal step.
B12 is the INC2 register; it specifies the X and Y increments for
a nondiagonal step.
B10 is the COUNT register; it specifies the number of pixels to
be drawn in the line.
B13 is the PATTRN register; it is reserved for future LINE draw
enhancement. It should be set to OFFFFFFFFh before executing
the LI N E instruction to ensure software compatibility.
B14 is a temporary register (TEMP) that holds intermediate va-
lues.
5-17
CPU Registers and Instruction Cache - Status Register
5.2 Status Register
The status register (ST) is a special-purpose, 32-bit register that specifies the
processor status. The ST also contains several parameters that specify the
characteristics of two programmable data types, fields 0 and 1. The ST is ini-
tialized to 00000010h at reset.
Figure 5-4 illustrates the status register. Table 5-2 lists the functions associ-
ated with the status bits. Table 5-3 describes the encoding of the field size
bits in FSO and FS1.
Note: The status register bits marked reserved (bits 12-20, 22-24, and 26-27)
are currently unused. When read, a reserved bit returns the last value
written to it. At reset, all reserved bits are forced to Os.
Figure 5-4. Status Register
Table 5-2. Definition of Bits in Status Register
Bit Field
No. Name Function
0-4 FSO Field Size O. Length in bits of first memory data field (see Table 5-3 for values).
5 FEO Field Extend O. Bit determines whether field from memory is extended with Os or
with the sign bit when loaded into 32-bit general-purpose register.
FEO = 0 selects zero extension for field 0
FEO = 1 selects sign extension for field 0
6-10 FS1 Field Size 1. Length in bits of second memory data field (see Table 5-3 for values).
11 FE1 Field Extend 1. Bit determines whether field from memory is extended with Os or
with the sign bit when loaded into 32-bit general-purpose register.
FE1 = 0 selects zero extension for field 1
FE1 = 1 selects sign extension for field 1
21 IE Interrupt Enable. Master interrupt enable/disable bit.
IE = 0 disables all maskable interrupts
IE = 1 enables all maskable interrupts
25 PBX Pix Bit Executing. Indicates upon return from an interrupt that the interrupt oc-
curred between instructions or in the middle of a PIXBLT or FI LL instruction.
o = Indicates interrupt occurred at PIXBLT or FILL instruction boundary
1 = Indicates interrupt occurred in the middle of a PIXBLT or FI LL instruction
28 V Overflow. Set according to instruction execution.
29 Z Zero. Set according to instruction execution.
30 C Carry. Set according to instruction execution.
31 N Negative. Set according to instruction execution.
12
20
22-24
- Reserved
26-27
5-18
CPU Registers and Instruction Cache - Status Register/Program Counter
Table 5-3. Decoding of Field-Size Bits in Status Register
Five FS Field Five FS Field Five FS Field Five FS Field
Bits Size t Bits Size t Bits Size t Bits Sizet
00001 1 01001 9 10001 17 11001 25
00010 2 01010 10 10010 18 11010 26
00011 3 01011 11 10011 19 11011 27
00100 4 01100 12 10100 20 11100 28
00101 5 01101 13 10101 21 11101 29
00110 6 01110 14 10110 22 11110 30
00111 7 01111 15 10111 23 11111 31
01000 8 10000 16 11000 24 00000 32
t In bits
5.3 Program Counter
The program counter (PC) is a dedicated 32-bit register that points to the next
instruction word to be executed. Instructions are always aligned on even
16-bit word boundaries, and as shown in Figure 5-5, the four LSBs of the PC
are always Os.
~ 48 0
I Word Addreaa !O 0 0 01
~1·---------28~---------~·1~·4~~
Figure 5-5. Program Counter
An instruction consists of one or more instruction words. The first word
contains the opcode for the instruction. Additional words may be required for
immediate data, displacements, or absolute addresses. As each instruction
word is fetched, the PC is incremented by 16 to point to the next instruction
word. The PC contents are replaced during a branch instruction, subroutine
call instruction, return instruction, or interrupt .. Instructions may be categor-
ized according to their effect on the PC, as indicated in Table 5-4.
Table 5-4. Instruction Effects on the PC
Category Description
Non-branch The PC is incremented by 16 at the end of the instruction,
allowing execution to proceed sequentially to the next in-
struction.
Absolute Branch The PC is loaded with an absolute address; the four LSBs
(TRAP, CALL, JAcc) of the address are set to Os.
Relative Branch The signed displacement (8 or 16 bits) is added to the
(J Rcc, DSJxx) current contents of the PC. The signed displacement is
treated as a word displacement; that is, it is shifted left four
bit positions before it is added to the PC.
Indirect Branch The PC is loaded with the register contents. The four LS Bs
(JUMP, CALL, are set to Os.
EXGPC)
5-19
CPU Registers and Instruction Cache - Instruction Cache
5.4 Instruction Cache
Most program execution time is spent on repeated execution of a few main
procedures or loops. Program execution can be speeded up by placing these
often used code segments in a fast memory. The TMS3401 0 uses a 256-byte
instruction cache for this purpose.
Only instruction words (memory words that are pointed to by the PC) can be
accessed from the cache. This includes opcodes, immediate operands, dis-
placements, and absolute addresses. Instructions and data may reside in the
same area of memory; therefore, data may occasionally be copied into the in-
struction cache along with instruction words. However, the processor cannot
access data from the cache. All reads and writes of data in memory bypass the
cache.
5.4.1 Cache Hardware
The instruction cache contains 256 bytes of RAM, used to store up to 128
16-bit instruction words. Each instruction word in cache is aligned on an even
word boundary. Figure 5-6 illustrates cache organization.
p
segment start Addreea Raga Data Reglstera
'~I
A
6SA Repl!!ter 0 _ ~ent ,
If 23 ..
A
•
:
•
~
--!m
SeA Regllter 1
- or Subaegment 2
..... or of segment 1
.......... or
M--18-t1
SSA Replater 2
m
Moat
Recently
uaect LRU
Least Staok
6SA Register 3
Rec=
Figure 5-6. TMS34010 Instruction Cache
The cache is divided into four 32-word segments. Each cache segment may
contain up to 32 words of a 32-word segment in memory. This memory seg-
5-20
CPU Registers and Instruction Cache - Instruction Cache
ment is a block of 32 contiguous words beginning at an even 32-word
boundary in memory.
Each cache segment is divided into eight subsegments; each subsegment
contains four words. Dividing each segment into subsegments reduces the
number of word fetches required from memory when fewer than 32 words of
a memory segment are used. Each of the four cache segments is associated
with a segment start address (SSA) register. Figure 5-7 shows how an in-
struction word is partitioned into the components used by the cache control
algorithm.
If-~------- 32-BIt Unear Addr888-------+l~1
f 23B1t8 ~
II I _ _ ~mml_
word address are always O.
Instruotlon word address
within subsegment
Subsegment addrese
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ Segment start address
(SSA register)
Figure 5-7. Segment Start Address
The 23 bits of the SSA register correspond to the 23 MSBs of the segment's
memory address. These 23 MSBs are common to all eight subsegments within
a segment. The next three bits (bits 6-8) identify one of the eight subseg-
ments. Bits 4 and 5 identify one of the four words contained in a subsegment.
The four LSBs are always Os because instructions are aligned on word boun-
daries.
5.4.2 Cache Replacement Algorithm
When the TMS3401 0 requests an instruction word from a segment that is not
in the cache, the contents of one of the four cache-resident segments must
be discarded to make room for the segment that contains the requested word.
A modified form of the least-recently-used (LRU) replacement algorithm is
used to select the segment to be discarded.
The LRU segment manager (part of the cache control logic) maintains an LRU
stack to track use of the four segments. The LRU stack contains a queue of
segment numbers, 0 through 3. Each time a segment is accessed, its segment
number is moved to the top of the stack, pushing the other segment numbers
down as necessary to make room at the top. Thus, the number at the top of
the LRU stack identifies the most-recently-used segment and the number at
the bottom identifies the least-recently-used segment.
When a new segment must be loaded into cache, the least-recently-used
segment is discarded. The eight P flags (described in Section 5.4.3) of the
selected segment are set to Os, and the segment's SSA register is loaded with
the new segment address. After the requested subsegment has been loaded
from memory, its P flag is set to 1, and the requested instruction fetch is al-
lowed to complete.
Following a reset, all P flags in the cache are set to 0 and the four segment
numbers in the LRU stack are stored in numerical order (0-1-2-3).
5-21
CPU Registers and Instruction Cache - Instruction Cache
5.4.3 Cache Operation
When the TMS3401 0 requests an instruction word, it checks to see if the word
is contained in cache. First, it compares the 23 MSBs of the instruction ad-
dress to the four SSA registers. If a match is found, the processor searches for
the appropriate subsegment. A present (P) flag, associated with each sub-
segment, indicates the presence of a particular subsegment within a cache
segment. P=1 indicates that the requested word is in cache; this is called a
cache hit. If there is no match, or if there is a match and P=O, the word is not
in cache; this is called a cache miss.
5.4.3.1 Cache Hit
The cache contains the requested instruction word. The processor performs
the following actions:
1) A short (one machine state) access cycle reads the instruction word from
cache.
2) The segment number is moved to the top of the LRU stack, pushing the
other three segment numbers toward the bottom of the stack.
Due to pipelining, instruction fetches from the cache frequently overlap com-
pletion of preceding instructions. The overhead due to instruction fetches in
such cases is effectively zero.
5.4.3.2 Cache Miss
The cache does not contain the instruction word. There are two types of
cache miss - subsegment miss and segment miss.
• Subsegment Miss. The 23 MSBs of the instruction word address
match one of the four SSA registers' 23 MSBs; that is, the appropriate
segment is in the cache. However, the P flag for the requested subseg-
ment is not set. The processor performs the following actions:
1) The four-word subsegment containing the requested instruction
word is read from local memory into the cache.
2) The segment number is moved to the top of the LRU stack, push-
ing the other three segment numbers toward the bottom of the
stack.
3) The subsegment's P flag is set.
4) The instruction word is read from the cache.
• Segment Miss. The instruction word address does not match any of
the SSA registers. The processor performs the following actions:
1) The least-recently-used segment is selected for replacement; the P
flags of all eight subsegments are cleared.
2) The SSA register for the selected segment is loaded with the 23
MSBs of the address of the requested instruction word.
5-22
CPU Registers and Instruction Cache - Instruction Cache
3) The four-word subsegment in memory that contains the requested
instruction word is read into the cache. It is placed in the appro-
priate subsegment of the least-recently-used segment. The sub-
segment's P flag is set to 1.
4) The LRU stack is adjusted by moving the number of the new seg-
ment from the bottom (indicating that it is least recently used) to
the top (indicating that it is most recently used). This pushes the
other three segment numbers in the stack down one position.
5) The instruction word is read from the cache.
5.4.4 Self-Modifying Code
Avoid using self-modifying code; it can cause unpredictable results. When a
program modifies its own instructions, only the copy of the instruction that
resides in external memory is affected. Copies of the instructions that reside
in cache are not modified, and the internal control logic does not attempt to
detect this situation.
5.4.5 Flushing the Cache
Flushing the cache sets it to an initial state which is identical to the state of
the cache following reset. The cache is empty and all 32 P flags are set to O.
The cache is flushed by setting the CF (cache flush) bit in the HSTCTL register
to 1. The CF bit retains the last value loaded until a new value is loaded or
until the TMS3401 0 is reset. The contents of the cache remain flushed as long
as the CF bit is set to 1. All instruction fetches bypass the cache and are ac-
cessed directly from memory.
Unless the cache is disabled, normal cache operation will resume when the
CF bit is set to O.
One use for flushing the cache is to facilitate downloading new code from a
host processor to TMS34010 local memory. The host typically halts the
TMS34010 during downloading by writing a 1 to the HLT bit in the HSTCTL
register. Before allowing the TMS34010 to execute downloaded code, the
host should flush the cache to purge it of stale instructions.
For performance reasons, the CD bit should not remain set to 1 for long peri-
ods. While CD=1, each instruction-word fetch is interpreted as a cache miss,
causing the four words in the subsegment to be fetched from memory.
Though the word pointed to by the PC is executed, none of the four words is
preserved in cache.
5-23
CPU Registers and Instruction Cache - Instruction Cache
5.4.6 Cache Disable
Disabling the cache facilitates program debugging and emulation. The cache
is disabled by setting the CD (cache disable) bit in the CONTROL register to
1. While disabled, the cache is bypassed and all instructions are fetched from
external memory.
CD=1 is similar in effect to CF=1, with several exceptions:
• While CD=1 and CF=O, data already in the cache are protected from
change. When the CD bit is set back to 0, the state of the cache prior
to setting the CD bit to 1 is restored. The instructions in the cache are
once again available for execution. If the contents of the cache become
invalid while CD=1, they can be flushed by setting CF to 1.
• While CD=1 and CF=O, each instruction word is fetched from memory
as it is requested, but the other three words in the subsegment are not
fetched. In contrast, if CF=1 and CD=O, all four words in the subseg-
ment that contain the requested instruction word are fetched, although
all but the requested word are immediately discarded.
The CD bit can be manipulated to preserve code in the cache for faster exe-
cution in some time-critical applications. For example, if an inner loop just
exceeds 256 bytes, most of the loop, but not all of it, can fit in the cache.
During execution of the few instructions that are not in the cache, the CD bit
can be set to 1 to prevent the code in the cache from being replaced. In this
instance, the loop's execution speed is improved by eliminating the thrashing
of cache contents. Use this technique carefully; in some cases, it can nega-
tively affect execution speed.
5.4.7 Performance with Cache Enabled versus Cache Disabled
When the instruction cache is disabled, instruction words are fetched from
external memory. Assuming no wait states are necessary, each instruction
fetch from external memory adds 3 machine cycles to the access time. This is
considerably slower than a program which uses the cache efficiently (when
each word in cache is used several times before it is replaced).
A less efficient use of cache occurs when words in cache are used only once
before replacement. This produces a cache miss every fourth word (even in
this case, operation is usually much better than operation when the cache is
disabled). With the cache enabled, the time penalty due to cache misses in
this case is 2.25 machine states per single-word instruction (compare this to
3 states when the cache is disabled), which is calculated as follows:
• Eight machine cycles are required to load four words into cache from
memory.
• An additional machine state is required to start processing the in-
struction.
• Dividing the total of nine machine states by four instruction words yields
an average of 2.25 machine states per instruction word.
Performance using the cache is nearly always better than performance with the
cache disabled. There are two exceptions. The first occurs when the code
contains so many jumps that only a portion of each subsegment is executed
before control is transferred to another subsegment. The second occurs when
5-24
CPU Registers and Instruction Cache - Cachet Internal Parallelism
an inner loop is larger than the cache, in which case only some portion of the
instructions in the inner loop can be contained in the cache at any time. In this
case, performance may be improved by manipulating the CD bit as described
in Section 5.4.6.
While the cache is disabled, the TMS34010's internal memory controller
fetches each instruction word from memory only as it is requested by the in-
ternal execution unit. This differs from operation with the cache enabled, in
which case a cache miss causes the entire four-word subsegment containing
the requested instruction word to be loaded into the cache at once.
5.5 Internal Parallelism
Figure 5-8 illustrates the internal data paths associated with TMS3401 0 pro-
cessor functions. The TMS3401 0 has a single, logical memory space for sto-
rage of both data and instructions. However, internal parallelism provides the
TMS34010 with the benefits found in architectures which contain separate
data and instruction storage (sometimes referred to as Harvard architectures).
The ability to fetch instructions from cache in parallel with data accesses from
memory greatly enhances execution speed. Hardware parallelism allows the
following three storage areas to be accessed simultaneously:
• Instruction cache
• Dual-ported, general-purpose register files A and B
• External memory
,------------------------------'
ITM834010
I
I
I Instruction Instruotlons
Caohe
I
I
I
I
I
I
I
I
I
I
I
I General- ... Data Memory
I pu=
Re era
CPU Interfaoe t---+-t External
Memory
I I
I I
I I
I I
I I
1_ _ _ _ _ _ - - - - - - - - - - - - - - - - - - - - - - - - -
Figure 5-8. Internal Data Paths
5-25
CPU Registers and Instruction Cache - Internal Parallelism
Each storage area can also be accessed independently of the other two. This
allows the TMS3401 0 to perform the following actions in parallel during a pair
of machine states:
• One external memory cycle
• Two instruction fetches from cache
• Four reads and two writes to the general-purpose register files
The need to schedule conflicting internal operations can limit the TMS3401 O's
ability to perform these actions in parallel. For example, an instruction which
requires the memory controller to perform a read must finish executing before
the next instruction can be executed.
Figure 5-9 illustrates an example of internal parallelism. Figure 5-9 a shows
three activities occurring in parallel:
• Instructions are fetched from cache.
• Instructions are executed through the general-purpose registers and
the ALU.
• The local memory interface controller performs memory accesses.
Figure 5-9 a represents execution of the code in Figure 5-9 b, which is the
inner loop of a graphics routine. The memory controller accesses pixels while
the ALU fetches instructions from cache. The memory controller completes a
write cycle while execution begins on the next instruction.
(I)
~ One iteration ~I
State: ~1""2"",,3*4"""5*e""'7""8*9*10*11*12*-
MOVE ADD PIXT ADD DSJS MOVE
Instruction Fetch:~~t~~~~~tl I B It?~ttl I 0 nJ~ttl m
~ ~
Memory Interface:
Read Cycle Read Write
(b)
A L1: MOVE E1+,B10,O Get DB..TAX
B ADD B10,88 Adjust pixel pointer
C PIXT wB1,.aa Draw next pixel
o ADD BO,B1 Add field size
E DSJS B11,L1 Loop N Times
Figure 5-9. Parallel Operation of Cache, Execution Unit, and Memory Interface
5-26
Section 6
I/O Registers
The TMS3401 O's 28 on-chip I/O registers control and monitor the following
functions:
• Host interface communications
• Local memory interface control
• Interrupt control
• Video timing and screen refresh
This section describes these functions, I/O register addressing, and then pro-
vides an alphabetical presentation of the I/O registers:
Section Page
6.1 I/O Register Addressing ........................................................................... 6-2
6.2 Latency of Writes to I/O Registers .......................................................... 6-4
6.3 I/O Registers Summary ............................................................................. 6-5
6.4 Alphabetical Listing of I/O Registers .................................................... 6-10
6-1
I/O Registers - Addressing
6.1 I/O Register Addressing
TMS34010 I/O registers occupy addresses COOOOOOOh to C00001 FFh. These
registers can be directly accessed by the TMS34010; they can also be indi-
rectly accessed by a host processor through the host interface registers. For
example, the host processor can indirectly read the contents of the PSIZE re-
gister by loading the address C0000150h into the HSTADRL and HSTADRH
registers, and reading the HSTDATA register. Figure 6-1 illustrates the I/O
register memory map.
C00001FOh REFCNT DRAM Refresh Count
C00001EOh DPYADR Display Address
C00001DOh VCOUNT Vertical Count
C00001COh HCOUNT Horizontal Count
C00001BOh DPYTAP Display Tap Point
C00001AOh
C0000190h Reserved
C0000180h
C0000170h
C0000160h PMASK Plane Mask
C0000150h PSIZE Pixel Size
C0000140h CONVDP Destination Conversion Pitch
C0000130h CONVSP Source Conversion Pitch
C0000120h INTPEND Interrupt Pending
C0000110h INTENB I nterrupt Enable
C0000100h HSTCTLH Host Control (MSBs)
COOOOOFOh HSTCTLL Host Control (LSBs)
COOOOOEOh HSTADRH Host Address (MSBs)
COOOOODOh HSTADRL Host Address (LSBs)
COOOOOCOh HSTDATA Host Data
COOOOOBOh CONTROL Control
COOOOOAOh DPYINT Display Interrupt
C0000090h DPYSTRT Display Start
C0000080h DPYCTL Display Control
C0000070h VTOTAL Vertical Total
C0000060h VSBLNK Vertical Start Blank
C0000050h VEBLNK Vertical End Blank
C0000040h VESYNC Vertical End Sync
C0000030h HTOTAL Horizontal Total
C0000020h HSBLNK Horizontal Start Blank
C0000010h HEBLNK Horizontal End Blank
COOOOOOOh HESYNC Horizontal End Sync
Figure 6-1. I/O Register Memory Map
The two MSBs of an I/O register's 32-bit internal address are not output on
the TMS3401 0 pins; however, the address is fully decoded internally. Thus,
the two MSBs of a 32-bit address must both be 1s for an address to be re-
cognized as that of an I/O register. When an I/O register is accessed, the ac-
companying memory cycle (as seen at the TMS3401 0 pins) is altered so that
the row address strobe is output, but the column address strobe is inhibited.
This is true whether the access is initiated directly by the TMS3401 0 or indi-
rectly by a host processor.
6-2
I/O Registers - Addressing
An access of any address in the range COOOOOOOh-C00001 FFh is decoded as
an access of an on-chip register location, and the column address strobe re-
mains inactive high through the cycle. An access of any location outside this
range is treated as an access of an external memory location.
All I/O registers, with one exception, are cleared to 0 at reset. The exception
is the HLT (halt) bit in the HSTCTL register, which is set depending on the
value at the HCS input pin at the end of the reset pulse:
• If HCS is high at reset, the HLT bit is set to 1
• If HCS is low at reset, the HLT bit is set to 0
6-3
I/O Registers - Latency of Writes to I/O Registers
6.2 Latency of Writes to I/O Registers
When an instruction alters the contents of an I/O register, the memory write
cycle that modifies the register may not be completed before execution of the
next instruction begins. If the second instruction relies on the I/O register
value loaded by the first instruction, the second instruction may cause incor-
rect results. This type of problem could occur, for example, if a PIXBLT in-
struction were immediately preceded by a MOVE register-to-memory
instruction that modified the CONTROL register. This situation is easily
avoided by ensuring that the write to the I/O register is allowed to complete
before the I/O register value is used as an implied operand by a subsequent
instruction. For example, by immediately following a write to an I/O register
with a read of the register, the write is certain to have been completed by the
time subsequent instructions begin execution.
Internal to the TMS34010, the memory controller operates semi-autono-
mously with respect to the execution unit that processes instructions. Paral-
lelism between the execution unit and memory controller may allow a write
initiated by an instruction to be completed only after one or more subsequent
instructions have been executed. An instruction that alters an I/O register (or
any other address in memory) transmits its request for a write cycle to the
memory controller. Once the request is accepted, the memory controller is
responsible for completing the write cycle; in the meantime, execution of the
next instruction can begin.
A field insertion request submitted to the memory controller can take as many
as five cycles to complete in the case in which a field of 18 or more bits
straddles two word boundaries. This case requires a read-modify-write oper-
ation to one word, a write to a second word, and a read-modify-write opera-
tion to a third word. Although this would be an unusual way of altering
locations in the I/O register file, it represents the theoretical worst case number
of memory cycles for a field insertion.
The start of a pending field-insertion cycle may be delayed by the following
conditions:
• Screen-refresh cycle
• DRAM-refresh cycle
• Host-indirect read or write cycle
• Wait states required for slower memories
• Hold request from an external device
Any uncertainty as to whether a pending write to memory has been completed
can be eliminated by making use of the fact that only one field insertion re-
quest can be queued at the memory controller at a time. An instruction that
requests a second memory access before the earlier field insertion has been
completed will be forced to wait. Hence, by following an instruction that al-
ters an I/O register with an instruction that requests a second memory access
(any memory access), the I/O register is certain to have been updated before
the second instruction finishes executing.
6-4
I/O Registers - Summary
6.3 I/O Registers Summary
Table 6-1 summarizes the I/O registers. Descriptions of the four categories
of I/O registers follow the table.
Table 6-1. I/O Registers Summary
Host Interface Registers
Register Address Description
HSTADRH COOOOOEOh Host interface address, high word. Contains the 16 MSBs of a
32-bit pointer address used by a host processor for indirect accesses of
TMS34010 local memory.
HSTADRL COOOOODOh Host interface address, low word. Contains the 16 LSBs of a 32-bit
pointer address used by a host processor for indirect accesses of
TMS34010 local memory.
HSTCTLH COOOO100h Host interface control. high byte Contains seven programmable bits
that control host interface functions:
NMI (bit 8) - Nonmaskable interrupt
NMIM (bit 9) - NMI mode bit
INCW (bit 11) - Increment pointer address on write
INCR (bit 12) - Increment pointer address on read
LBL (bit 13) - Lower byte last
CF(bit14) - Cache flush
HLT (bit 15) - Halt TMS3401 0 execution
Bits 0 through 7 and 10 are reserved
HSTCTLL COOOOOFOh Host interface control. low byte. Contains eight programmable bits
that control host interface functions:
MSGIN (bits 0-2) - Input message buffer
INTIN (bit 3) - Input interrupt bit
MSGOUT (bits 4-6) - Output message buffer
INTOUT (bit 7) - Output interrupt bit
Bits 8 through 15 are reserved
HSTDATA COOOOOCOh Host interface data. Buffers data transferred between TMS3401 0 local
memory and a host processor.
Local Memory Interface Registers
Register Address Description
CONTROLt COOOOOBOh Memory control. Contains several parameters that control local mem-
ory interface operation:
RM (bit 2) - D RAM refresh mode
RR (bits 3-4) - DRAM refresh rate
T (bit 5) - Transparency enable
W (bits 6-7) - Window violation detection mode
PBH (bit 8) - PixBlt horizontal direction
PBV (bit 9) - PixBlt vertical direction
PPOP (bits 10-14) - Pixel processing operation select
CD (bit 15) - Cache disable
Bits 0 and 1 are reserved
CONVDPt COOOO140h Destination pitch conversion factor. Used during XY to linear con-
version of a destination memory address.
CONVSPt COOOO130h Source pitch conversion factor. Used during XY to linear conversion
of a source memory address.
t Implied graphics operands
6-5
I/O Registers - Summary
Table 6-1. I/O Registers Summary (Continued)
Local Memory Interface Registers (Continued)
Register Address Description
PMASKt COOO0160h Plane mask register. Selectively enables/disables the various planes
in the bit map of a display system in which each pixel is represented by
multiple bits.
PSIZEt COOO0150h Pixel size register. Specifies the pixel size (in bits). Possible pixel
sizes include 1, 2, 4, 8, and 16 bits.
REFCNT COOO01FOh Refresh count register. Generates the addresses output during DRAM
refresh cycles and counts the intervals between successive DRAM refresh
cycles:
RINTVL (bits 2-7) - Refresh interval counter
ROWADR (bits 8-15) - Row address
Bits 0 and 1 are reserved
Interrupt Control Registers
Register Address Description
INTENB COOO0110h Interrupt enable. Contains the interrupt mask used to selectively
enable/disable the three internal and two external interrupts:
X1 E (bit 1) - External interrupt 1 enable
X2E (bit 2) - External interrupt 2 enable
HIE (bit 9) - Host interrupt enable
DIE (bit 10) - Display interrupt enable
WVE (bit 11) - Window violation interrupt enable
Bits 0, 3 through 8, and 12 through 15 are reserved
INTPEND COOO0120h Interrupt pending. Indicates which interrupt requests are currently
pending:
X1 P (bit 1 ) - External interrupt 1 pending
X2P (bit 2) - External interrupt 2 pending
HIP (bit 9) - Host interrupt pending
DIP (bit 10) - Display interrupt pending
WVP (bit 11) - Window violation interrupt pending
Bits 0, 3 through 8, and 12 through 15 are reserved
Video Timing and Screen Refresh Registers
Register Address Description
DPYADR COOO01EOh Display address. Counts the number of scan lines output between
successive screen refresh cycles and contains the source of the row and
column addresses output during a screen refresh cycle:
LNCNT (bits 0-1 ) - Scan line counter
SRFADR (bits 2-15) - Screen refresh address
DPYCTL COOOO080h Display control. Contains several parameters that control video timing
signals:
HSD (bit 0) - Horizontal sync direction
DUDATE (bits 2-9) - Display address update
ORG (bit 10) - Screen origin select
SRT (bit 11) - VRAM serial-register transfer enable
SRE (bit 12) - Screen refresh enable
DXV (bit 13) - Disable external video
NIL (bit 14) - Noninterlaced video enable
ENV (bit 15) - Enable video
Bit 1 is reserved.
DPYINT COOOOOAOh Display interrupt. Specifies the next scan line that will cause a display
interrupt request.
t Implied graphics operands
6-6
I/O Registers - Summary
Table 6-1. I/O Registers Summary (Concluded)
Video Timing and Screen Refresh Registers (Continued)
Register Address Description
DPYSTRT COOOOO90h Display start address. Provides control of the automatic memory-to-
register cycles necessary to refresh a screen:
LCSTRT (bits 0-1) - Specifies the number of scan lines to
be displayed between screen refreshes
SRSTRT (bits 2-15)- Starting screen-refresh address
DPYTAP COOOO1BOh Display tap point address. Contains a VRAM tap point address output
during shift register transfer cycles.
HCOUNT COOOO1COh Horizontal count. Counts the number of VCLK periods per horizontal
scan line.
HEBLNK COOOOO10h Horizontal end blank. Designates the endpoint for horizontal blanking.
HESYNC COOOOOOOh Horizontal end sync. Specifies the endpoint of the horizontal sync
interval.
HSBLNK COOOOO20h Horizontal start blank. Specifies the starting point of the horizontal
blanking interval.
HTOTAL COOOOO30h Horizontal total. Specifies the total number of VCLK periods per hori-
zontal scan line.
VCOUNT COOOO1DOh Vertical count. Counts the horizontal scan lines in a video display.
VEBLNK COOOOO50h Vertical end blank. Specifies the endpoint of the vertical blanking in-
terval.
VESYNC COOOOO40h Vertical end sync. Specifies the endpoint of the vertical sync pulse.
VSBLNK COOOOO60h Vertical start blank. Specifies the starting point of the vertical blank-
ing interval.
VTOTAL COOOOO70h Vertical total. Specifies the value of VCOUNT at which the vertical
sync pulse begins.
6.3.1 Host Interface Registers
Five I/O registers are dedicated to host interface communications, allowing the
TMS34010 to:
• Directly transfer status messages or command information
• Indirectly transfer large blocks of data through local memory
• Receive interrupt requests from a host processor
• Transfer interrupt requests to a host processor
The ability to indirectly transfer large blocks of data makes the host interface
extremely flexible. For example, a host can transfer blocks of commands to the
TMS34010, can halt the TMS3401 0 temporarily to download a new program
for the TMS3401 0 to execute, or can read blocks of graphics data generated
by the TMS3401 O.
The host interface registers occupy five TMS3401 0 register locations, and are
typically mapped into four consecutive 16-bit locations in the memory or I/O
address space of the host processor. The host processor accesses the
6-7
1/0 Registers - Summary
HSTCTLL and HSTCTLH registers as the eight LSBs and eight MSBs, re-
spectively, of a single location (the HSTCTL register).
The HSTCTL (host control) register controls functions such as the transfer of
interrupt requests and 3-bit status codes between a host processor and the
TMS34010. These requests are typically used by software to coordinate the
transfer of large blocks of data through TMS34010 local memory. The
HSTCTL register also allows the host to flush the instruction cache, halt
TMS34010 execution, and transmit nonmaskable interrupt requests to the
TMS34010.
The host processor uses the remaining three host interface registers to indi-
rectly access selected data blocks within TMS34010 local memory. The
HSTADRL and HSTADRH registers contain a 32-bit address that points to the
current word location in memory. The HSTDATA register buffers data trans-
ferred to and from the memory under control of the host processor. The host
interface can be programmed to automatically increment the address pointer
following each transfer, providing the host with rapid access to a block of se-
quential locations.
6.3.2 Local Memory Interface Registers
Six of the I/O registers support local memory interface functions such as:
• Frequency of DRAM refresh cycles
• Type of DRAM refresh cycles
• Pixel size
• Color plane masking
• Various pixel access control parameters
6.3.3 Interrupt Interface Registers
Two I/O registers monitor and mask interrupt requests to the TMS34010.
These include two external and three internal interrupts. External interrupt re-
quests are transmitted to the TMS3401 0 via input pins L1NT1 and L1NT2. The
TMS34010 can be programmed to generate an internal interrupt request in
response to any of the following conditions:
• Window violation - an attempt is made to write a pixel to a location in-
side or outside a specified window, depending on the selected win-
dowing mode.
• Host interrupt - the host processor sets the INTI N interrupt request bit
in the HSTCTL register.
• Display interrupt - the specified line number in a frame is displayed on
the monitor.
A nonmaskable interrupt occurs when the host processor sets the NMI bit in
the HSTCTL host interface register. Reset is controlled by a dedicated pin.
6-8
I/O Registers - Summary
6.3.4 Video Timing and Screen Refresh Registers
Fifteen I/O registers support video timing and screen refresh functions. The
TMS34010's on-chip CRT timing generator creates the sync and blanking
signals used to drive the CRT monitor in a bit-mapped display system. The
timing of these signals can be controlled through the appropriate I/O registers,
allowing the TMS3401 0 to support various screen resolutions and interlaced
or noninterlaced video.
The TMS3401 0 directly supports VRAMs (such as the TMS4461) by gener-
ating the memory-to-register cycles necessary to refresh the screen of a CRT
monitor. Programmable features include the locations in memory to be dis-
played on the monitor, as well as the number of horizontal scan lines displayed
between individual screen-refresh cycles.
The TMS34010 can optionally be programmed to synchronize to externally
generated sync signals. This permits TMS34010-created graphics images to
be superimposed upon externally-created images. This external sync mode
can also be used to synchronize the video timing of two or more TMS3401 0
devices in a multiple-TMS3401 0 display system.
6-9
I/O Registers - Alphabetical Listing
6.4 Alphabetical listing of I/O Registers
The remainder of this section describes the I/O registers individually; they are
listed in alphabetical order. Fields within each register are identified and
functions associated with each register are discussed.
Bits within I/O registers that are identified as reserved are not used by the
TMS34010. When read, a reserved bit returns the last value written to it. No
control function, however, is affected by this value. All reserved bits are
loaded with Os at reset. A good software practice is to maintain Os in these
bits.
6-10
Memory Control Register CONTROL
Address COOOOOBOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I CD I PPOP IPBV IPBH I W T RR I RM I reserved I
Fields Bits Name Function
0-1 Reserved Not used
2RM DRAM refresh mode
3-4 RR DRAM refresh rate
5 T Pixel transparency enable
6-7 W Window violation detection mode
8 PBH PixBlt horizontal direction
9 PBV PixBlt vertical direction
10-14 PPOP Pixel processing operation select
15 CD Instruction cache disable
Description The CONTROL register contains several control parameters used to config-
ure local memory interface operation.
• RM (DRAM refresh mode, bit 2)
The RM bit selects the type of DRAM refresh cycle to be performed. De-
pending on the value of this bit, the TMS34010 performs each DRAM-
refresh cycle as either a RAS-only cycle or as a CAS-before-RAS cycle.
DRAMs and VRAMs that rely on the TMS34010 to generate an 8-bit row
address during a refresh cycle typically use the RAS-only refresh cycle, while
those that generate their own 9-bit row address internally use the CAS-be-
fore- RAS refresh cycle.
RM Description
0 Selects RAS-only refresh cycle
1 Selects CAS-before- RAS refresh cycle
• R R (DRAM refresh rate, bits 3 and 4)
The RR field controls the frequency of DRAM refresh cycles. The
TMS34010 automatically generates DRAM refresh cycles at regular inter-
vals. The duration of the interval is specified by the value of RR. If required,
DRAM refreshing can be disabled by setting RR to the appropriate value.
The initial value of RR after reset is 002. No DRAM refresh cycles are per-
formed while the TMS3401 0 RESET signal is active.
6-11
CONTROL Memory Control Register
RR Description
00 Refresh every 32 local clock periods
01 Refresh every 64 local clock periods
10 Reserved code
11 No DRAM refreshing
• T (Pixel transparency, bit 5)
The T bit enables or disables the pixel attribute of transparency. When
transparency is enabled, a value of 0 resulting from a pixel operation on
source and destination pixels is inhibited from overwriting the destination
pixel. In the case of a replace operation (PPOP = 0), a source pixel value
of 0 is inhibited from overwriting the destination pixel. Disabling transpar-
ency allows a pixel value of 0 to be written to the destination.
T Effect
0 Disable transparency
1 Enable transparency
• W (Window checking, bits 6 and 7)
The W field selects the course of action to be taken when a pixel operation
will cause a pixel to be written to a location lying either inside or outside the
specified window limits. Window checking applies only to attempts to write
to pixel locations defined by XY addresses; writes to pixel locations defined
by linear memory addresses are not affected. Nonpixel data writes are not
affected.
W Description
00 No pixel writes are inhibited, and no interrupt requests are generated
01 Generate interrupt request on attempt to write to pixel lying inside window,
and inhibit all pixel writes
10 Generate interrupt request on attempt to write to pixel lying outside window
11 Inhibit pixel writes outside window, but do not request interrupt
A request for a window violation interrupt can occur when W=012 or
W=102' The WVP bit in the INTPEND register is set to 1 to indicate that a
window violation has occurred. This in turn causes the TMS3401 0 to be
interrupted if the WVE bit in the I NTEN B register and the status I E bit are
set to 1.
• PBH (PixBlt horizontal direction, bit 8)
The PBH bit determines the horizontal direction (increasing X or decreasing
X) of pixel processing for the following instructions:
PIXBLT XY,XY
PIXBLT L,XY
6-12
Memory Control Register CONTROL
PIXBLT XY,L
PIXBLT L,L
PBH Effect
0 Increment X (move from left to right)
1 Decrement X (move from right to left)
• PBV (PixBlt vertical direction, bit 9)
The PBV bit determines the vertical direction (increasing Y or decreasing
Y) of pixel processing for the following instructions:
PIXBLT XY,XY
PIXBLT L,XY
PIXBLT XY,L
PIXBLT L,L
PBV Effectt
0 Increment Y (move from top to bottom)
1 Decrement Y (move from bottom to top)
t Default screen origin assumed
• PPOP (Pixel processing operation, bits 10-14)
The PPOP field selects the operation to be performed on the source and
destination pixels during a pixel operation. The following 16 PPOP codes
perform Boolean operations on pixels of 1, 2, 4, 8, and 16 bits.
PPOP Operation Description
00000 S--+D Replace destination with source
00001 SAND D --+ D AND source with destination
00010 SAND 0 --+ D AN D source with NOT destination
00011 O--+D Replace destination with Os
00100 S OR 0 --+ D OR source with NOT destination
00101 S XNOR D --+ D XNOR source with destination
00110 O--+D Negate destination
00111 S NOR D --+ D NOR source with destination
01000 S OR D --+ D OR source with destination
01001 D--+D No change in destination t
01010 S XOR D --+ D XOR source with destination
01011 SAND D --+ D AND NOT source with destination
01100 1--+D Replace destination with 1s
01101 S OR D --+ D OR NOT source with destination
01110 S NAND D --+ D NAN D source with destination
01111 S--+D Replace destination with NOT source
t Although the destination array is not changed by this operation,
memory cycles still occur.
The following six PPOP codes perform arithmetic operations on 4-, 8-, and
16- bit pixels (but not 1 or 2 bits).
6-13
CONTROL Memory Control Register
PPOP Operation Description
10000 O+S-+O Add source to destination
10001 AOOS(O,S) -+ 0 Add S to 0 with saturation
10010 O-S-+O Subtract source from destination
10011 SUBS(O,S) -+ 0 Subtract S from 0 with saturation
10100 MAX( D,S) -+ 0 Maximum of source and destination
10101 MIN(O,S) -+ 0 Minimum of source and destination
PPOP codes 101102 through 111112 are reserved.
Standard addition and subtraction allow the result of the operation to over-
flow. However, add-with-saturation and subtract-with-saturation (ADDS
and SUBS) do not allow overflow or underflow. In cases in which addition
would allow an overflow, ADDS produces a result whose value is all 1s. In
cases in which subtraction would allow an underflow, SUBS produces a
result whose value is all Os.
• CD (Cache disable, bit 15)
The CD bit selectively enables or disables the instruction cache.
CD Effect
0 Enable instruction cache
1 Disable instruction cache
When the cache is disabled, cache contents (including data, P flags, SSA
registers, and so on) remain undisturbed. While the cache remains disabled,
all instructions are fetched from memory rather than cache. When the cache
is subsequently enabled, its previous state (before it was disabled) is re-
stored. The instructions retained within the cache are once again available
for execution.
6-14
Destination Pitch Conversion Factor CONVDP
Address C0000140h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I CONVDP
Description CONVDP is a full 16-bit register that contains a control parameter used
during execution of a pixel operation instruction. CONVDP is used with:
• XY addressing
• Window clipping
• PIXBLTs or FILLS (except for PIXBLT L,L) that process pixels from
the bottom of the array to the top (PBV=1 )
CONVDP is calculated as the result of an LMO instruction whose input
operand is the destination pitch value in register B3 (DPTCH). The fol-
lowing assembly code calculates the CONVDP value.
LMO B3,AO ; Convert DPTCH value
MOVE AO,@CONVDP,O ; place result in CONVDP register
In this example, AO is used as a scratch register. Constant CONVDP has
the value OC0000140h, and the size of Field 0 is 1 6 bits.
TMS34010 internal hardware uses the CONVDP value during XY -to-linear
conversion of a destination address. PIXBLT and FILL instructions which
specify the destination address in XY format use the DPTCH and CONVDP
values to convert the XY coordinates to a linear memory address before
actually beginning the pixel block move. During a PIXBLT or FILL in-
struction that requires preclipping of the destination array in the Y direction,
the TMS34010 uses the CONVDP value to calculate the effect of the
clipped starting Y coordinate on the starting linear address of the destina-
tion array. When a PIXBLT instruction's starting Y coordinate is specified
to lie in one of the lower two corners of the destination array (when
PBV=1), the TMS34010 uses CONVDP to calculate the linear address
corresponding to the specified starting coordinates.
The value contained in the five LSBs of CONVDP should be the 1 s com-
plement of lo92(DPTCH). When an XY address is specified for the desti-
nation, DPTCH must bea power of two; thus, lo92(DPTCH) is an integer.
During XY -to-linear conversion, the product of the Y value and the desti-
nation pitch is calculated by shifting Y left by lo92(DPTCH).
One instruction, the PIXBLT XY,L instruction, specifies the destination ad-
dress in linear format but also requires DPTCH to be a power of two. This
restriction is necessary when the PBV bit is set to 1.
6-15
CONVSP Source Pitch Conversion Factor
Address C0000130h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I CONVSP I
Description CONVSP is a full 16-bit register that contains a control parameter used
during execution of a pixel operation instruction. CONVSP is used with:
• XY addressing
• Window clipping
• PIXBLTs or FILLS (except for PIXBLT L,L) that process pixels from
the bottom of the array to the top (PBV=1)
CONVSP is calculated as the result of an LMO instruction whose input
operand is the source pitch value in register B1 (SPTCH). The following
assembly code calculates the CONVSP value
LMO B1,AO ; Convert SPTCH value
MOVE AO,@CONVSP ; Place result in CONVSP register
In this example, AO is used as a scratch register. Constant CONVSP has the
value OC0000130h, and the size of Field 0 is 16 bits.
TMS34010 internal hardware uses the CONVSP value during XY -to-linear
conversion of a source address. PIXBLT and FI LL instructions which spe-
cify the source address in XY format use the SPTCH and CONVSP values
to convert the XY coordinates to a linear memory address before actually
beginning the pixel block move. During a PIXBLT or FILL instruction that
requires preclipping of the destination array in the Y direction, the starting
source address is modified to accommodate the resulting changes to the
starting destination address. When a PIXBLT instruction's starting Y coor-
dinate is specified to lie in one of the lower two corners of the destination
array (when PBV=1), the TMS3401 0 uses CONVSP to calculate the linear
address at the corresponding corner of the source array.
The value contained in the five LSBs of CONVSP should be the 1 s com-
plement of 1092(SPTCH). When an XY address is specified for the source,
SPTCH must be a power of two; thus, 1092(SPTCH) is an integer. During
XY -to-linear conversion, the product of the Y value and the source pitch is
calculated by shifting Y left by 1092(SPTCH).
Two instructions that specify the source address in linear format also require
SPTCH to be a power of two. This is necessary when window clipping is
required during execution of either of the following instructions:
• PIXBLT B,XY
• PIXBLT L,XY
It is also necessary when either of these two instructions is executed and
the PBV bit in the CONTROL register is set to 1. If PBV=O and window
clipping is disabled, or if window clipping is enabled but the specified array
does not require preclipping in the Y dimension, CONVSP is not used, and
SPTCH is not required to be a power of two.
6-16
Display Address Register DPYADR
Address C00001EOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I SRFADR I LNCNT I
Fields Bits Name Function
cr1 LNCNT Scan line counter
2-15 SRFADR Screen refresh address
Description The 16-bit DPYADR register contains two separate counters that control
the generation of screen-refresh cycles. A screen-refresh cycle transfers the
video data for a new scan line to the VRAMs' serial data registers.
• LNCNT (Scan line counter, bits 0 and 1)
LNCNT counts the number of scan lines output to the screen between suc-
cessive screen-refresh cycles. Providing explicit control over the line count
permits the implementation of systems that do not reload the VRAMs' in-
ternal serial data register on every horizontal scan line. The two-bit LNCNT
field is loaded from the two-bit LCSTRT field of the DPYSTRT register at
the end of each screen-refresh cycle. The value loaded determines whether
the next screen-refresh cycle occurs after 1, 2, 3 or 4 scan lines:
When LCSTRT = 0, a screen-refresh cycle occurs after every line.
When LCSTRT = 1, 2 or 3, a screen-refresh cycle occurs after every
2, 3 or 4 lines, respectively.
• SRFADR (Screen refresh address, bits 2-15)
SRFADR is the source of the row and column addresses output during a
screen-refresh cycle. The 14 bits of SRFADR are output as logical address
bits 10-23 during screen-refresh cycles. During row address time,
DPYADR4-DPYADR15 are output on LAD0-LAD11, and Os are output on
the remaining LAD pins (except as modified by the contents of the DPYTAP
register). During column address time, DPYADR2-DPYADR7 are output
on LAD6-LAD11 and Os are output on the remaining LAD lines. Following
the completion of each screen-refresh cycle, the value in SRFADR is dec-
remented by the amount indicated in the DUDATE field of the DPYCTL re-
gister.
The following diagrams illustrate the mapping of bits to LAD0-LAD15 from
1) The logical address as seen by the programmer and
2} The bits of the DPYADR register
The bits of a 32-bit logical address are numbered 0 to 31, beginning with
the LSB. The 14 MSBs of DPYADR, shown in Figure 6-2, are output as
logical address bits 10-23 during a screen-refresh cycle. DPYADR2 corre-
sponds to logical address bit 10, DPYADR3 corresponds to logical address
bit 11, and so on.
6-17
DPYADR Display Address Register
15 14 13 12 11 10 9 8 7 8 5 4 3 2 1 0
DPYADR , SRFADR iLNCNT I
I I
I I
Logical
Adar888 123 22 21 20 19 18 17 18 15 14 13 12 11 10 !
Figure 6-2. Correlation Between SRFADR and Logical Address
Bits
Figure 6-3 shows the mapping of logical addresses to LADo-LAD15 during
the row and column address times of the cycle. The symbol xx indicates
status information output with the row and column addresses.
LAD Pin Number
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Logical Row
Address Bits xx 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row
Address
Corresponding Time
DPYADR bits 15 14 13 12 11 10 9 8 7 6 5 4
Logical Column
Address Bits xx xx 29 28 27 14 13 12 11 10 9 8 7 6 5 4 Column
Address
Corresponding Time
DPYADR bits 7 6 543 2
Figure 6-3. Correlation Between DPYADR Bits and Row/Column
Addresses
A board designer typically selects eight consecutive address lines from
LADo-LAD11 to connect to the multiplexed address inputs of the VRAMs.
For example, by selecting the eight lines LAD2-LAD9, bits 14-21 of the
logical address become the row address bits output to the RAMs, and bits
6-13 of the logical address become the column address bits. This means
that during a screen-refresh cycle, bits 6-13 of DPYADR become the row
address bits output to the RAMs, and bits 4-5 of DPYADR become the two
MSBs of the tap point address.
6-18
Display Control Register DPYCTL
Address C0000080h
Bit
Assignments 15 14 13 12 11 10 9 8 7 6 5 4 3 210
DUDATE I Res IHSDI
Fields Bits Name Function
0 HSD Horizontal sync direction
1 Reserved Not used
2-9 DUDATE Display address update
10 ORG Screen origin select
11 SRT Shift register transfer enable
12 SRE Screen refresh enable
13 DXV Disable external video
14 NIL Noninterlaced video enable
15 ENV Enable video
Description The DPYCTl register contains several parameters that control video timing
signals and serial-register transfer cycles using VRAMs.
• HSD (Horizontal sync direction, bit 0)
The HSD bit controls the direction (input or output) of the HSYNC (hori-
zontal sync) pin when the TMS34010 is in external video mode (DXV=O).
If HSD=O, HSYNC is configured as an input, the same as VSYNC. In this
case, the on-chip horizontal sync interval begins when either:
The start of the external horizontal sync pulse input at the HSYNC pin
is detected, or
HCOUNT = HTOTAl,
whichever condition occurs first. VSYNC and HSYNC are configured as in-
puts or outputs according to the values of the HSD and DXV bits:
HSD UXV HSYNC VSYNC
0 0 Input Input
0 1 Output Output
1 0 Output Input
1 1 Undefined
When VSYNC and HSYNC are both configured as inputs, the on-chip vertical
sync interval begins when any of the following conditions occur:
The start of the external vertical sync pulse input at the VSYNC pin is
detected, or
VCOUNT=VTOTAl, and the start of the horizontal sync pulse input
at the HSYNC pin is detected, or
VCOUNT=VTOTAl and HCOUNT=HTOTAL.
6-19
DPYCTL Display Control Register
When VSVNC is an input and HSVNC is an output, the vertical sync interval
begins when either the first or third of the listed conditions occurs.
• DUDATE (Display update amount, bits 2-9)
The DUDATE field indicates the amount by which the SRFADR field in the
DPYADR register is incremented (if ORG=O) or decremented (ORG=1)
following completion of each memory-to-register cycle used to refresh the
screen. DUDATE is loaded with a value containing seven Os and a single
1. The 1 indicates the bit position at which DPYADR is to be incremented
(or decremented if ORG=1).
Increment
DUDATE Size
00000000 0
00000001 1
00000010 2
00000100 4
00001000 8
00010000 16
00100000 32
01000000 64
10000000 128
The increment size is undefined when more than one bit in the DUDATE
field is a 1. When interlaced scan mode is enabled, SRFADR is increment-
ed/decremented by half the value indicated in DUDATE at the start of a
vertical blanking interval preceding the start of an even field, just after
DPYADR2-DPYADR15 have been loaded from DPYSTRT2-DPYSTRT15.
For noninterlaced scanning, DUDATE is programmed to increment the
screen address by one scan line. For interlaced scanning, DUDATE is pro-
grammed to increment the screen address by two scan lines. Larger incre-
ments are typically not used since screen-refresh cycles do not occur more
often than once per active scan line.
• ORG (Screen origin select, bit 10)
The ORG bit controls the origin of the screen coordinate system.
ORG Effect
0 XV coordinate origin located in upper left corner of screen
1 XV coordinate origin located in lower left corner of screen
If ORG =0 then DPYADR is updated by being incremented by the value in
the DUDATE field. If ORG=1 then DPYADR is updated by being decre-
mented by the value in the DUDATE field. Unless explicitly stated other-
wise, the discussion in this document assumes that the default origin
(ORG=O) is used.
6-20
Display Control Register DPYCTL
• SRT (Shift-register-transfer enable, bit 11)
The SRT bit enables conversion of an ordinary pixel access into a VRAM
serial-register transfer cycle.
SRT Effect
0 Pixel access cycles occur normally
1 Pixel access cycles are converted into
VRAM shift-register-transfer cycles
The TMS34010 instruction set includes several instructions (DRAV, PIXT,
LINE, FILL, and PIXBLT) that operate specifically on pixels. By default,
SRT=O and memory accesses performed during accesses of pixel data are
the usual memory read and write cycles. When SRT=1, however, accesses
of pixel data are converted to shift-register-transfer cycles:
A pixel read cycle is converted to a memory-to-register cycle
A pixel write cycle is converted to a register-to-memory cycle
This register-transfer cycle is performed under explicit program control, as
opposed to the screen-refresh cycles enabled by the SRE bit, which are au-
tomatically generated at regular intervals.
Uses of the SRT bit include bulk initialization of the entire VRAM array; the
entire screen can be cleared to a specified background color in only 256
memory cycles. (While the TMS4461 has this capability, not all VRAMs
support this function.) Only pixel accesses are affected by the state of the
SRT bit. Instruction fetches and non-pixel data accesses are not altered in
any way.
• SRE (Screen-refresh enable, bit 12)
The SRE bit enables automatic screen refreshing. Screen refreshes are per-
formed by means of the VRAM memory-to-register cycles which the
TMS34010 performs automatically during selected horizontal blanking in-
tervas. The frequency of screen-refresh cycles and the generation of the
addresses output during these cycles are programmed by means of the
DPYSTRT and DPYCTL registers.
SRE Effect
0 Disable screen refresh
1 Enable screen refresh
Changing the value of the SRE bit affects screen refreshes with the start of
the next horizontal blanking interval. When SRE changes from 0 to 1, the
first screen-refresh cycle occurs at the start of the next horizontal blanking
level. When SRE changes from 1 to 0, screen-refresh cycles are disabled
beginning at the start of the next horizontal blanking level.
6-21
DPYCTL Display Control Register
• DXV (Disable external video, bit 13)
The DXV bit selects between internally generated or externally generated
video timing.
DXV Effect
0 Selects external video source
1 Selects internally generated video timing
When DXV=O, the TMS3401 0 video timing circuitry is programmed to lock
onto an external video source. The VSYNC pin is configured as an input and
is connected to an external vertical sync signal. If HSD=O, HSYNC is also
configured as an input and is connected to an external horizontal sync sig-
nal.
When DXV=1, the TMS3401 0 generates its own video timing, according to
the values loaded into the video timing registers. The HSYNC and VSYNC
pins are configured as outputs, and provide the horizontal and vertical sync
signals required to drive the video monitor.
• Nil (Noninterlaced video enable, bit 14)
The NIL bit selects between an interlaced or a noninterlaced display. The
video timing signals output by the TMS3401 0 are modified according to this
selection. The timing differences between interlaced and non interlaced
displays are described in Section 9.
NIL Effect
0 Selects interlaced video timing
1 Selects non interlaced video timing
• ENV (Enable video, bit 15)
The ENV bit enables or disables the video display. The display remains
blanked when ENV=O. During this time, the signal output at the BLANK pin
is forced to remain at its active-low level throughout the frame, and setting
of the DIP (display interrupt) bit in the INTPEND register is inhibited. (If
DIP is already set at the time the ENV is changed from 1 to 0, DIP remains
set until explicitly cleared.) When ENV=1, the video display is enabled. The
BLANK output signal is controlled according to the parameters contained in
the video timing registers, and the DIP bit becomes set when the condition
VCOUNT = DPYINT occurs.
ENV Effect
0 Blank entire screen
1 Enable video
6-22
Display Interrupt Register DPYINT
Address COOOOOAOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I DPYINT I
Description The DPYI NT register designates the next scan line at which a display in-
terrupt will be requested. This register facilitates the coordination of soft-
ware activity with the refreshing of selected horizontal lines on the screen
of a video monitor.
The contents of DPYINT are compared to the VCOUNT register. When
VCOUNT = DPYINT, a display interrupt is requested and the DIP bit in the
INTPEND register is set to 1. This coincides with the start of the horizontal
blanking interval that marks the end of the line designated by the value
contained in DPYINT.
For split-screen applications, a new value can be loaded into the DPYADR
register immediately following detection of the 0-to-1 transition of DIP.
The new DPYADR value will not affect the line that immediately follows the
end of the current horizontal blanking interval, but will affect the next line.
The details of this timing are as follows. A screen-refresh cycle may be
scheduled to occur at the start of the same horizontal blanking interval
during which DIP becomes set. At the end of the screen-refresh cycle, the
screen-refresh address in the DPYADR register will be automatically incre-
mented. Requests for screen-refresh cycles have a higher priority than re-
quests for cycles initiated by the on-chip processor. Hence, if the processor
loads a new value into DPYADR immediately following detection of DIP's
transition from 0 to 1, the value will become the address used for the next
screen-refresh cycle, which cannot occur before the next horizontal blank-
ing interval. Between the time that DIP becomes set to 1 and the com-
pletion of the next screen-refresh cycle at least one full scan line later, the
DPYADR register is guaranteed not to be incremented. Its contents will
change during this interval only if it is loaded with a new value under ex-
plicit program control. The display interrupt is disabled when the ENV bit
in the DPYCTL register is O.
6-23
DPYSTRT Display Start Address Register
Address C0000090h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I SRSTRT I LCSTRTI
Fields Bits Name Function
0-1 LCSTRT Starting line count
2-15 SRSTRT Starting screen-refresh address
Description The DPYSTRT register contains two parameters that control the automatic
memory-to-register cycles necessary to refresh the screen.
• LCSTRT (Starting line count, bits 0 and 1)
LCSTRT is a two-bit code designating the number of scan lines to be dis-
played between screen refreshes.
Scan Lines
LCSTRT Between
Value Refresh
Cycles
00 1
01 2
10 3
11 4
LCSTRT is loaded into the LNCNT field of the DPYADR register at the end
of each screen-refresh cycle. LCSTRT is also loaded into LNCNT at the start
of the last horizontal blanking interval preceding the first active scan line of
a new frame.
• SRSTRT (Starting screen-refresh address, bits 2-15)
The 14-bit SRSTRT field contains the starting address loaded into the
DPYADR register at the start of each frame. Its value identifies the start of
the region of the graphics bit map to be displayed on the screen. SRSTRT
is loaded into the SRFADR field of the DPYADR register at the beginning
of each vertical blanking interval. (Loading occurs coincides with the start
of the horizontal blanking interval at the end of the last active scan line in
the frame.)
The sense of the SRSTRT value depends on the value of the ORG (origin
select) bit in the DPYCTL register. When ORG=O, SRSTRT is loaded with
the 1's complement of the starting address. When ORG=1, SRSTRT is
loaded with the unmodified starting address. Regardless of the value of the
ORG bit, the starting address points to the location in memory of the first
pixel output to the screen during each frame. For a typical CRT display, the
first pixel of each frame is output to the top left corner of the screen. Refer
to the description of the DPYADR register for mo~e information on the
generation of screen-refresh addresses.
6-24
Display Tap Point Address Register DPYTAP
Address C00001BOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
IReserved I DPYTAP
Fields Bits Name Function
0-13 DPYTAP Display tap point address
14-15 Reserved Not used
Description The DPYTAP register contains a VRAM tap point address output during a
screen-refresh (memory-to-register) cycle. (The contents of DPYTAP are
not output during a serial-register transfer initiated under program control
while the SRT bit in the DPYCTL register is set to 1.) During a screen-
refresh cycle, the 16 bits of the DPYTAP register are bitwise-ORed with the
value output at the LADo-LAD15 pins during the column address time.
DPYTAP bit 0 is ORed with LADO, DPYTAP bit 1 is ORed with LAD1, and
so on. This means that the column address output during the cycle is the
OR of bits 2-7 of DPYADR and bits 0-15 of DPYTAP.
One application of the DPYTAP register is to permit horizontal panning of
the screen over a frame buffer that is wider than the screen. A DPYTAP
value of 0 locates the scree~ at its leftmost position within the frame buffer.
Incrementing DPYTAP causes the display to pan to the right through the
frame buffer.
DPYTAP is typically used to alter (set to a value other than all Os) only
those column address bits of the SRFADR field of DPYADR that are never
incremented. For instance, given a VRAM that requires an 8-bit column
address, assume that SRFADR alternately sets the two MSBs of the column
address to 002, 012, 102, and 112. In this case, DPYTAP should contain
1 s only in the bit positions corresponding to the six LSBs of the column
address.
6-25
HCOUNT Horizontal Count Register
Address C00001 COh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I HCOUNT
Description The HCOUNT register is a 16-bit counter used in the generation of the
horizontal sync and blanking signals. HCOUNT is incremented on the fail-
ing edge of the video input clock, and is used to count the number of video
clock periods per horizontal scan line. To generate horizontal sync and
blanking signals, the value of HCOUNT is compared to the value of the four
horizontal timing registers: HESYNC, HEBLNK, HSBLNK, and HTOTAL.
When external sync mode is disabled and the value in HCOUNT = HTO-
TAL, HCOUNT is reset to 0 on the next VCLK falling edge and the HSYNC
output is driven active low. HCOUNT is also reset to 0 if the external sync
mode is enabled and the input signal HSYNC is driven low.
Two separate, asynchronous elements of the TMS3401 0 logic can access
the HCOUNT register:
• The internal processor, which runs synchronously to local clocks
LCLK1 and LCLK2, can access HCOUNT as an I/O register.
• The video timing control logic, which runs synchronously to the video
clock VCLK, increments and clears HCOUNT in generating the sync
and blanking signals.
No synchronization between these two subsystems is provided, and
HCOUNT can only be reliably read or written to while VCLK is held at the
logic-high level. HCOUNT is typically not read or written to except during
chip test.
6-26
Horizontal End Blank Register HEBlNK
Address C0000010h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I HEBLNK
Description The HEBLNK register is used during the generation of the blanking signal
output to the video monitor. The 16-bit value loaded into HEBLNK is
compared to HCOUNT, and designates the point at which the horizontal
blanking interval ends. The blanking signal output at the BLANK pin is a
composite of the internal horizontal and vertical blanking signals. When the
value in HCOUNT = HEBLNK, the BLANK output is driven inactive high
unless vertical blanking is currently active. Most video monitors require
HEBLNK to be set to a value that is less than the value in HSBLNK, but
greater than the value in HESYNC.
6-27
HESYNC Horizontal End Sync Register
Address COOOOOOOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I HESYNC I
Description The HESYNC register is used during generation of the horizontal sync sig-
nal output to the video monitor. The 16-bit value loaded into HESYNC
determines the point at which the horizontal sync pulse ends. When the
value in HCOUNT = HESYNC, the signal output from the HSYNC pin is
driven inactive high to signal the end of the horizontal sync interval. Typical
monitors require that HESYNC be set to a value less than the value con-
tained in the HEBLNK register. (However, the HESYNC value is not re-
quiredto be less than the HEBLNK value.) The minimum value of HESYNC
is O.
When external video is enabled and the HSYNC pin is configured as an in-
put, HESYNC should be loaded with a value that ensures that the condition
HCOUNT = HESYNC occurs after the external HSYNC signal has gone in-
active-high, but before HSYNC goes active low again. For example, a good
HESYNC value might be the average of the values in HEBLNK and
HSBLNK.
6-28
Horizontal Start Blank Register HSBLNK
Address C0000020h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I HSBLNK
Description The HSBLNK register is used during generation of the blanking signal out-
put to the video monitor. The 16-bit value in HSBLNK is compared to
HCOUNT, and designates the point at which the horizontal blanking inter-
val begins. The blanking signal output at the BLANK pin is a composite of
the internal horizontal and vertical blanking signals. When the condition
HCOUNT = HSBLNK occurs, the BLANK output is driven from its inac-
tive-high level to its active-low level (unless it is already low due to vertical
blanking being active).
Several internal events coincide with the start of horizontal blanking. First,
when a screen-refresh cycle is programmed to occur during a particular
horizontal scan line, a request for the cycle is sent to the memory controller
at the beginning of the horizontal blanking interval that occurs at the end
of the line. Second, if a display interrupt request is programmed to occur
during a particular horizontal scan line, the request is generated at the start
of horizontal blanking. Typical monitors require that HSBLNK be set to a
value that is less than the value in HTOTAL, but greater than the value in
HEBLNK.
6-29
HSTADRH Host Interface Address Register, High Word
Address COOOOOEOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I HSTADRH I
Description The HSTADRH register contains the 16 MSBs of a 32-bit pointer address;
the 16 LSBs are contained in HSTADRL. The contents of HSTADRL and
HSTADRH are concatenated to form a single 32-bit address during an in-
direct access by a host processor. The pointer address can be accessed by
both the host processor and the TMS3401 O. The host accesses the pointer
address through two 16-bit host interface registers that are mapped into the
host's memory or I/O address space.
The four LSBs of the 32-bit pointer address are forced to 0 to point to an
even word boundary in memory. If the address pointer is incremented past
the largest word address in memory, it will wrap around to the lowest ad-
dress (aliOs).
When you use the HSTADRH and HSTADRL registers to read data indi-
rectly from the host, be sure that you access them in the correct order. If
LBL=O, HSTADRH should be written last. If LBL=1, HSTADRL should
be written last.
Note:
When the TMS34010's on-chip processor writes to HSTADRH or
HSTADRL, the referenced data is not automatically read into
HSTDAT A. For more information about the host interface, refer to
Section 10.
6-30
Host Interface Address Register, Low Word HSTADRL
Address COOOOODOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I HSTADRL
Description The HSTADRL register contains the 16 LSBs of a 32-bit pointer address;
the 16 MSBs are contained in HSTADRH. The contents of HSTADRL and
HSTADRH are concatenated to form a single 32-bit address during an in-
direct access by a host processor. The pointer address can be accessed by
both the host processor and the TMS3401 O. The host accesses the pointer
address through two 16-bit host interface registers that are mapped into the
host's memory or I/O address space.
The four LSBs of the 32-bit pointer address are forced to 0 to point to an
even word boundary in memory. If the address pointer is incremented past
the largest word address in memory, it will wrap around to the lowest ad-
dress (a II Os).
When you use the HSTADRH and HSTADRL registers to read data indi-
rectly from the host, be sure that you access them in the correct order. If
LBL=O, HSTADRH should be written last. If LBL=1, HSTADRL should
be written last.
Note:
When the TMS34010's on-chip processor writes to HSTADRH or
HSTADRL, the referenced data is not automatically read into
HSTDATA. For more information about the host interface, refer to
Section 10.
6-31
HSTCTLH Host Interface Control Register, High Byte
Address C0000100h
Bit
Assignments 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I HLT I CF I LBL HNCRllNCwl Res INMIMI NMII Reserved
Fields Bits Name Function
0-7 Reserved Not used
8 NMI Nonmaskable interrupt
9 NMIM Mode bit for NMI
10 Reserved Not used
11 INCW Increment pointer address on write
12 INCR Increment pointer address on read
13 LBL Lower byte last
14 CF Cache flush
15 HLT Halt TMS3401 0 processing
Description The HSTCTLH register contains seven programmable bits used to control
host interface communications. A host processor can access the control
bits in the HSTCTLL and HSTCTLH registers as a single host interface re-
gister, HSTCTL. The bits of the host interface's HSTCTL register are
mapped into two separate I/O register locations in the TMS3401 O's mem-
ory map, HSTCTLL and HSTCTLH, to allow the TMS3401 0 to alter the bits
in one location without affecting the bits in the other.
The HSTCTLH bits can be both written to and read by both the host pro-
cessor and the TMS3401 O. Unpredictable results occur if the TMS3401 0
and host simultaneously write different values to the HSTCTLH bits. Typi-
cally only the host alters the bits in HSTCTLH.
• NMI (Nonmaskable interrupt, host to TMS34010, bit 8)
The nonmaskable interrupt allows the host processor to redirect the exe-
cution flow of TMS3401 0 processing to an N M I routine, regardless of the
current state of the interrupt mask flags. The host writes a 1 to the NMI bit
to send a nonmaskable interrupt request to the TMS3401 O. The interrupt
request cannot be disabled, and will always be executed (unless the
TMS34010 is reset before it can complete interrupt execution). The inter-
rupt is initiated immediately upon NMI becoming set (at the time the current
instruction completes execution, or in the case of a pixel array instruction,
at the next interruptible point in the instruction). Once the interrupt is taken,
internal logic automatically clears the NMI bit to O.
One use of the NMI is to generate a soft reset after the host downloads new
program code into TMS34010 memory. Following execution of a non-
maskable interrupt, screen-refresh and DRAM -refresh functions continue
unaffected. The contents of internal. registers other than the HSTCTL reg-
ister are not altered by the interrupt, although they can be modified by the
N M I service routine.
6-32
Host Interface Control Register, High Byte HSTCTLH
• N M I M (Nonmaskable interrupt mode, bit 9)
The N M I mode bit determines whether or not the context of the interrupted
program is saved when a nonmaskable interrupt occurs. When N M I M =0,
the context is saved on the system stack before the NMI service routine is
executed. When NMIM=1, the context is discarded when the NMI service
routine is executed.
The NMIM=O mode supports applications such as single stepping of in-
structions where the status and PC must be preserved between consecutive
nonmaskable interrupts. When NMIM=1, a nonmaskable interrupt can be
used to simulate a hardware reset in software (using the NMI vector).
Saving the context may be of no benefit if either:
Control is never to be returned to the interrupt program or
The integrity of the stack pointer is suspect.
The nonmaskable interrupt does not cause the I/O registers to be reset.
Consequently, if an NMI is used to simulate a hardware reset, the I/O reg-
isters should be reset by software within the NMI service routine.
NMI NMIM Effect
0 0 No effect
0 1 Undefined
1 0 NMI (save context on stack)
1 1 NMI (discard previous context)
• C F (Cache flush, bit 14)
While CF is set to 1, the contents of the instruction cache are flushed. All
four P (present) flags in the cache control logic remain forced to 0 as long
as CF remains 1. When CF=1, the cache is disabled; instruction words are
fetched from local memory one at a time as they are needed for execution
by the TMS3401 O. Normal cache operation resumes when CF is set to 0,
assuming the CD bit in the CONTROL register is also O. When the value of
CF is changed from 1 to 0, the cache begins operation in the same initial
state as that which immediately follows reset.
One use of the CF bit is during downloads of new software from the host
processor to TMS34010 local memory. By setting CF to 1 and then to 0
again, the host processor forces the TMS34010 to begin to load new in-
structions into the cache from memory rather than continue execution of
stale instructions already contained in the cache. A 0 must be loaded into
CF for normal cache operation to resume.
CF Effect
0 No effect
1 Flush and disable cache
6-33
HSTCTLH Host Interface Control Register, High Byte
• LBL (Lower byte last, bit 13)
The LBL bit specifies whether an indirect access of TMS34010 memory,
initiated by a host register access, begins when the upper or lower byte of
the register is accessed by the host processor.
LBL is provided to accommodate host processors with 8-bit data paths.
An 8-bit processor must access a 16-bit TMS3401 0 host interface register
as a series of two 8-bit bytes. Processors which access the lower byte (bits
0-7) first and the upper byte (bits 8-15) second should typically set LBL to
0, and those that access bytes in the opposite sequence should set LBL to
1.
When LBL is 0, a local bus cycle is initiated if:
The host writes to the upper byte of HSTADRH, or
The host reads from or writes to the upper byte of HSTDAT A.
If LBL is 1, a local bus cycle is initiated if
The host accesses the lower byte of HSTDATA, or
The host writes to the lower byte of HSTADRL
With this capability, the TMS3401 0 is capable of automatically resolving so
called "Little- Endian/Big- Endian" byte addressing incompatibilities be-
tween various processors, and promotes software transparency between 8-
and 16-bit versions of the same processor architecture (such as the 8088
and 8086).
LBL Effect
0 Initiate 16-bit local bus cycle on host access of upper byte of HSTDATA
or on load of upper byte of HSTADRH
1 Initiate 16-bit local bus cycle on host access of lower byte of HSTDATA
or on load of lower byte of HSTADRL
• INCR (Increment address before local read, bit 12)
The INCR bit controls whether or not the 32-bit address pointer contained
in the HSTADRL and HSTADRH registers is incremented before each read.
INCR Effect
0 Do not increment address pointer before read cycle on local memory bus
1 Increment address pointer before read cycle on local memory bus
When INCR=1, the 32-bit address contained in registers HSTADRL and
HSTADRH is incremented by 16 before being used for the next read of the
TMS34010 memory. This means that HSTDATA is updated to the contents
of the next sequential word in the local memory in preparation for the next
anticipated read of HSTDATA by the host processor. A local read cycle also
occurs when the host loads a new address into the HSTADRL and
HSTADRH registers, but the address is not incremented in this case. When
incrementing is enabled, repeated reads of the HSTDATA register by the
6-34
Host Interface Control Register, High Byte HSTCTLH
host result in a series of adjacent words in TMS3401 0 memory being read;
otherwise, the same memory word is read each time. Regardless of the va-
lue of the INCR bit, each time HSTDATA is read by the host, a new word
is automatically read into HSTDATA from the TMS3401 O's memory.
• INeW (Increment address after local write, bit 11)
The INCW bit controls whether or not the 32-bit address pointer contained
in the HSTADRL and HSTADRH registers is incremented after each write.
INew Effect
0 Do not increment address pointer after write cycle on local memory bus
1 Increment address pointer after write cycle on local memory bus
When INCW=1, the 32-bit address contained in registers HSTADRL and
HSTADRH is incremented by 16 after being used as the memory write ad-
dress. When incrementing is enabled, repeated writes to the HSTDATA re-
gister by the host cause a series of adjacent words in TMS34010 memory
to be modified; otherwise, the same memory word is modified repeatedly.
Regardless of the value of the INCW bit, each time HSTDATA is written to
by the host, a new cycle is initiated to write the contents of HSTDATA to
the TMS3401 O's memory.
• HlT (Halt TMS34010 program execution, bit 11)
When the HLT bit is set to 1, the TMS3401 0 suspends instruction process-
ing at the next instruction boundary. Once halted, the TMS3401 0 does not
respond to interrupt requests (including NMI). Local memory refresh and
video timing functions continue unaffected while the TMS3401 0 is halted.
When HLT is again set to 0, the TMS3401 0 continues execution.
While the TMS3401 0 is halted, external bus-master devices can arbitrate for,
obtain, and release control of the local bus via the TMS34010 hold inter-
face. While the TMS3401 0 is in the hold state, it cannot perform DRAM-
refresh or screen -refresh cycles.
The state of the H LT bit immediately following reset is determined by the
state of the HCS pin at the time of the low-to-high transition of RESET:
If HCS is low, HLT is set to 0, and the TMS3401 0 is enabled to begin
executing its reset routine.
If HCS is high, HLT is set to 1, and the TMS3401 0 is halted.
Both the host processor and TMS3401 0 can write to the H LT bit; this means
the TMS3401 0 can halt itself by loading a 1 into H LT.
HLT Effect
0 Allow TMS3401 0 to run
1 Halt TMS3401 0 instruction execution
6-35
HSTCTLL Host Interface Control Register, Low Byte
Address COOOOOFOh
Bit
Assignments 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I Reserved
16~~1 MSGOUT III~TI MSGIN
Fields Bits Name Function
0-2 MSGIN Input message buffer
3 INTIN Input interrupt bit
4-6 MSGOUT Output message buffer
7 INTOUT Output interrupt bit
8-15 Reserved Not used
Description The HSTCTLL register contains eight programmable bits used to control
host interface communications. A host processor can access the control
bits in the HSTCTLL and HSTCTLH registers as a single host interface re-
gister, HSTCTL. The bits of the host interface's HSTCTL register are
mapped into two separate I/O register locations in the TMS3401 O's mem-
ory map, HSTCTLL and HSTCTLH, to allow the TMS3401 0 to alter the bits
in one location without affecting the bits in the other.
The HSTCTLH bits can be read by both the host processor and the
TMS34010. The following restrictions apply to writes:
• The MSGOUT field can be modified only by the TMS3401 O.
• The MSGIN field can be modified only by the host.
• The host can write a 1 to the INTI N bit, but writing a 0 has no effect.
• The TMS34010 can write a 0 to the INTIN bit, but writing a 1 has no
effect.
• The TMS3401 0 can write a 1 to the INTOUT bit, but writing a 0 has
no effect.
• The host can write a 0 to the INTOUT bit, but writing a 1 has no ef-
fect.
Internal arbitration logic permits the TMS3401 0 and host processor to ac-
cess HSTCTLL at the same time without hazard. Synchronization of asyn-
chronous signals at the host interface pins is performed internally.
• MSGIN (Message in, host to TMS34010, bits 0-2)
The MSGIN field buffers a 3-bit interrupt message to the TMS3401 0 from
the host. The MSGIN field can be both written to and read by the host, but
only read by the TMS3401 O. The MSGIN field typically contains a com-
mand or status code from the host, which is read by the TMS3401 0 in re-
sponse to a host-generated interrupt (INTIN=1). The meaning of this code
is defined in the software of the host and TMS3401 O.
6-36
Host Interface Control Register, Low Byte HSTCTLL
• INTIN (Interrupt in, host to TMS34010, bit 3)
The INTIN bit controls the interrupt request to the TMS3401 0 from the host.
To generate an interrupt request, the host processor loads a 1 to INTIN. The
TMS34010 deactivates the request by loading a 0 to INTIN. An attempt by
the host to load a 0 to INTIN has no effect. Similarly, an attempt by the
TMS34010 to load a 1 to INTIN has no effect. A read-only copy of the
INTIN bit is available as the HIP bit in the INTPEND register. The HIP bit
faithfully represents the state of the INTI N bit at all times.
INTIN Effect
0 No interrupt request to TMS3401 0
1 Send interrupt request to TMS3401 0
• MSGOUT (Message out, TMS34010 to host, bits 4-6)
The MSGOUT field buffers a 3-bit interrupt message to the host from the
TMS34010. The MSGOUT field can be both written to and read by the
TMS34010, but only read by the host. The MSGOUT field permits an in-
terrupt request generated by means of the INTOUT bit to be qualified by an
additional command or status code, the meaning of which is defined in the
software of the host and TMS3401 O.
• INTOUT (Interrupt out, TMS34010 to host, bit 7)
The INTOUT bit controls the interrupt request to the host processor from the
TMS34010. An interrupt request is transmitted to the host by means of an
active-low level on the HINT pin. When INTOUT is 1, HINT is driven active
low; when INTOUT is 0, HINT is driven inactive high. The TMS3401 0 acti-
vates the interrupt request by loading a 1 to INTOUT, and the host deacti-
vates the interrupt request by loading a 0 to INTOUT. An attempt by the
TMS34010 to load a 0 to I NTOUT has no effect. Similarly, an attempt by
the host to load a 1 to INTO UT has no effect.
INTOUT Effect
0 No interrupt request to host
1 Send interrupt request to host
6-37
HSTDATA Host Interface Data Register
Address COOOOOCOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I HSTDATA I
Description The HSTDATA register buffers data transferred through the host interface
between TMS34010 local memory and a host processor. HSTDATA can
be accessed by the TMS3401 0 at address COOOOOCOh. It is one of the four
16-bit registers that can be accessed by the host register through the
TMS34010 host interface. HSTDATA is typically accessed by the host
rather than the TMS34010. Using the HSTDATA register, the host can ei-
ther read the TMS3401 O's memory or write to it. The host initiates the in-
direct access through the host interface using the 32-bit pointer address in
the HSTADRL and HSTADRH registers. During each indirect access, a
16-bit word is transferred between the HSTDATA register and TMS3401 0
memory. The host processor can access the contents of the HSTDATA re-
gister in one 16-bit data transfer or two 8-bit transfers. When the
TMS34010's on-chip processor reads from or writes to HSTDATA, no au-
tomatic read or write cycle takes place between HSTDATA and the memory
word pointed to by HSTADRL and HSTADRH.
6-38
Horizontal Total Register HTOTAL
Address C0000030h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I HTOTAL
Description The HTOTAl register is used during generation of the horizontal sync signal
output to the video monitor from the TMS3401 O. It determines the dura-
tion of each horizontal scan line on the screen in terms of the number of
VClK (video clock) periods. The contents of HTOTAl are compared with
the horizontal count in HCOUNT to determine the point at which the hori-
zontal sync pulse begins, which also represents the beginning of a new
scan line. HCOUNT counts from 0 to the value contained in HTOTAL.
When HCOUNT = HTOTAl, the HSYNC output is driven active low on the
next falling edge of the VClK signal, and HCOUNT is reset to 0 on the same
clock edge.
HTOTAl is loaded with a 16-bit value greater than that contained in
HSBlNK, but less than or equal to 65535. In interlaced scan mode, the
value in HTOTAl should be an odd number (lSB=1) to achieve equal
spacing between adjacent scan lines. The total number of VClK video
clocks in each horizontal scan line is calculated as HTOTAl + 1. When
external sync mode is enabled (DXV=O) and HSYNC is configured as an
input (HSD=O), HTOTAl should be loaded with a value greater than the
value of HCOUNT at the point at which the external sync pulse is expected.
If the external sync pulse does not occur, HCOUNT will be reset when
HCOUNT = HTOTAL.
6-39
INTENB Interrupt Enable Register
Address C0000110h
Bit
Assignments 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I Reserved IwvEI DIE I HI§ Reserved
Fields Bits Name Function
0 Reserved Not used
1 X1E External interrupt 1 enable
2 X2E External interrupt 2 enable
3-8 Reserved Not used
9 HIE Host interrupt enable
10 DIE Display interrupt enable
11 WVE Window-violation interrupt enable
12-15 Reserved Not used
Description The I NTEN B register contains the interrupt mask used to selectively enable
the three internally and two externally generated interrupt requests. The
following interrupts are enabled by the INTENB register:
• External interrupts 1 and 2 are generated by active-low signals on the
input pins L1NT1 and L1NT2, respectively.
• The host interrupt is generated when the host processor sets the IN-
T N bit in the HSTCTL register to 1.
• The display interrupt is generated when the vertical count in the
VCOUNT register reaches the value contained in the DPYINT register.
• The window-violation interrupt is caused by an attempt to write a
pixel to a region of the bit map lying outside the limits of the cur-
rently-defined window.
The status register contains a global interrupt enable bit, I E. The I NTEN B
register contains individual interrupt enable bits associated with each of the
interrupts (X1 E, X2E, HIE, DIE, and WVE). Interrupts are enabled through
a combination of setting the IE bit and the appropriate bit in the INTENB
register. When IE=O, all interrupts are disabled regardless of the values of
the bits in the INTENB register. When IE=1, each interrupt is enabled or
disabled according to the corresponding enable bit in the INTENB register
(1 enables the interrupt, 0 disables it).
6-40
Interrupt Pending Register INTPEND
Address C0000120h
Bit
Assignments 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I Reserved Iwvpl DIP IHlrl Reserved
Fields Bits Name Function
0 Reserved Not used
1 X1P External interrupt 1 pending
2 X2P External interrupt 2 pending
3-8 Reserved Not used
9 HIP Host interrupt pending
10 DIP Display interrupt pending
11 WVP Window-violation interrupt pending
15-12 Reserved Not used
Description The INTPEND register indicates which interrupt requests are currently
pending. INTPEND's six active bits indicate the status of the following in-
terrupts:
• External interrupts 1 and 2 are generated by active-low signals on the
input pins L1NT1 and L1NT2, respectively.
• The host interrupt request is generated when the host processor sets
the INTIN bit in the HSTCTL register to 1.
• The display interrupt request is generated when the vertical count in
the VCOUNT register reaches the value contained in the DPYINT re-
gister.
• The window-violation interrupt request is caused by an attempt to
write a pixel to a region of the bit map lying inside or outside the limits
of the currently-defined window, depending on the selected win-
dowing mode.
The individual pending bits in the INTPEND register reflect the status of
interrupt requests. The interrupt is requested if the corresponding pending
bit is 1. There is no request if the pending bit is O. The status of each in-
terrupt request is reflected in the INTPEND register regardless of whether
the interrupt is enabled or not; this allows the TMS3401 0 to poll interrupts.
The X1 P and X2P bits of INTPEND are read only. They reflect the input
levels on the L1NT1 and L1NT2 pins, and are not affected when the INTPEND
register is written to. The L1NT1 and L1NT2 pins are asynchronous inputs,
but the signals to these pins are synchronized internally so that the X1 P and
X2P bits in the INTPEND register may be reliably read at any time. If an
external interrupt is disabled, the interrupt request is ignored, even though
the corresponding pending flag in I NTPEN D is set. The interrupt will be
taken by the TMS34010 only if the external request is maintained at the
corresponding interrupt request pin until the interrupt is again enabled.
6-41
INTPEND Interrupt Pending Register
The DIP and WVP bits in the INTPEND register reflect the status of interrupt
requests generated by conditions internal to the TMS3401 O. These two bits
are implemented as latches. Once set, DIP or WVP will remain set until a
o is written to it (or the TMS3401 0 is reset). Writing a 1 to either of these
bits has no effect at any time. While an internal interrupt is disabled, the
interrupt request is ignored, even though the corresponding pending flag
in INTPEND is set. If the interrupt is subsequently enabled while the in-
terrupt pending flag remains set (because of a prior interrupt request) then
the interrupt will be taken by the TMS3401 O.
The HIP bit in the INTPEND register is a read-only bit that always displays
the current contents of the INTIN bit in the HSTCTL register. Writing to the
INTPEND register has no effect on the HIP bit. A host interrupt request is
generated when the host processor writes a 1 to the I NT! N bit of the
HSTCTL register. The TMS3401 0 clears the interrupt request by writing a
o to the INTI N bit.
6-42
Plane Mask Register PMASK
Address C0000160h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I PMASK
Description The PMASK register selectively enables or disables various planes in the
bit map of a display system in which each pixel is represented by multiple
bits. PMASK contains a 16-bit value that determines which bits of each
pixel can be modified during execution of a DRAV, PIXT, FILL, LINE, or
PIXBLT instruction. Via the PMASK register, the programmer specifies
which bits within each pixel are protected (mask bit=1) and not protected
(mask bit=O) from modification. During a pixel write operation, the Os in
the plane mask represent bit positions within the destination pixel that are
to be modified by the pixel operation. The 1 s in the plane mask represent
bit positions in the destination pixel that are protected from modification.
During a pixel read operation, the Os in the mask indicate which bits within
a pixel may be read; bits corresponding to 1 s in the mask are always read
as Os.
The organization of a display memory is sometimes described in terms of
bit planes. If the pixel size is four bits, for example, and the bits in each
pixel are numbered from 0 to 3, the display memory is said to be composed
of four bit planes, numbered from 0 to 3. Plane 0 contains all the bits
numbered 0 from all the pixels, plane 1 contains all the bits numbered 1
from all the pixels, and so on. A 4-bit mask is constructed such that bit 0
of the mask enables (if 0) or disables (if 1) writes to the bits in plane 0,
mask bit 1 enables or disables writes to plane 1, and so on.
The plane mask for a 4-bit pixel is four bits; the plane mask for an 8-bit pixel
is eight bits; and so on. The plane mask must be replicated throughout the
16 bits of the PMASK register. For example, with four bits per pixel, the
PMASK register is loaded with four identical copies of the corresponding
4-bit plane mask, as indicated below.
15 12 11 8 7 43 o
PMASK I MASK I MASK I MASK I MASK
With a pixel size of eight bits, the corresponding 8-bit plane mask is repli-
cated twice - once in bits 0-7 of PMASK, and again in bits 8-15. In gen-
eral, all 16 bits of the register are used, and a mask for a pixel size of less
than 16 bits must be duplicated n times, where n is 16 divided by the pixel
size.
The individual bits of the PMASK register are associated with the corre-
sponding bits of the 16-bit local data bus (data are in fact multiplexed over
the same LADo-LAD15 pins as addresses). PMASK register bit 0 is asso-
ciated with bit 0 of the data bus (the bit transferred on LADO), PMASK bit
1 is associated with bit 1 of the data bus, and so on. In general, if PMASK
bit n is a 0, then bit n of the data bus is enabled by the mask; if PMASK
bit n is a 1, bit n is disabled by the mask.
Plane masking is effectively disabled (allowing all bits of each pixel to be
modified) by loading aliOs into the PMASK register. This is the default
state of PMASK following reset.
6-43
PMASK Plane Mask Register
To maintain upward compatibility with future versions of the GSP, software
drivers should treat the PMASK register as a 32-bit register beginning at
address C0000160h. In other words, software should write the plane mask
value not only to the 16-bit word at address C0000160h, but also to the
word at C0000170h. Writing the second word will have no effect on the
TMS34010, but will ensure software compatibility with future graphics
processors which may extend the PMASK register from 16 to 32 bits.
6-44
Pixel Size Register PSIZE
Address C0000150h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I PSIZE I
Description The PSIZE register is used to specify the pixel size in bits. If the pixel size
is four, for example, PSIZE is loaded with the value four. If the pixel size
is eight, PSIZE is loaded with the value eight, and so on. All 16 bits of the
PSIZE register can be written to or read. Legal pixel sizes are 1, 2, 4, 8, and
16 bits; any other value of PSIZE is undefined.
PSIZE Pixel Size
0OO1h 1 bit/pixel
0OO2h 2 bits/pixel
0OO4h 4 bits/pixel
0OO8h 8 bits/pixel
0010h 16 bits/pixel
6-45
REFCNT Refresh Count Register
Address C00001FOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I ROWADR RINTVL I Reservedl
Fields Bits Name Function
0-1 Reserved Not used
2-7 RINTVL Refresh interval
8-15 ROWADR Row address
Description The REFCNT register generates the addresses output during DRAM refresh
cycles and counts the intervals between successive DRAM refresh cycles.
DRAMs require periodic refreshing to retain their data. The TMS34010
automatically generates DRAM refresh cycles at regular intervals. The in-
terval between refresh cycles is programmable. The DRAM refresh mode
is selected by loading the appropriate value to the two-bit RR (refresh rate)
field in the CONTROL register. DRAM refreshing can be disabled in sys-
tems that do not require it. The modes are defined as follows.
RR Description
00 Refresh every 32
local clock periods
01 Refresh every 64
local clock periods
10 Reserved for future
expansion
11 No DRAM refreshing
At reset, the RR field is set to the initial value 002. During the time that the
reset signal to the TMS3401 0 is active, no DRAM-refresh cycles are per-
formed.
Bits 2-15 of REFCNT form a continuous binary counter. Bits 2-7 form the
RINTVL field, which counts the intervals between successive requests for
DRAM-refresh cycles. When RR=012, the RINTVL field is decremented
by 1 every local clock cycle; that is, the register is decremented at bit 2. This
means that RINTVL underflows into ROWADR (a borrow ripples from bit
7 to bit 8 of REFCNT) every 64 local clock cycles. The underflow has two
effects:
• ROWADR is decremented by 1 and
• A request for a DRAM-refresh cycle is sent to the memory control
logic.
When RR=002, the RINTVL field is decremented by 2 every local clock
period. This means that a DRAM-refresh cycle is generated every 32 local
clock periods, twice the rate that results when RR=012. When RR=112,
DRAM refreshing is disabled and no DRAM-refresh cycles occur.
6-46
Refresh Count Register REFCNT
During a DRAM-refresh cycle, the row address output to memory is taken
from the 8-bit ROWADR field of REFCNT. Specifically, bits 8-15 of
REFCNT are output on LADO-LAD7. REFCNT bits 8-14 are simultaneously
output on LAD8-LAD14. (The RF bus status signal is output as a low level
on LAD15.) This means that the 8-bit row address needed to refresh a
DRAM can be taken from any eight adjacent LAD pins in the range
LAD0-LAD14. Note that as ROWADR counts from 255 to 0, the refresh
addresses output at the selected eight LAD pins will sequence through all
256 values in the range 255 to 0, though not necessarily in the same order
as ROWADR.
REFCNT is set to 0 at reset; after that, refresh address generation is auto-
matic. Typically there is no reason to read this register or write to it, al-
though it can be accessed similarly to the way other I/O registers are
accessed. In order to reliably write a value to REFCNT, DRAM refresh
should be disabled (by setting RR to 112) before writing to REFCNT.
6-47
VCOUNT Vertical Count Register
Address C00001 DOh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I VCOUNT I
Description The VCOUNT register is a 16-bit counter used during generation of the
vertical sync and blanking signals. VCOUNT counts the horizontal lines in
the video display, incrementing at the same clock edge at which HCOUNT
is internally reset to O. This causes the falling edges of HSYNC and VSYNC
to coincide.
In order to generate vertical sync and blanking signals, the value of
VCOUNT is compared to the value of the four vertical timing registers,
VESYNC, VEBLNK, VSBLNK, and VTOTAL. When HCOUNT = HTOTAL
and VCOUNT = VTOTAL at the same time, VCOUNT is reset to 0 on the
next VCLK falling edge and the VSYNC output is driven active low.
If interlaced scan mode is enabled and the current field is even, and if
VCOUNT = VTOTAL and HCOUNT = HTOTAL/2, then VCOUNT is reset
to 0 and VSYNC goes low (HCOUNT is not reset until it reaches the value
HCOUNT = HTOTAL). When external sync mode is enabled, VCOUNT is
reset to 0 when the VSYNC input signal goes active low.
A display interrupt request is generated when VCOUNT = DPYINT. This
can be used to coordinate software activity with the refreshing of selected
lines on the screen.
Two separate, asynchronous elements of the TMS3401 0 internal logic can
access VCOUNT:
• The internal processor, which runs synchronously to local clocks
LCLK1 and LCLK2, can access VCOUNT as an I/O register.
• The video timing control logic, which runs synchronously to the video
clock VCLK, increments and clears VCOUNT in the course of gener-
ating the sync and blanking signals.
No synchronization between these two subsystems is provided, and
VCOUNT can only be reliably read or written while VCLK is held at the
logic-high level. VCOUNT is typically not read or written to except during
chip test.
6-48
Vertical End Blank Register VEBLNK
Address C0000050h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I VEBLNK I
Description VEBLNK is a video timing register that designates the time at which the
vertical blanking interval ends. The 16-bit value contained in VEBLNK is
compared to VCOUNT to determine when to end the vertical blanking in-
terval. The vertical blanking interval ends when the following conditions
are satisfied:
• VCOUNT = VEBLNK
• HCOUNT = HTOTAL
The end of the vertical blanking interval coincides with the start of the
horizontal sync, occurring at a time when the internal horizontal blanking
signal is active. The blanking signal output from the BLANK pin is a com-
posite of the horizontal and vertical blanking signals generated internally,
and will not reach its inactive-high level until both internal blanking signals
have become inactive.
When external video is enabled (DXV=O) and the HSYNC pin is configured
as an input (HSD=O), the vertical blanking interval ends when the follow-
ing conditions are satisfied:
• VCOUNT = VEBLNK and
• The leading edge of the external horizontal sync pulse is detected
The beginning of the sync pulse is seen as a high-to-Iow transition at the
HSYNC pin.
Typical video monitors require VEBLN K to be set to a value less than the
value in VSBLNK, and greater than the value in VESYNC.
6-49
VESYNC Vertical End Sync Register
Address C0000040h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I VESYNC
Description VESYNC is a video timing register that designates the time at which the
vertical sync pulse ends. The 16-bit value contained in VESYNC is com-
pared to VCOUNT to determine when to end the vertical sync pulse. The
sync pulse ends when the following conditions are satisfied:
• VCOUNT = VESYNC
• HCOUNT = HTOTAl
The VSYNC output is driven inactive high to signal the end of the vertical
sync interval.
When interlaced mode is enabled and the next vertical field is odd, VSYNC
is driven high when VCOUNT = VESYNC and HCOUNT = HTOTAlj2.
Typical video monitors require VESYNC to be set to a value less than the
value contained in the VEBlNK register; the minimum value of VESYNC is
O.
When external sync mode is enabled (DXV=O), the end of the external
vertical sync pulse is detected as a low-to-high transition at the VSYNC pin,
which is configured as an input. VESYNC should be loaded with a value
greater than the value in VCOUNT at the point at which the external VSYNC
input signal should go inactive high, but lower than the value in VCOUNT
when the external VSYNC should again become active low. For example,
VESYNC could be loaded with the sum of the values in VEBlNK and
VSBlNK divided by two.
6-50
Vertical Start Blank Register VSBLNK
Address C0000060h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I VSBLNK
Description VSBLNK is a video timing register that designates the time at which the
vertical blanking interval starts. The 16-bit value contained in VSBLNK is
compared to VCOUNT to determine when to start the vertical blanking in-
terval. The vertical blanking interval starts when the following conditions
are satisfied:
• VCOUNT = VSBLNK
• HCOUNT = HTOTAL
The start of the vertical blanking interval coincides with the start of the
horizontal sync, occurring at a time when the internal horizontal blanking
signal is active. The blanking signal output from the BLANK pin is a com-
posite of the horizontal and vertical blanking signals generated internally,
and reaches its active-low level when either or both internal blanking sig-
nals are active.
When external video is enabled (DXV=O) and the HSYNC pin is configured
as an input (HSD=O), the vertical blanking interval starts when the follow-
ing conditions are satisfied:
• VCOUNT = VSBLNK
• The leading edge of the external horizontal sync pulse is detected
The beginning of the horizontal sync pulse is seen as a high-to-Iow transi-
tion at the HSYNC pin.
VSBLNK should be set to a value less than the value in VTOTAL, and
greater than the value in VEBLNK.
6-51
VTOTAL Vertical Total Register
Address C0000070h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I VTOTAL I
Description VTOTAL contains a 16-bit value that designates the value of VCOUNT at
which the vertical sync pulse begins. The contents of VTOTAL are com-
pared to VCOUNT to determine when to start the vertical sync pulse. Ver-
tical sync begins when the following two conditions are satisfied:
• VCOUNT = VTOTAL
• HCOUNT = HTOTAL
These conditions cause HCOUNT to begin counting from 0 again.
The VSYNC output is driven active low to signal the start of the vertical sync
interval. The high-to-Iow transitions of VSYNC and HSYNC occur at the
same clock edge.
When interlaced mode is enabled and the next vertical field is odd, VSYNC
is driven low when VCOUNT = VESYNC and HCOUNT = HTOTALj2. The
total number of horizontal lines in each vertical field is calculated as VTO-
TAL + 1. In interlaced mode the total number of horizontal lines in both
fields of the vertical frame is calculated as 2 x VTOTAL-1.
When external video is enabled (DXV=O), the VSYNC pin is configured as
an input rather than an output. The high-to-Iow transition of VSYNC is re-
cognized as the beginning of the vertical sync pulse, unless the condition
VCOUNT = VTOTAL and the start of horizontal sync are detected first.
VTOTAL should be loaded with a value at least as large as the value of
VCOUNT at which the external sync pulse should begin. Should the ex-
ternal sync pulse not occur, VCOUNT will be reset one VCLK period after
the conditions VCOUNT = VTOTAL and HCOUNT = HTOTAL occur.
VTOTAL should be set to a value greater than the value in VSBLNK. The
maximum value that can be loaded into VTOT AL is 65535.
6-52
Section 7
Graphics Operations
This section provides an overview of the graphics drawing capabilities of the
TMS34010. Topics in this section include:
Section Page
7.1 Graphics Operations Overview ............................................................... 7-2
7.2 Pixel Block Transfers ................................................................................ 7-4
7.3 Pixel Transfers ......................................................................................... 7 -10
7.4 Incremental Algorithm Support ............................................................ 7-10
7.5 Transparency ........................................................................................... 7 -11
7.6 Plane Masking ........................................................................................ 7 -12
7.7 Pixel Processing ..................................................................................... 7-15
7.8 Boolean Processing Examples .............................................................. 7 -17
7.9 Multiple- Bit Pixel Operations ............................................................... 7 -19
7.1 0 Window Checking .................................................................................. 7 -25
7-1
Graphics Operations - Overview
7.1 Graphics Operations Overview
The TMS3401 0 instruction set provides several fundamental graphics drawing
operations:
• The PIXBlT and Fill instructions manipulate two-dimensional arrays
of pixels.
• The LINE instruction implements the fast inner loop of the Bresenham
algorithm for drawing lines.
• The DRAV (draw and advance) instruction draws a pixel and increments
the pixel address by a specified amount. This function supports the im-
plementation of incremental algorithms for drawing circles, ellipses, arcs,
and other curves.
• The PIXT (pixel transfer) instruction transfers individual pixels from one
location to another.
The PIXBlT instruction plays an important role in rapidly drawing high-
quality, bit-mapped text. In particular, the PIXBlT B,XY and PIXBlT B,l in-
structions expand character patterns stored as bit maps (at one bit per pixel)
into color or gray-scale characters of 1, 2, 4, 8 or 16 bits per pixel. This allows
character shape information to be stored independently of attributes such as
color and intensity, providing greater storage efficiency.
The TMS34010 provides several methods for processing the values of the
source and destination pixels before the result is written to the destination.
These operations include:
• Boolean and arithmetic pixel processing operations for combining source
pixels with destination pixels.
• A plane mask which specifies which bits within pixels can be altered
during pixel operations.
• Transparency, an option which permits objects written onto the screen
to have transparent regions through which the background is visible.
Pixel processing, plane masking, and transparency can be used simultane-
ously. These operations on pixel values can be used in combination with any
of the pixel drawing instructions listed above. The arithmetic operations are
especially important in displays that use multiple bits per pixel to encode color
or intensity information. For example, the MAX and MIN operations allow two
objects with antialiased edges to be smoothly merged into a single image.
The TMS3401 0 has features such as automatic window checking to support
windowed graphics environments. Three window-checking modes are pro-
vided:
• Clipping a figure to fit a rectangular window.
• Requesting an interrupt on an attempt to write to a pixel outside of a
window.
7-2
Graphics Operations - Overview
• Requesting an interrupt on an attempt to write to a pixel inside of a
window.
The last of these modes can be used to identify screen objects that are pointed
to by a cursor. The window checking modes can be used with any of the pixel
drawing instructions that use XY addressing. Window checking is optional
and can be turned off.
The TMS3401 0 provides further support for windowed environments by rap-
idly detecting the following conditions:
• Whether a point lies inside or outside a rectangular window.
• Whether a line lies entirely inside or entirely outside a window.
Lines that lie entirely outside a window can be trivially rejected, meaning that
they take no further processing time. These conditions are detected via the
CPW (compare point to window) instruction, which takes only one machine
state to compare the XY coordinates of a point to all four sides of a window.
Another operation that occurs frequently in windowed environments is calcu-
lating the region where two rectangles intersect. This is a feature available
with the PIXBLT and FILL instructions. Based on the window-checking
mode, one of two methods can be selected to calculate the region of inter-
section:
• The destination pixel array is preclipped to a rectangular window before
the PixBlt or fill operation begins.
• The intersection of the destination pixel array with a rectangular window
is calculated, but no pixels are transferred.
7-3
Graphics Operations - Pixel Block Transfers
7.2 Pixel Block Transfers
The TMS34010 supports a powerful set of raster operations, known as
PixBlts (pixel block transfers), that manipulate two-dimensional arrays of bits
or pixels. A pixel array is defined by the following parameters:
• A starting address (by default, the address of the pixel with the lowest
address in the array)
• A width DX (the number of pixels per row)
• A height DY (the number of rows of pixels)
• A pitch (the difference between the starting addresses of two successive
rows)
A pixel array appears as a rectangular area on the screen. The array pitch is the
same in this case as the pitch of the display. The default starting address is
the address of the pixel in the upper left corner of the rectangle. (This assumes
that the ORG bit in the DPYCTL register and the PBH and PBV bits in the
CONTROL register are all set to their default values of 0.)
Two operands must be specified for a PIXBLT instruction:
• A source pixel array and
• A destination pixel array
The two arrays must have the same width and height, although they may have
different pitches. Each pixel in the source array is combined with the corre-
sponding pixel of the destination array. A Boolean or arithmetic pixel proc-
essing operation is selected and applied to the PIXBLT operation. The default
pixel processing operation is replace. If replace is selected, source pixel values
are simply copied into destination pixels.
Before executing a PIXBLT instruction, load the following parameters into the
appropriate GSP internal registers:
DYDX Composed of two portions: OX, which specifies the width of the
array, and DY, which specifies the height of the array.
PSIZE Pixel size (number of bits per pixel).
SADDR Starting address of source array (XY or linear address).
DADDR Starting address of destination array (XY or linear address).
SPTCH Source pitch, or difference in memory addresses of two vertically
adjacent pixels in the source array.
DPTCH Destination pitch, or difference in memory addresses of two verti-
cally adjacent pixels in the destination array.
If either the source or destination array is specified in XY format, the contents
of the CONVSP and CONVDP registers will be used in instances in which the
Y component of the starting address must be adjusted prior to the start of the
7-4
Graphics Operations - Pixel Block Transfers
PixBIt. The Y component may require adjustment, either to preclip the array
or to select a starting pixel in one of the lower two corners of the array.
Pitches and starting addresses must be specified separately for the two arrays
(source and destination). The width, height, and pixel size are common to
both arrays. (During a color expand operation, only the destination pixel size
is specified; the source pixel size is assumed to be one bit.)
The starting address of a pixel array can be specified as a linear (memory)
address or as an XY address. Window checking can be used only when the
destination array is pointed to by an XY address.
On-screen objects may be defined as XY arrays but may be more efficiently
stored as linear arrays in off-screen memory. An array specified in linear format
can be transferred to an array specified in XY format (and vice versa) by means
of the PIXBLT L,XY and PIXBLT XY,L instructions.
The FI LL instruction fills a specified destination pixel array with the pixel value
specified in the COLOR1 register. A fill operation can be thought of as a
special type of PixBlt that does not use a source pixel array. The source pixel
value used in pixel processing is the value in the COLOR1 register. The des-
tination array of a FILL instruction can be specified in either XY or linear for-
mat.
7.2.1 Color-Expand Operation
The TMS3401 0 allows shape information to be stored separately from attri-
butes such as color and intensity. A shape can be stored in compressed form
as a bit map containing 1s and Os. The color information is added as the shape
is drawn to the screen; the 1s in the bit map are expanded to the specified
Color 1 value, and the Os are expanded to the Color 0 value. This saves a
significant amount of memory when the pixel size in the display memory is two
bits or more.
Two PIXBLT instructions, PIXBLT B,XY and PIXBLT B,L, provide the color-
expand capability. The source array for either instruction is a bit map (one bit
per pixel) stored off-screen in linear format for greater storage efficiency. The
destination array can be specified in either XY or linear format. The pixel size
for the destination array is governed by the value in the PSIZE register. The
colors to which the 1 s and Os in the source array are expanded are specified
in the COLOR1 and COLORO registers.
A primary benefit of the color-expand capability is the reduction in table area
needed to store text fonts. Font bit maps are stored in compressed form at one
bit per pixel. The color-expand operation adds color to a character shape at
draw time, allowing color to be treated as an attribute separate from the shape
of the character. The alternative would be to store the fonts in expanded form,
which can be costly. The amount of table storage necessary to store red letters
A-Z, blue letters A-Z, and so on, multiplied by the number of font styles
needed for an application program, would be prohibitive. Furthermore, the
color-expand operation is inherently faster than using pre-expanded fonts
because far fewer bits of character shape information have to be read from the
font table when a character is drawn to the screen.
Figure 7 -1 shows the expansion of a bit map, one bit per pixel and four bits
wide, into four 4-bit pixels (transforming 0-1 -1 -0 into yellow-red-red-yellow,
7-5
Graphics Operations - Pixel Block Transfers
for example). Before transferring the expanded source array to the destination
array, any of the Boolean or arithmetic pixel processing operations can be ap-
plied.
Four bits per pixel example
of color expand
L l Four bit binary or unexpanded Image
hIla 13 la I Iala Ilia I I al aIlia I I al alll aICOLOR1
Register
COLORO
U~ljlaljl laljlalU laljlalU I al 31 al H Register
Execute Expand
I D
1
1 III I III (;
1 1 I (; I I D I.l 1 I.l I I D 1I
~--------------~v~----------------~
Reaultlng 18-b1t expanded Image
Figure 7-1. Color-Expand Operation
The expand function is also useful in applications that generate shapes or
patterns dynamically. During the first stage of this process, a compressed im-
age is constructed in an off-screen buffer area at one bit per pixel. The image
is built up of geometric objects such as rectangles, circles or polygons. Pat-
terns can also be added. When complete, the compressed image is color-
expanded onto the screen. This method defers the application of color and
intensity attributes until the final stage.
Combining color expand with the replace-with-transparency operation yields
a new operation that is particularly useful in drawing overlapping or kerned
text. The color value used to replace the Os in the source array is selected by
the programmer as all Os, which is the transparency code. The GSP defers the
check for transparency until after the color-expand operation has been per-
formed. As the color-expand operation is performed, the Os in the source array
are expanded to all Os. Only the pixels in the destination array that correspond
to nontransparent pixels in the resulting source array are replaced.
The PIXBLT B,XY and PIXBLT B,L instructions can be used in conjunction
with pixel processing, transparency and plane masking. Source pixels are ex-
panded before being processed. Window checking can be used with PIXBLT
B,XY.
7-6
Graphics Operations - Pixel Block Transfers
7.2.2 Starting Corner Selection
The default starting address of a pixel array is the lowest pixel address in the
array. When an array is displayed on the screen, as shown in Figure 7 -2 a, the
starting address is the address of the pixel in the upper left corner of the array.
(The XY origin is located in its default position at the upper left corner of the
screen.) During a PixBlt operation, this pixel is processed first. The PixBlt
processes pixels from left to right within each row, beginning at the top row
and moving toward the bottom row. The pixel at the lower right corner of the
array is processed last.
Certain PixBlt operations allow any of the other three corners to be used as the
starting location. This may be necessary, for instance, if the source and des-
tination arrays overlap. The sequence in which pixels are moved when the
arrays overlap should be controlled so as to not overwrite the pixels in the
source array before they are written to the destination array.
Figure 7-2 shows how the PBV and PBH bits in the CONTROL register de-
termine the starting corner for the Pix Bit operation. The starting corner is in-
dicated for each of four cases. PBH selects movement in the X direction, from
left to right or right to left. PBV selects movement in the Y direction, from top
to bottom or bottom to top.
+Y
G
+X
Pixel Array
Address
Pixel Array
Address
PBH=O. PBV=O PBH=1. PBV=O
Pixel Array Pixel Array
Address Address
PBH=O. PBV=1 PBH=1. PBV=1
Note: Starting corners are shaded.
Figure 7-2. Starting Corner Selection
7-7
Graphics Operations - Pixel Block Transfers
PBH=O The PixBlt processes pixels from left to right; that is, in the direction
of increasing X.
PBH =1 The PixBlt processes pixels from right to left; that is, in the direction
of decreasing X.
PBV=O The PixBlt processes rows from top to bottom; that is, in the di-
rection of increasing Y.
PBV=1 The PixBlt processes rows from bottom to top; that is, in the di-
rection of decreasing Y.
All the pixels in one row are processed before moving to the next row.
When one or both of the arrays is specified in XY format, the GSP automat-
ically calculates the actual starting address (specified by PBH and PBV) from
the default starting address (that is, the lowest pixel address in the array) and
the width and height of the array. Automatic starting address adjustment is
available with the following instructions:
• PIXBLT L,XY
• PIXBLT XY,L
• PIXBLT XY,XY
The programmer supplies the default starting addresses for these PixBlts in the
SADDR and DADDR registers. During the course of instruction execution,
SADDR and DADDR are automatically adjusted to the address of the corner
selected by PBH and PBV.
When both arrays are specified in linear format, the starting addresses of the
appropriate corner pixels must be provided by the programmer. The PIXBLT
L,L instruction allows any of the four corners to be used as the starting lo-
cation, but in this case the programmer must adjust the addresses in SADDR
and DADDR to the corner selected by PBH and PBV.
7.2.3 Interrupting PixBlts and Fills
PIXBLT and FILL are interruptible instructions. An interrupt can occur during
execution of one of these instructions; when interrupt processing is com-
pleted, execution of the PIXBLT or FILL resumes at the point at which the in-
terruption occurred.
The execution time of a PIXBLT or FI LL instruction depends on the specified
pixel array size. In order to prevent high-priority interrupts from being delayed
until completion of PixBlts and fills of large arrays, the PIXBLT and FILL in-
structions check for interrupts at regular intervals during their execution.
When a PIXBLT or FILL instruction is interrupted the PBX (PixBlt executing)
status bit is set to 1. This records the fact that the interrupt occurred during
a pixel array operation. The PC and the ST are pushed onto the stack, and
control is transferred to the appropriate interrupt service routine. At the end
of the interrupt service routine, an RETI (return from interrupt) instruction is
executed to return control to the interrupted program. The RETI instruction
7-8
Graphics Operations - Pixel Block Transfers
pops the ST and PC from the stack. When the PBX bit is detected, execution
of the interrupted PIXBLT or FILL instruction resumes.
At the time of the interrupt, the state of the PIXBLT or FILL instruction is saved
in certain B-file registers. The source and destination address registers contain
intermediate values. The source and destination pitches may also contain in-
termediate values, depending on the instruction. The SADDR, SPTCH,
DADDR, DPTCH registers and registers B1 o-B14 (as well as the original set
of implied operands) contain the information necessary to resume the in-
struction upon return from an interrupt.
If the interrupt routine uses any of these registers, they should be saved on the
stack and restored when interrupt processing is complete. By following this
procedure, PIXBLTor FI LL instructions can be safely executed within interrupt
service routines.
Note:
The PBX bit is not set to 1 when a PIXBLT or FILL instruction is aborted
due to a window violation.
7-9
Graphics Operations - Pixel Transfers/Incremental Algorithm Support
7.3 Pixel Transfers
The TMS3401 0 uses the PIXT (pixel transfer) instructions to transfer individ-
ual pixels from one location to another. The following pixel transfers can be
performed:
• From an A- or B-file register to memory,
• From memory to an A- or B-file register, or
• From one memory location to another.
The address of a pixel in memory can be specified in XY or linear format. Li-
near addresses must be pixel aligned.
The pixel size for all PIXTs is specified by the value in the PSIZE register. Pixel
sizes are restricted to 1, 2, 4, 8, or 16 bits to facilitate XY address computa-
tions, window checking, transparency, and arithmetic pixel processing.
The PIXT instruction can be used in conjunction with window checking,
Boolean or arithmetic pixel processing, plane masking, and transparency.
7.4 Incremental Algorithm Support
The TMS3401 0 supports incremental drawing algorithms via its DRAV (draw
and advance) and LINE instructions. The DRAV instruction is used primarily
in the construction of algorithms for incrementally drawing circles, ellipses,
arcs, and other curves. The DRAV instruction can also be used in the inner
loop of algorithms for drawing straight lines incrementally. Lines, however,
are treated as a special case by the TMS3401 0 in order to achieve even faster
drawing rates. A separate instruction, LI N E, implements the entire inner loop
of the Bresenham algorithm for drawing lines.
The DRAV (draw and advance) instruction draws a pixel to a location pointed
to by a register; the pointer register is then incremented to point to the next
pixel. The pointer is specified as an XY address. The X and Y portions of the
address are incremented independently, but in parallel. The value written to
the destination pixel in memory is taken from the COLOR1 register.
The DRAV instruction is embedded in the inner loop of an incremental algo-
rithm to speed up its execution. As an incremental algorithm plots each pixel
on a curve, it also determines where the next pixel will be drawn. The next
pixel is typically one of the eight pixels immediately surrounding the pixel just
plotted on the screen. Advancing in this manner, the algorithm tracks the
curve from one end to the other.
The DRAV and LINE instructions may be used in conjunction with Boolean
or arithmetic pixel processing operations, window checking, plane masking
and transparency.
7-10
Graphics Operations - Transparency
7.5 Transparency
When a PixBlt is used to draw an object to the screen, some of the pixels in
the rectangular pixel array that contains the object may not be part of the ob-
ject itself. Transparency is a mechanism that allows surrounding pixels in
the array to be specified as invisible. This is useful for ensuring that only the
object, and not the rectangle surrounding it, is written to the screen.
Transparency is enabled by setting the T bit in the CONTROL register to 1, or
disabled by setting the T bit to O. When enabled, a pixel that has a value of 0
is considered transparent, and will not overwrite a destination pixel. Trans-
parency detection is applied not to the source pixel values, but to the pixel
values resulting from plane masking and pixel processing. When an operation
performed on a pair of source and destination pixels yields a 0 result, the GSP
detects this and prevents the destination pixel from being altered. In the case
of pixel processing operations such as AND, MIN, and replace, a source pixel
value of 0 ensures that the result of the operation will be a transparent pixel.
Figure 7 -3 illustrates how transparency works in the GSP. Assuming four bits
per pixel, the hardware must detect strings of Os of length four falling between
pixel boundaries. While bit strings A and B are both of pixel length, only
string A is detected as transparent. String B crosses the pixel boundary. The
memory interface logic generates an internal mask to govern which bits are
modified during a write cycle. This mask contains Os in the bits corresponding
to the transparent pixel. Only destination bits corresponding to 1 s in the mask
will be modified.
~ String A~ r-- String B--1
Data to be written 010 o
Mask generated
Data to be modified IA A A AlB B B B Ie e e e ID D 0 DI
Resulting data
10 0 1IB B B B 11 0 0 01 0 o I
Note: This example assumes four bits per pixel.
Figure 7-3. Transparency
Figure 7-7 (page 7-17) and Figure 7-8 (page 7 -20) illustrate several pixel
processing operations. Figure 7 -8 h shows an example of a replace operation
performed with transparency enabled. The pixels surrounding the letter A
pattern in the source array are transparent (all Os). Compare Figure 7 -8 h with
Figure 7-7 d; this replace-with-transparency operation is analogous to the
logical OR operation in a one-bit-per-pixel display.
Transparency can be used with any instruction that writes to pixels, including
the PIXBLT, FILL, DRAV, LINE, and PIXT instructions. Transparency does not
affect writes to non-pixel data.
7 -11
Graphics Operations - Plane Masking
7.6 Plane Masking
The plane mask is a hardware mechanism for protecting specified bits within
pixels. Mask-protected pixels will not be modified during graphics in-
structions. The plane mask allows the bits within pixels to be manipulated as
though the display memory were organized into bit planes (or color planes)
that can selectively be protected from modification. The number of planes
equals the number of bits per pixel.
Consider an example in which the pixel size is four bits. The bits within each
pixel are numbered 0-3, and belong to planes 0-3, respectively. All the bits
numbered 0 in all the pixels form plane 0, all the bits numbered 1 in all the
pixels form plane 1, and so on.
The plane mask allows one or more planes to be manipulated independently
of the other planes. Given four planes of display memory, for example, three
of the planes can be dedicated to eight-color graphics, while the fourth plane
can be used to overlay text in a single color. The plane mask can be set so that
the text plane can be modified without affecting the graphics planes, and vice
versa.
The PMASK register contains the plane mask. Each bit in the plane mask
corresponds to a bit position in a pixel. The 1s in the mask designate pixel
bits that are protected, while Os in the mask designate pixel bits that can be
modified. Those pixel bits that are protected by the plane mask are always
read as Os during read cycles, and are protected from alteration during write
cycles. While °no single control bit enables or disables plane masking, it is ef-
fectively disabled by setting PMASK to all Os; this is the default condition
following reset.
The logical width of a quantity in the plane mask is the same as the pixel size.
However, in order to maintain a consistent effect on all of the pixels within a
destination region, regardless of their position within the destination words,
you should replicate the mask for a single pixel to fill the entire 16-bit PMASK
register. (To provide upward compatibility with future versions of the GSP,
you should replicate the plane mask through the 32 bits beginning at address
C0000170h.) For example, if the pixel size is four bits, the 4-bit mask is rep-
licated four times within PMASK; in bits 0-3, 4-7, 8-11, and 12-15. These
four copies of the mask are applied to the four pixels in a word written to or
read from memory. A 16-bit PMASK value for pixels of 1, 2, 8, or 16 bits is
constructed similarly by replicating the mask 16, 8, 2, or 1 times, respectively.
The plane mask affects only pixel accesses performed during execution of the
PIXBLT, FILL, PIXT, DRAV, and LINE instructions. Data accesses by non-
graphics instructions are not affected.
The following list summarizes operation of the PMASK register during pixel
reads and writes:
• Pixel Read:
The Os in PMASK correspond to unprotected bits in the source pixel that
are seen by the GSP to contain the actual values read from memory.
The 15 in PMASK correspond to protected bits in the source pixel that
are seen as Os by the GSP, regardless of the values read from memory.
7-12
Graphics Operations - Plane Masking
• Pixel Write:
The Os in PMASK specify those bits in the destination pixel in memory
which may be altered.
The 15 in PMASK specify protected bits in the destination pixel which
cannot be altered.
When a pixel is being transferred from a source to a destination location, plane
masking is applied to the values read from the source and destination before
pixel processing is applied. As the operands are read from memory, the bits
protected by the plane mask are replaced with Os before the specified Boolean
or arithmetic pixel processing operation is performed. and destination before
pixel processing is applied. Transparency detection is performed on the result
of this operation. When the result is written back to the destination, those bits
of the destination that are protected by the plane mask are not modified.
Source pixels that originate from registers are not affected by the plane mask,
and undergo pixel processing in unmodified form. The FILL, DRAV, LINE,
PIXT Rs,*Rd, and PIXT Rs,*Rd.XY instructions obtain their source pixels from
registers.
Figure 7 -4 shows how special hardware in the local memory interface of the
TMS34010 applies the plane mask to pixel data during a read cycle. The pixel
size for this example is eight bits per pixel. This could represent the execution
of a PIXT *Rs.XY,Rd instruction, for instance.
Move this pixel
Into a asp register
8 7
(a) Original data In memory (2 pixels) A A A A A A B B B B
(b) Plane mask (PMASK) 11 0 0 0 0 o !1 0 0 0 0 oI
(0) Data read Into GSP register 10 0 0 0 0 0 0 010 0 B B 0 B B B I
Notes: 1. This example assumes eight bits per pixel.
2. The pixel moved into the GSP register is left justified. All register bits to the left of
the pixel are zero filled.
Figure 7-4. Read Cycle With Plane Masking
• Figure 7 -4 a shows the 16-bit word containing the pixel as it is read
from memory.
• The word is AN Ded with the inverse of the plane mask shown in b.
• The result in Figure 7 -4 c shows that the bits within the data word that
correspond to 1s in the mask have been set to Os.
7-13
Graphics Operations - Plane Masking
After plane masking, the designated pixel is loaded into the eight LSBs of the
32-bit destination register, and the 24 MSBs of the register are filled with Os.
Figure 7 -5 shows the effect of combining plane masking with pixel transpar-
ency. Again, the performance of the special hardware in the local memory
interface controller is demonstrated. The example shows the transfer of two
pixels during the course of a PixBlt operation with transparency enabled, the
pixel size set at eight bits, and the replace pixel processing operation. The
inverse of PMASK is AN Ded with the source data, and transparency detection
is applied to the resulting entire pixel. In other words, the result is used to
control the write in the manner described in the previous discussion of pixel
transparency. Since the three LSBs of the source pixel in bits 8-15 are Os, and
the rest of the pixel is masked off, the entire source pixel is interpreted as
transparent. The memory interface logic generates an internal mask to govern
which bits are modified during a write cycle. This mask contains Os in the bits
corresponding to the transparent pixel.
16(MSB) 8 7 O(LSB)
(8) Original data In memory (2 pixels) A A A A A A A A B B B B B B B B
(I) Source data In memory y y y y y
(to be moved) 0 0 0 Z Z Z Z Z Z Z Z
(c) Plane mask (PMASI<) 0 0 0 0 0 0
(d) Mask source data for trans-
parency detecUon (SRC. ~ 0 0 0 0 0 0 0 0 0 0 0 0 0 Z Z Z
(e) Transparency mask 0 0 0 0 0 0 0 0
(1) Combined mask ~. trans-
parency mask) 0 0 0 0 0 0 0 0 0 0 0 0 0
(g) R88UItIng memory data after A A A A A A A A B B B B B Z Z Z
write cycle (Combined Mask.
aRC DATA + coiribined M88k.
DST DATA)
Note: This example assumes eight bits per pixel.
Figure 7-5. Write Cycle With Transparency and Plane Masking
• Figure 7 -5 a shows the original data at the destination location.
• b shows the source data.
• In c, the source data is ANDed with the inverse of the plane mask.
• d shows the intermediate result produced by c.
• This result is used to generate the transparency mask in e, which is
AN Ded with the inverse of the plane mask in c to produce the composite
mask shown in f.
• The result in G is produced by replacing with the source only those bits
of the destination corresponding to 1s in the composite mask in f.
7-14
Graphics Operations - Pixel Processing
7.7 Pixel Processing
Source and destination pixel values can be combined according to the pixel
processing operation (or raster operation) selected. The TMS34010's pixel
processing operations include 16 Boolean and 6 arithmetic operations. The
Booleans are performed in bitwise fashion on operand pixels of 1, 2, 4, 8, or
16 bits. The arithmetic operations treat operand pixels of 4, 8, or 16 bits as
unsigned binary numbers.
When a pixel is read from its source location, it is arithmetically combined with
the corresponding destination pixel according to the Boolean or arithmetic
pixel processing option selected, and the result is written to the destination
pixel. The pixel processing operation is selected by the PPOP field in the
CONTROL register. Table 7-1 and Table 7-2 list the 22 PPOP codes and their
meanings.
Table 7-1. Boolean Pixel Processing Options
PPOP Field Operation
00000 Source -+ Destination
00001 Source AN D Destination -+ Destination
00010 Source AN D ,..., Destination -+ Destination
00011 Os -+ Destination
00100 Source OR ,..., Destination -+ Destination
00101 Source XNOR Destination -+ Destination
00110 - Destination -+ Destination
00111 Source NOR Destination -+ Destination
01000 Source OR Destination -+ Destination
01001 Destination -+ Destination
01010 Source XOR Destination -+ Destination
01011 -Source AND Destination -+ Destination
01100 1s -+ Destination
01101 -Source OR Destination -+ Destination
01110 Source NAND Destination -+ Destination
01111 - Source -+ Destination
Table 7-2. Arithmetic (or Color) Pixel Processing Options
PPOP Field Operation
10000 Source + Destination -+ Destination
10001 ADDS(Source, Destination) -+ Destination
10010 Destination - Source -+ Destination
10011 SUBS(Source, Destination) -+ Destination
10100 MAX(Source, Destination) -+ Destination
10101 MIN(Source, Destination) -+ Destination
1011 0-11111 Reserved
7-15
Graphics Operations - Pixel Processing
In Table 7 -2, pixel processing codes 100002 and 100102 correspond to stan-
dard 2s complement addition and subtraction. A result that overflows the
specified pixel size causes the pixel value to wrap around within its 4, 8, or
16-bit range. Carry bits are, however, prevented from propagating to adjacent
pixels.
The ADDS (add with saturation) and SUBS (subtract with saturation) oper-
ations shown in Table 7 -2 produce results identical to those of standard ad-
dition or subtraction, except when arithmetic overflow occurs. When the
ADDS operation would produce an overflow result, the result is replaced with
all 1 s. When the SUBS operation would produce an underflow result, the re-
sult is replaced with all Os.
The MAX operation shown in Table 7 -2 compares the source and destination
pixels and then writes the greater value to the destination location. The MIN
operation is similar, but writes the lesser value to the destination.
Figure 7 -6 depicts the interaction of pixel processing with other graphics op-
erations when a source pixel is transferred to a destination pixel. Note that this
is a general description; some of these operations do not occur if they are not
selected. Pixels are first read from memory and modified by the plane mask.
Pixel processing is then performed on the modified pixel values. The plane
mask is applied to the result. Bits which are 1s in the PMASK produce 0 bits
in the result of this process. Thus, some processed pixels may become trans-
parent as the result of plane masking. Next, transparency detection is applied
to the data, and finally, a read-modify-write operation is invoked.
t Not performed if replace is selected.
Only performed when plane masking or transparency is active and the pixel size is not
:j:
16, or the data being written is not word-aligned.
Figure 7-6. Graphics Operations Interaction
7-16
Graphics Operations - Boolean Processing Examples
7.8 Boolean Processing Examples
Figure 7 -7 illustrates the effects of five commonly used Boolean operations
when applied to one-bit pixels. Black regions contain Os, and white regions
contain 1 s. Figure 7 -7 a and b show the original source and destination ar-
rays. The source operand in a is the letter A, and the destination in b is a
calligraphic-style X.
g
(A) SOURCE ARRAY
x
(8) ORIGINAL DESTINATION
ARRAY
y
11(C) REPLACE
¥ ,~
(D) OR
X (E) ANO-NOT
II (F) AND
1{ (G) XOR
Figure 7-7. Examples of Operations on Single-Bit Pixels
7-17
Graphics Operations - Boolean Processing Examples
7.8.1 Replace Destination with Source
A simple replacement operation overwrites the pixels of the destination array
with those of the source. Figure 7 -7 c shows the letter A written over the
center portion of a larger X using the replace operation. The rectangular region
around the letter A obscures a portion of the X lying outside the A pattern.
Other operations allow only those pixels corresponding to the A pattern within
the rectangle to be replaced, permitting the background pattern to show
through. These are the logical OR and logical AND-NOT (NOT source AND
destination) operations. The replace-with-transparency operation performs
similarly in color systems.
7.8.2 Logical OR of Source with Destination
Figure 7-7 d illustrates the use of the logical OR operation during a PixBIt.
For a one-bit-per-pixel display, the OR function leaves the destination pixels
unaltered in locations corresponding to Os in the source pixel array. Destina-
tion pixels in positions corresponding to 1 s in the source are forced to 1s.
7.8.3 Logical AND of NOT Source with Destination
Logically AN Ding the negated source with the destination is complementary
to the logical OR operation. Destination pixels corresponding to 1 s in the
source array remain unaltered, but those corresponding to Os in the source are
forced to Os. Figure 7-7 e is an example of the AND-NOT PixBlt operation
(notice the negative image of the letter A). For comparison, Figure 7 -7 f
shows the result of simply ANDing the source and destination.
7.8.4 Exclusive OR of Source with Destination
The XOR operation is useful in making patterns stand out on a screen in in-
stances where it is not known in advance whether the background will be 1 s
or Os. At every point at which the source array contains a pixel value of 1, the
corresponding pixel of the destination array is flipped - a 1 is converted to a
0, and vice versa. XOR is a reversible operation; by XORing the same source
to the same destination twice, the original destination is restored. These pro-
perties make the XOR operation useful for placing and removing temporary
objects such as cursors, and in "rubberbanding" lines. As seen in the example
of Figure 7 - 7 g, however, the object may be difficult to see if both the source
and destination arrays contain intricate shapes.
7-18
Graphics Operations - Multiple-Bit Pixel Operations
7.9 Multiple-Bit Pixel Operations
The Boolean operations described in Section 7.8 are sufficient for single-bit
pixel operations, but they may be inappropriate for multiple-bit pixel oper -
ations, especially when color is involved. For example, the result of a bit-
wise - OR operation on a black-and-white (one bit per pixel) display is easily
predicted - DRing black and white yields white. However, the meaning of this
operation is less intuitive when it is applied to multiple - bit pixels. For exam-
ple, in a population -density map, colors may be used to represent numeric
values. If one color, such as red, represents one level of population density,
and blue represents another, what happens when the two colors are bit-
wise - ORed? When pixels represent numeric values, numerical operations such
as addition and subtraction yield more useful results.
Boolean operations are usually inadequate for merging antialiased objects into
a single bit-mapped image. Older graphics systems that are limited to Boolean
operations on pixels are incapable of supporting many practical applications
on multiple-bit-per-pixel images. For instance, where two antialiased lines
cross, AN D and OR operations yield chaotic pixel intensities that defeat the
purpose of the antialiasing . However, merging the two lines by means of the
GSP 's MAX operation (for white on black) or MIN operation (for black on
white) yields a smooth and aesthetically pleasing image.
7.9.1 Examples of Boolean and Arithmetic Operations
Figure 7 -8 illustrates Boolean and arithmetic operations on multiple-bit pixels.
Figure 7 -8 a illustrates a source array that contains a red letter A; the red pixels
have the value 8 (10002) and the black background pixels have the value 0
(00002) ' Figure 7 -8 b shows the destination array, a yellow X; the yellow
pixels have the value 12 (11002) and the pixels in the blue background pixels
have the value 2 (00102) '
Boolean operations can be applied to multiple - bit pixels by combining the
corresponding bits of each pair of source and destination pixels on a bit - by - bit
basis according to the specified Boolean operation. Figure 7 -8 c through g
show the effects of combining the source and destination arrays using the re-
place, OR. AND-NOT, AND, and XOR PixBlt operations . Compare these to
Figure 7-7 (page 7-17) .
Arithmetic operations treat 4-bit, 8 - bit, and 16-bit pixels as unsigned binary
numbers. An n-bit pixel represents a positive integer in the range 0 to 2n-1
(all 1 s) . Examples of arithmetic operations on source and destination pixels
are shown in Figure 7 -8 i through n and discussed in Section 7 .9.1.1 through
Section 7 .9.1 .4.
(a) Source (b) Destination
Figure 7-8. Examples of Boolean and Arithmetic Operations
7 - 19
Graphics Oper ations - Multiple-Bit Pixel Operations
(c) Src Re pl ac es Dst (d ) Src OR Dst (e ) SrC A ND Dst
(t) Src A N D Dst (g) Src XO R Dst (h) Replace with
Transparency
(i) Add (j) Subtract (k) Add with Saturation
(I) Subtract with (m) MAX (n) MIN
Saturation
Figure 7-8. Examples of Boolean and Arithmetic Operations (Concluded)
7-20
Graphics Operations - Multiple-Bit Pixel Operations
7.9.1.1 Figure 7-8 i and i-Simple Addition and Subtraction
Figure 7 -8 i shows the result of adding the source and destination arrays.
Simple binary 2s complement addition is used. When the sum of the two
pixels exceeds the maximum pixel value, the result overflows. Figure 7 -8 j
shows the result of subtracting the source array from the destination array.
Underflow occurs for those pixels whose calculated difference is negative.
Simple addition and subtraction are complementary operations. They are re-
versible operations in the same sense as the XOR operation - by adding a
source pixel to a destination pixel, and then subtracting the same source pixel,
the original destination pixel is recovered.
7.9.1.2 Figure 7-8 k and 1- Add and Subtract with Saturate
The add and subtract operations described in Section 7.9.1.1 are binary 2s
complement operations which allow overflow and underflow. An add-with-
saturate operation stops the result at the maximum unsigned value without
allowing the result to overflow. For example, with four bits per pixel, adding
00102 to 11102 produces 11112. Similarly, a subtract-with-saturate operation
stops the result at 0 without allowing it to underflow.
Figure 7 -8 k and I illustrate examples of addition with saturation and sub-
traction with saturation. In these examples, the pixel size is four bits. By
dedicating a different color to each value, the effects of each PixBlt operation
become more visible. .
An alternate method of encoding 4-bit pixels uses the 16 values 0 to 15 to
represent increasing intensities of a single color component: red, green, and
blue. The addition and subtraction operations now have obvious meaning -
increasing or decreasing the intensity by specified amounts. At 12 bits per
pixel, four bits of intensity can be dedicated to each of the three color com-
ponents. Arithmetic operations are then performed on the corresponding
components of each pair of source and destination pixels.
Figure 7 -9 (page 7 -22) presents examples in which the pixel values represent
intensities of a gray from black to white.
7.9.1.3 Figure 7-8 m - Maximum
Figure 7 -8 m illustrates the results of the MAX operation on the source and
destination arrays. MAX compares two pixel values and replaces the destina-
tion pixel with the larger value. In some respects, MAX is the arithmetic
equivalent of the Boolean OR function (compare Figure 7 -8 m with Figure 7-7
b). The use of MAX in gray-scale and color displays is similar to that of OR
in simple black and white.
If the most-significant bits in each pixel are assigned to represent object pri-
ority (whether an object appears in front of or behind another object), the
MAX operation can be used to replace only those pixels of the destination ar-
ray whose priorities are lower than those of the corresponding pixels in the
source array. This allows an object to be drawn to the screen so that it appears
either in front of or behind other objects previously drawn. In Figure 7 -8 m
the red A has a numerical value that is greater than that of the blue back-
ground, but less than that of the X.
The MAX function is also useful for smoothly combining two antialiased ob-
jects that overlap.
7-21
Graphics Operations - Multiple-Bit Pixel Operations '
7.9.7.4 Figure 7-8 n - Minimum
Figure 7-8 n illustrates the results of the MIN operation on the source and
destination arrays. MIN compares two pixel values and replaces the destina -
tion pixel with the smaller value . MIN is similar to the Boolean AN D function .
MIN can be used with priority -encoded pixel values, similar to MAX, but the
effect is reversed . In Figure 7 -8 n, the priorities of the two objects are reversed
from that of the MAX example shown in Figure 7-8 m. The MIN operation
also has uses similar to those of MAX in smoothly combining antialiased ob -
jects that overlap.
7.9.2 Operations on Pixel Intensity
Figure 7 -9 illustrates the visual effects of various PixBlt operations on two
intersecting disks. In these examples, each pixel is a four-bit value represent-
ing an intensity from 0 (black) to 15 (white) . Before the Pix Bit operation ,
only a single disk resides on the screen, as shown in Figure 7 -9 a. The in-
tensity of the disk is greatest at the center (where the value is 12) , and grad-
uay falls off as the distance from the center increases. Figure 7 - 9 b through
f show the effects of combining a second, identical disk with the first. Figure
7 -9b through e are produced using arithmetic operations; f is the result of a
logical OR of the source and destination . These operations are discussed in
Section 7 .9.2.1 through Section 7 .9.2.4.
(a) Original Disk (b) Replace with Transparency (c) Add
(d) Add with Saturate (e) MAX (f) OR
Figure 7-9. Examples of Operations on Pixel Intensity
7-22
Graphics Operations - Multiple-Bit Pixel Operations
The gradual change in intensity at the edge of the disk in Figure 7 -9 a is similar
to the result produced by certain antialiasing techniques whose purpose is to
reduce jagged-edge effects. A text font might be stored in antialiased form,
for example, to give the text a smoother appearance. When two characters
from the font table are PixBIt'd to adjacent positions on the screen, they may
overlap slightly. The particular arithmetic or Boolean operation selected for the
PixBlt determines the way in which the antialiased edges of the characters are
combined within regions of overlap.
7.9.2.1 Figure 7-9 b - Replace with Transparency
In Figure 7 -9 b, a second disk is PixBIt'd into a position near the first disk. A
replace-with-transparency operation is performed. Those pixels of the first
disk that lie within the rectangular region containing the second disk, but are
not part of the second disk, remain intact. The visual effect is that the second
disk (at the right) appears to lie in front of the original disk (at the left).
However, assuming that the gradual change in intensity at the perimeter of the
disks is done for the purpose of antialiasing, the sharp edge that results where
the second disk covers the first defeats this purpose. In other applications, this
sharp edge may be desirable; for example, it might be used to make a text
character or a cursor stand out from the background. The replace-with-
transparency operation also supports object priority by writing objects to the
screen in ascending order of priority.
7.9.2.2 Figure 7-9 c - Add with Overflow and Subtract with Underflow
In Figure 7 -9 C, a second disk is PixBlt'd into an area overlapping the first disk,
using an add-with-overflow operation. In this example, when 1 is added to
an intensity of 15, the sum is truncated to four bits to produce the result O.
The effect of arithmetic overflow is visible at the intersection of the two disks
as discontinuities in intensity.
This effect is useful for making objects stand out against a cluttered back-
ground. Add with overflow has an additional benefit - the object can be re-
moved by subtracting (with underflow) the object image from the screen.
7.9.2.3 Figure 7-9 d - Add and Subtract with Saturation
In Figure 7 -9 d, the original disk is on the left. A second disk is PixBlt'd into
a region overlapping the original disk, using an add-with-saturate operation.
Whenever the sum of two pixels exceeds the maximum intensity value, which
is 15 for this example, the sum is replaced with 15. The bright region that
occurs where the two disks intersect is produced when the corresponding
pixels of the two disks are added in this manner. Subtract-with-saturate is the
complementary operation; when the difference of the two pixel values is neg-
ative, the sum is replaced by the minimum intensity value, O.
The add-with-saturate operation shown in Figure 7 -9 d approximates the ef-
fect of two light beams striking the same surface; the surface is brightest in the
area in which the two beams overlap.
These operations can be used to achieve an effect similar to that of an airbrush
in painting. Consider a display system that represents each pixel as 12 bits,
and dedicates four bits each to represent the intensities of the three color
7-23
Graphics Operations - Multiple-Bit Pixel Operations
components, red, green, and blue. This method permits the intensity of each
component to be directly manipulated. With each pass of the simulated air-
brush over the same area of the screen, the color changes gradually toward the
color of the paint in the airbrush. For example, assume that the paint is yellow
(a mixture of red and green). Each time a pixel is touched by the airbrush, the
intensity of the red and green components is increased by 1, and the intensity
of the blue component is decreased by 1. With each sweep of the airbrush,
the affected area of the screen turns more yellow until the red and green
components reach the maximum intensity value (and are not allowed to over-
flow), and the blue component reaches 0 (and is not allowed to underflow).
7.9.2.4 Figure 7-9 e - MAX and MIN Operations
In Figure 7 -9 e, the original disk is on the left. A second disk is PixBlt'd into
the rectangular region to its right using the MAX operation. In the region in
which the disks overlap, each pair of corresponding pixels from the two disks
is compared and the greater value is selected. This produces a relatively
smooth blending of the two disks. Unlike add with saturate, the MAX function
does not generate a "hot spot" where two objects intersect.
The visual effect achieved using the MAX operation is desirable in an appli-
cation, for instance, in which white antialiased lines are constructed on top of
each other over a black background. MAX also smooths out places in which
the lines are overlapped by antialiased text. MAX is successful in maintaining
two visually distinct antialiased objects, while the add-with-saturate tends to
run them together.
MIN, which is complementary to MAX, can be used'similarly to smooth the
appearance of intersecting black antialiased lines and text on a white back-
ground.
The MAX and MIN operations are particularly useful in color applications in
which the number of bits per color gun is small (eight bits or less). Other
operators could also be used to smooth the transition between the two over-
lapping antialiased objects in Figure 7 -9 e, but any additional accuracy at-
tained by using a more complex smoothing function would probably be lost
in truncating the result to the resolution of the integer used to represent the
intensity at each point.
7-24
Graphics Operations - Window Checking
7.10 Window Checking
The TMS34010's hardware window clipping confines graphics drawing op-
erations to a specified rectangular window in the XV address space. Other
window checking modes cause an interrupt to be requested on a window hit
or a window miss.
Window checking affects only pixel writes performed by the following graph-
ics instructions:
• PIXBLT
• FILL
• LINE
• DRAV
• PIXT
Data writes by non-graphics instructions are not affected.
A window is a rectangular region of display memory specified in terms of the
XV coordinates of the pixels in its two extreme corners (minimum X and Y, and
maximum X and V). The corner pixels are considered to lie within the window.
Window checking is available only in conjunction with XV addressing; it is not
available with linear addressing. Specifically, the destination pixel address
must be an XV address.
One of four window checking modes is selected by the value loaded into the
W field of the CONTROL register:
W=O: Window checking disabled. No window checking is performed.
W=1: Window hit detection. Request interrupt on attempt to write inside
window.
W=2: Window miss detection. Request interrupt on attempt to write outside
window.
W=3: Window clipping. Clip all pixel writes to window.
When window checking is enabled (modes 1, 2 or 3), an attempt to write to
a pixel outside the window causes the V (overflow) bit in the status register
to be set to 1; a write (or attempt to write) to a pixel inside the window sets
V to O. When window checking is turned off (mode 0), the V bit is unaffected
during pixel writes.
7-25
Graphics Operations - Window Checking
7.10.1 W=1 Mode - Window Hit Detection
The W=1 mode detects attempts to write to pixels within the window. This
form of window checking supports applications which permit objects on the
screen to be picked by pointing to them with a cursor. In this mode, all pixel
writes are inhibited, whether they address locations inside or outside the
window. A window violation interrupt is requested on an attempt to write to
a pixel inside the window.
For the PIXBLT and FILL instructions, the V (overflow) bit is set to 1 if the
destination array lies completely outside the window. No interrupt request is
generated (the WVP bit in the INTPEND register is not affected) in this case.
However, if any pixel in the destination array lies within the window, the V
bit is set to 0 and a window violation interrupt is requested (the WVP bit is
set to 1). If the interrupt is enabled, the saved PC points to the instruction that
follows the PIXBLT or FILL that caused the interrupt. If the interrupt is disa-
bled, execution of the next instruction begins.
While no pixel transfers occur during the PIXBLT and FILL instructions exe-
cuted in this mode, the specified destination array is clipped to lie within the
window. In other words, the DADDR and DYDX registers are adjusted to be
the starting address, width, and height of the reduced array that is the inter-
section of the two rectangles represented by the destination array and the
window. This function can be adapted to determine the intersection of two
arbitrary rectangles on the screen - a calculation that is often performed in
windowed graphics systems.
In the case of a DRAV or PIXT instruction, an attempt to write to a pixel out-
side the window causes the V bit to be set to 1. No interrupt request is gen-
erated (the WVP bit is not affected). An attempt to write to a pixel inside the
window causes the V bit to be set to 0, and a window violation interrupt re-
quest is generated (the WVP bit is set to 1 ).
At the end of a LINE instruction, the V bit is 0 if any destination pixel proc-
essed by the instruction lies within the window; otherwise, V is 1. Attempts
to write to pixels outside the window do not cause interrupt requests to be
generated (the WVP bit is not affected). An attempt to write to a pixel inside
the window causes a window violation interrupt to be requested (the WVP
bit is set to 1) and the LI N E instruction aborts. If the interrupt is enabled, the
PC saved during the interrupt points to the instruction that follows the LI N E
instruction. If the interrupt is disabled, execution of the next instruction be-
gins.
The W=1 mode can be used to pick an object on the screen by means of the
following simple algorithm. An object previously drawn on the screen is
picked by moving the cursor to the object's position and selecting it. To de-
termine which object is pointed to, the software first sets the window to a
small region surrounding the position of the cursor. The software next steps
a second time through the same display list used to draw the current screen
until one of the objects causes a window interrupt to occur. This should be
the object pointed to by the cursor. If no object causes an interrupt, the pick
window can be enlarged and the process repeated until the object is found.
If two objects cause interrupts, the size of the pick window can be reduced
until only one object causes an interrupt.
7-26
Graphics Operations - Window Checking
7.10.2 W=2 Mode - Window Miss Detection
The W=2 mode permits a PIXBLT or FILL instruction to be aborted if any pixel
in the destination array lies cutside the window. The destination array is
written only if the array lies entirely within the window, in which case the V
(overflow) bit is set to 0, and no interrupt request is generated (the WVP bit
is not affected). If any pixel in the destination array lies outside the window,
the V bit is set to 1, and a window violation interrupt is requested (the WVP
bit is set to 1).
For the DRAV and PIXT instructions, the destination pixel is drawn only if it
lies within the window. In this case, the V bit is set to 0, and no interrupt re-
quest is generated (the WVP bit is not affected). If the destination location
lies outside the window, the pixel write is inhibited, the V bit is set to 1, and
a window violation interrupt is requested (the WVP bit is set to 1 ).
At the end of a LI N E instruction, the V bit is 0 if the last destination pixel
processed by the instruction lies within the window; otherwise, V is 1. At-
tempts to write to pixels inside the window do not cause interrupt requests to
be generated (the WVP bit is not affected). An attempt to write to a pixel
outside the window causes a window violation interrupt to be requested (the
WVP bit is set to 1) and the instruction aborts. If the interrupt is enabled, the
PC saved during the interrupt points to the instruction that follows the LINE
instruction. If the interrupt is disabled, execution of the next instruction be-
gins.
7.10.3 W=3 Mode - Window Clipping
In the W=3 mode, only writes to pixels within the window are permitted;
writes to pixels outside the window are inhibited. No interrupt request is
generated for any case.
For a PIXB LT or FI LL instruction, only the portion of the destination array ly-
ing within the window is drawn. At the start of instruction execution, the
specified destination array is automatically preclipped to lie within the window
before the first pixel is transferred. Hence, no execution time is lost attempting
to write destination pixels which lie outside the window. In the case of a
PIXBLT, the source array is preclipped to fit the adjusted dimensions of the
destination array before the transfer begins.
During execution of a DRAV or PIXT instruction, a write to a pixel inside the
window is permitted, and the V bit is set to O. An attempted write to a pixel
outside the window is inhibited, and the V bit is set to 1.
For the LI N E instruction, writes to pixels outside the window are inhibited at
drawing time; no preclipping is performed. The value of the V bit at the end
of a LINE instruction is determined by whether the last pixel calculated by the
instruction fell inside (V=O) or outside (V=1 ) the window.
7-27
Graphics Operations - Window Checking
7.10.4 Specifying Window Limits
The limits of the current window are specified in the WSTART (window start)
and WEND (window end) registers. WSTART specifies the minimum XY co-
ordinates in the window, and WEND specifies the maximum XY coordinates.
As Figure 7-10 shows, WSTART specifies the XY coordinates (Xstart,Ystart)
at the upper left corner of the window, and WEND specified the XY coordi-
nates (Xend,Yend) at the bottom right corner of the window. The origin is lo-
cated in its default position in the top left corner of the screen.
DIapIay
Origin Memory
+x
'" I'e
+y
, "-,...
v
Window
A pixel with cocrdlnates (X,V)
1188 within the window If both
X start .s X .s Xend and V start .s V S Vend
Figure 7-10. Specifying Window Limits
Figure 7-10 shows that a pixel that has coordinates (X,Y) lies within the
window if Xstart S X S Xend and Ystart S Y S Yend. If a pixel does not meet
these conditions, it lies outside the window.
When Xstart > Xend or Ystart> Yend, the window is empty; that is, it contains
no pixels. Under these conditions, the window checking hardware detects all
destination pixel addresses as lying outside the window. Note that the con-
ditions Xstart = Xend and Ystart = Yend together specify a window containing
a single pixel.
Window start and end coordinates must lie in the range (O,O) to
(+32767,+32767). A window cannot contain pixels with negative X or Y
coordinates.
7-28
Graphics Operations - Window Checking
7.10.5 Window Violation Interrupt
A window violation (WV) interrupt is requested (the WVP bit in the INTPEND
register is set to 1 ) when:
• W=1 and an attempt is made to write to a pixel inside the window or
• W=2 and an attempt is made to write to a pixel outside the window
The interrupt occurs if it is enabled by the following conditions:
• The WVE bit in the I NTEN B register is 1
• The I E bit in the status reg ister is 1
Alternatively, if the WV interrupt is disabled (IE=O or WVE=OL the window
violation can be detected by testing the value of either the V bit in the status
register or the WVP bit following the operation.
When a WV interrupt occurs, the registers that change during the LINE,
PIXBLT and FI LL instructions contain their intermediate values at the time the
violation was detected.
7.10.6 Line Clipping
The TMS34010 supports two methods for clipping straight lines to the
boundaries of a rectangular window: postclipping and preclipping. Postclip-
ping means that just before each pixel on the line is drawn, it is compared with
the window limits. If it lies outside the window, the write is inhibited. In
contrast, preclipping involves determining in advance of any drawing oper-
ations which pixels in the line lie within the window. The algorithm draws
only these pixels, and makes no attempt to write to pixels outside the window.
A preclipped line may take less time to draw since no calculations are per-
formed for pixels lying outside the window. In contrast postclipping spends
the same amount of time calculating the position of a pixel outside the win-
dow as it does calculating a pixel inside the window.
When postclipping is used, special window comparison hardware compares
the coordinates of the pixel being drawn against all four sides of the window
at once. The W=3 window-checking mode is selected, and window checking
is performed in parallel with execution of the LI N E instruction, so no overhead
is added to the time to draw a pixel. However, unless this form of clipping is
used carefully, another type of overhead may become significant. For example,
in a CAD (computer-aided design) environment where only a small portion
of a system diagram is to be displayed at once, potentially a great deal of time
could be spent performing calculations for points (or entire lines) lying off-
screen.
Preclipping is generally faster than postclipping, depending on how likely a
line is to lie outside the window. The first step in preclipping a series of lines
is to identify those that lie either entirely inside or outside the window. This
is accomplished by using an "outcode" technique similar to that of the Co-
hen-Sutherland algorithm. Those lines lying entirely outside are "trivially re-
jected" and consume no more processing time. Those lines lying entirely
within are drawn from one endpoint to the other with no clipping required.
This still leaves a third category of lines that may cross a window boundary,
and these require intersection calculations. However, this technique is pow-
7-29
Graphics Operations - Window Checking
erful for reducing the number of lines that require such calculations. While the
calculation of outcodes could be performed in software, this would represent
significant overhead for each line considered. The TMS3401 0 provides a more
efficient implementation via its CPW (compare point to window) instruction,
which compares a point to all four sides of the window at once.
The outcode technique classifies a line according to where its endpoints fall
in relation to the current clipping window. The area surrounding the window
is partitioned into eight regions, as indicated in Figure 7-11. Each region is
assigned a 4-bit code called an outcode. The outcode within the window is
00002' When an endpoint of a line falls within a particular region, it is as-
signed the outcode for that region. If the two endpoints of a line both have
outcodes 00002, the line lies entirely within the window. If the bitwise AND
of the outcodes of the two endpoints yields a value other than 00002, the line
lies entirely outside the window. Lines that fall into neither of these categories
mayor may not be partially visible within the window.
+y 0101 0100 : 0110
1
1
1
1
1
_________ +-__.....;1 __________ Y = Y MIN
1
0001 0000 0010
+-_~-+_--------- Y = Y MAX
1010
Window X=XMIN X=XMAX
Figure 7-11. Outcodes for Line Endpoints
For those lines that require intersection calculations after the outcodes have
been determined, midpoint subdivision is an efficient means of preclipping.
The object again is to ensure that drawing calculations are performed only for
pixels lying within the window. An example of the midpoint subdivision
technique is illustrated in Figure 7 -12. The line AB lies partially within the
window. The first step is to determine the coordinates of the line's midpoint
at C. These are calculated as follows:
XA + XB Y A + YB
(Xc' Yc) =
2 2
7-30
Graphics Operations - Window Checking
+y
1--------""*- V = V MAX
X=XMIN X=XMAX
(X v ) =(XA +XB VA +VB)
C· C 2' 2
(X v ) =(XA 2
D' 0
+XC VA +VC)
' 2
Figure 7-12. Midpoint Subdivision Method
Comparing the outcodes of Band C, segment BC lies entirely outside the
window and can be trivially rejected. Segment AC still lies partially within the
window and will be subdivided again. The coordinates of point D, the mid-
point of AC, are calculated as before. Point D is determined to lie within the
window. The LINE instruction is now invoked two times, for segments DC
and DA, with D selected as the starting point in each case. For each segment
the W=2 window-checking mode is selected, but the window violation inter-
rupt is disabled. When each line crosses the window boundary, the win-
dow-checking hardware detects this and the LINE instruction aborts. In this
way the LINE instruction performs drawing calculations only for portions of
DA and DC lying within the window.
7-31
Graphics Operations
7-32
Section 8
Interrupts, Traps, and Reset
The TMS3401 0 supports eight interrupts, including reset. Memory addresses
FFFFFCOOh to FFFFFFFFh contain the 32 vector addresses used during in-
terrupts, software traps and reset. Each vector is a 32-bit address that points
to the beginning of the appropriate interrupt service routine.
This section includes the following topics:
Section Page
8.1 Interrupt Priorities and Vector Addresses ............................................... 8-2
8.2 Interrupt Interface Registers ..................................................................... 8-3
8.3 External Interrupts ...................................................................................... 8-3
8.4 Internal Interrupts ...................................................................................... 8-5
8.5 Interrupt Processing .................................................................................. 8-6
8.6 Traps ............................................................................................................ 8-9
8.7 Illegal Opcode Interrupts .......................................................................... 8-9
8.8 Reset .......•.•............................................................................................... 8-10
8-1
Interrupts, Traps, and Reset - Interrupt Priories and Vector Addresses
8.1 Interrupt Priorities and Vector Addresses
Table 8-1 and Figure 8-1 summarize the TMS3401 0 interrupt vector addresses
and the interrupt priorities. RESET has the highest priority, and the illegal op-
code interrupt has the lowest. If two interrupts are requested at the same time,
the highest priority interrupt is serviced first (assuming it is enabled). RESET
and the nonmaskable interrupt cannot be disabled.
Table 8-1. Interrupt Priorities
Internal/
Int. Priority External Description and Source
Reset 1 I Device reset. Taken when the input signal at the
RESET pin is asserted low.
NMI 2 I Nonmaskable interrupt. Generated by a host
processor.
HI 3 I Host interrupt. Generated by a host processor.
01 4 I Display interrupt. Generated by the TMS3401 O.
WV 5 I Window violation interrupt. Generated by the
TMS34010.
INn 6 E External interrupts 1 and 2. Generated by
external devices.
INT2 7 E
ILLOP 8 I Illegal opcode interrupt. Generated by the
TMS34010 when an illegal opcode is en-
countered.
Trap
Number ~
OFFFFFFEOh Re..t Re..t
OFFFFFFCOh INT1 Extemel Interrupt 1
OFFFFFFAOh Extemel Interrupt 2
OFFFFFF80h
4 OFFFFFF80h
OFFFFFF40h Traps 3·7
OFFFFFF20h
OFFFFFFOOh
OFFFFFEEOh MNI Nonmaskable
OFFFFFECOh HI Host Interrupt
10 OFFFFFEAOh 01 DIsplay Interrupt
11 OFFFFFE80h WV WIndow Violation
12 OFFFFFE80h
13 OFFFFFE40h
14 OFFFFFE20h
15 OFFFFFEOOh
16 OFFFFFOEOh
17 OFFFFFDCOh
18 OFFFFFOAOh
19 OFFFFF080h
Treps 12·29
20 OFFFFFD80h
21 OFFFFFD4Oh
22 OFFFFF020h
23 OFFFFFDOOh
24 OFFFFFCEOh
25 OFFFFFCCOh
26 OFFFFFCAOh
27 OFFFFFC80h
28 OFFFFFC80h
29 OFFFFFC40h
30 OFFFFFC20h ILLDP Illegal Dpcode
31 OFFFFFCOOh Trap 31
1--32----1
Figure 8-1. Vector Address Map
8-2
Interrupts, Traps, and Reset - Registers/External Interrupts
8.2 Interrupt Interface Registers
Two registers, a subset of the I/O registers discussed in Section 6, monitor and
mask interrupt requests. These registers are summarized below; for more in-
formation, please refer to the register descriptions in Section 6.
The interrupt enable register, INTEN B, contains the interrupt mask that se-
lectively enables various interrupts. An interrupt is enabled when the status
IE (global interrupt enable) bit and the appropriate bit in the INTENB register
are both set to 1.
• X1 E (bit 1) enables external interrupt 1.
• X2E (bit 2) enables external interrupt 2.
• HIE (bit 9) enables the host interrupt.
• DIE (bit 10) enables the display interrupt.
• WVE (bit 11) enables the window violation interrupt.
The interrupt pending register, INTPEN 0, indicates which interrupts are cur-
rently pending. When an interrupt is requested, the appropriate bit in the
INTPEND register is set.
• X1 P (bit 1) indicates that external interrupt 1 is pending.
• X2P (bit 2) indicates that external interrupt 2 is pending.
• HIP (bit 9) indicates that the host interrupt is pending.
• DIP (bit 10) indicates that the display interrupt is pending.
• WVP (bit 11) indicates that the window violation interrupt is pending.
8.3 External Interrupts
External interrupt requests are received through input pins L1NT1 and L1NT2.
The two request pins are level-sensitive, active-low inputs. Each pin is dedi-
cated to an individual interrupt, allowing two independent interrupt requests
to be generated. (The pins are not encoded.) The state of the L1NT1 and
L1NT2 inputs is reflected in the X1 P and X2P bits in the INTPEND register.
The register bit is 1 if the corresponding request is active.
The interrupts generated by requests at the L1NT1 and L1NT2 inputs are referred
to as INT1 and INT2. Interrupts INT1 and INT2 are selectively enabled by
means of the X1 E and X2E bits in the INTENB register. If external interrupt
requests become active at L1NT1 and L1NT2 at the same time, and both inter-
rupts are enabled, I NT1 will be serviced first. If one or both of these interrupts
is disabled, the state of the LlNT1 and L1NT2 inputs continues to be reflected
in the X1 P and X2P bits. These bits may be polled by software to detect
transitions at the interrupt inputs.
Table 8-2 shows the interrupt trap vectors for INT1 and INT2.
8-3
Interrupts, Traps, and Reset - External Interrupts
Table 8-2. External Interrupt Vectors
Input Vector
Name Pin Address
INT1 LlNT1 FFFFFFCOh
INT2 LlNT2 FFFFFFAOh
Once an interrupt request has been initiated by driving an interrupt request pin
low, the input should continue to be driven low until the interrupt service
routine can respond to the interrupting device. If the interrupt pin is permitted
to go inactive high before it has been recognized by the interrupt service rou-
tine, the request may be missed. If the active level is maintained after returning
from the interrupt service routine, however, the interrupt will be taken once
again.
The RETI instruction restores the ST (status) and PC (program counter) reg-
isters to their original state just prior to the interrupt. (This would not be the
case, however, if for some reason the values for these registers, saved on the
stack, were altered by the interrupt service routine). Assuming that the IE bit
in the restored ST is a 1, interrupts are again enabled by the time the RETI in-
struction finishes executing. If an interrupt request is active during the last
state of the RETI instruction, and the interrupt is enabled in the INTENB reg-
ister, the interrupt will be taken immediately following the RET!.
The interrupt service routine typically writes to the interrupting device to clear
the interrupt· request before executing an RETI (return from interrupt) in-
struction. An example of the last three instructions in a typical interrupt service
routine is shown below, where DEVICE is the symbolic address of the inter-
rupting device:
CLR AO
MOVE AO,@DEVICE
RETI
The interrupt request is cleared by the MOVE instruction above, which writes
a 0 to the device address. The maximum asynchronous delay from the end of
the write cycle (measured from the low-to-high transition of W) to the result-
ing low-to-high transition at the GSP's interrupt request input should be no
more than six local clock periods.
Signals input to the local interrupt pins are assumed to be asynchronous to the
GSP local clocks, and are synchronized internally by the GSP before they are
processed. The GSP samples the state of the LlNT1 and LlNT2 inputs at each
high-to-Iow transition of LCLK1, and updates the X1 P and X2P bits in the
INTPEND register accordingly (an active-low input is seen as a one in the
appropriate register bit). The delay from the transition at the input to the
corresponding change in the X1 P or X2P bit is from one to two states, de-
pending on the transition's phase relationship to LCLK1.
8-4
Interrupts, Traps, and Reset - Internal Interrupts
8.4 Internal Interrupts
Several internal conditions are associated with specific interrupts. Table 8-3
summarizes these interrupts. If two internal interrupts are requested simul-
taneously, or if two or more internal interrupt requests are pending, the highest
priority interrupt is serviced first; NMI has the highest priority, followed by HI,
01, and WV. When internal and external interrupts are pending, the internal
interrupts are serviced first (with the exception of the ILLOP interrupt).
Table 8-3. Interrupts Associated with Internal Events
Vector
Name Function Level Location Description
NMI Nonmaskable 8 FFFFFEEOh The host processor sets the NMI bit in the
interrupt HSTCTL register to a 1.
HI Host interrupt 9 FFFFFECOh The host processor sets the INTIN bit in the
HSTCTL register to a 1.
DI Display interrupt 10 FFFFFEAOh A particular horizontal line on the video display
is being refreshed. The line number is specified
in the DPYINT register.
WV Window violation 11 FFFFFE80h An attempt has been made to move a pixel to a
interrupt destination location that lies inside or outside a
specified window. depending on the selected
windowing mode.
ILLOP Illegal operand 30 FFFFFC20h See Section 8.7.
interrupt
The nonmaskable interrupt, or N M I, occurs when a host processor requests
an interrupt by writing a 1 to the N M I bit in the HSTCTL register. This inter-
rupt cannot be disabled, and always occurs as soon as possible following the
request. The N M I is delayed only for completion of an instruction already in
progress, or until the next interruptible point of an interruptible instruction
such as a PIXBLT is reached.
The NMI mode bit in the HSTCTL register determines whether or not context
information is saved on the stack when a nonmaskable interrupt occurs:
• If NMIM = 0, the PC and ST are pushed on the stack before the interrupt
is serviced.
• If NMIM = 1, nothing is saved on the stack before the interrupt is ser-
viced.
The TMS3401 0 automatically clears the NMI bit at the time it takes the inter-
rupt. After setting the NMI bit, the host processor can determine when the
TMS34010 has taken the interrupt by polling the NMI bit until it changes from
a 1 to a O.
The display interrupt (01) is used to coordinate processing activity with the
refreshing of particular areas of the display. The display interrupt request be-
comes active when a particular display line, specified in the OPYINT register,
is output to the monitor screen. At the start of each horizontal blanking period,
the VCOUNT register is compared to the OPYINT register. When the vertical
count value in VCOUNT = OPYINT, a display interrupt request is generated.
If enabled, the interrupt is taken.
8-5
Interrupts, Traps, and Reset - Interrupt Processing
8.5 Interrupt Processing
An interrupt is said to be pending if it has been requested but has not yet been
processed. If a pending interrupt is enabled, and no interrupt of higher priority
is pending at the same time, the interrupt is accepted by the TMS3401 0 at the
end of the current instruction (or at the next interruptible point in the middle
of a PIXBLT or FILL instruction). When the TMS3401 0 takes an interrupt, it
performs the following actions:
1) The TMS3401 0 pushes the PC on the stack.
2) The TMS34010 pushes the ST on the stack. PIXBLT and FILL in-
structions that are interrupted by external, host, and nonmaskable (if
NMIM=O) interrupts set the PBX bit in the ST before pushing the ST.
3) The TMS3401 0 modifies the contents of the ST as follows:
Reserved
4) The TMS34010 fetches the interrupt vector from external memory into
the PC.
5) The TMS3401 0 begins executing the instruction pointed to by the new
PC value.
In step 5, the TMS3401 0 resumes instruction execution at the entry point of
the interrupt service routine. At the time the first instruction of the service
routine begins execution, the new status register contents imply the following
conditions:
• All interrupts are disabled (except NMI and reset)
• Field 0 is 16 bits long and is zero extended
• Field 1 is 32 bits long and is zero extended
The service routine can allow itself to be interrupted by loading a new inter-
rupt-enable mask into the INTENB register and setting status bit IE to 1. The
INTENB mask value is selected to determine which interrupts can interrupt the
currently executing service routine. The service routine can also load new field
sizes if values other than the defaults are required.
The last instruction in any interrupt service routine must be RETI (return from
interrupt). Unlike the RETS (return from subroutine) instruction, which only
pops the PC from the stack, RETI pops both the ST and PC. This restores the
original state of the interrupted program so that execution can proceed from
the point at which the interrupt occurred.
8-6
Interrupts, Traps, and Reset - Interrupt Processing
8.5.1 Interrupt Latency
An external interrupt, host interrupt request, or NMI request is delayed by an
amount of time that depends on the instruction in progress and on the local
memory bus traffic at the time of the request.
The delay from an interrupt request to the time that the first instruction of the
interrupt service routine begins execution is the sum of six potential sources
of delay:
1) Interrupt request recognition
2) Screen-refresh cycle
3) DRAM-refresh cycle
4) Host- indirect cycle
5) Instruction interrupt
6) Interrupt context switch
In the best case, items 2 through 5 cause no delay. The minimum delay due
to items 1 and 6 is 17 machine states.
• The interrupt request recognition delay is the time required for a
request to be internally synchronized to the local clock. In the case of
an external interrupt request, the delay is measured from the high-to-Iow
transition of the INT1 or INT2 pin. In the case of a host interrupt or NMI
request, the delay is measured from completion of the host's write to the
INTIN or NMI pin.
• The screen-refresh and DRAM-refresh cycles are a potential source
of delay, but in fact occur rarely and are unlikely to delay an interrupt.
• The likelihood of a delay caused by a host-indirect cycle is small in
most instances, but this depends on the application. The delay due to a
single host-indirect cycle is two machine states, assuming no wait states,
but mUltiple host-indirect cycles occurring within a brief period of time
could cause additional delays. Theoretically, a fast host processor could
generate so many local memory cycles that the TMS34010 would be
prevented from servicing interrupts for an indefinite period.
• The instruction interrupt time refers to the time required for an in-
struction that was already executing at the time the interrupt request was
received to either complete or to reach the next interruptible point in an
instruction (such as a PIXBLT, FILL, or LINE).
• The interrupt context switch operation pushes the PC and ST onto
the stack, and fetches the PC for the interrupt service routine from the
appropriate vector in memory.
Table 8-4 shows the minimum and maximum times for each of the six oper-
ations listed. The interrupt latency is calculated as the sum of the numbers in
the six rows. In the best case, the interrupt latency is only 17 machine states.
The worst-case latency can be as high as 22 machine states plus the delays
due to host-indirect cycles and instru~tion completion. Table 8-5 shows in-
struction interrupt times for some of the longer, non interruptible instructions.
Table 8-5 also shows the instruction completion time for a JRUC instruction
8-7
Interrupts, Traps, and Reset - Interrupt Processing
that jumps to itself - the TMS3401 0 may be executing this instruction if the
software is simply waiting for an interrupt.
Table 8-4. Six Sources of Interrupt Delay
Latency (In States)
Operation
Min Max
Interrupt recognition 1 2
Instruction interrupt 0 See Table 8-5
DRAM-refresh cycle 0 2
See Note 2
Screen-refresh cycle 0 2
See Note 2
Host-indirect cycle 0 See Note 1
Interrupt context switch 16 16
Notes: 1) The latency due to host-indirect cycles depends on both the
hardware system and the application. Theoretically, a host pro-
cessor could generate so many local memory cycles that the
TMS34010 could effectively be prevented from servicing inter-
rupts. The delay due to a single host-indirect cycle is two machine
states, assuming no wait states.
2) DRAM-refresh and screen-refresh cycle times assume no wait
states.
3) Context switch time assumes that the SP is aligned to a word
boundary; that is, the four LSBs of the SP are Os. If the SP is not
aligned, the delay is 28 states.
Table 8-5. Sample Instruction Completion Times
Worst-Case Instruction
Instruction Interrupt Time (In States)
SP Aligned SP Not Aligned
DIVS AO,A2 43 43
MMFM SPALL 72 144
MMTM SPALL 73 169
Wait: JRUC wait 1 1
Notes: 1) The worst-case instruction interrupt time is equal to the instruction
execution time less one machine state (except for PIXBLTs, FILLs,
and LINE).
2) The SP-aligned case assumes that the SP is aligned to a word
boundary in memory.
8-8
Interrupts, Traps, and Reset - Traps/Illegal Opcodes
8.6 Traps
The TMS3401 0 supports 32 software traps, numbered 0 through 31. Soft-
ware traps behave similarly to interrupts, except that they are initiated when
the TMS3401 0 executes a TRAP instruction. Unlike an interrupt, a software
trap cannot be disabled.
When the TMS3401 0 executes a TRAP instruction, it performs the same se-
quence of actions that it performs for interrupts. The TRAP 1 through TRAP
31 instructions cause the status register and the PC to be pushed onto the
stack. TRAP 0 is similar to a hardware reset because it does not push the
status register or PC onto the stack; it differs from a hardware reset because it
does not cause the TMS3401 O's internal registers to be set to a known initial
state. TRAP 8 is similar to an NMI interrupt, except that the NMIM (NMI
mode) bit in the HSTCTLL register has no effect on instruction execution; the
status register and PC are stacked unconditionally when TRAP 8 is executed.
A 32-bit vector address is associated with each software trap. To determine
the vector address for a trap number N, where N = 0 through 31, subtract
32N from FFFFFFEOh. Figure 8-1 on page 8-2 shows the vector addresses
for the software traps.
8.7 Illegal Opcode Interrupts
The TMS3401 0 recognizes several reserved opcodes as illegal. When one of
these opcodes is encountered in the instruction stream, the TMS34010 traps
to vector number 30, located at memory address FFFFFC20h. An illegal op-
code is similar in effect to a TRAP 30 instruction. The illegal opcode interrupt
cannot be disabled. Table 8-6 lists ranges of illegal opcodes.
Table 8-6. Illegal Opcodes Ranges
0200h through 02FFh
0400h through 04FFh
0800h through 08FFh
OAOOh through OAFFh
OCOOh through OCFFh
OEOOh through OEFFh
3400h through 37FFh
7000h through 7FFFh
9EOOh through 9FFFh
BEOOh through BFFFh
D800h through DEFFh
FEOOh through FFFFh
8-9
Interrupts, Traps, and Reset - Reset
S.S Reset
Reset puts the TMS3401 0 into a known initial state that is entered when the
input signal at the RESET pin is asserted low. RESET must remain active low
for a minimum of 40 local clock (LCLK1 or LCLK2) periods to ensure that the
TMS34010 has sufficient time to establish its initial internal state. While the
reset signal remains asserted, all outputs are in a known state, no DRAM-
refresh cycles take place, and no screen-refresh cycles are performed.
At the low-to-high transition of the RESET signal, the state of the HCS input
determines whether the TMS3401 0 is halted (host-present mode) or whether
it begins executing instructions (self-bootstrap mode):
• Host-Present Mode
If HCS is high at the end of reset, TMS34010 instruction execution is
halted and remains halted until the host clears the H LT (halt) bit in
HSTCTL (host control register). Following reset, the eight RAS-only
refresh cycles required to initialize the dynamic RAMs are performed
automatically by the TMS3401 0 memory control logic. As soon as the
eight RAS-only cycles are completed, the host is allowed access to
TMS34010 memory. At this time, the TMS34010 begins to automat-
ically perform DRAM refresh cycles at regular intervals. The TMS3401 0
remains halted until the host clears the H LT bit. Only then does the
TMS34010 fetch the level-O vector address from location FFFFFFEOh
and begin executing its reset service routine.
• Self-Bootstrap Mode
If HCS is low at the end of reset, the TMS3401 0 first performs the eight
RAS-only refresh cycles required to initialize the DRAMs. Immediately
following the eight RAS-only cycles, the TMS3401 0 fetches the level-O
vector address from location FFFFFFEOh, and begins executing its reset
service routine.
Unlike other interrupts and software traps, reset does not save previous ST or
PC values. This is because the value of the stack pointer just before a reset is
generally not valid, and saving its value on the stack is unnecessary. A TRAP
o instruction, which uses the same vector address as reset, similarly does not
save the ST or PC values.
8.8.1 Asserting Reset
A reset is initiated by asserting the RESET input pin at its active-low level. To
reset the TMS3401 0 at power up, RESET must remain active low for a mini-
mum of 40 local clock periods after power levels have become stable. At times
other than power up, the TMS3401 0 is also reset by holding RESET low for a
minimum of 40 clock periods. The 40-clock interval is required to bring
TMS34010 internal circuitry to a known initial state. While RESET remains
asserted, the output and bidirectional signals are driven to a known state.
The TMS34010 drives its RAS signal inactive high as long as RESET remains
low. The specifications for certain DRAM and VRAM devices, including the
TMS4161, TMS4164 and TMS4464 devices, require that the RAS signal be
driven inactive-high for 100 microseconds during system reset. Holding the
RESET signal low for 150 microseconds causes the RAS signal to remain high
8-10
Interrupts, Traps, and Reset - Reset
for the 100 microseconds required to bring the memory devices to their initial
states. DRAMs such as the TMS4256 specify an initial RAS high time of 200
microseconds, requiring that RESET be held low for 250 microseconds. In
general, holding RESET low for t microseconds ensures that RAS remains high
initially for t - 50 microseconds.
8.8.2 Suspension of DRAM-Refresh Cycles During Reset
An active-low level at the RESET pin is considered to be a power-up condition,
and DRAM refresh is not performed until RESET goes inactive high. Conse-
quently, the previous contents of the local memory may not be valid after a
reset.
8.8.3 State of VCLK During Reset
In many systems, the VCLK pin continues to be clocked during reset. How-
ever, a system in which VCLK is not clocked during reset should maintain
VCLK at the logic high level while it is not being clocked. This is necessary
to ensure that the video counters are reset properly. In fact, VCLK should be
held at the logic high level when it is not being clocked regardless of whether
the device is being reset. While VCLK is low, storage nodes in the VCOUNT
and HCOUNT registers rely on their internal capacitance to maintain their
state. If VCLK remains low for a sufficiently long period, these registers are
subject to bit errors due to charge leakage.
8.8.4 Initial State Following Reset
While the RESET pin is asserted low, the TMS3401 O's output and bidirectional
pins are forced to the states listed in Table 8-7.
Table 8-7. State of Pins During a Reset
Outputs Driven Outputs Driven Bidirectional
To High level To Low Level Pins Driven to
High Impedance
OOOUT BLANK HSYNC
HROY t VSYNC
DEN HOQ-H015
LAL LAOQ-LA015
TR/QE
RAS
CAS
W
HINT
HLOA/EMUA
t HROY will stay high during reset if the HCS input is also high.
Immediately following reset, all I/O registers are cleared (set to OOOOh), with
the possible exception of the HLT bit in the HSTCTL register. The HLT bit is
set to 1 if HCS is high just before the low-to-high transition of RESET.
8-11
Interrupts, Traps, and Reset - Reset
Just before execution of the first instruction in the reset routine, the
TMS34010's internal registers are in the following state:
• General-purpose register files A and Bare uninitialized.
• The ST is set to 0000001 Oh.
• The PC contains the 32-bit vector fetched from memory address
FFFFFFEOh.
The instruction cache is in the following state at this time:
• The SSA (segment start address) registers are uninitialized.
• The LRU (least recently used) stack is set to the initial sequence 0,1,2,3,
where 0 occupies the most-recently-used position, and 3 occupies the
least-recently-used position.
• All P (present) flags are cleared to Os.
S.S.5 Activity Following Reset
Immediately following the low-to-high transition of RESET, the TMS34010
performs a series of eight RAS-only memory cycles to bring the DRAMs and
VRAMs to their initial operating states. These cycles are completed before any
accesses of the TMS34010's memory (by either the TMS34010 or host pro-
cessor) are allowed to occur. If the host processor attempts to access the
TMS34010 memory indirectly before the eight RAS-only cycles have com-
pleted, it receives a not-ready signal from the TMS3401 0 until the cycles have
completed. The eight RAS-only cycles occur regardless of the initial value to
which the H LT bit in the HSTCTL register is set.
Each of the eight RAS-only cycles is a standard DRAM-refresh cycle. The RF
bus status signal output with the row address is active low. The row address
is all Os.
Following the eight RAS-only cycles, the TMS34010 automatically begins to
initiate a new DRAM-refresh cycle every 32 TMS34010 local clock cycles.
The first DRAM refresh cycle begins approximately 32 local clock periods after
the end of reset. A DRAM-refresh cycle is initiated every 32 TMS3401 0 clock
cycles until the DRAM-refresh rate is changed by the TMS34010 or host
processor.
The TMS3401 0 is configured by means of an external signal input on the HCS
pin to either:
• Begin executing instructions immediately after reset is completed (self-
bootstrap mode), or
• Halt until the host processor instructs it to begin executing (host-present
mode).
8-12
Interrupts, Traps, and Reset - Reset
8.8.5.1 Self -Bootstrap Mode
In self-bootstrap mode, the TMS34010 begins executing instructions imme-
diately following reset. This mode is typically used in a system in which the
reset vector and reset service routine are contained in nonvolatile memory,
such as a bootstrap ROM. This type of system does not necessarily require a
host processor, and the TMS34010 may be responsible for performing host
processor functions for the system.
The TMS3401 0 is configured in self-bootstrap mode when the HCS pin is low
just before the low-to-high transition of RESET. The low HCS level forces the
HLT bit to O. Immediately following the end of reset and the eight RAS-only
cycles, the TMS3401 0 fetches the level-O vector address and begins executing
the reset interrupt routine.
At the low-to-high transition of RESET, the HCS input is internally delayed
before being checked to determine how to set the HLT bit. In a system with-
out a host processor, for instance, this permits the HCS and RESET pins to be
tied together, eliminating the need for additional external logic.
Transitions of the HCS and RESET signals are assumed to be asynchronous
with respect to the TMS3401 0 local clock. HCS and RESET are internally syn-
chronized to the local clock by being held in latches for at least one clock pe-
riod before being used by the TMS3401 O. The delay through the synchronizer
latch is from one to two local clock periods, depending on the phase of the
signal transitions relative to the clock. To permit the HCS and RESET pins to
be wired together, TMS340"i 0 on-chip logic delays the HCS low-to-high
transition to ensure that it is detected after the RESET low-to-high transition.
The level of the delayed HCS signal at the time the low-to-high RESET transi-
tion is detected determines the setting of the HLT bit.
8.8.5.2 Host-Present Mode
Host-present mode assumes that a host processor is connected to the
TMS34010's host interface pins. In this mode, the TMS3401 0 local memory
can be composed entirely of RAM (no ROM). Fo"owing reset, the host pro-
cessor must download the initial program code, interrupt vectors, and so on,
before allowing the TMS3401 0 to begin executing instructions.
The TMS3401 0 is configured in host-present mode as follows. On the trailing
edge of RESET, the HCS (host interface chip select) input is sampled. If the
HCS pin is inactive high, internal logic forces the HLT (halt) bit to a 1. In this
fashion, the TMS3401 0 is automatically halted following reset, and does not
begin execution of its reset service routine until the host processor loads a 0
to HLT. In the meantime, the host processor is able to load the memory and
I/O registers with the appropriate initial values before the TMS3401 0 begins
executing instructions. This may include writing the reset vector and reset
service routine into the TMS3401 O's memory, for example.
No additional external logic is required to force HCS high before the low-to-
high transition of RESET. The simple external decode logic typically used
drives the HCS input active low only when one of the TMS34010's host in-
terface registers is addressed by the host processor. Assuming that the host
processor is not actively chip-selecting the TMS3401 0 at the end of reset, HCS
is high.
8-13
Interrupts, Traps, and Reset
8-14
Section 9
Screen Refresh and Video Timing
The TMS34010 generates the synchronization and blanking signals used to
drive a video screen in a graphics system. The GSP can be programmed to
support a variety of screen resolutions and interlaced or noninterlaced video.
If desired, the GSP can be programmed to synchronize to externally generated
video signals. The GSP also supports the use of video RAMs by generating
the memory-to-register cycles necessary to refresh a screen.
This section includes the following topics:
Section Page
9.1 Screen Sizes ............................................................................................... 9-2
9.2 Video Timing Signals ................................................................................ 9-3
9.3 Video Timing Registers ............................................................................. 9-4
9.4 Relationship Between Horizontal and Vertical Timing Signals ........... 9-5
9.5 Horizontal Video Timing ........................................................................... 9-6
9.6 Vertical Video Timing ................................................................................ 9-8
9.7 Display Interrupt ...................................................................................... 9-13
9.8 Dot Rate .................................................................................................... 9-14
9.9 External Sync Mode ................................................................................ 9-15
9.10Video RAM Control ................................................................................. 9-18
9-1
Screen Refresh and Video Timing - Screen Sizes
9.1 Screen Sizes
The TMS3401 O's 26-bit word address provides direct addressing of up to 128
megabytes of external memory. This address reach supports very high-
resolution displays. For example, the designer of a large TMS34010-based
system could decide to use the lower half of the address space for display
memory, and use the upper half for storing programs and data. Half of this
memory space, for example, could be used as a display memory, and the re-
maining memory can be used for programs and data. The 64-megabyte dis-
play memory in this example could support the following display sizes:
., 81 92 by 4096 pixels at 1 6 bits per pixel
• 8192 by 8192 pixels at 8 bits per pixel
• 16,384 by 8192 pixels at 4 bits per pixel
• 16,384 by 1 6,384 pixels at 2 bits per pixel
• 32,768 by 16,384 pixels at 1 bit per pixel
The video timing registers also support high-resolution displays. The 16-bit
vertical counter register, VCOUNT, directly supports screen lengths of up to
65,536 lines. The 16-bit horizontal counter register, HCOUNT, does not di-
rectly limit the horizontal resolution. Each horizontal line can be programmed
to be up to 65,536 VCLK (video clock) periods long. The VCLK period,
however, is an arbitrary number of dot-clock periods in length, depending on
the external divide-down logic used to produce the VCLK signal from the dot
clock. Thus, the number of pixels per line supported by the GSP horizontal
timing registers is limited only by the amount of video memory that is present.
Note that frame buffers in excess of 224 bits may require an external counter
to determine which VRAM serial outputs should be enabled during a scan line.
This external counter would increment upon detecting a 1 -to-O transition of
the logical address bit 23 during successive screen-refresh cycles. To support
applications requiring panning and scrolling of the frame buffer, the initial va-
lue of this counter immediately following vertical retrace should be capable of
being loaded under program control.
9-2
Screen Refresh and Video Timing - Video Timing Signals
9.2 Video Timing Signals
The TMS3401 0 generates horizontal sync, vertical sync, and blanking signals
(HSYNC, VSYNC, and BLANK) on chip. The GSP's video timing logic is driven
by the video input clock (VClK). The sync and blanking signals control the
horizontal and vertical sweep rates of the screen and synchronize the screen
display to data output by the VRAMs.
HSYNC is the horizontal sync signal used to control external video circuitry.
It may be configured as an input or an output via the DXV and HSD
bits in the DPYCTl register. When DXV=O and HDS=O, external
video is selected and HSYNC is an input. Otherwise, HSYNC is an
output.
VSYNC is the vertical sync signal used to control external video circuitry. It
may be configured as an input or an output via the DXV bit in the
DPYCTl register. If DXV=1, internal video is selected and VSYNC is
an output. If DXV=O, external video is selected and VSYNC is an in-
put.
BlAN K is used to turn off a CRT's electron beam during horizontal and
vertical retrace intervals. The signal output at the BLANK pin is a
composite of the internally generated horizontal and vertical blank-
ing signals. BLANK can also be used to control starting and stopping
of the VRAM shift registers.
VCLK is derived from the dot clock of the external video system. VClK
drives the internal video timing logic.
Holding VClK low for long periods may cause video counter errors. When
VClK is not being clocked for long periods, it should be held at the logic high
level. While VClK is low, the storage nodes within the device rely on their
internal capacitance to maintain state information, and if VClK is held low for
a sufficiently long time, charge leakage may cause bit errors.
9-3
Screen Refresh and Video Timing - Video Timing Registers
9.3 Video Timing Registers
The video timing registers are a subset of the 110 registers described in Section
6. The values in the video timing registers control the video timing signals.
These registers are divided into two groups:
• Horizontal timing registers control the timing of the HSYNC signal
and the internal horizontal blanking signal.
HCOUNT counts the number of VCLK periods per horizontal scan
line.
HESYNC specifies the point in a horizontal scan line at which the
HSYNC signal ends.
HEBLNK specifies the endpoint of the horizontal blanking interval.
HSBLNK specifies the starting point of the horizontal blanking
interval.
HTOTAL defines the number of VCLK periods allowed per hori-
zontal scan line.
• Vertical timing registers control the timing of the VSYNC signal and
the internal vertical blanking signal.
VCOUNT counts the horizontal scan lines in the screen display.
VESYNC specifies the endpoint of the VSYNC signal.
VEBLN K specifies the endpoint of the vertical blanking interval.
VSBLNK specifies the starting point of the vertical blanking in-
terval.
VTOTAL specifies the value of VCOUNT at which VSYNC may
begin.
9-4
Screen Refresh and Video Timing - Horizontal vs. Vertical Signals
9.4 Relationship Between Horizontal and Vertical Timing Signals
Figure 9-1 illustrates the relationship between the horizontal and vertical tim-
ing signals in the construction of a two-dimensional raster display pattern.
The vertical sync and blanking signals span an entire frame. The horizontal
sync and blanking signals span a single horizontal scan line within the frame.
I Horizontal Internal-----tl
W LHSYNe
L..HBLNK
I
Vertloal
'I~
TT T
i (.)
I; I~
~ ~
; m~
z
!z ~W
:)
o(.) ::t: ::t: ~
CD
::t:
::t:
t Start New Line
Figure 9-1. Horizontal and Vertical Timing Relationship
Figure 9-1 illustrates the following terms and phrases, which are used
throughout this section:
• HBLNK and VBLNK are internal horizontal and vertical blanking signals
that combine to form the BLANK signal output. (HBLNK and VBLNK
cannot be accessed at TMS34010 pins.) The display is active (not
blanked) only when HBLNK and VBLNK are both inactive high.
• Horizontal front porch refers to the interval between the beginning
of horizontal blanking and the beginning of the horizontal sync signal.
• Horizontal back porch is the interval between the end of the hori-
zontal sync signal and the end of horizontal blanking.
• Vertical front porch refers to the interval between the beginning of
vertical blanking and the beginning of the vertical sync signal.
• Vertical back porch is the interval between the end of the vertical sync
signal and the end of vertical blanking.
9-5
Screen Refresh and Video Timing - Horizontal Video Timing
9.5 Horizontal Video Timing
The following discussion applies to internally generated video timing (the DXV
and HSD bits in the DPYCTL register are set to 1 and 0, respectively). Hori-
zontal timing signals are the same for interlaced and non interlaced video.
The HESYNC, HEBLNK, HSBLNK, and HTOTAL registers control horizontal
signal timing as shown in Figure 9-2. All horizontal timing parameters are
specified as mUltiples of VCLK. The time between the start of two successive
HSYNC pulses is specified by HTOTAL. HCOUNT counts from 0 to the value
in HTOTAL and then repeats. The value in HTOTAL represents the number
of VCLK periods, minus one, per horizontal scan line. The value in HESYNC
represents the duration of the sync pulse, minus one. The values in HEBLNK
and HSBLNK specify the beginning and end points of the horizontal blanking
interval.
I Horz. I Horz I Horz. I
~
I
I ~~~~ I Sync I ~~ I I
-~t Y l~1
!L-
HESYNC+1 I I
J4 .1 I I I
:'-HEBLNK+1--..l I I
111 HSBLNK+1---~~1
I
1 I I
~~-----HTOTAL+1-----.t~1
Figure 9-2. Horizontal Timing
Figure 9-3 shows the internal logic used to generate the horizontal timing
signals. HCOUNT is incremented once each VCLK period (on the high-to-Iow
transition) until it equals the value in HTOTAL. On the next VCLK period
following HCOUNT=HTOTAL, HCOUNT is reset to 0, and begins counting
again.
The limits of the horizontal sync pulse are defined by the values in HESYNC
and HTOTAL. HSYNC is driven active low when HCOUNT=HTOTAL; it is
driven inactive high when HCOUNT=HESYNC. After HCOUNT becomes
equal to HTOTAL or HESYNC, there is a one-clock delay before the
active/inactive transition takes place at the HSYNC pin.
The internal HBLNK signal is driven active low after HCOUNT=HSBLNK; it is
driven inactive high after HCQUNT=HEBLNK. HBLNK is logically ORed (ne-
gative logic) with VBLNK to produce the BLANK signal; that is, BLANK goes low
when either HBLNK or VBLNK is low. After HCOUNT becomes equal to
HSBLNK or HEBLNK, there is a one-clock delay before the transition takes
place at the BLANK pin.
9-6
Screen Refresh and Video Timing - Horizontal Video Timing
VCLK - - - - - t i l
Figure 9-3. Horizontal Timing logic - Equivalent Circuit
Figure 9-4 illustrates horizontal signal generation. In this example,
HTOTAL=N, HSBLNK=N-2, HESYNC=2, and HEBLNK=4. Signal transitions
at the HSYNC and BLANK pins occur at high-to-Iow VCLK transitions. After
HCOUNT becomes equal to HTOTAL, HSBLNK, HESYNC, or HEBLNK, there
is a one-clock delay before the transition takes place at the HSYNC or BLANK
pin. When HCOUNT=HSBLNK (shortly before the end of the horizontal
scan), horizontal blanking begins. At this time, the DIP (display interrupt) bit
in the INTPEND register is set to 1 if VCOUNT=DPYINT. The next screen-
refresh cycle may also occur at this time - the GSP can be programmed to re-
fresh the screen after one, two, three, or four scan lines.
VCLK
Horizontal Horizontal Horizontal
Front Porch Sync Pulse Back Porch
HSBLNK = N-2 HTOTAL = N
HESYNC = 2 HEBLNK = 4
Figure 9-4. Example of Horizontal Signal Generation
9-7
Screen Refresh and Video Timing - Vertical Video Timing
9.6 Vertical Video Timing
The following discussion applies to internally generated video timing (the DXV
bit in the DPYCTL register is set to 1).
The VESYNC, VEBLNK, VSBLNK, and VTOTAL registers control vertical signal
timing as shown in Figure 9-5. All vertical timing parameters are specified as
multiples of the horizontal sweep time H, where
H = (HTOTAL + 1) x (VCLK period)
VTOTAL specifies the time interval between the start of two successive vertical
sync pulses; this value is the number of H intervals, less one, in each vertical
frame. VESYNC represents the duration of the VSYNC pulse, less one, in each
vertical frame. VSYNC's high-to-Iow and low-to-high transitions coincide with
high-to-Iow transitions at the HSYNC pin.
VSBLNK and VEBLNK specify the starting and ending points of vertical
blanking. Blanking begins when VCOUNT=VSBLNK and ends when
VCOUNT=VEBLNK. Assuming that horizontal blanking is active at the start
of each HSYNC pulse, transitions of the internal vertical blanking signal,
VBLNK, occur while horizontal blanking is active.
I Vert I I Vert I
~
I
I Front I Vert. I Back I I
I Porch I Sync I Porch I '. ~I
------t 1 I ! L-
IVESVNC+1 I I I
f4 ~I I I I
~VEBLNK+1~ I I
L V6BLNK+1---~~1 I
r ' I
!e-~-----VTOTAL+1-----.t~1
Figure 9-5. Vertical Timing for Noninterlaced Display
Figure 9-6 shows the internal logic that generates the vertical timing signals.
VCOUNT increments at the beginning of each HSYNC pulse until it equals the
value in VTOTAL. When VCOUNT=VTOTAL, VCOUNT is reset to 0 and be-
gins counting again. VSYNC is driven active low after VCOUNT=VTOTAL; it
is driven inactive high after VCOUNT=VESYNC. The internal VBLNK signal is
driven active low after VCOUNT=VSBLNK; it is driven inactive high after
VCOUNT=VEBLNK. VBLNK is logically ORed (negative logic) with HBLNK to
produce the BLANK signal. This description applies to a noninterlaced display.
The vertical timing changes slightly for an interlaced display.
9-8
Screen Refresh and Video Timing - Vertical Video Timing
HSYNC----M
Figure 9-6. Vertical Timing logic - Equivalent Circuit
9.6.1 Noninterlaced Video Timing
Noninterlaced scan mode is selected by setting the NIL bit in the DPYCTL
register to 1. In this mode, each video frame consists of a single vertical field.
Figure 9-7 shows the path traced by the electron beam on the screen. Box A
shows the vertical retrace, which is an integral number of horizontal scan lines
in duration. Box B shows the active portion of the frame. Solid lines represent
lines that are displayed; dashed lines are blanked.
Monitor Screen Monitor Screen
..................................
............................................
(a)
Figure 9-7. Electron Beam Pattern for Noninterlaced Video
Figure 9-8 illustrates the video timing signals that generate the display. In this
example, VSBLNK=8, VTOTAL=9, VESYNC=1, and VEBLNK=2. (In actual
9-9
Screen Refresh and Video Timing - Vertical Video Timing
applications, much larger values are used; these values were chosen for illus-
tration only.) Each horizontal scan line is preceded by a horizontal retrace.
The horizontal scan pattern repeats until VCOUNT=VTOTAL; VCOUNT is then
reset to 0, and vertical retrace returns the beam to the top of the screen. BLANK
is active low during both horizontal and vertical retrace intervals.
VCOUNT is incremented each time HCOUNT is reset to 0 at the end of a scan
line. The VSYNC output begins when VCOUNT=VTOTAL, coinciding with the
start of HSYNC. The VSYNC output ends when VCOUNT=VESYNC; this also
coincides with the start of an HSYNC pulse.
The starting screen-refresh address is loaded from DPYSTRT into DPYADR
at the end of the last active horizontal scan line preceding vertical retrace. This
load is triggered when HCOUNT=HSBLNK and VCOUNT=VSBLNK.
VCOUNT
"HBLNK"
I I
I I
II II I I
VBLNK I I
~~~----~I--~ ~--~I-----
I I I
Vertical
Sweep
Horizontal
-------4~,~_ll__------------------1r,'---
I I
I
I
•
Sweep
I I
~~••l•.-----------~(!)~----------~
VSBLNK =.8 VTOTAL = 9
VESYNC = 1 VEBLNK = 2
Figure 9-8. Noninterlaced Video Timing Waveform Example
9-10
Screen Refresh and Video Timing - Vertical Video Timing
9.6.1.1 Interlaced Video Timing
Interlaced scan mode is selected when the NIL bit in the DPYCTL register is
set to O. In this mode, each display frame is composed of two fields of hori-
zontal scan lines. The display consists of alternate lines from the two fields.
This doubles 'the display resolution while only slightly increasing the frequency
with which data is supplied to the screen.
Figure 9-9 illustrates the path traced by the electron beam on the screen.
Figure 9-10 shows the timing waveforms used to generate the display in Fig-
ure 9-9. In this example, VSBLNK=6, VTOTAL=7, VESYNC=1, and
VEBLNK=2. (In actual applications, much larger values are used; these values
were chosen for illustration only.)
In interlaced mode, two separate vertical scans are performed for each frame -
one for the even line numbers (even field) and one for the odd line numbers
(odd field). The even field is scanned first, starting at the top left of the screen
(see Figure 9-9 b). When VCOUNT=VTOTAL, the vertical retrace returns the
beam to the top of the screen, and the odd field is scanned (Figure 9-9 d).
The electron beam starts scanning the odd and even fields at different points.
The reason for this is illustrated in Figure 9-10. The end of the VSYNC pulse
that precedes the even field coincides with start of an HSYNC pulse; however,
the VSYNC pulse that precedes the odd field ends exactly halfway between two
HSYNC pulses
Even Reid ~ Odd Reid
____________ ______
~A~ ~ ____ ~
A
Monitor Screen Monitor Screen Monitor Screen Monitor Screen
............................
......................... ................
(a) (b) (c) (d)
Juxtaposition of even
and odd fields on
monitor screen.
Figure 9-9. Electron Beam Pattern for Interlaced Video
In interlaced mode, video timing logic operation is altered so that the odd field
begins when HCOUNT=HTOTAL/2. The beam is thus positioned so that
horizontal scan lines in the odd field fall between horizontal scan lines in the
even field. To place each line of the odd field precisely between two lines of
the even field, load HTOTAL with an odd number.
9-11
Screen Refresh and Video Timing - Vertical Video Timing
The transition from d to a in Figure 9-9 shows that the vertical retrace at the
end of the odd field begins at the end of a horizontal scan line; that is, it co-
incides with the start of an HSYNC pulse, which results from the condition
HCOUNT=HTOTAL. The VSYNC pulse duration is an integral number of hor-
izontal scan retrace intervals. When vertical retrace ends and the active portion
of the next even field begins, the beam is positioned at the beginning of a
horizontal scan line.
Horizontal timing is similar for interlaced and noninterlaced displays.
HCOUNT is reset to 0 at the end of each horizontal scan line. A screen-refresh
cycle begins before the end of the line, coinciding with the start of the hori-
zontal blanking interval. Assuming that the starting corner of the display is the
upper left corner, the DUDATE field of the DPYCTL register is added to the
screen-refresh address (SRFADR in the DPYADR register) to generate the row
address for the next screen-refresh cycle. In interlaced mode, the DUDATE
value must be twice that of the value needed to produce the same display in
noninterlaced mode (that is, two times the difference in addresses between
consecutive scan lines). This causes the screen refresh to skip alternate lines
during the odd and even fields.
At the beginning of each vertical blanking interval, the screen-refresh address
(SRFADR in the DPYADR register) is loaded with the starting value specified
by the DPYSTRT register. When vertical blanking precedes an even field, the
new DPYADR row address is incremented by half the value in the DUDATE
field. This is in preparation to display line 2 (Figure 9-9 b). When vertical
blanking precedes an odd field, the row address loaded into DPYADR from
DPYSTRT is not incremented. In this case, the starting row address in
DPYSTRT points to the beginning of line 1 (Figure 9-9 d).
VCOUNT
"HIDfj("
im'flC ----,!-__
1
1
---I
"V8[Nj("l, __...,.i_ _ _- j - - - - '
1
VerticaI~
Sweep
1
i ------..!.r----
1
--'
....
1
1' - - - -
1
i
1
-..!...r----
1,----
1
1
1
I 1 1
Horizontal I
Sweep 1 I I
~~~---~~r-----.M:.~~r~.~i-.---~~r---~
Even Field VSBLNK = 6 VTOTAL = 7 Odd Field
VESYNC = , VEBLNK = 2
Figure 9-10. Interlaced Video Timing Waveform Example
9-12
Screen Refresh and Video Timing - Display Interrupt
9.7 Display Interrupt
The TMS3401 0 can be programmed to interrupt the display when a specified
line is displayed on the screen. This is called a display interrupt. It is ena-
bled by setting the DIE bit in the INTENB register to 1 and loading the DPY-
INT register with the desired horizontal scan line number. When VCOUNT =
DPYINT, the interrupt request is generated to coincide with the start of hori-
zontal blanking at the end of the specified line.
The display interrupt request can be polled by disabling the interrupt (setting
DIE=O) and checking the value of the DIP bit in the INTPEND register.
Writing a 0 to DIP clears the request.
The display interrupt has several applications. It can be used to coordinate
modifications of the bit map with the display of the bit map's contents, for
example. While the bottom half of the screen is displayed, the GSP can modify
the bit map of the top half of the screen, and vice versa.
Another use for the display interrupt is in maintaining a cursor on the monitor
screen. The cursor image resides in the on-screen memory only during the
time the electron beam is scanning the lines containing the cursor. The cursor
remains free from flicker even during periods in which the TMS3401 0 busy
drawing to the screen. The technique is to load the DPYI NT register with the
VCOUNT value of a scan line just above where the top of the cursor is to ap-
pear. When the display interrupt occurs, the interrupt service routine performs
the following tasks:
• Sets DPYINT to the scan line just below the cursor,
• Saves the portion of the screen where the cursor is to appear, and
• PixBlts the cursor onto the screen.
The cursor remains on the screen until the electron beam reaches the bottom
of the cursor, at which time a second interrupt request occurs. The original
screen is then restored, and the TMS3401 0 can resume drawing to the screen.
The display interrupt is also useful in split screen applications. By modifying
the contents of the DPYADR register halfway through a frame, different parts
of the bit map can be displayed on the top and bottom halves of the screen.
No special steps are necessary to ensure that loading a new value to DPYADR
does not interfere with an ongoing screen-refresh cycle. The display interrupt
is requested at the beginning of the horizontal blanking interval. If a screen-
refresh cycle occurs during the same horizontal blanking interval, the GSP
cannot respond to the interrupt request until the refresh cycle and subsequent
updating of DPYADR are complete. This is true whether the interrupt is taken
or the GSP simply polls the DIP bit and detects a 0-to-1 transition. After DIP
has been set to 1, DPYADR can be loaded with a new value to achieve the
split screen anytime before the next screen-refresh cycle.
In interlaced mode, the display interrupt can be used to detect the start of the
even field. For this purpose, the DPYINT register is loaded with the value from
the VESYNC register. Figure 9-10 (page 9-12) shows that during the odd
field, VCOUNT is incremented by 1 halfway through the horizontal interval
when the condition VCOUNT=VESYNC is detected. Assuming that
HSBLNK=HTOTALj2, VCOUNT contains the value VESYNC+1 by the time
horizontal blanking begins. This means that if DPYINT=VESYNC, the display
interrupt is effectively prevented from occurring during the odd field.
9-13
Screen Refresh and Video Timing - Dot Rate
9.8 Dot Rate
A typical screen must be refreshed 60 times per second for a noninterlaced
scan or 30 times per second for an interlaced scan. For a noninterlaced dis-
play, the dot period (time to refresh one pixel) is estimated as:
(0.8) (1/60 second)
Dot Period =
(pixels/line) x (lines/frame)
For an interlaced display, the dot period is estimated as
(0.8) (1/30 second)
Dot Period =
(pixels/line) x (lines/frame)
The 0.8 factor in the numerator accounts for the fact that the display is typi-
cally blanked for about 20% of the duration of each frame. This factor varies
somewhat from monitor to monitor.
During each dot period, the complete information for one pixel must be ob-
tained from the display memory (or frame buffer). Thus, the rate at which vi-
deo data must be supplied from the display memory (which is usually the
limiting factor for large systems) is a function of pixel size as well as screen
dimensions.
9-14
Screen Refresh and Video Timing - External Sync Mode
9.9 External Sync Mode
External sync mode allows the TMS3401 0 to use horizontal and vertical sync
signals from an external source. This permits graphics images generated by
the GSP to 'be superimposed upon or mixed with images from external
sources.
External sync mode is selected by setting the DXV and HSD bits in the
DPYCTL register to O. HSYNC and VSYNC are now configured as inputs. (Al-
ternately, HSYNC can be configured as an output and VSYNC as an input by
setting DXV=O and HSD=1.) When an active-low sync pulse is input to one
of these pins, the corresponding counter (HCOUNT or VCOUNT) is forced to
all Os. By forcing the counters to follow the external sync signals, the blanking
intervals and screen-refresh cycles are also forced to follow the external video
signals.
The HSYNC and VSYNC inputs are sampled on each VCLK rising edge.
HCOUNT or VCOUNT are cleared 2.5 clock periods (on a VCLK falling edge)
following a high-to-Iow transition at the HSYNC or VSYNC pin, respectively.
BLANK remains an output, but its timing is affected because the point at which
HCOUNT and VCOUNT are cleared is controlled by the external sync signals.
The 2.5-clock delay must be considered when selecting values for the
HSBLNK and HEBLNK registers.
9.9.1 A Two-GSP System
One GSP can generate video timing for two GSPs. As Figure 9-11 shows,
GSP #1 is configured for internal sync mode (DXV=1) and generates the sync
timing. GSP #2 is configured for external sync mode (DXV=O and HSD=O),
and receives the HSYNC and VSYNC inputs from GSP #1. Assume that the vi-
deo timing registers of the two devices are named as follows:
GSP #1 GSP#2
HCOUNT1 HCOUNT2
HESYNC1 HESYNC2
HSBLNK1 HSBLNK2
HEBLNK1 HEBLNK2
HTOTAL1 HTOTAL2
VCOUNT1 VCOUNT2
VESYNC1 VESYNC2
VSBLNK1 VSBLNK2
VEBLNK1 VEBLNK2
VTOTAL1 VTOTAL2
GSP #2's registers should be programmed in terms of the values in GSP #1's
registers, as shown in Table 9-1. The BLANK signals from GSP #1 and GSP
#2 are the same, and switch in unison on the same VCLK edges. When
HCOUNT1 is cleared on a VCLK falling edge, HCOUNT2 is cleared three full
VCLK periods later. For short horizontal blanking periods, HEBLN K2 may
need to be loaded with a value that is less than zero. For example, assume that
HSBLNK1 =HTOTAL1-4 and HEBLNK1 =1 (that is, the horizontal blanking
interval is six VCLK periods). To ensure that GSP #2's horizontal blanking
interval begins and ends at the same time as GSP #1 's, GSP #2's registers
must be loaded with values so that HSBLNK2=HTOTAL 1-8 and
HEBLNK2=HTOTAL1-2.
9-15
Screen Refresh and Video Timing - External Sync Mode
VCLK
~
HCOUNT
________________ ~I
~~~-----------------------------
HSYNC
(output to GSP .2)
m..!2i
HCOUNT
Figure 9-11. External Sync Timing - Two GSP Chips
The values in HTOTAL2 and VTOTAL2 must be large enough so that the
conditions HCOUNT=HTOTAL and VCOUNT=VTOTAL do not cause
HCOUNT and VCOUNT, respectively, to be cleared before the leading edges
of the external horizontal and vertical sync pulses occur. In the example in
Table 9-1, HTOTAL2 and VTOT AL2 are set to their maximum values. The
value of HESYNC2 must be such that HCOUNT=HESYNC2 occurs between
the end of an external HSYNC pulse and the beginning of the next external
HSYNC pulse. The value of VESYNC2 must be such that VCOUNT=VESYNC2
occurs between the end of an external VSYNC pulse and the beginning of the
next external VSYNC pulse.
Table 9-1. Programming GSP #2 For External Sync Mode
HEBLNK2 HEBLNK1 - 3
HSBLNK2 HSBLNK1 - 3
HTOTAL2 65535
HESYNC2 (HEBLNK2 + HSBLNK2)/2 t
VEBLNK2 VEBLNK1
VSBLNK2 VSBLNK1
VTOTAL2 65535
VESYNC2 (VEBLNK2 + VSBLNK2)!2 t
t Suggested value; see description in text.
Since the internal counter can only be resolved to the nearest VCLK edge,
precise synchronization with an external video sourc~ can be achieved only
when VCLK is harmonically related to the external horizontal sync signal. In
general, however, the HSYNC and VSYNC inputs are allowed to change asyn-
chronously with respect to VCLK, although the precise VCLK edge at which
an external sync pulse is recognized can be guaranteed only if the setup and
hold times specified for sync inputs are met.
9-16
Screen Refresh and Video Timing - External Sync Mode
9.9.2 External Interlaced Video
External sync mode can be used for both interlaced and non interlaced dis-
plays. When locking onto external interlaced sync signals, the GSP discrimi-
nates between the odd and even fields of the external video signals based on
whether its internal horizontal blanking is active at the time that the start of the
external vertical sync pulse is detected. In Figure 9-10, for example, the even
field begins at a point where HBLNK is active low, and the odd field begins
while HBLNK is high.
In interlaced mode, the discrimination between the even and odd fields of an
external video source is based on the value of HCOUNT at a point two VCLK
periods past the rising VCLK edge at which the GSP detects the VSYNC input's
high-to-Iow transition. If HCOUNT contains a value greater than the value in
HEBLNK, but less than or equal to the value in HSBLNK, the GSP assumes
that the vertical sync pulse precedes the start of an odd field. Otherwise, the
next field is assumed to be even. Alternatively, the GSP can be placed in
non interlaced mode, even though the external sync signals it is locking onto
are for an interlaced display. In this case, the GSP simply causes identical
display information to be output to the monitor during the odd and even fields.
The program can determine at any time whether an even or odd field is being
scanned by inspecting the least significant bits of the DPYADR register to
determine whether they have been incremented by DUDATE/2. Recall that
that at the start of an even field, the initial address loaded into DPYADR from
the DPYSTRT register is automatically incremented by DUDATE/2 (that is,
incremented by half the value specified in the DUDATE field of the DPYCTL
register). At all other times, DPYADR is incremented by DUDATE rather than
DUDATE/2.
9-17
Screen Refresh and Video Timing - Video RAM Control
9.10 Video RAM Control
The TMS34010 automatically schedules the VRAM (video RAM) memory-
to-register cycles needed to refresh a video monitor screen. These cycles are
referred to as screen-refresh cycles.
In addition to automatic screen-refresh cycles, the GSP can be configured to
perform memory-to-register and register-to-memory cycles under the explicit
control of software executing on the GSP's internal processor. One of the
primary uses for this capability is to facilitate nearly instantaneous clearing of
the screen. The screen is cleared in 256 memory cycles or less by means of a
technique referred to here as bulk initialization of the display memory.
9.10.1 Screen Refresh
A screen-refresh cycle loads the VRAM shift registers with a portion of the
display memory corresponding to a scan line of the display. The internal re-
quests for these cycles occur at regular intervals coinciding with the start of
the horizontal blanking intervals defined by the video timing registers. When
horizontal blanking ends, the contents of the shift registers are clocked out
serially to drive the video inputs of a monitor. A screen-refresh cycle typically
occurs prior to each active line of the display.
9.10.1. 1 Display Memory
The display memory is the area of memory which holds the graphics image
output to the video monitor. This memory is typically implemented with
VRAMs. During a screen-refresh cycle, a portion of the display memory cor-
responding to one (or possibly more) scan lines of the display are loaded into
the VRAM shift registers. Depending on the screen dimensions selected, not
all portions of the display memory are necessarily output to the monitor.
The width of the display memory is referred to as the screen pitch, which is the
difference in 32-bit memory addresses between two vertically-adjacent pixels
on the screen. The screen pitch is also the difference in starting memory ad-
dresses of the video data for two consecutive scan lines. When XY addressing
is used, the screen pitch must be a power of two to facilitate the conversion
of XY addresses to memory addresses. The value loaded into the DUDATE
field of the DPYCTL register represents the screen pitch, and is the amount
by which the screen-refresh address is incremented (or decremented) follow-
ing each screen-refresh cycle.
The portion of display memory that is actually output to the monitor is referred
to as the on-screen memory. The starting location of the on-screen memory
is specified by the SRFADR field in the DPYSTRT register.
The starting screen-refresh address is output during the screen-refresh cycle
that occurs at the start of each frame. At the end of the screen-refresh cycle,
the address is incremented to point to the area of memory containing the pixels
for the second scan line. The process is repeated for each subsequent scan
line of the frame.
9-18
Screen Refresh and Video Timing - Video RAM Control
A screen-refresh cycle typically affects all video RAMs in the system. A me-
mory-to-register cycle transfers data from a selected row of memory to the
internal shift register of each VRAM. The data is then shifted out to refresh the
display.
A screen-refresh cycle takes place during the horizontal blanking interval that
precedes a Scan line to be displayed. Typically, the shift registers containing
the video data for the line are clocked only during the active portion of the
scan line, that is, when the BLANK output is high. At higher dot rates, the pixel
clock or dot clock used to shift video data to the monitor is run through a
frequency divider to create the VCLK signal input to the GSP.
The 8-bit row address output during the screen-refresh cycle specifies the row
in memory to be loaded into the shift register internal to the VRAM. The
number of bits of video data transferred to the shift registers of all the VRAMs
in the system during a single screen-refresh cycle is calculated by multiplying
the number of VRAMs times the length of the shift register in each VRAM.
For example, 64 TMS4161 (64K-by-1) VRAM devices are sufficient to con-
tain the bit map for a 1 024-by-1 024-pixel display with four bits per pixel. The
length of the shift register in each TMS4161 is 256 bits. Thus, in a single
screen-refresh cycle, a total of 64 times 256, or 16,384, bits are loaded. This
is enough data to refresh four complete scan lines of the display. In general,
a single screen-refresh cycle performed during a horizontal blanking interval
is sufficient to supply one or more complete scan lines worth of data to the
video monitor screen.
9.10.1.2 Generation of Screen-Refresh Addresses
The DPYADR, DPYCTL, DPYSTRT, and DPYTAP registers are used to gener-
ate the addresses output during screen-refresh cycles. Figure 9-12 shows
these four registers, and indicates the register fields which determine the way
in which screen-refresh addresses are generated.
15 210
DPYADR I :
15 210
DPVSTRT I : : 6~6tRt
1514131211109
DPYCll. II rI' : .. !<:I rI : : QUD.Alj
NIL ORG
151413 0
DPYTAP 1;;31 : : : : : ®AF! : : : : : I
Figure 9-12. Screen-Refresh Address Registers
9-19
Screen Refresh and Video Timing - Video RAM Control
• DPYADR contains the SRFADR field, which is a counter that generates
the addresses output during screen-refresh cycles.
• DPYSTRT contains the SRSTRT field, the starting address loaded into
SRFADR at the beginning of each frame.
• DPYCTL contains several fields that affect screen-refresh addresses. The
8-bit DUDATE field is loaded with seven Os and a single 1 that points
to the bit position within SRFADR (bits 2-9 of DPYADR) at which the
address is to be incremented (or decremented) at the end of each
screen-refresh cycle. The ORG bit determines whether the screen-
refresh address is incremented or decremented. If ORG =0, the screen
origin is located at the top left corner of the screen and the address is
incremented; otherwise, it is decremented. The NIL bit determines
whether the GSP is configured to generated an interlaced (NIL=O) or
noninterlaced (NIL=1) display. The generation of screen-refresh ad-
dresses can be modified to accommodate either type of display.
• The DPYTAP register is used to specify screen-refresh address bits to
right of the position at which D U DATE increments the address. D PY-
TAP provides the additional control over screen -refresh address gener-
ation necessary to allow the screen to pan through the display memory.
Bits not directly involved in address generation are shaded in Figure 9-12.
The address output during a screen-refresh cycle identifies the starting pixel
on the scan line about to be output to the monitor. Figure 9-13 (page 9-21 )
shows a 32-bit logical address of the first pixel on one of the scan lines ap-
pearing on the screen. The screen-refresh address consists of bits 4-23 of the
logical address, whis:;h are generated by combining the values contained in
SRFADR and DPYTAP. Where SRFADR and DPYTAP overlap (bits 10-17
of the logical address), the address bits are generated by logical ~Ring the
corresponding bits of SRFADR and DPYTAP. The 8-bit DUDATE value con-
tains seven Os and a single 1 pointing to the position at which SRFADR is to
be incremented (or decremented). The DPYTAP register should be loaded
with the portion of the pixel address in Figure 9-13 lying to the right of the
position indicated by the DUDATE pointer bit. SRFADR contains the portion
of the pixel address that is incremented by the DUDATE pointer bit.
Following system power up, the software should load the starting screen-
refresh address into the SRSTRT field of the DPYSTRT register, and load the
increment to the screen-refresh address into the DPYCTL register. For a typi-
cal CRT display, the starting address is the address in memory of the pixel that
appears in the upper left corner of the display. If ORG bit in DPYCTL is 0, the
15 complement of the starting address should be loaded into DPYSTRT. If
ORG =1, the starting address loaded into DPYSTRT should not be comple-
mented.
DPYADR is automatically loaded with the starting display address from
DPYSTRT prior to the start of each frame. As shown in Figure 9-14 a, bits
2-15 of DPYSTRT (SRSTRT) are loaded into bits 2-15 of DPYADR
(SRFADR). The load occurs coincident with the start of the horizontal
blanking interval that occurs just at the end of the last active scan line of the
preceding frame.
9-20
Screen Refresh and Video Timing - Video RAM Control
~
output During Row________
_________ A~
Address Time ~
( \ output During
:: ~ _ _ _ I:
__ _Column Addrees
__ __
A~ ____Time
__ ~
I I \
I I I
I I I
I I I
31 28 24 : 20 18 12: 8 4 : o
32-BIt Logical Pixel Ad rees
SRFADR
(DPYADR BIts 2-15)
I i
I I
I I
I I
r~; I
I
DUDATE
(DPYCTL Bits 2-9)
~~I
I
I
I
DPYTAP
I
I4-f-----(BIts 0-13)-----.,
Figure 9-13. logical Pixel Address
The address output during each screen-refresh cycle is contained in bits 2
through 15 of the DPYADR register (the 14-bit SRFADR field). As shown in
Figure 9-14 b, DPYADR bits 4-15 are output at the lAD0-LAD11 pins during
the row address time of the screen-refresh cycle. If ORG =0, the DPYADR bits
are inverted before being output; otherwise, they are output unaltered. Zeros
(logic-low level) are output on LAD12-LAD14, and a one (logic-high level)
is output on LAD15; this is the RF status bit.
During the column address time of the screen-refresh cycle, bits 2-6 of
DPYADR are output at LAD6-LAD10. If ORG=O, the DPYADR bits are in-
verted before being output. DPYTAP bits 6-11 are ORed with DPYADR bits
2-7 and output at LAD6-LAD11. Bits 0-5 and 12-13 of DPYTAP are output
at LAD0-LAD5 and LAD11-LAD13, respectively. Zeros are output at
LAD14-LAD15 (the TR and IAQ status bits).
After the row and column addresses have been output, the address in
DPYADR bits 2-15 is decremented by the 8-bit value in DPYCTL bits 2-9 (the
DUDATE field). This is done in preparation for the next screen-refresh cycle.
The 8-bit DUDATE value is a binary number consisting of seven Os and a
single 1. This single 1 indicates the position at which DPYADR is decre-
mented. If ORG =0, the screen-refresh address in DPYADR is effectively in-
cremented; the 1s complement of the address contained in DPYADR is
decremented by the DUDATE amount, but is inverted before being output.
This is equivalent to incrementing the address. If ORG=1, the address is de-
cremented.
9-21
Screen Refresh and Video Timing - Video RAM Control
SRSTRT
A
(a) Display-Address Initial Value
1614131211109878543210
DPYADR
Register ~+'-1t-'-+..&...+-'+-'-+-'-+....L..f-L...t-L+-'-II-'-""""'----I..--'
LAD Bus Pins
1-----....,
o
2
3
4
5
8
7
8
9
ORG - - - - I ~--------I
(b) Row-Address Time
Figure 9-14. Screen-Refresh Address Generation
9-22
Screen Refresh and Video Timing - Video RAM Control
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D:a:~~e~ I~--:==~RG=~=:=:=~=~b=~~=t~=t~l='= :I
~AAAA)~~ ---, Bus Pins
I o
.- I 1
oPYTAP
Register I 2
15
14
-...- !
3
.....-
13
--. i 4
12
11 -
-
.-
r"...-
II I
I 5
-. ~~ I
10
9
--
.-
.....- 6
~
8
7
-----.-. ~
I
I
7
6 ---
-- l
I
~
8
9
5
--... ~
!
4
--.
...
i 10
3
2
_.
--. - -.....c:
- I 11
I
12
o
"" .
- I - 13
o....J..-...14(TR)
I
o -}-.15(1AQ)
L____ -'
(c) Column-Address Time
Figure 9-14. Screen-Refresh Address Generation (Continued)
9-23
Screen Refresh and Video Timing - Video RAM Control
0
- ...
...
..... 1'1 - .:
--PI
~
-
_1lI_ ---~
CD _
li-
t,)
-
-
,...- ,--- .
co
en
- ~~
0
-
... -
...
~c(
-
1'1
...
::!
- _
~
~
~
~
~
III
... -
0
...
r--
15
c(;
~l
:D ------
...
CIr
r-
1'1 ..
f-'(
w
~
PI
~
III
. 1-'r-
..
..
---/
I-
(
~<
~
C CD
,...
co
.
.. 1-'
'"""/
.. 1-'
(
(
en~ 1-/
:=
;::
!::!
::!
~
~
'--
(d) Display-Address Update
Figure 9-14. Screen-Refresh Address Generation (Concluded)
9-24
Screen Refresh and Video Timing - Video RAM Control
9.10.1.3 Screen Refresh for Interlaced Displays
The size of the DUDATE increment specified for an interlaced display should
be twice that required for a noninterlaced display of the same dimensions.
This allows every other line to be skipped during the even or odd field of an
interlaced frame. Before the start of the even field, half the value of the DU-
DATE increment is added to the starting address loaded into DPYADR to ob-
tain the necessary starting displacement. The SRSTRT field in DPYSTRT
points to the area of memory containing the video data for scan line 1 in the
example of Figure 9-9 on page 9-11.
9.10.1.4 Panning the Display
The DPYTAP register supports horizontal panning of the screen across a dis-
play memory that is larger than the screen. The value contained in the low-
order bits of DPYTAP furnish the LSBs of the column address output during
the screen-refresh cycle. Incrementing this value results in panning to the
right; decrementing this value results in panning to the left.
9.10.1.5 Scheduling Screen-Refresh Cycles
The internal request for a screen-refresh cycle is generated when horizontal
blanking begins. This gives the GSP essentially the entire horizontal blanking
interval in which to perform the screen-refresh cycle. The delay from the start
of horizontal blanking to the start of the screen-refresh cycle is called the
screen-refresh latency, and is determined by the internal memory controller.
The best and worst case screen-refresh latencies are given in Table 9-2. In the
best case, the delay from the high-to-Iow transition of the BLANK output to the
start of the screen-refresh cycle (the time the row address is output) is only
3.25 machine states (or local clock periods). In the worst case, the delay is
(7.25 + 2 W) states, where W represents the number of wait states required
per memory cycle. The worst case number is based on the fact that the start
of the screen-refresh cycle can be delayed by up to three states if a read-
modify-write operation began one state before the memory controller received
the request for the screen-refresh cycle. A screen-refresh request is given
higher priority than requests for DRAM-refresh, host-indirect or GSP CPU
cycles; hence, no further delays occur unless an external device generates a
hold request.
Table 9-2. Screen-Refresh latency
Min Max
3.25 states (7.25 + 2W) states
Note: W is the number of wait states per memory
cycle.
The horizontal blanking interval should be sufficiently long in duration for the
screen-refresh cycle to be completed before blanking ends. The required mi-
nimum blanking interval is therefore about (9.25 + 3W) machine states, de-
pending on how soon after the end of blanking the external video logic begins
clocking the VRAM shift registers. Of course, this time must be translated from
9-25
Screen Refresh and Video Timing - Video RAM Control
machine states (local clock periods) to VCLK periods to program the HEBLNK
register.
The horizontal sync pulse is permitted to be as small as a single VCLK period
in duration.
No screen-refresh cycles are performed during vertical blanking until nearly the
end of vertical blanking - at the start of the horizontal blanking interval that
precedes the first active scan line of the new frame.
The screen-refresh latency specified in Table 9-2 assumes that a local bus hold
request (HOLD low) is not asserted between the start of blanking and the start
of the screen-refresh cycle. If a hold request prevents the TMS34010 from
initiating a scheduled screen-refresh cycle during this time, the TMS3401 0 is
forced to delay its screen-refresh cycle until the bus is released by the external
device asserting the hold request. A hold request occurring during the hori-
zontal blanking interval preceding an active scan line on the display should
be deasserted in time to allow the TMS34010 to complete the pending
screen-refresh cycle before blanking ends. If a screen-refresh cycle is pending
at the time the external device releases the bus, the screen-refresh cycle is the
first cycle performed by the TMS3401 0 after it regains control of the bus.
9.10.2 Video Memory Bulk Initialization
VRAMs may be rapidly loaded with an initial value using a special GSP feature
that converts pixel accesses to register transfers. This rapid loading method
is referred to (IS bulk initialization of the video memory, and can be used with
VRAMs such as the TMS4461. When the SRT (shift register transfer) bit in
the DPYCTL register is set to a 1, all reads and writes of pixel data are con-
verted at the memory interface of the GSP to register-transfer cycles. When
SRT=O, pixel accesses are performed in normal fashion.
When SRT=1, the processor can initiate register-transfer cycles under explicit
program control. By performing a series of such cycles, some or all of the
display memory can be set to an initial background color or pattern very rapidly
(in a small fraction of one frame time). First, the VRAM shift registers are
loaded with the initial value. The video memory is then set to the initial color
or pattern one row at a time by writing the shift register contents to the me-
mory.
During a register-transfer cycle (when SRT=1), the row and column addresses
are output in unaltered form; that is, the address is not affected by the state
of SRT. The 8-bit row address output during the cycle designates which row
in memory is involved in the transfer. The direction of the transfer is deter-
mined by whether the cycle is a read or a write. A write cycle such as a PIXT
transfer from a general-purpose register to memory is converted to a VRAM
register-to-memory cycle. Similarly, a read cycle such as a PIXT transfer from
memory to a general-purpose register is converted to a VRAM memory-to-
register cycle.
Only pixel transfers are affected by the SRT bit. The manner in which all other
data accesses and instruction fetches are performed is not affected.
9-26
Screen Refresh and Video Timing - Video RAM Control
Before bulk initialization of the display memory, the VRAM shift registers are
loaded with the solid color or pattern with which the display memory is
loaded. This can be done in one of two ways, by either:
• Serially shifting bits into the shift register
or
• First loading a row of display memory with the color or pattern using a
series of "normal" pixel writes (when SRT=O), and then loading the
contents of this row into the shift register by means of a PIXT memo-
ry-to-register instruction (executed while SRT=1).
To speed up the bulk initialization operation further, a series of transfers can
be made more rapidly by using a single FI LL instruction in place of a series of
PIXT instructions. The fill region is selected so that each pixel write cycle
generates a new row address. The fill region is specified to be precisely 16
bits wide, the width of the memory data bus. Also, plane masking is disabled,
transparency is turned off, and the pixel processing rep/ace operation is se-
lected. This ensures that each row is addressed only once during the course
of the fill operation.
The number of bits of the display memory that are altered by a single regis-
ter-to-memory transfer cycle is calculated by multiplying the number of VRAM
devices by the number of shift register bits in each device. The entire frame
buffer is loaded with the initial color or pattern in 256 memory cycles.
9-27
Screen Refresh and Video Timing
9-28
Section 10
Host Interface Bus
A host processor can communicate with the TMS3401 0 by means of an in-
terface bus consisting of a 16-bit data path and several transfer-control sig-
nals. The TMS34010's host interface provides a host with access to four
programmable 16-bit registers (resident on the TMS34010), which are
mapped into four locations in the host processor's memory or I/O address
space. Through this interface, commands, status information, and data are
transferred between the TMS3401 0 and host processor.
A host processor may read from or write to TMS3401 0 local memory indirectly
via an autoincrementing address register and data port. This optional autoin-
crement feature supports efficient block moves. The TMS3401 0 and host can
send interrupt requests to each other. A pin is dedicated to the interrupt re-
quest from the TMS3401 0 to the host. To allow block moves initiated by a
host to take place more efficiently, the host may suspend TMS3401 0 program
execution to eliminate contention with the TMS34010 for local memory.
DRAM-refresh and screen-refresh cycles continue to occur while the
TMS34010 is halted.
This section includes the following topics:
Section Page
10.1 Host Interface Bus Pins ......................................................................... 10-2
10.2 Host Interface Registers ........................................................................ 10-2
10.3 Host Register Reads and Writes ........................................................... 10-4
10.4 Bandwidth ............................................................................................ 10-22
10.5 Worst-Case Delay ................................................................................ 10-23
10-1
Host Interface Bus - Pins/Registers
10.1 Host Interface Bus Pins
The TMS3401 O's host interface bus consists of a 16-bit bidirectional data bus
and nine control lines. These signals are described in detail in Section 2.
HDo-HD15
form a 16-bit bidirectional bus, used to transfer data between the
TMS34010 and a host processor.
HCS is the host chip select signal. It is driven active low to allow a host
processor to access one of the host interface registers.
HFSO, HFS1
are function select pins. They specify which of four host interface
registers a host can access (see Section 10.2).
H READ is driven active low to allow a host processor to read the contents
of the selected host interface register, output on H OQ-H 015.
HWRITE is driven active low to allow a host processor to write the contents
of H OQ-H 01 5 to the selected host interface register.
is driven low to enable a host processor to access the lower byte
of the selected host interface register.
is driven low to enable a host processor to access the upper byte
of the selected host interface register.
HRDY informs a host processor when the TMS34010 is ready to com-
plete an access cycle initiated by the host.
transmits interrupt requests from the TMS3401 0 to a host proces-
sor.
10.2 Host Interface Registers
The host interface registers are a subset of the I/O registers discussed in Sec-
tion 6. The host interface registers can be accessed by both the TMS3401 0
and the host processor. These registers occupy four 16-bit locations in the
host processor's memory or I/O address map. One of these four locations is
selected by placing a particular code on the two function select inputs, H FSO
and HFS1, as shown in Table 10-1.
Table 10-1. Host Interface Register Selection
HFS1 HFSO Selected
Register
0 0 HSTADRL
0 1 HSTADRH
1 0 HSTDATA
1 1 HSTCTL
A 16-bit host processor typically connects two of its low-order address lines
to HFSO and HFS1. An 8-bit processor typically connects two low-order ad-
dress lines to HFSQ-HFS1 and uses a third low-order address bit to enable
either the upper or lower byte of the selected register by activating one of the
10-2
Host Interface Bus - Registers
byte select inputs, HUDS or HLDS. In the second case, the registers occupy
eight 8-bit locations in the host processor's memory map.
• The HSTADRL and HSTADRH registers contain the 16 LSBs and 16 MSBs,
respectively, of a 32-bit pointer address. A host processor uses this address
to indirec~ly access TMS3401 0 local memory.
• The HSTDATA register buffers data that is transferred through the host inter-
face between TMS34010 local memory and a host processor. HSTDATA
contains the contents of the address pointed to by the HSTADRL and
HSTADRH registers.
• The HSTCTL register is accessible to the TMS3401 0 as two separate I/O re-
gisters, HSTCTLL and HSTCTLH, but is accessed by a host processor as a
single 16-bit register. HSTCTL contains several programmable fields that
control host interface functions.
NMI (nonmaskable interrupt, bit 8): Allows a host processor to interrupt
TMS34010 execution.
NMIM (NMI mode, bit 9): Specifies if the context of an interrupted
program is saved when a nonmaskable interrupt occurs.
CF (cache flush, bit 14): Setting this bit flushes the contents of the
TMS34010 instruction cache. A host processor can force the TMS3401 0
to execute new code after a download by flushing old instructions out
of cache.
LBL (lower byte last, bit 13): Specifies which byte of a register an 8-bit
host processor accesses first.
INCR (increment address before local read, bit 12): Controls whether the
32-bit pointer in the HSTADR registers is incremented before being used
in a local read cycle that updates the HSTDATA register.
INCW (increment address after local write, bit 11): Controls whether the
32-bit pointer in the HSTADR registers is incremented after being used
in a local write cycle that transfers the contents of the HSTDATA register
to memory.
HLT (halt TMS3401 0 program execution, bit 15): A host processor can
halt the TMS3401 O's on-chip processor by setting this bit to 1.
MSGIN (message in, bits 0-2): Buffers a 3-bit interrupt message from a
host processor to the TMS3401 O.
INTIN (input interrupt bit, bit 3): A host must load a 1 into this bit to
generate an interrupt request to the TMS3401 O.
MSGOUT (message out, bits 4-6): Buffers a 3-bit interrupt message
from the TMS3401 0 to a host.
INTOUT (Interrupt out, bit 7): The TMS3401 0 must load a 1 to this bit
to send an interrupt request to a host processor.
10-3
Host Interface Bus - Reads and Writes
10.3 Host Register Reads and Writes
Host interface read and write cycles are initiated by the host processor and are
controlled by means of the HCS, HWRITE, HREAD, HUDS, and HLDS signals.
Host-initiated accesses of the register selected by the function-select code
input on HFSO and HFS1 are controlled as follows:
• While HCS, HLDS, and HWRITE are active low, the contents of HOo-H07
are latched into the lower byte of the selected register.
• While HCS, HUDS, and HWRITE are active low, the contents of
H OS-H 015 are latched into the upper byte of the selected register.
• While HCS, HLDS, and HREAD are active low, the contents of the lower
byte of the selected register are driven onto H Oo-H 07.
• While HCS, HUDS, and HREAD are active low, the contents of the upper
byte of the selected register are driven onto H OS-H 015.
As this list indicates, at least three control signals must be active at the same
time to initiate an access. The last of the three signals to become active begins
the access, and the first of the three signals to become inactive signals the end
of the access. A signal that begins or completes an access is referred to in the
following discussion as the strobe signal for the cycle. Any of the signals
listed above may be a strobe. Figure 10-1 shows a functional representation
of the logic that controls the TMS3401 O's host interface.
TMS34010
n WrIte to upper
byte of selected
register
n WrIte to lower
byte of selected
register
n Read from upper
byte of selected
register
n Read from lower
byte of selected
register
Figure 10-1. Equivalent Circuit of Host Interface Control Signals
10-4
Host Interface Bus - Reads and Writes
The designer must ensure that HREAD and HWRITE are never active low si-
multaneously during an access of a host interface register; this may cause in-
ternal damage to the device.
10.3.1 Functional Timing Examples
The functional timing examples in this section are based on the circuit shown
in Figure 10-1.
• The HCS input is the strobe in Figure 10-2 and Figure 10-3.
• The HWRITE signal is the strobe in Figure 10-4.
• The HREAD signal is the strobe in Figure 10-5.
• The HUDS and HLDS signals are strobes in Figure 10-6 and Figure 10-7.
HFSO-HFS1
HREAD
=-.J \'----
HWRITE
=-\ /
HLOS =-\ Enable WrIte to Lower Byte /
HUDS
=-.J Inhibit Write to Upper Byte \"'_ _ _ __
HCS ',"--_0-..1/
HOo-H016
HRDY (High)
Figure 10-2. Host 8-Bit Write with HCS Used as Strobe
10-5
Host Interface Bus - Reads and Writes
I-FSO-I-FS1
HWRITE
:J ,
HREAD
HLDS
=-\
:J Inhibit Read from Lower Byte
,I
HUDS \ Enable Read from Upper Byte I
HCI
\ I
HOO-HD15 ----------( Valid Data Out
r-------
HRDY (HIgh)
Figure 10-3. Host 8-Bit Read with HCS Used as Strobe
HFSO-HFS1
HWRITE:J
HCS =-\
,----
I
HLDS =-\ Enable Read from Lower Byte I
HUDS =-\ Enable Read from Upper Byte
I
HREAD \ I
HDO-HD15 - - - - - - - - - - ( Valid Data Out r-------
HROY (High)
Figure 10-4. Host 16-Bit Read with HREAD Used as Strobe
10-6
Host Interface Bus - Reads and Writes
HFSO-HFS1
IiREAD
HCS
:J
-=\
,----
/
HLDS -=\ Enable WrIte to Lower Byte /
HUDS -=\ Enable WrIte to Upper Byte /
HWRITE ' ___I
HDO-HD15
HRDY (HIgh)
Figure 10-5. Host 16-Bit Write with HWRITE Used as Strobe
HFSO-HFS1
HREAD
HCS
:J
-=\
,----
/
HWRITE -=\ /
, strobe Low Byte /
HLDS
, strobe High Byte/
HUDS
HDO-HD15
HRDY (High)
Figure 10-6. Host 16-Bit Write with HLDS, HUDS Used as Strobes
10-7
Host Interface Bus - Reads and Writes
HFSO-HFS1
HCS
~ I
HWRfTE
:-..J \
HREAD \ I
HLDS
\ strobe Low Byte I
\ strobe High Byte /
HUDS
HDO-HD15 - - - - - - - - - - ( Vllid Data Out }--------
HRDY (High)
Figure 10-7. Host 16-Bit Read with HLDS, HUDS Used as Strobes
10.3.2 Ready Signal to Host
The default state of the bus ready output pin, HRDY, is active high. HRDY is
driven inactive low to force the host processor to wait in circumstances in
which the TMS3401 0 is not prepared to allow a host-initiated register access
to be completed immediately.
HRDY is always driven low for a brief period at the beginning of a read or write
access of the HSTCTL register. When the host attempts to read from or write
to the HSTCTL register, HRDY is driven low at the beginning of the access,
and is driven high again after a brief interval of one to two local clock cycles.
When the host processor performs certain types of host interface register ac-
cesses, a local memory cycle results. For example, in reading from or writing
to the HSTDATA register, a read or write cycle on the local bus results. If the
host processor attempts to perform an access that initiates a second local
memory cycle before the TMS3401 0 has had sufficient time to complete the
first, the TMS3401 0 drives its HRDY output low to indicate that the host must
wait before completing the access. When the TMS3401 0 has completed the
local memory cycle resulting from the previous access, it drives HRDY high to
indicate that the host processor can now complete its second access.
A data transfer through the host interface takes place only when some com-
bination of HCS, HREAD, HWRITE, HUDS, and HLDS are active simultaneously;
however, the HRDY signal is activated by the HCS input alone. HRDY can be
active-low only while the TMS3401 0 is chip-selected by the host processor,
10-8
Host Interface Bus - Reads and Writes
that is, while HCS is active low. A high-to-Iow transition on HRDY follows a
high-to-Iow transition on HCS. The benefit of this mode of operation is that
HRDY becomes valid as soon as HCS goes low, which typically is early in the
cycle. HRDY is always driven high when HCS is inactive high.
A transient low level on the HCS input may cause a corresponding low pulse
on the HRDY output. Systems that cannot tolerate such transient signals must
be designed to prevent HCS from going low except during a valid host inter-
face access.
In summary, the following rules govern the HRDY output:
1) If a high-to-Iow HCS transition occurs while the TMS34010 is still
completing a local memory cycle resulting from a previous host-indirect
access, HRDY goes low. If the register selected is HSTDATA, HSTADRL
or HSTADRH, HRDY remains low until the local memory cycle is com-
pleted. If the register selected is HSTCTL, the HRDY output remains low
for one to two local clock periods.
2) If the host is given a ready signal (HRDY high) to allow it to complete
a register access that causes a local memory read or write cycle, HRDY
stays high to the end of the access. The access ends when the strobe
for the cycle ends. The strobe ends when HREAD and HWRITE are both
inactive high, or when HLDS and HUDS are both inactive high, or when
HCS is inactive high, whichever is the first to occur. As soon as the
strobe ends, a low level on HCS allows HRDY to go low again. If the
strobe is an input other than HCS, and HCS remains low after the strobe
ends, HRDY can go low as a delay from the end of the strobe. If HCS is
the strobe for the access, the access ends when HCS goes high, and
HRDY can go low again as soon as HCS goes low again.
3) If HSTCTL is selected (FSO = FS1 = 1) at the high-to-Iow transition
of HCS, HRDY goes low as a delay from the fall of HCS, and remains low
for one to two local clock periods. To avoid a low-going pulse on HRDY
when accessing a register other than HSTCTL, FSO and FS1 should be
valid prior to the high-to-Iow transition of HCS.
Figure 10-8 and Figure 10-9 (page 10-10) show examples of host interface
register accesses in which HRDY is driven low.
10-9
Host Interface Bus - Reads and Writes
I<
HFSo-HFS1 Valid Function Select )II
HRER5J C
HCS~ /
RID~ \ I
HRDY
\ I
HDO-HD16
Figure 10-8. Host Interface Timing - Write Cycle With Wait
HFSo-HFS1
I< Valid Function Select )81
HWRITE
J C
HCS
~ I
H~ \ I
HRDY
\ I
HDO-HD16 -·I-I-Z----
Figure 10-9. Host Interface Timing - Read Cycle With Wait
10-10
Host Interface Bus - Reads and Writes
10.3.3 Indirect Accesses of local Memory
The host processor indirectly accesses TMS34010 local memory by reading
from or writing to the HSTDATA register. HSTDATA buffers data written to
or read frQm the local memory. The word in local memory that is accessed is
the word pointed to by the 32-bit address contained in the HSTADRL and
HSTADRH registers. The pointer address is loaded into HSTADRL and
HSTADRH by the host processor before performing one or more indirect ac-
cesses of local memory using the HSTDATA register.
The four LSBs of HSTADRL are forced to Os internally so that the address
formed by HSTADRL and HSTADRH always points to a word boundary in
local memory. Between successive indirect accesses of local memory using
the HSTDATA register, the local memory address contained in the HSTADR
registers can be autoincremented by 16. This allows the host processor to
access a block of sequential words in local memory without the overhead of
loading a new address prior to each access.
During a sequence of one or more indirect reads of local memory by the host,
the TMS3401 0 maintains in HSTDATA a copy of the local memory word cur-
rently addressed by the HSTADRL and HSTADRH registers. Reading from
HSTDATA returns the word prefetched from the local memory location
pointed to by the HSTADRL and HSTADRH registers, and causes HSTDATA
to be updated from local memory again. Writing to HSTDATA causes the
word written to HSTDATA to subsequently be written to the location in local
memory pointed to by the HSTADRL and HSTADRH registers.
Two increment-control bits, INCR and INCW (contained in the HSTCTL reg-
ister), are set to 1 to cause the pointer address in HSTADRL and HSTADRH
to be incremented by 16 during reads and writes, respectively. In preparing
to use the autoincrement feature, the appropriate increment-control bit, INCR
or INCW, is loaded with a 1, and the HSTADRL and HSTADRH registers are
set up to point to the first location of a buffer region in the local memory.
• When INCR::;:1, a read of HSTDATA causes the address in HSTADRL
and HSTADRH to be incremented before it is used in the local memory
read cycle that updates HSTDATA.
• When INCW::;:1, a write to HSTDATA causes the address in HSTADRL
and HSTADRH to be incremented after it is used in the local memory
read cycle that writes the new contents of HSTDATA to local memory.
Loading the pointer address automatically triggers an update of HSTDATA to
the contents of the local memory word pointed to. No increment of HSTADRL
and HSTADRH takes place at this time regardless of the state of the increment
bits. Each subsequent host access of HSTDATA causes HSTADRL and
HSTADRH to be automatically incremented (assuming INCR or INCW is set)
to point to the next word location in the local memory. In this manner, a series
of contiguous words in local memory can be accessed following a single load
of the HSTADRL and HSTADRH registers without additional pointer-
management overhead.
10-11
Host Interface Bus - Reads and Writes
10.3.3.1 Indirectly Reading from a Buffer
Figure 10-10 illustrates the procedure for reading a block of words beginning
at local memory address N. Assume that the INCR bit in the HSTCTL register
is set to 1 and the LBL bit in HSTCTL is set to O.
• In Figure 10-10 a, the host processor loads the 32-bit address N into
HSTADRL and HSTADRH.
• The loading of the second half of the address into HSTADRH causes the
TMS34010 host interface control logic to automatically initiate a read
cycle on the local bus. This read cycle, shown in Figure 10-10 b,
transfers the contents of memory address N to the HSTDATA register.
• In c, the host processor reads the HSTDATA register, fetching the data
previously read from address N.
• The read of HSTDATA by the host processor causes the TMS3401 0 to
automatically increment the contents of HSTADRL and HSTADRH by
16, as shown in d.
• The contents of the new address are read into HSTDATA, as shown in
Figure 10-10 e. This data will be available in HSTDATA the next time
it is read by the host processor.
The process shown in c through e repeats for every word read from
TMS34010 local memory.
10-12
Host Interface Bus - Reads and Writes
Host Host Local
Processor Interface Memory
Registers
N+18
(a) N
0
Host Host Local
Processor Interface Memory
Registers
N+18
(b) N
0
Host Host Local
Processor Interface Memory
Registers
N+18
(c) N
0
Host Host Local
Processor Interface Memory
Registers
HSTADRH HSTADRL
r N+16 B N+18
(d) .~ A N
HSTDATA
I A I
o
Host Host Local
Processor Interface Memory
Registers
HSTADRH HSTADRL
[ N+16 B N+18
(e) A N
HSTDATA ........
r B F
o
Figure 10-10. Host Indirect Read from Local Memory (INCR=1)
10-13
Host Interface Bus - Reads and Writes
10.3.3.2 Indirectly Writing to a Buffer
Figure 10-11 illustrates the procedure for writing a block of words to
TMS34010 local memory. The block begins at address N. Assume that the
INeW bit is set to 1 and the LBL bit is set to O.
• In Figure 10-11 a, the host processor loads the 32-bit address N into
HSTADRL and HSTADRH.
• The loading of the second half of the address into HSTADRH causes the
TMS34010 host interface control logic to automatically initiate a read
cycle on the local bus. This read cycle, which takes place in Figure
10-11 b, fetches the contents of memory address N into HSTDATA.
• The data loaded into this register is not used, however. Instead, the host
processor writes to the HSTDATA register in Figure 10-11 c, overwriting
its previous contents.
• In response to the host's write to HSTDATA, the TMS34010 automat-
ically initiates a write cycle to transfer the contents of HSTDATA to the
local memory address N as shown in d.
• Following the write, the TMS34010 automatically increments the ad-
dress in HSTADRL and HSTADRH to point to the next word, as shown
in e. At this point the host interface registers are ready for the host pro-
cessor to write the next word to HSTDATA.
The process shown in c through e repeats for every word written to
TMS34010 local memory.
10-14
Host Interface Bus - Reads and Writes
Host Host Local
Processor Interface Memory
Registers
N+18
(a) N
0
Host Host Local
Processor Interface Memory
Registers
N+18
(b) N
0
Host Hcst Local
PrOC888or Interface Memory
Registers
HSTADRH HSTADRL
B N+18
(c)
I N I-
----. A N
~ .-.I
HSTDATA
C I
o
Host Host Local
Proc888or Interface Memory
Registers
HSTADRH HSTADRL
I N r- t--- -S N+18
(d) "1 (" N
I
HSTDATA
C 1-- V
o
Host Host Local
Proc888or Interface Memory
Registers
HSTADRH HSTADRL
I N+16 --g N+18
(e) '~ C N
HSTDATA
I C I
o
Figure 10-11. Host Indirect Write to Local Memory (INeW=1)
10-15
Host Interface Bus - Reads and Writes
10.3.3.3 Combining Indirect Reads and Writes
If the HSTDATA register in Figure 10-11 is read by the host processor fol-
lowing step e, the value returned is the value that the host previously loaded
into the register. The host must read HSTDATA a second time to access data
from TMS34010 local memory. This principle is illustrated in Figure 10-12,
which shows how the host interlace performs when a write is followed by two
reads. For this example, INCW=1 and INCR=O.
• In Figure 10-12 a, HSTADRL and HSTADRH together point to location
N in the TMS3401 O's local memory. The host processor is shown writ-
ing to HSTDATA.
• In b, the data buffered in HSTDATA is written to location N in memory.
• The address registers are incremented in c.
• In d, the host processor reads the HSTDATA register, which returns the
value that the host loaded into the register in step a.
• Reading HSTDATA causes a memory read cycle to take place in e, which
loads the value from memory address N+16 into HSTDATA.
• In f, a second read of HSTDATA by the host processor returns the value
from memory address N+16.
Host Host Local
Proo8880r Interface Memory
Registers
HSTADRH HSTADRL
(a)
I fiI 1-
-------. A
B N+16
N
~ . HSTDATA I
C
o
Host Host Local
Proceaaor Interface Memory
Registers
(b)
- ......
___ --z.----1 N+16
~--tN
....._ _... 0
Figure 10-12. Indirect Write Followed by Two Indirect Reads
(INCW=1, INCR=O)
10-16
Host Interface Bus - Reads and Writes
Host Host Local
Procesaor Interface Memory
Registers
HSTADRH HSTADRL
I N+1S B N+16
(c)
''t.0' C N
HSTDATA
I ~ I
o
Host Host Looal
Procesaor Interface Memory
Registers
HSTADRH HSTADRL
I N+.16 B N+16
(d) C N
~ ---;
HSTDATA
( I
o
Host Host Local
Procesaor Interface Memory
Registers
HSTADRH HSTADRL
I N+.16 B N+16
(e) C N
I
HSTDATA
B 14--
/
o
Host Host Local
Pr008880r Interfaoe Memory
Registers
HSTADRH HSTADRL
I N+.16 B N+18
(1) C N
~ --;
HSTDATA
B I
o
Figure 10-12. Indirect Write Followed by Two Indirect Reads (INCW=1,
INCR=O) (Concluded)
10-17
Host Interface Bus - Reads and Writes
10.3.3.4 Accessing Host Data and Address Registers
When the TMS34010 internal processor accesses the HSTDATA, HSTADRL,
or HSTADRH register, no subsequent cycle occurs to transfer data between
HSTDATA and local memory. Also, the address in HSTADRL and HSTADRH
is not incremented, regardless of the state of the INCR and INCW bits.
The host processor can indirectly access any register in the TMS3401 O's in-
ternal I/O register file by first loading HSTADRL and HSTADRH with the ad-
dress of the register, and they writing to or reading from HSTDATA.
No hardware mechanism is provided to prevent simultaneous accesses of the
HSTDATA, HSTADRL and HSTADRH registers by the host processor and by
the TMS3401 0 internal processor. Software must be written to avoid simul-
taneous accesses, which can result in invalid data being read from or written
to these reg isters.
10.3.3.5 Downloading New Code
The TMS34010 host interface provides a means of efficiently downloading
new code from a host processor to TMS3401 0 local memory. The host initi-
ates this operation through the following process:
• Before downloading, the ho'st interrupts and halts the TMS34010 by
writing 1s to the HLT and NMI bits in the HSTCTL register. The host
processor should then wait for a period of time equal to the TMS3401 0
interrupt latency. (TMS34010 hardware resets the NMI bit if the non-
maskable interrupt is initiated before the halt occurs.)
• The code is then downloaded using the auto-increment features of the
host interface registers.
• After downloading the code, the host should flush the cache as de-
scribed in Section 5.4.5, Flushing the Cache (page 5-23).
• The nonmaskable interrupt vector is written through the host port to lo-
cation FFFFFEEOh so that the new code begins execution at the vec-
tored address.
• The NMI bit in the HSTCTL register should be set to 1 to initiate a non-
maskable interrupt. At the same time, the NMIM bit in the HSTCTL re-
gister should be set to 1. If the host does not need the current context
to be stored on the stack, or if the nonmaskable interrupt was taken in
the first step, the NMIM bit should be set to 1. Otherwise, NMIM should
be set to O.
• The host restarts the TMS34010 by writing a 0 to the H LT bit in the
HSTCTL register.
Setting the HLT and NMI bits to 1 simultaneously reduces the worst-case
delay (compared to setting HLT only). NMI latency is the delay from the 0-
to-1 transition of the N M I bit and the start of execution of the first instruction
of the N M I service routine. Halt latency is the delay from the 0-to-1 transition
of the H LT bit and the time at which the TMS3401 0 actually halts (see Sec-
tion 10.3.4). The maximum NMI latency may be much less than the halt la-
10-18
Host Interface Bus - Reads and Writes
tency if a PIXB LT, FI LL, or LI N E instruction is in progress at the time of the
NMI or halt request. An NMI request interrupts instruction execution at the
next interruptible point, but a halt request is ignored until the executing in-
struction completes or is interrupted. When NMI and HLT are set to 1 simul-
taneously, the TMS34010 halts before beginning execution of the first
instruction in the NMI service routine. Therefore, the delay from the setting
the N M I and H LT bits to the time that the TMS3401 0 actually halts is simply
the N M I latency.
10.3.4 Halt Latency
The TMS34010 may be halted by a host processor via the H LT bit in the
HSTCTL register. The delay from the receipt of a halt request to the time that
the TMS3401 0 actually halts is the sum of five potential sources of delay:
1) Halt request recognition
2) Screen-refresh cycle
3) DRAM-refresh cycle
4) Host-indirect cycle
5) Instruction completion
In the best case, items 2 through 5 cause no delay. The minimum delay to due
to item 1 is one machine state.
• The halt request recognition delay is the time required for the setting
of the HLT bit to be internally synchronized after the low-to-high transi-
tion of the HRDY pin.
• The screen-refresh and DRAM-refresh cycles are a potential source
of delay, but in fact occur rarely and are unlikely to delay a halt.
• The likelihood of a delay caused by a host-indirect cycle is small in
most instances, but this depends largely on the application. It would
only occur if the host had written to the data register just prior to writing
to the H LT bit. The delay due to a single host-indirect cycle is two ma-
chine states, assuming no wait states.
• The instruction completion time refers to the time required for an in-
struction that was already executing at the time the halt request was re-
ceived to complete. Note that the TMS3401 0 halt condition is entered
only on instruction boundaries. This means that a PIXBLT, FILL, or
LI N E instruction that is already in progress runs to completion before the
TMS34010 halts.
Table 10-2 shows the minimum and maximum times for each of the five op-
erations listed. The halt latency is calculated as the sum of the numbers in the
five rows. In the best case, the halt latency is only one machine state. The
worst-case latency is six machine states plus the delays due to host-indirect
cycles and instruction completion. Table 10-3 shows instruction completion
times for some of the longer instructions. However, a PIXBLT, FILL, or LINE
instruction may take longer than the times shown in Table 10-3, depending
on the size of the pixel array or line specified. Table 10-3 also shows the in-
struction completion time for a J RUC instruction that jumps to itself - the
TMS34010 may be executing this instruction if the software is simply waiting
for a halt.
10-19
Host Interface Bus - Reads and Writes
Table 10-2. Five Sources of Halt Delay
Latency (I n States)
Operation
Min Max
Halt recognition 1 2
Instruction completion 0 See Table 10-3
DRAM-refresh cycle 0 2
See Note 2
Screen-refresh cycle 0 2
See Note 2
Host-indirect cycle 0 See Note 1
Notes: 1) The latency due to host-indirect cycles depends
on both the hardware system and the application.
The delay due to a single host-indirect cycle is two
machine states, assuming no wait states.
2) DRAM-refresh and screen-refresh cycle times as-
sume no wait states.
Table 10-3. Sample Instruction Completion Times
Worst-Case Instruction
Instruction Completion Time (In States)
SP Aligned SP Not Aligned
DIVS AO,A2 43 43
MMFM SP,ALL 72 144
MMTM SP,ALL 73 169
PIXBLT, FILL, and LINE See Note 1 See Note 1
Wait: JRUC wait 1 1
Notes: 1) The worst-case instruction completion time is equal to the in-
struction execution time less one machine state.
2) The SP-aligned case assumes that the SP is aligned to a word
boundary in memory.
10.3.5 Accommodating Host Byte-Addressing Conventions
Processor architectures differ in the manner in which they assign addresses to
bytes. The TMS3401 0 host interface logic can be programmed to accommo-
date the particular byte-addressing conventions used by a host processor.
This ability is important in ensuring software compatibility between 8- and
16-bit versions of the same processor, such as the 8088 and 8086 or the
68008 and 68000. The 8088 transfers a 16-bit word as a series of two 8-bit
bytes, low byte first, high byte second. The 68008 transfers the high byte first,
and low byte second.
The HSTCTL register's LBL bit is used to configure the TMS34010 host in-
terface to accommodate different byte-accessing methods. The host interface
is configured to operate according to the following two principles:
10-20
Host Interface Bus - Reads and Writes
1) First, when a host processor with an 8-bit data bus reads from or writes
to the HSTDATA register, it accesses the high and low bytes of the reg-
ister in separate cycles. The TMS3401 0 does not initiate its local mem-
ory access until both bytes of HSTDATA have been accessed.
2) Second, when HSTADRH and HSTADRL are loaded by the host, the
TMS34010 must not initiate its read of the local memory until the com-
plete pointer address has been loaded into HSTADRL and HSTADRH.
When lBl=O:
• A local memory read cycle is intitiated by the TMS3401 0 when the host
processor reads the high byte of HSTDATA, or writes to the high byte
of HSTADRH.
• A local memory write cycle is initiated by the TMS3401 0 when the host
processor writes to the high byte of HSTDATA.
When lBl=1:
• A local memory read cycle is initiated by the TMS3401 0 when the host
processor reads the low byte of HSTDATA, or writes to the low byte of
HSTADRL.
• A local memory write cycle is initiated by the TMS3401 0 when the host
processor writes to the low byte of HSTDATA.
When the host processor is an 8088, for example, the TMS3401 0 is typically
configured by setting the LBL bit of the HSTCTL register to O. When config-
ured in this manner, the TMS34010 expects the HSTADRL register to be
loaded first, and HSTADRH loaded second. Furthermore, the high byte of the
HSTADRH register is expected to be loaded after the low byte. When LBL is
set to 0, a local read cycle is initiated when the upper byte of the HSTADRH
register is written to by the host processor. This permits the lower byte of
HSTADRH to be loaded first without causing side effects.
10-21
Host Interface Bus - Bandwidth
10.4 Bandwidth
One measure of the performance of the host interface is its data rate, or
bandwidth. The bandwidth is the number of bits per second that can be
transferred through the host interface during a block transfer of data to or from
TMS34010 memory. Assume that the host interface address register is pro-
grammed to autoincrement. The maximum data rate through the host interface
can be expected to approach the bandwidth of the TMS3401 O's memory. For
example, assume a 50- M Hz TMS34010 and a memory requiring no wait
states. The memory cycle time is about 320 nanoseconds (bandwidth = 50
megabits/second). The host's access cycle time at the host interface is so-
mewhat longer than this due to certain additional delays inherent in the oper-
ation of the TMS34010's internal host interface logic. Also, the throughput
of the host interface may depend on whether or not the TMS3401 0 is halted.
The bandwidth is calculated as the width of the host data path (16 bits) times
the frequency of access cycles through the host interface. Given a continuous
series of word accesses, with successive accesses occurring at regular inter-
vals, what is the minimum interval between host accesses that the interface
can sustain without having to send not-ready signals to the host? (The
TMS34010 drives its HRDY output low temporarily to inform the host when
the TMS3401 0 is not yet ready to complete the host's current access.)
First, when the TMS34010 is halted, the host interface should support con-
tinuous accesses occurring at regular intervals no less than about 400 nano-
seconds apart. As long as the host attempts to maintain a throughput no
greater than this limit, delays due to not-ready signals occur rarely, if at all.
The bandwidth for this case is calculated in Table 10-4 a as approximately 40
megabits per second. This value can be expected to vary slightly with sys-
tem-dependent conditions such as the frequency of DRAM-refresh and
screen-refresh cycles.
When the TMS3401 0 is running, the host interface should support continuous
accesses occurring at regular intervals no less than approximately 550 nano-
seconds. The bandwidth for this case is calculated in Table 10-4 as approxi-
mately 29 megabits per second. This value varies slightly with conditions such
as the frequency of DRAM-refresh and screen-refresh cycles, and also with the
characteristics of the program being executed by the TMS3401 O.
Table 10-4. Host Interface Estimated Bandwidth
Assumptions Approximate Throughput
TMS34010 halted 1 6 bits/transfer
50-MHz TMS34010 = 40 megabits/s
No wait states 400 ns/transfer
TMS34010 running 16 bits/transfer
50-MHz TMS3401 0 = 29 megabits/s
No wait states 550 ns/transfer
10-22
Host Interface Bus - Worst-Case Delay
10.5 Worst-Case Delay
In some applications, designers must determine not only the effective
throughput of the host interface, but also the delays that can occur under
worst-case conditions. These conditions occur too rarely to affect overall
throughput, but the important consideration here is not how often they occur,
but that they can occur at all. First, with the TMS34010 halted, the worst
delay is given by the formula (6 + 2N) T, where N is the number of wait states
per TMS3401 0 memory cycle, and T is the local clock period (nominally 160
nanoseconds for a 50-MHz TMS3401 0). Second, with the TMS3401 0 run-
ning, the worst delay is given by the formula (9 + 4N) T. The derivation of
these formulas, summarized in Figure 10-13, may be helpful in illustrating the
mechanisms of the host interface.
2T Synchronization delay
(2 + N)T Screen-refresh cycle
+ (2 + N)T DRAM-refresh cycle
(6 + 2N)T Worst-case delay (total)
(a) Worst-Case Delay with TMS34010 Halted
2T Synchronization delay
(1 + N) T TMS34010 CPU read
(2 + N)T TMS34010 CPU write
(2 + N)T Screen-refresh cycle
+ (2 + N)T DRAM-refresh cycle
(9 + 4N)T Worst-case delay (total)
(b) Worst-Case Delay with TMS34010 Running
N = Number of wait states per memory cycle
T = Local clock period (nominal 160 nanoseconds for 50-MHz device)
Note: These are worst-case delays and have negligible effect on performance. The case
shown in a, for example, could be expected to occur less than once per thousand
(0.1 percent of) host accesses in a typical system.
Figure 10-13. Calculation of Worst-Case Host Interface Delay
Consider case a, in which the TMS3401 0 is halted, first; the worst-case delay
is calculated as the sum of the three delays. The first of these delays is the time
required to internally synchronize the host interface cycle to the TMS34010
local clock. The host's signals are generally not synchronous to the
TMS34010 local clocks. A signal from the host must therefore be passed
through a synchronizer latch (part of the TMS34010 on-chip host interface
logic) before being used by the TMS34010. The delay through the syn-
chronizer is from one to two local clock periods (1 T to 2T), depending on the
phase of the host clock relative to the TMS3401 O's local clock. The second
and third delays in Figure 10-13 represent the time needed to perform a
screen-refresh cycle followed by a DRAM-refresh cycle. The arbitration logic
internal to the TMS3401 0 assigns these two types of cycles higher priorities
than host-requested indirect accesses. (Screen refresh has a higher priority
than DRAM refresh.) Thus, a host access requested at the same time as one
of these cycles must wait. The worst-case assumption is that a screen-refresh
cycle is generated internal to the TMS3401 0 on the same clock edge at which
the request for the host access arrives. Furthermore, a DRAM-refresh cycle is
10-23
Host Interface Bus - Worst-Case Delay
requested during this same clock edge or during the next 1 + N clock edges.
An equivalent delay occurs in the case in which a DRAM refresh and host
access are requested on the same clock edge (the DRAM refresh wins), and
a screen refresh is requested on a later clock edge before the host access can
begin. This case is not shown in Figure 10-13, but the delay in this instance
is also (6 + 2N) T. In a typical system, DRAM-refresh cycles consume about
2 percent of the available memory bandwidth, and screen-refresh cycles take
about 1.5 percent (using VRAMs). The probability of either sequence of
events is therefore very small (less than one in a thousand, assuming N = 0;
that is, no wait states), and the performance degradation due to these unlikely
events is negligible.
Now consider the case in which the TMS3401 0 is running. Host accesses are
of higher priority than TMS34010 instruction fetches and data accesses, but
still of lower priority than DRAM-refresh or screen-refresh cycles. The worst-
case delay is calculated as the sum of the five delays indicated in Figure 10-13
b. This assumes that the TMS34010 begins a read-modify-write operation
on a memory word (this is performed as a read cycle followed by a separate
write cycle) just one clock before the TMS3401 0 receives the host access re-
quest. The TMS3401 0 CPU read cycle is actually (2 + N) T in duration, but
since it begins one clock before the host access is requested, only (1 + N) T
is left in the cycle. The TMS34010's local memory controller treats a read-
modify-write operation as indivisible; once the read has started, no other re-
quest can be granted until the write completes. The write cycle is (2 + N) T
in duration. Again, assume that sometime before the write cycle does com-
plete, screen-refresh and DRAM-refresh cycles are also requested. The prob-
ability of this case is somewhat more difficult to calculate than that of Figure
10-13 a, since the frequency of read-modify-write operations is very program
dependent. This sequence of events rarely occurs, however.
10-24
Section 11
Local Memory Interface
The TMS34010 local memory interface consists of a triple-multiplexed
address/data bus and associated control signals. Several types of memory
cycles, including read, write, screen-refresh, and DRAM-refresh cycles are
supported. During a memory cycle, the row address, column address, and data
are transmitted over the same physical bus lines. The row and column ad-
dresses necessary to address DRAMs and VRAMs are available directly at the
address/ data pins, eliminating the need for external multiplexing hardware.
The TMS34010 interfaces directly to DRAMs (such as the TMS4256 and
TMS4C1024) and VRAMs (such as the TMS4461), and can be programmed
to perform DRAM-refresh cycles at regular intervals. CAS-before-RAS or
RAS-only refresh cycles may be selected. The TMS34010 can also be pro-
grammed to perform screen refresh by scheduling VRAM register-transfer cy-
cles to occur at regular intervals.
The local memory interface provides a hold/hold acknowledge capability that
allows external devices to request control of the bus. After acknowledging a
hold request, the TMS3401 0 releases the bus by driving its address/data bus
and control outputs into high impedance.
Section Page
11.1 Local Memory Interface Pins ................................................................ 11-2
11.2 Local Memory Interface Registers ........................................................ 11 -3
11.3 Memory Bus Request Priorities ............................................................ 11 -4
11.4 Local Memory Interface Timing ............................................................ 11 -5
11.5 Addressing Mechanisms ..................................................................... 11-23
11 -1
Local Memory Interface Bus - Local Memory Interface Pins
11.1 Local Memory Interface Pins
Section 2 describes TMS34010 pin functions in detail. This section briefly
summarizes the local memory interface pins.
LADG-LAD15
These pins form the local multiplexed address/data bus.
DEN The local data enable signal is driven active low to allow data to
be written to or read from LADo-LAD15. (Connects to the G pins
of a pair of optional '245-type octal bus transceivers.)
DDOUT The local data direction out signal is driven high to enable data to
be output on LADo-LAD15. It is driven low to enable data to be
input on LADo-LAD15. (Connects to the DIR pins of a pair of
optional '245-type octal bus transceivers.)
LAL The high-to-Iow transition of the local address latched signal is
used by an external '373-type latch to capture the column address
from LADo-LAD15.
RAS The local row address strobe signal drives the RAS inputs of
D RAMs and VRAMs.
CAS The local column address strobe signal drives the CAS inputs of
D RAMs and VRAMs.
W The local write strobe signal drives the Vii inputs of DRAMs and
VRAMs.
TR/QE The local register transfer/output enable signal connects to the
TR/QE (or DT/OE) pins of a VRAM.
LRDY The local ready signal is driven low by external circuitry to inhibit
the TMS3401 0 from completing a local memory cycle.
INCLK TMS34010 processor functions are synchronous to this input
clock signal. (Video timing is controlled by VCLK.)
LCLK1,
LCLK2 These output clocks are available to the board designer for syn-
chronous control of external circuitry.
LlNT1,
LlNT2 Interrupt requests are transmitted to the TMS3401 0 on these pins.
11-2
Local Memory Interface Bus - Local Memory Interface Registers
11.2 Local Memory Interface Registers
The local memory interface registers are summarized below. These registers
are a subset of the I/O registers which are detailed in Section 6.
• The memory CONTROL register contains several programmable param-
eters that provide control of the local memory interface:
RM (DRAM refresh mode, bit 2): Selects RAS-only or
CAS-before-RAS refresh cycles.
RR (DRAM refresh rate, bits 3 and 4): Controls the frequency of
DRAM refresh cycles.
T (transparency enable, bit 5): Enables or disables the pixel attri-
bute of transparency.
W (window violation detection mode, bits 6 and 7): Selects the
course of action the TMS3401 0 follows when it detects a window
violation.
PBH (PIXBLT horizontal direction, bit 8): Determines the hori-
zontal direction (increasing X or decreasing X) for pixel operations.
PBV (PIXBLT vertical direction, bit 9): Determines the vertical di-
rection (increasing Y or d~c::reasing Y) for pixel operations.
PPOP (pixel processing operation select, bits 10-14): Selects
among several Boolean and arithmetic pixel processing options.
CD (instruction cache disable, bit 15): Enables or disables the in-
struction cache.
• The CONVDP register contains the destination pitch conversion factor
that is used during XY -to-linear conversion of a destination pixel ad-
dress.
• The CONVSP register contains the source pitch conversion factor that
is used during XY -to-linear conversion of a source pixel address.
• The PMASK (plane mask) register selectively disables or enables vari-
ous planes in a multiple-bit-per-pixel bit map display.
• The PSIZE (pixel size) register specifies the number of bits per pixel.
• The REFCNT (refresh count) register generates the addresses output
during DRAM-refresh cycles and counts the intervals between succes-
sive DRAM-refresh cycles.
11-3
Local Memory Interface Bus - Memory Bus Request Priorities
11.3 Memory Bus Request Priorities
The TMS34010's local memory interface controller assigns priorities to re-
quests from various sources, both on and off chip, for local memory cycles.
Table 11-1 lists these priorities (priority 1 is highest).
Table 11-1. Priorities for Memory Cycle Requests
Priority Memory Cycle Requested
1 Hold request from external bus master device
2 Screen-refresh cycle
3 DRAM-refresh cycle
4 Host-initiated indirect read or write cycle
5 TMS34010 CPU memory cycle
A TMS34010 CPU memory cycle is a read or write performed by the
TMS34010's on-chip 32-bit processor. Insertion of a field (or a portion of a
field spanning multiple words) into a word requires two CPU memory cycles
when the field does not begin and end on word boundaries. The two cycles
are a read followed by a write. This sequence is called a read-modify-write
operation. The read and write are performed as separate memory cycles, but
are treated as indivisible; that is, the memory controller does not permit another
memory request to be serviced between the read and its accompanying write.
The only exception to this statement is the hold request. If a read-modify-
write is interrupted by a hold, the entire read-modify-write operation is re-
started after the hold is released.
While a read-modify-write operation on an individual memory word is indi-
visible, the accesses necessary to extract or insert a field spanning multiple
memory words are not. For example, if a field spans portions of two memory
words, a higher priority access such as a host-indirect cycle can occur be-
tween the two read-modify-write operations required to insert the field.
The hold request has the highest priority. An external device requests control
of the bus by signalling a hold request to the TMS3401 O. The external device
may perform multiple memory cycles following acknowledgment from the
TMS34010. However, the device should not control the bus for so long that
necessary screen-refresh and DRAM-refresh cycles are prevented from occur-
ring. Indirect accesses initiated by a host processor are blocked as long as the
external device continues to control the bus. If the host processor attempts
to initiate another indirect access during this time, the host is forced to wait
at the host interface (the TMS34010 sends it a not-ready signal) until the
external device releases the local bus.
A memory cycle already in progress is always permitted to complete, even if a
higher priority request is received while the cycle is still in progress.
11-4
Local Memory Interface Bus - Local Memory Interface Timing
11.4 Local Memory Interface Timing
The TMS34010 memory interface contains a triple-multiplexed address/data
bus on which row addresses, column addresses and data are transmitted.
Figure 11 -1 illustrates mUltiplexing of addresses and data.
RF = DRAM-Refreah bus status bit
IAQ =Instruction acquisition bus status bit
TR = VRAM Shlft-Reglster-Transfer bus status bit
Figure 11-1. Triple Multiplexing of Addresses and Data
The TMS34010 LAD pins directly provide the multiplexed row and column
addresses needed to drive dynamic RAMs (like the TMS4256) and video
RAMs (such as the TMS4461). Any eight adjacent pins in the range
LADo-LAD10 provide 16 contiguous logical address bits; the eight MSBs are
output as part of the row address, and the eight LSBs are output as part of the
column address. For example, Figure 11 -1 shows that logical address bits
5-20 are output at LAD1-LAD8.
The control signals output to memory support direct interfacing to DRAMs
and VRAMs. At the beginning of a memory cycle, the address is output in
multiplexed fashion as a row address followed by a column address. The re-
mainder of the cycle is used to transfer data between the TMS34010 and
memory. Figure 11 -2 (page 11-6) illustrates general timing (the local
address/data pins are identified as the LAD Bus)
11-5
Local Memory Interface Bus - Local Memory Interface Timing
LAD Bus
:=x ROW Ifd~~=X
&I'1t111
Data
C
RAS
\ I
CAS
\ /
Figure 11-2. Rowand Column Address Phases of Memory Cycle
Figure 11-3 through Figure 11-8 show functional timing of the local memory
interface. Several timing features are common to the memory read and write
cycles in Figure 11 -3 and Figure 11 -4, and to the register-transfer cycles in
Figure 11 -6 and Figure 11 -7. A row address is output on LADQ-LAD15 at the
start of the cycle, and is valid before and after RAS falls. A column address is
then output on LADQ-LAD15. The column address is valid briefly before and
after the falling edge of LAL, but is not valid at the falling edge of CAS. The
column address is clocked into an external transparent latch (such as a
74AS373 octal latch) on the falling edge of LAL to provide the hold time on
the column address required for DRAMs and VRAMs. A transparent latch is
required so that the row address is available at the outputs of the latch during
the start of the cycle.
11-6
Local Memory Interface Bus - Local Memory Interface Timing
11.4.1 Local Memory Write Cycle Timing
Figure 11 -3 illustrates a memory write cycle. Data are output on
LADQ-LAD15 following the latching of the column address. DEN goes active
low at the same time the data become valid, and remains low as long as the
data remain valid. In a large system that requires buffering of the data bus to
memory, DEN is typically used as the enable signal to an external bidirectional
buffer (such as a 74AS245 octal buffer). DDOUT is used as the direction
control signal to the buffer. The write strobe, W, goes active low after the data
have become valid and CAS is low. This is interpreted as a "late write" cycle
by the DRAMs and VRAMs, which are prevented by the inactive-high TR/QE
signal from enabling their read drivers. Because the data are valid on both
sides of the W write strobe, external devices can latch the data on either the
high-to-Iow or low-to-high edge of W.
Irnl~IOOI~lrnl~IOOI~lrnl
LCLK1 ~ : :' i: 1'-. . . .:--k:, 1: (,..-+:--
LCLK2 LJI 1 I,l 1 V-"'I-"~""'!:. . . .I_-¥II
LADO-LAD15 ---v.' _....'_~'~I
I
Row
I I I I:
Data
I I
x::=
I'
r - - i ' , ~I ,1"'fi"1 I Iii
-RAS I II I I I I II ..I'I " 'I
I I I: I I I I I
LALV ! 1 1~I 1 1 v,-. . . . .I-
I I I I I I I I I I
CAS I II 1 II I' ~
I I I
1 I
I
VI 1
I I I
-
W I
I
I I
I
I
I
I
I
" V~ "
i\I "-.,....--t.r--f. I
I
I I I I I I I I
DDOUT
LRDY
Figure 11-3. Local Bus Write Cycle Timing
11-7
Local Memory Interface Bus - Local Memory Interface Timing
11.4.2 Local Memory Read Cycle Timing
Figure 11 -4 illustrates a memory read cycle. LADO-LAD15 are forced to high
impedance following the latching of the column address. DEN and TR/OE both
go active low after CAS becomes low in order to enable read data from the
memory to the LAD pins. TR/OE enables the output drivers of the DRAMs and
VRAMs. DEN enables the external bidirectional buffers needed with memories
so large that external buffering (using a device such as a 74AS245 octal buf-
fer) of the data bus is required. The DDOUT signal serves as the direction
control for the external bidirectional buffers, and is low well in advance of the
high-to-Iow transition of DEN, and remains low well after the low-to-high
transition of DEN. The data that is read from memory must be valid during the
middle of the Q4 clock phase, as indicated in Figure 11 -4. The low-to-high
transitions of TR/OE and DEN occur well in advance of the time at which the
LAD drivers turn on to output the row address of the next cycle. This prevents
bus conflicts.
I 01 Q2 04 I 01 Q2 I 03 I 01 I
V~--:--"""lI
~VI
LCLK1
I I
LADO-LAD15
I
I I
I V..t--I---;--
I I r.--~
I
DDOUT I
Figure 11-4. local Bus Read Cycle Timing
11-8
Local Memory Interface Bus - Local Memory Interface Timing
11.4.3 Local Register-to-Memory Cycle Timing
A register-to-memory cycle is a special type of cycle used in systems with
VRAMs. The cycle transfers the contents of the VRAM's internal serial-data
register to a selected row of its internal memory array. The cycle typically af-
fects all VRAMs in the system. During the register-to-memory cycle shown
in Figure 11 -5, both TR/QE and Ware low during the fall of RAS. VRAMs re-
cognize this timing as the beginning of a register-to-memory cycle. Conven-
tional DRAMs may need to be de-selected (by withholding the row or column
address strobe, for example) to prevent them from interpreting the cycle as a
conventional read cycle. Alternately, the output enable signal required by a
DRAM such as the TMS4464 can be synthesized by connecting DEN and
DDOUT to the inputs of a two-input OR gate. (In fact, any pair of the signals
DEN, DDOUT, and TR/QE will work.) The low-to-high transition of TR/QE
occurs after the fall of CAS but prior to the rising edge of RAS. This timing
provides compatibility with a variety of VRAMs.
The TMS3401 0 performs a register-to-memory cycle when writing to a pixel
while the DPYCTL register's SRT bit is set to 1. For example, the instruction
PIXT AO, *Al writes the pixel in AO to the address pointed to by A1. The
PSIZE register should contain the value 16 so that the write cycle is not pre-
ceded by a read cycle. When SRT is set to 1, this write is converted to the
register-to-memory cycle shown in Figure 11 -5. The row address is selected
from bits 12-26 of A 1, which are output on LADo-LAD14 during the cycle.
I 011 02 I 03 I 04 I 01 I 02 I 03 I 04 I 01 I
LCLK1 ('
,I I..'\ I, I~V I '\'0 I~: 'V~--+-'--
I
I ~ , I ,
"
!J
LCLK2!L....-..V ,,
I
,' \I : ',
0
'V '
"
• ,
k
: ,
:....', _ . . . . 'I, /r--
j\.,-o!-I
, , "~'L ,,:,'
LADO-LAD 15 --v. Row . Col. Undefined x::=
',\''I: ,
0
r--f',
, I
"
"'I
I, , I
RAS I I I:I ,0 I V! I I
LAL V I I I~I I I: v~~II---
, I ' " " :, ,
~I
CAS I
W
h i::
,
I I I VI
' I 1\
:I ::::
"
I: I I
I
TR/OE I~!' I, I" I It'"
r I I I
DEN t::J I I I I I I I
, , , " ""
DDOUTlJ' " " I '
LRDY
,
1---1
, ,, "" "
"
"
Figure 11-5. Local Bus Register-to-Memory Cycle Timing
11-9
Local Memory Interface Bus - Local Memory Interface Timing
11.4.4 Local Memory-to-Register Cycle Timing
A memory-to-register cycle is a special type of cycle used in systems with
VRAMs. The cycle transfers the contents of a selected row of a video RAM's
memory array to its internal shift register.
VRAM memory-to-register cycles are primarily used to refresh the screen of a
CRT monitor. The cycles referred to elsewhere in this document as screen-
refresh cycles are in fact memory-to-register cycles. The TMS34010 also
performs a memory-to-register cycle when reading a pixel (for example, by
executing a PIXT *AO ,AI instruction) while the SRT bit of the DPYCTL reg-
ister is set to 1.
During the memory-to-register cycle shown in Figure 11-6, TR/QE is low
during the fall of RAS, but W remains high. VRAMs recognize this timing as
the beginning of a memory-to-register cycle, and their data outputs remain in
high impedance. Conventional DRAMs may need to be de-selected to prevent
them from interpreting the cycle as a memory read cycle. Alternately, the
output enable signal required by a DRAM such as the TMS4464 can be syn-
thesized by connecting DEN and DDOUT to the inputs of a two-input OR gate.
The low-to-high transition of TR/QE occurs after the fall of CAS but prior to the
rising edge of RAS. This timing provides compatibility with a variety of
VRAMs.
1 01 I 02 103 104 1 01 1 02 I 03 I 04 I 01 I
V
~ i 1\ I ~
I 1 I 1 1
LCLK1 I
1
1\
1
I I
1 II 1 I
1
1
LCLK2 LJI 1
1 1\: I V I
1 If
I
~l 1
1
I I 1 I : 1 I 1 1 : 1 1
L.ADO-l.AD15 ~ Row
i ~ i
x::
Undefined
i i i I
I
: 1
~
I 1 I
RAS I
1
I
i
1
I 1
:I I
I I
I
I
VI
I
1
II
I
1
I
~I
I I I
V I
I
LALV I
I I I I I I
I
I
I
CAS i
_I
1
I
I
I
I
I
I
I
; !\
I
I
I
I
I
I
I I
1
1
I I
V II
I
W I I (High) I I I I
--I
TRlOE I
hi I
1
I
I
1
I
I
V
I
I
I
I
I
I
I I I I I I I
-t::J1
DEN I
I
I
I
I
I
1
I
1
1 1 I 1 1 I I
OOOUTLJ 1
1
I
1
I
I
I
I
I
1
LRDY
Figure 11-6. Local Bus Memory-to-Register Cycle Timing
11 -10
Local Memory Interface Bus - Local Memory Interface Timing
11.4.5 LOC,ll Memory RAS-Only DRAM Refresh Cycle Timing
During the RAS-only DRAM refresh cycle shown in Figure 11-7, RAS and LAL
are the only active control signals. All other signals, including CAS, W, and
TR/QE, remain inactive high through the cycle. The row address, output on the
LAD pins during the high-to-Iow transition of RAS, is generated by the
REFCNT (DRAM-refresh counter) register.
I~I~I~I~I~I~I~I~I~I
LCLK1 V 1 1\ I : V I 1\ I : I/~-+I--
I I I I I I I: I
I I 1
LCLK2 W~-+I-'""'I\: 1 V 1 ~~:__
I_-¥II
II:IIII:II
LADO-LAD15
RAS
~ I X
Row
I:
1-1- . .'--1\1\:
Undefined
I
1
I I I
x::::
I/~~I--+I--
~I~~I_~I:::::!~I__~___
I __JI I I
LALV I 1 t\_t-I-t--~II-~I~-fV--;-1-
CAS! 1 (HI~h) I I I I I
I I: I 1 I I I
II II (HI~h)I
TR/OE II II II II II
DENt::) I II II 1 II 1
I I I I I
DDOUTU 1 I 1 1 I 1
I I I .1 I I I
LRDY :
Figure 11-7. Local Bus RAS-Only DRAM-Refresh Cycle Timing
11 -11
Local Memory Interface Bus - Local Memory Interface Timing
11.4.6 Local Memory CAS-before-RAS DRAM Refresh Cycle Timing
During the CAS-before-RAS DRAM-refresh cycle shown in Figure 11-8, CAS
goes low before RAS goes low. Certain types of DRAMs (like the TMS4256
and TMS4C1 024) and VRAMs (such as the TMS4461) recognize this as the
beginning of a DRAM-refresh cycle in which the address of the row to be re-
freshed is generated by a counter on the RAM chip itself, rather than by an
external device such as the TMS34010. The row address output by the
TMS34010 during the cycle is the same as would be output if the TMS3401 0
were configured to perform a RAS-only refresh cycle rather than a
CAS-before-RAS cycle. The address bits output on LADQ-LAD15 remain sta-
ble from the start of the row address time (start of 02) to the end of the col-
umn address time (end of 04). LAD15, on which the RF bus status bit is
output, is low during the row address times. In contrast to other types of cy-
cles in which RAS goes low, the LAL output goes low at the start of 03, after
the fall of CAS and before the fall of RAS. The timing of LAL is designed to
support the use of decode circuitry which latches the state of selected
address/data pins during the fall of LAL, and which recognizes a
CAS-before-RAS cycle by detecting a high level at the RAS output during the
fall of LAL.
LCLKl
LCLK2
LADO-LAD15
lin I I
I
Dr:(: 1\ 1 I v'
~ Il\ I Vtt-I-+---1-
I I ~I--+-+--+---t----t---t-f: I
w I I (High) :I
I I ! I
I 1
I
I
DDOUT
Figure 11-8. Local Bus CAS-before-RAS DRAM-Refresh Cycle
Timing
11 -12
Local Memory Interface Bus - Local Memory Interface Timing
11.4.7 Local Memory Internal Cycles
When the TMS3401 0 is not performing one of the memory operations shown
in Figure 11 -3 through Figure 11 -8, its memory interface control signals re-
main inactive, as shown in Figure 11 -9. This is called an internal cycle. Figure
11-9 shows two sequential internal cycles. During internal cycles, the LRDY
input is ignored.
1~1~IOOI~I~I~ I 03 I 04 I 01 I
LCU<1 r : ~,--+i_:. . . ,(,. . . ,. : ,1\ I V,
--tt.
I
I
I
I
:
LCLK2 W"'-+I--tt..I\: I V"'-+-'"
,, ,~i ,I II
L-....\,' ':1 ,
I
I
I
LAD0-LAD15 ~~~__~~~u_n_d~d_n_ed~__~~~~IX:::
I
I ':
I (High)
II II
I I I I
V I I I I
I I I I I
wi I (High) I I
I I I I I
I ,I I I
I I (High) I I
t:J I
I I I
II !I
ODOlIT CJ
I I
II II II
LRDY
Figure 11-9. Local Bus Internal Cycles Back to Back
11.4.8 I/O Register Access Cycles
A special memory read or write cycle is performed when the TMS3401 0 ad-
dresses an on-chip I/O register. During this cycle, the external RAS signal falls,
but the external CAS remains inactive high for the duration of the cycle. I/O
register locations begin at address COOOOOOOh, and all 32 bits of the I/O reg-
ister address are decoded internally. The two MSBs of the 32-bit logical ad-
dress are not output at the LADo-LAD15 pins.
Figure 11 -10 shows an I/O register read cycle and Figure 11 -11 shows an I/O
register write cycle. These cycles occur when one of the TMS3401 O's on-chip
I/O registers is accessed by the on-chip processor or by the host processor via
a host-indirect access. An address in the range COOOOOOOh to C00001 FFh is
interpreted as an I/O register access by on-chip decode logic, and the read or
write cycle is modified as shown in Figure 11 -10 or Figure 11 -11. The two
11-13
Local Memory Interface Bus - Local Memory Interface Timing
MSBs of the internal address (bits 30 and 31) are available internally and are
included in the internal decoding operation.
An I/O register read or write cycle is always two clock periods in duration, and
LRDY is ignored. The only control outputs that are active low during the cycle
are RAS and LAL. The CAS, W, TR/QE, DEN and DDOUT outputs all remain in-
active high. The row and column addresses output at the LADQ-LAD15 pins
are all Os. All three bus status bits are inactive (RF is high, lAO is low, and TR
is high). During the read cycle shown in Figure 11-10, the LADQ-LAD15 pins
are driven to high impedance during the data phase of the cycle. During the
write cycle shown in Figure 11-11, the LADQ-LAD15 pins contain the valid
data being written to the I/O register.
, 01 , 02 I 03 , 04 , 01 , 02 I 03 i 04 i 01 "
LCLK1V 1 1\ ,': V I 1\ I: V---+- --
I I I ,r I , I " I
I
LCLK2' !J I 1\: l IV 1\; I II
~
~I 1v.6t1 11:1 ~
LADO-LAD15 Row ~--HI-Z ~+-I-~
, I I" , " I
I
RAS , i
"
,\ I:: I I 'I
if: I
I
I
, I , I: I 'I I
LALVIII~' V-.........
:-
, I I I:: I
CAS i (High) i , i
, ,I I I
i ! I , I
WiI (Hi~h) II 1 II
- I I I I I
TR/QE I I (High) I I I
I I I I I
DENt::J I I 1
'I I' I
DDOUT'~I I
I 'I II
I I I I
LRDY
Figure 11-10. I/O Register Read Cycle Timing
11 -14
Local Memory Interface Bus - Local Memory Interface Timing
I 01 i i i ~ i I i i ~ i ~0_1 i__
02 03 01 02 03 ...
LCLK1 Y I I' I i I' I I' I: V I
I I I 1\: I I~ I L: I ~r-
LCLK2
LADO-LAD15
H
---y
I
I
I
Row
I .: I
I~
~
• I
I
Data
i\: I
I "+:--1-"1
!!
x:::
RAS
r-r
1 I
I I: I
I, I : I
I: I
VI i I
LAC >
I
1
I
1
I
1
I:
~ ; I
III l-
!- ~-.........
I
CAS I I (High) i i i i
I i I I I I I
I i I I I I I
WI I (High) I I I I
I I I I I I I
I I I I I I I
hI'
TR/OE I I(HI~h)1 I I I
I I I i i
DEN I I I i I I
I I I I I I
DOOUTI'; I I I I I
'--' I I I I I
I I I I I I I
LRDY
Figure 11-11. I/O Register Write Cycle Timing
11.4.9 Read-Modify-Write Operations
The TMS34010's read-modify-write operation, which consists of separate
read and write cycles, is not the same as the read-modify-write cycle specified
for some DRAMs. As explained in Section 5, when inserting a field into me-
mory that is not aligned to 16-bit word boundaries, the TMS34010 memory
interface logic may be required to perform read-modify-write (RMW) oper-
ations on one or more words in memory. A RMW operation consists of the
following sequence of steps:
1) A word is read from memory.
2) The portion of that word corresponding to the field being inserted is
loaded with the new value.
3) The modified word is written back to memory.
The read cycle is as shown in Figure 11 -4 (page 11 -8), and the write cycle is
as shown in Figure 11-3 (page 11-7).
A local bus request (HOLD low) may cause the TMS3401 0 to release the bus
after the read cycle of a RMW operation has completed, but before the ac-
companying write cycle has begun. When the TMS3401 0 later regains control
of the bus, it performs both the read and the write cycles of the RMW opera-
tion. The RMW operation is performed only when it is the highest priority bus
operation pending. Any pending screen-refresh, DRAM-refresh, or host-
indirect cycle has higher priority, and is performed first.
11 -15
Local Memory Interface Bus - Local Memory Interface Timing
11.4.10 Local Memory Wait States
The timing shown in Figure 11-3 through Figure 11-8 assumes that the LRDY
input remains high during the cycle. The LRDY pin is pulled low by slower
memories requiring a longer cycle time. The TMS3401 0 samples the LRDY
input at the end of Q1, as indicated in the figures. If LRDY is low, the
TMS34010 inserts an additional state, called a wait state, into the cycle.
Wait states continue to be inserted until LRDY is sampled at a high level. The
cycle then completes in the manner indicated in Figure 11 -3 through Figure
11 -8.
The LRDY input is ignored by the TMS3401 0 during internal cycles, as indi-
cated in Figure 11 -9.
Figure 11 -12 shows an example of a read cycle extended by one wait state.
The first time LRDY signal is sampled, a low level is detected by the
TMS34010, causing the cycle to be delayed by a wait state. When LR DY is
sampled again one local clock period later, a high level is detected, permitting
the cycle to complete. The time during which RAS, CAS, LAL, TR/QE, DEN, and
DDOUT remain low is extended by one state (one local bus clock period).
iWaitStati
01 I Q2 I 01 I Q2 03 I 04 I 01 I I Q2
I I
lClK1 I I
lClK2
LAl I
I
I I I I I
I I
~ I
I
I
i\
I
I
I
I
IVII
I
I
I
I I I
W i I I (Hlghl
I I I
I I i
fR/tlE I
I
I
I
I
I
1\
I
I
i
I
DERJ: I
I
I
I
1\
I
I
Figure 11-12. Local Bus Read Cycle with One Wait State
11-16
Local Memory Interface Bus - Local Memory Interface Timing
Figure 11 -13 is an example of a write cycle extended by one wait state. The
first time LRDY signal is sampled, a low level is detected by the TMS3401 0,
causing the cycle to be delayed by a wait state. When LRDY is sampled again
one local clock period later, a high level is detected, permitting the cycle to
complete. The time during which RAS, CAS, LAL, Wand DEN remain low is
extended by one state.
5m II
~:
Figure 11-13. Local Bus Write Cycle with One Wait State
Figure 11 -14 is an example of a register-to-memory cycle extended by one
wait state. The first time the LR DY signal is sampled, a low level is detected
by the TMS3401 0, causing the cycle to be delayed by a wait state. When
LRDY is sampled again one local clock period later, a high level is detected,
permitting the cycle to complete. The time during which RAS, CAS, and LAL
remain low is extended by one state. The Wand TRjQE low times are not ex-
tended, however. Similarly, during a memory-to-register cycle, TR/QE is not
extended.
11-17
Local Memory Interface Bus - Local Memory Interface Timing
w
TRIM
DDOUT i
I
I I I I I
LRDY~
Figure 11-14. local Bus Register-to-Memory Cycle with One Wait
State
11.4.11 Hold Interface Timing
The TMS3401 0 includes a hold interface through which external bus-master
devices can request control of the local memory bus. When the TMS34010
grants a hold request, it drives its local memory address/data bus and control
outputs to high impedance, and the requesting device becomes the new bus
master. When the requesting device no longer requires the bus, it removes its
hold request, and the TMS3401 0 again assumes control of the local bus.
Figure 11 -15 shows the TMS3401 0 releasing control of the local bus in re-
sponse to a hold request. The TMS3401 0 samples the state of the HOLD input
at each LCLK2 rising edge (at the end of the 01 phase of the clock). HOLD
is a synchronous input, and must not change during the time that the
TMS34010 samples it; refer to the TMS34010 Data Sheet for HOLD setup and
hold times. The state of the hold acknowledge signal (active or inactive) is
output on the HLDA/EMUA pin during the 03 and 04 clock phases (LCLK1
low). During the first (or leftmost) LCLK2 rising edge, the hold request is
inactive. Consequently, the hold acknowledge signal remains inactive during
11-18
Local Memory Interface Bus - Local Memory Interface Timing
the first LCLK1 low phase. By the second LCLK2 rising edge, the hold request
has been activated, and the TMS3401 0 responds by acknowledging the hold
request during the next LCLK1 low phase. The address/data lines and ma-
jority of the control lines are driven to high impedance at the start of the next
Q2 phase (LCLK2 rising edge). The DDOUT and DEN pins are driven to high
impedance a quarter clock later.
Figure 11-16 shows the TMS34010 resuming control of the local bus after
deactivation of the hold request. Again, the TMS3401 0 samples the state of
the HOLD input at each LCLK2 rising edge. During the first LCLK2 rising edge,
the hold request is still active, and the TMS3401 0 responds during the next
LCLK1 low phase with an active hold acknowledge signal. By the second
LCLK2 rising edge, the hold request has been removed. The TMS3401 0 re-
sponds by outputting an inactive hold acknowledge signal during the next
LCLK1 low phase. At the next LCLK2 rising edge, the TMS3401 0 begins to
drive its address/data pins and the majority of its control pins to logic-high or
logic-low levels. The DEN and DDOUT signals remain in high impedance for
one additional quarter clock before they too begin to be driven.
LCLKl
RAl
m
~
w I
I
I
fli/M I
I
I
om
:\
I
I
RIl5A/EMUA I
I
I
LNo-l
Ack
Figure 11-15. TMS34010 Releases Control of Local Bus
In Figure 11-15, the first active-low pulse of the HLDA/EMUA output is an
early acknowledgment, and the bus is not released for another three quarters
11-19
Local Memory Interface Bus - Local Memory Interface Timing
of a clock. The early acknowledgment gives advance warning to the device
requesting the hold that the bus is about to be released by the TMS3401 0,
allowing the device time to prepare to become the new bus master. The
TMS34010 outputs the active hold acknowledge signal only when it is pre-
pared to release the bus within the next clock period. If the TMS3401 0 must
wait longer than this to release the bus, its hold acknowledgment is withheld
until it can release the bus.
For instance, if the LR DY signal in Figure 11 -15 were low instead of high at
the second rising edge of LCLK2, the TMS3401 0 would be forced to wait, and
would therefore not acknowledge the hold request until later, when the not-
ready condition was removed. Also, if the hold request in Figure 11 -15 was
asserted initially during the first LCLK2 rising edge rather than the second, the
TMS34010 would delay its hold acknowledgment until the second LCLK1 low
clock phase, knowing that the cycle in progress would not be completed until
the third 02 phase in the diagram.
A hold request has a higher priority than any internally generated memory cy-
cle requests, including:
• Screen refresh
• DRAM refresh
• Indirect access by the host processor
• TMS34010 instruction fetch or data access
A hold request is delayed only to allow a memory cycle already in progress to
complete.
External devices can activate or deactivate the HOLD input during any clock
of an ongoing cycle, as long as the input is stable during the rising edge of
LCLK2. The HOLD input is synchronous and is required to meet specified
setup and hold times to ensure that the TMS3401 0 operates correctly. After
the TMS3401 0 grants the bus to an external device (via an active-low level
on the HLDA/EMUA output during the 03 clock phase), it continues to ac-
knowledge the hold request during the 03 phases of subsequent clock cycles.
The external device retains control of the bus until it deactivates its hold re-
quest.
External devices should avoid placing the TMS3401 0 in hold for long periods.
While the TMS34010 is in hold, it can perform neither screen-refresh nor
DRAM-refresh cycles. Furthermore, a host processor attempting to access the
TMS34010's local memory through the host interface registers while the
TMS34010 is in hold may receive a not-ready signal. When this occurs, the
host is forced to wait to complete its access until the TMS34010 leaves the
hold state. (Refer to Section 9.10.1.5, Scheduling Screen-Refresh Cycles, on
page 9-27 for more information.)
If a request for a DRAM-refresh or screen-refresh cycle is generated within the
TMS34010 while an external device controls the bus, the TMS3401 0 retains
the request and perform the DRAM-refresh or screen-refresh cycle after the
external device has returned control of the bus to the TMS3401 O. However,
if a requested DRAM-refresh cycle is prevented from occurring for so long that
a second DRAM-refresh cycle is requested before the first DRAM-refresh cy-
cle can occur, the first DRAM-refresh request is lost. Similarly, if a screen-
refresh request is prevented from occurring for so long that a second
11-20
Local Memory Interface Bus - Local Memory Interface Timing
screen-refresh cycle is requested before the first screen-refresh cycle can oc-
cur, the first screen - refresh request is lost.
The HLDA/EMUA output is multiplexed between the hold acknowledge
(HLDA) and emulate acknowledge (EMUA) signals. The HLDA signal is output
during the LCLK1 low phase, and the EMUA signal is output during the LCLK1
high phase.
I I I I
I 01 02 I 03 I 04 I
LCLK1
~~~--~~~~!~~ ~I--~V
I I I
I
LCLK2 I
LADO-LAD15
TR/OE
DDOUT
LRDY
Figure 11-16. TMS34010 Resumes Control of Local Bus
11-21
Local Memory Interface Bus - Local Memory Interface Timing
11.4.12 Local Bus Timing Following Reset
Figure 11 -17 shows the timing of the local bus signals following reset. At the
end of reset, the TMS3401 0 automatically performs a series of eight RAS-only
refresh cycles, as required to initialize certain DRAMs (such as the TMS4256
and TMS4464) and VRAMs (such as the TMS4461) following power-up.
The asynchronous low-to-high transition of RESET is sampled at the second
high-to-Iow LCLK1 transition in Figure 11-17. In less than two local clock
periods following this LCLK1 transition, the first of the eight RAS-only cycles
begins, as shown at the right side of Figure 11 -17.
Each of the eight RAS cycles following reset is two clock periods in duration,
but can be extended by a not-ready signal (LRDY low). The timing for each
cycle is identical to that of a RAS-only DRAM-refresh cycle, including the bus
status codes output during the row and column address times. The row ad~
dress for each of the eight RAS-only cycles is all Os.
FIRST OF 8 RAS-ONL Y
1 4 - - - - - 7t
a - - - - - I..-.t1 /
CYCLES BEGINS
LCLK1
LCLK2
RESET I I I
I I I I
I
I
I
I
II I
I I
I I
I
I
I I
I I
I
II II I II II II II II
LADO-LAD15 ..... HI-Zr--I--..,--.l--r-~--.,.--.j....-I-""'--T--I--I\
II II Jt RO~
I: K '
I I I I I I
I,.. I I I I I
I I I I I
~~~~--+-~--~--~-+__~__~~__+-~-~~
III
I
I I I I I I I
I
RAS
I
I I
I
I
I
I
~.W.ffi/Q£. ~~~-+--~~~~--+-~--~-r--+--~~~-r--+-~--~
DEN. DDOUT
Figure 11-17. Local Bus Timing Following Reset
11-22
Local Memory Interface Bus - Addressing Mechanisms
11.5 Addressing Mechanisms
The TMS3401 0 addresses memory by means of a 32-bit logical address. As
explained in Section 3, each 32-bit logical address points to a bit in memory.
Logical address bits are numbered from 0 to 31, where bit 0 is the LSB and
bit 31 is the MSB. Figure 11-18 illustrates the manner in which address bits
4-29 are output to physical memory. Each column in the figure indicates an
address/data bus pin, LADO-LAD15, and below it is the corresponding bit of
the logical address output at the LAD pin during the fall of RAS and during the
fall of CAS. Bus status bits RF, TR, and IAQ are output on LAD14-LAD15.
LAD Pin Numbers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMS34010 At Fall RF 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
Logical of RAS
Addfess At Fall lAC TR 29 28 27 14 13 12 11 10 9 8 7 6 5 4
Bits
of CAS
t Bus status signals:
RF - DRAM refresh cycle
IAQ - Instruction acquisition cycle
TR - Register-transfer cycle
Figure 11-18. External Address Format
Key features of the local bus addressing mechanism include the following:
• The two MSBs of the 32-bit logical address (bits 30 and 31) are not
output.
• The four LSBs of the 32-bit logical address (bits 0 to 3) are not output,
but are used internally to designate a bit boundary within a 16-bit word
accessed in the external memory.
• The address bits output on LADo-LAD10 during the falling edges of RAS
and CAS are aligned so that 16 consecutive bits from the logical address
are available at any eight consecutive pins in the range LADO to LAD10.
The address bits are output in this way in order that the 8-bit row ad-
dress and 8-bit column address presented to the dynamic RAMs can al-
ways be taken from the same eight address/data pins. This eliminates
the need for external address multiplexers.
• Logical address bits 12-14 are output twice during a memory cycle -
during both the RAS and CAS falling edges - but at different pins. This
allows a variety of memory organizations and decoding schemes to be
used.
Pins LADo-LAD10 form an 11 -bit zone in which logical address bits 12-14
are overlapped (that is, they are issued in both cycles, but on different pins).
The row and column address bus is connected to any eight consecutive pins
within this zone. The actual position is determined by the bank-decoding
scheme selected for a particular memory organization.
11-23
Local Memory Interface Bus - Addressing Mechanisms
Output along with the address are three bus status signals:
• The RF (DRAM refresh) bit is output on LAD15 during the fall of RAS.
It is low if the cycle that is just beginning is a DRAM-refresh cycle (ei-
ther RAS-only or CAS-before-RAS); otherwise, RF is high.
• The TR (VRAM register transfer) bit is output on LAD14 during the fall
of CAS, and is low· if the cycle in progress is a video RAM register
transfer. Otherwise, TR is high. In either event, the state of the TR bit
reflects the state of the TR/QE output during the falling edge of RAS
within the same cycle.
• The lAO bit is output on LAD15 during the fall of CAS, and is high if the
cycle is an instruction fetch; otherwise, lAO remains low. The term in-
struction fetch includes not only reads of opcodes, but also immediate
data, immediate addresses, and so on.
lAO is active high when words are fetched from memory to load the in-
struction cache. A cache subsegment (a block of four words) is loaded in a
series of read cycles, during which lAO is active high. The PC points to an
instruction word within the block, but the block may contain data as well as
instruction words (opcodes, immediate addresses, immediate data, and so on).
Only during execution can the TMS3401 0 distinguish instruction words from
data words residing in the cache. Instruction words are fetched from the
cache as they are needed, but data inadvertently loaded into the cache is ig-
nored and all memory data reads or writes result in accesses of the memory
rather than the cache.
When the cache is disabled, lAO is active high only when the first word of an
instruction is fetched; in the case of a mUltiple-word instruction, lAO is inac-
tive while the additional words are fetched.
11.5.1 Display Memory Hardware Requirements
The minimum number of bits of memory required to implement the display
memory is the product of the total number of pixels (on-screen and off-screen
areas combined) and the number of bits per pixel. The minimum number of
VRAMs required to contain the display memory is calculated as follows:
(pixels per line) x (lines per frame) x (bits per pixel)
N um b er 0 f VRAM s =
Number of bits per VRAM
This calculation yields the minimum number of VRAMs needed, but additional
VRAMs may be required in some applications. For instance, XY addressing
can be supported by making the number of pixels per line of the display me-
mory a power of two, but this may require more than the minimum number of
VRAMs needed to contain the display.
11-24
Local Memory Interface Bus - Addressing Mechanisms
11.5.2 Memory Organization and Bank Selecting
During a single local memory cycle, one data word (16 bits) is transferred
between the TMS34010 and the selected bank of memory. The memory is
partitioned into a number of banks, where each bank contains the number of
memory devices that can be accessed in a single memory cycle. The number
of devices per bank is therefore determined by dividing the width of the data
bus by the number of data pins per device. The TMS3401 0 data bus is 16 bits
wide, and can access 16 memory data pins during a single cycle. This means,
for example, that a bank composed of 64K-by-1 RAMs contains 16 RAM de-
vices. A bank composed of 64K-by-4 RAMs contains 4 RAM devices.
In a typical system, the local memory is divided into two parts, one consisting
of the display memory and the other consisting of additional DRAMs needed
to store programs and data. This additional RAM can be called the system
memory. A high-order address bit is typically used to select between the dis-
play memory and system memory. Within the display memory or system me-
mory, some address bits are provided as the row and column addresses to the
selected bank, while other address bits are used to select one of the banks.
The number of banks of VRAM needed for the display memory is calculated
by dividing the total number of VRAMs by the number of VRAMs per bank.
This in turn determines how many bank select bits must be decoded.
11.5.3 Dynamic RAM Refresh Addresses
DRAMs (and VRAMs) require periodic refreshing to retain their data. The
TMS34010 automatically generates DRAM-refresh cycles at regular intervals.
The interval between refresh cycles is programmable, and DRAM refreshing
can be disabled in systems that do not require it.
The TMS34010 can be configured to generate one of two types of DRAM-
refresh cycle timing:
• RAS-only (see Figure 11 -7) or
• CAS-before- RAS (see Figure 11-8).
During a RAS-only refresh cycle, the TMS34010 provides the 8-bit row ad-
dress needed to refresh a particular row within each of the DRAMs in the
memory system. DRAMs that support CAS-before-RAS cycles each contain
an on-chip counter which generates the row address needed during the cycle.
In other words, these devices do not rely on the TMS3401 0 to provide the row
address during the CAS-before-RAS cycle.
The row address output by the TMS3401 0 during a DRAM-refresh cycle is the
same regardless of whether the TMS34010 is configured for RAS-only or
CAS-before-RAS refresh timing. Since the TMS34010 outputs a valid row
address during a CAS-before-RAS cycle, a system can contain some DRAMs
that use CAS-before-RAS refresh timing and others that use RAS-only timing.
This hybrid approach configures the TMS34010 to perform CAS-before-RAS
refresh, and relies on external decode logic to prevent the active-low column
address strobe from reaching those DRAMs that require RAS-only refreshing.
The decode logic detects the fact that CAS falls before RAS during a CAS-be-
fore-RAS cycle, and uses this to inhibit transmitting the CAS signal to the
RAS-only DRAMs.
11-25
Local Memory Interface Bus - Addressing Mechanisms
Several bits in the CONTROL register determine the manner in which the
TMS34010 performs DRAM refreshing. The RM bit selects the type of
DRAM -refresh cycle:
• RM=O selects RAS-only cycles
• RM=1 selects CAS-before-RAS cycles
The RR bits determine the interval between DRAM-refresh cycles:
• RR=002 selects refreshing every 32 local clock periods.
• RR=012 selects refreshing every 64 local clock periods.
• RR = 1 02 is a reserved code.
• RR=112 inhibits DRAM refreshing.
At reset, internal logic forces the RM bit to 0 and the RR field to 002. While
the RESET signal to the TMS34010 is active, no DRAM-refresh cycles are
performed. Following reset, the TMS3401 0 begins to automatically perform
DRAM-refresh cycles at regular intervals.
Both the interval between DRAM-refresh cycles and the addresses output
during the cycles are generated within the REFCNT (DRAM-refresh count)
register. Bits 2-15 of REFCNT form a continuous binary counter. The RINTVL
field occupies bits 2-7, and counts the length of the interval between succes-
sive internal requests for DRAM-refresh cycles. The eight MSBs of REFCNT
form the ROWADR field, containing the row address output to memory during
the DRAM~refresh cycle.
11-26
Local Memory Interface Bus - Addressing Mechanisms
GSP
LAD16 ~ (DRAM Refreah
Bus Status BIt)
LAD1oi. ROWADR8 = REFCNT14
LAD13 ROWADR6 = REFCNT13
LAD12 ROWADRoi. = REFCNT12. eto.
LAD11 ROWADR3
LAD10 ROWADR2
LAD9 ROWADR1
LAD8 ROWADRO
LAD7 ROWADR7
Example:
LAD8 ROWADR8 LAD2-LAD9 provide the
LADS ROWADRS 8-bIt row address to a
blook of DRAMa or VRAMB.
LAD4 ROWADR4
LAD3 ROWADR3
LAD2 ROWADR2
LAD1 ROWADR1
LADO ROWADRO
Figure 11-19. Row Address for DRAM-Refresh Cycle
During a DRAM-refresh cycle, the 8-bit row address in the ROWADR field of
the REFCNT register is output on the LAD pins during the high-to-Iow tran-
sition of RAS. As shown in Figure 11 -19, the eight bits of ROWADR are out-
put on LADD-LAD7. The seven LSBs of ROWADR are also output on
LAD8-LAD14. LAD15 transmits the RF bus status signal, low during the fall
of RAS. .
Assume that LAD2-LAD9 are used as the 8-bit row address by a bank of
DRAMs, as indicated in Figure 11-19. The address bits output on
LAD2-LAD9 are the same eight bits output on LADD-LAD7, but in a different
order. During a series of 256 DRAM-refresh cycles, the row addresses output
on LADD-LAD7 and LAD2-LAD9 contain the same bits. Thus, if the ad-
dresses output on LADD-LAD7 cycle through all 256 row addresses then the
addresses output on LAD2-LAD9 also cycle through all 256 row addresses,
but in a different order.
11-27
Local Memory Interface Bus - Addressing Mechanisms
11.5.4 An Example - Memory Organization and Decoding
As an example, consider a memory organization based on the address decod-
ing scheme shown in Figure 11 -20. Three logical address bits (4, 21, and 26)
are used as bank-select bits. Logical address bits 5-12 are used as the 8-bit
column address, and bits 13-20 are used as the 8-bit row address. Referring
to Figure 11 -18, the row and column addresses are multiplexed out on the
same eight pins, LAD1-LAD8. The total number of address bits used to ad-
dress external memory is 19, for a total address reach of one megabyte. The
remaining address bits output by the TMS3401 0 are not used for this example.
~1f------------32-B1t Logical Addreas-----------~~
3222120191817161614131211109876
v v
Don' 8-B1t Row 8-BIt Column
Care Addreas Addreas
Bank Bank Bank
Select Select Select
BIt 2 Bit 1 BIt 0
(882) (881) (SSe)
Figure 11-20. Address Decode for Example System
Bank select bit 2 (BS2) in Figure 11-20 selects between the display memory
(BS2=O) and the system memory (8S2=1). System memory is a block of
conventional DRAM (such as the TMS4256 and TMS4C1 024) used for pro-
gram and data storage. BS2 becomes valid before RAS falls, and thus can be
used to determine whether the row-address strobe is gated to the display
memory or to the system memory. The average power dissipation is reduced
because only one or the other (the display memory or the system memory) is
enabled during a particular memory read or write cycle.
Figure 11-21 shows the structure of the display memory. Its dimensions are
1024 by 1024 at four bits per pixel. Bank select bit 1 (BS1) selects between
the top (BS1 =0) and bottom (BS1 =1) halves of the display memory. Since
BS1 becomes valid before the fall of RAS, it can be used to gate RAS to either
the upper or lower half of the display memory during a memory read or write
cycle. By transmitting the row address strobe to only half of the display me-
mory, the power dissipation for the cycle is significantly reduced.
Bank select bit 0 (BSO) selects between the even word and odd word of each
pair of adjacent words in the display memory. Each word contains four adja-
cent pixels. Odd and even words are stored in two separate banks of VRAMs,
and the decode logic gates the column address strobe to the selected bank
only. The row address strobe is gated to both banks (odd and even words).
This increases the power dissipation over that required if only one bank were
active. A compensating benefit of this organization, however, is that it reduces
the rate at which each VRAM must supply serial data to refresh the screen.
During screen refresh, the bank containing the even words and the bank con-
taining the odd words alternately provide data to the video monitor. Alter-
nating between the two banks in this fashion reduces the data bandwidth
11-28
Local Memory Interface Bus - Addressing Mechanisms
requirements of each bank to about 10M Hz, which is an eighth of the video
bandwidth.
Even Word Odd Word
(SSO = 0) (880 = 1)
/'\
(
//
/ /' /'
T
512 Unes
• l~ J
~r)
,I
512 Unes
~rfl
- - - 1 0 2 4 Pixels per Une
14'1_ -----1~-~ BIts
per Pixel
Figure 11-21. Display Memory Dimensions for the Example
The decode logic must be capable of more than just selecting a particular bank
of the display memory or system memory during a memory read or write cycle.
It must also be capable of enabling all DRAMs and VRAMs during a
DRAM-refresh cycle, and enabling all VRAMs during a screen-refresh (me-
mory-to-register) cycle. This means that the decode logic must distinguish
DRAM-refresh and screen-refresh cycles from memory access cycles, and
during a refresh cycle broadcast the row and column address strobes to all
devices that require them. The timing of the RF and TR bus status bits has
been designed to make these signals convenient for the design of the decode
logic ..
During a read or write cycle, the value of 8S2, output with the row address,
determines whether RAS is gated to the display memory or to system memory.
During a DRAM-refresh cycle, the decode logic must broadcast the row-
address strobe to all dynamic RAMs (including the VRAMs). The decode
logic must be able to determine prior to the fall of the row address strobe
whether the cycle that is beginning is a DRAM-refresh cycle, or a memory read
or write cycle. This is the reason the TMS34010 outputs the RF bus status
signal prior to the fall of RAS.
The decode logic uses the value of BS1 to determine whether the top or bot-
tom half of the display memory receives an active row-address strobe during
a memory read or write cycle. The same logic must also be capable of broad-
casting RAS to all VRAMs during either a DRAM-refresh cycle or a register-
transfer cycle. The decode logic therefore monitors the state of the
TMS3401 O's TR/OE output prior to the fall of RAS. A low level on TR/OE in-
dicates that the cycle just beginning is a register-transfer cycle, and that RAS
should be broadcast.
11-29
Local Memory Interface Bus - Addressing Mechanisms
While the decode logic uses the value of BSO to determine whether the even
or odd word receives a column-address strobe during a read or write cycle
involving the display memory, the same logic must be capable of broadcasting
CAS to all VRAMs during a screen-refresh cycle. Rather than require an ex-
ternal latch to capture the state of the TR/QE during the fall of RAS, the
TMS34010 outputs the same information a second time in the form of the TR
bus status signal, which is valid prior to and during the fall of CAS.
11-30
Section 12
TMS34010 Instruction Set
This section contains the TMS34010 instruction set (in alphabetical order).
Related subjects, such as addressing modes, are presented first.
Section Page
12.1 Style and Symbol Conventions .......................................................... 12-2
12.2 Addressing Modes and Operand Formats ........................................ 12-4
12.3 Instruction Set Summary Table ....................................................... 12-12
12.4 Arithmetic, Logical, and Compare Instructions ............................. 12-19
12.5 Move Instructions Summary ............................................................ 12-20
12.6 Graphics Instructions Summary ....................................................... 12-26
12.7 Program Control and Context Switching Instructions ................. 12-29
12.8 Shift Instructions ............................................................................... 12-32
12.9 XY Instructions ................................................................................... 12-33
12.10 Alphabetical Reference of Instructions ........................................... 12-34
12-1
Instruction Set - Style and Symbol Conventions
12.1 Style and Symbol Conventions
Table 12-1 defines symbols and abbreviations that are used throughout this
section; the list following the table describes style conventions used in the
instruction set descriptions. Section 12.2 (page 12-4) defines the symbols
that indicate various addressing modes.
Table 12-1. Instruction Set Symbol and Abbreviation Definitions
Symbol Definition Symbol Definition
Rs Source register Rd Destination register
RsX X half of source register RsY Y half of source register
RdX X half of destination register RdY Y half of destination register
An Register n in register file A Bn Register n in register file B
PC Program counter PC' PC prime, specifies the address of
Rp Pointer register the next instruction (current PC +
length of the current instruction)
ST Status Register SP Stack pointer (A15 or B15)
C Carry bit N Sign bit
V Overflow bit Z Zero bit
IE Global interrupt enable bit TOS Top of stack
SAddress Source address DAddress Destination address
SOffset Source offset DOffset Destination offset
LSB Least significant bit MSB Most significant bit
MSW Most significant word LSW Least significant word
IW 16-bit immediate value IL 32-bit immediate value
K 5- bit constant cc Condition code for a jump
F Optional field select parameter R Register file select, indicates
for MOVE instructions, which register file (A or B) the
F=O selects FSO/FEO, and operand registers are in. R=O
F=1 selects FS1/FE1 specifies register file A, R=1
specifies register file B
Program listings, coding examples, filenames, and symbol names are shown
in a special font. Some examples and listings use a bold version of
the special font for emphasis. Here is a sample program listing:
0011 00000210 0001 .field 1, 2
0012 00000212 0003 .field 3, 4
0013 00000215 0006 .field 6, 3
0014 00000220 .even
In syntax descriptions, the font indicates which parts of the syntax must
be entered as shown, and which parts act as place holders indicating the type
of information that should be entered. In addition, square brackets identify
optional parameters.
• The instruction and any part of the instruction that should be entered as
shown are in a bold face. Parameters that describe the type of infor-
mation that should be entered are in italics. Here is an example of an
instruction syntax:
12-2
Instruction Set - Style and Symbol Conventions
CVXVL Rs, Rd
CVXVL is an instruction that has two parameters, Rs and Rd Rs and Rd
are abbreviations for source register and destination register; when you
use CVXYL, these parameters must be real register names (such as AO,
B1, etc.). Applying these rules, a valid CVXYL instruction is CVXYL AO,
A3.
Another example of an instruction syntax is:
PIXBLT B,XV
In this case, B and XV do not specify values or data; they specify the
type of PIXBLT instruction, and the instruction should be entered as
shown: PIXBLT B,XY.
• Square brackets ( [ and ] ) identify an optional parameter. Here's an
example of an instruction that has an optional parameter:
CMPI IW, Rd [, W}
The CM PI instruction has three parameters. The first two parameters,
IW and Rd, indicate a 16-bit value and a destination register; these pa-
rameters are required. The third parameter, W, is optional. As this syntax
shows, if you use the optional third parameter, you must precede it with
a comma.
Each instruction contains an instruction execution field that describes the
actions that occur during instruction execution. These descriptions the fol-
lowing symbols and conventions:
• The -+ symbol means becomes the contents of. For example, Rs -+ PC
means that the contents of the source register become the contents of
the PC; that is, the contents of the source register are copied into the
PC.
• The I I symbols indicate an absolute value.
• The: symbol indicates concatenation. For example, Rd:Rd+ 1 identifies
the concatenation of two consecutive registers, such as AO and A 1.
Numeric constants such as hexadecimal, octal, and binary numbers are
identified by a letter suffix. Valid suffixes include:
• b or B (binary)
• q or Q (octal)
• h or H (hexadecimal)
Decimal constants have no suffix. Note that all constants must start with a
numeral; for example, ABCDh is an illegal constant; OABCDh is the legal form.
12-3
Instruction Set - Addressing Modes
12.2 Addressing Modes and Operand Formats
The TMS34010 instruction set supports eight addressing modes. Most in-
structions have register-direct operands or a combination of register-direct and
immediate operands; however, the move and graphics instructions use more
complex combinations of operands. This section discusses the TMS34010
addressing modes, and defines the symbols used in instruction syntax to in-
dicate an addressing mode.
12.2.1 Immediate Values and Constants
An instruction syntax may use one of these symbols to indicate an immediate
source operand:
IW is a 16-bit (short) signed immediate value.
IL is a 32-bit (long) signed immediate value.
K is a 5-bit constant.
Instructions that have immediate source operands have register-direct desti-
nation operands. Many instructions that have an immediate value can use ei-
ther a short or a long value.
Figure 12-1 illustrates a MOVI (move immediate) instruction whose first op-
erand is a 32-bit immediate value. The syntax for this MOVI is:
MOVI IL, Rd [, lJ
The instruction in Figure 12-1 is:
MOVI OFCOh, A2, L
Figure 12-1 shows the object code (at address N) in memory and the effect
of the instruction on the CPU registers. The value OFCOh is copied into reg-
ister A2 as a zero-extended 32-bit value. (Note that this is a 2-word in-
struction; the next instruction to be executed is at address N=2.)
Memory CPU Registers
/~O 31 o
15 ;'
\
r - .....
I L J AO
I I I J A1
I •••• •• A2
MOVI OFCOOh, A2,L { N+ ~ 09E2h
FCOOh ~ I l
N+2 next A14
instruction
I I
I'
60
1---------;I~pTC:4
N . PC'=N+2
Figure 12-1. An Example of Immediate Addressing
12-4
Instruction Set - Addressing Modes
12.2.2 Absolute Addresses
An instruction syntax may use one of these symbols to indicate an absolute
operand:
@SAddress is a source address that contains the source data.
@DAddress is a destination address.
Note that the @ character is entered as part of the operand (this distinguishes
it from an immediate operand).
Figure 12-2 illustrates a MOVB (move byte) instruction that has an absolute
operand (the first parameter is a 32-bit source address). The syntax for this
MOVB is:
MOVB @SAddress, Rd
The instruction in Figure 12-2 is:
MOVB @RoutineA, A13
Figure 12-2 shows the object code (at address N) in memory and the effect
of the instruction on the CPU registers. @RoutineA is the address of a byte;
this MOVB instruction copies the byte at address RoutineA into register A13.
(Note that this is a 3-word instruction; the next instruction to be executed is
at address N=3.)
Memory CPU Registers
31 o
1--------11I A~.
N 07EDh
MOVB@RoutineA, A13 N+ 1 RoutineA (MSW) r-~__I·II·I·I·II·I·IIII.._A13
{ N+2~~R-ou~ti~ne-A~(L~SW~)~ ~------------~A14
N+3~~~n~ex~t~~~ ~------------__iBO
B~4
instruction
'
RoutineA fZ~~~~~~~--_J
-----_ ... :~=~=~=~= = = =:N=:= -=-=-=-=-=-=-=-=-=-=~ E ~
I PC' N+ 3
"- ." .....
Figure 12-2. An Example of Absolute Addressing
12-5
Instruction Set - Addressing Modes
12.2.3 Register-Direct Operands
An instruction syntax may use one of these symbols to indicate a register-
direct operand:
Rs is a source register that contains the source data.
Rd is a destination register that will contain the result.
When both operands of an instruction are register-direct operands, the regis-
ters must be in the same file. (The MOVE Rs,Rd instruction is an exception
to this rule.)
Figure 12-3 illustrates a MOVE (move field) instruction that has two regis-
ter-direct operands. The syntax for this MOVE is:
MOVE Rs, Rd [, FJ
The example shows this instruction:
MOVE AO, Bl
Figure 12-3 shows the object code (at address N) in memory and the effect
of the instruction on the CPU registers. Assume that the field size for the move
is 32 bits; the entire contents of register AO are copied into register B1. (Note
that this is a 1 -word instruction; the next instruction to be executed is at ad-
dress N=1.)
CPU Registers
31 0
FCOOOCOOh AO
Memory
115_/-~ A14
80
I I 81
MOVE AO, Bl{ N 4E01h
next
I .
I~r
N+1 instruction
__I
l
'-- /"
N PC' = N+ 1
Figure 12-3. An Example of Register-Direct Addressing
12-6
Instruction Set - Addressing Modes
12.2.4 Register-Indirect Operands
An instruction syntax may use one of these symbols to indicate a register-
indirect operand:
* Rs is a register that contains the address of the source data.
* Rd is a register that contains the destination address.
Note that the * character is entered as part of the operand (this distinguishes
it from a register-direct operand).
Figure 12-4 illustrates a MOVE (move field) instruction that has two regis-
ter-indirect operands. The syntax for this MOVE is:
MOVE *Rs, *Rd
The example shows this instruction:
MOVE *A4, *A3
Figure 12-4 shows the object code (at address N) in memory and the effect
of the instruction on the destination address. The contents of register A4
specify the address of data to be moved; the contents of register A3 specify
the destination address. Assume that the field size for the move is 16 bits; the
16 bits of data at *A4 is moved to the location at *A3 .. (Note that this is a
1 -word instruction; the next instruction to be executed is at address N=1.)
Memory 0
15 ",,/,-,
r-..... ,
MOVE *A4, *A3 < N
N+1
8883h
next
31
CPU Registers
0
AO
instruction
'-- .....
" ,_ ..... )1
OOOOAOOOh
OOQOC080h
A3
1--"", A4
I '_ ..... 1 1
1 I
OOOOAOOOh
1 I
1~?4
1.
OOOOC080h __ I
,-..... /""" N
IE4 PC' = N+ 1
Figure 12-4. An Example of Register-Indirect Addressing
12-7
Instruction Set - Addressing Modes
12.2.5 Register-Indirect with Offset
An instruction syntax may use one of these symbols to indicate a register-
indirect operand that uses a signed offset:
*Rs(offset) is a source address formed by adding an offset to the contents
of the source register.
* Rd(offset) is a destination address formed by adding an offset to the
contents of the destination register.
The offset is only used to form an address - the contents of the register are
not affected. Note that the * character is entered as part of the operand. If
both operands use offsets, the syntax may list the operands as *Rs(SOffset)
or * Rd(DOffset).
Figure 12-5 illustrates a MOVE (move field) instruction; the first operand of
this instruction is a register-direct operand; the second operand is a register-
indirect operand with an offset. The syntax for this MOVE is:
MOVE Rs, *Rd(offsetj [, FJ
The example shows this instruction:
MOVE B5, *B7(32)
Figure 12-5 shows the object code (at address N) in memory and the effect
of the instruction on the destination location. The destination address is spe-
cified by adding the offset (32 bits, which is equivalent to 2 words) to the
contents of register 87; this yields a destination location of 05020h. Assume
that the field size for the move is 16 bits; the 16 LS8s in register 85 are copied
into the destination location. (Note that this is a 2-word instruction; the next
instruction to be executed is at address N=2.)
Memory
o
15 .,/--"';:
1-- \ CPU Registers
31 o
MOVE ".'.7(32).1 { N+ ~ :~~~ t--------IIA~
next 1.
N+2
~------------~1~4
instruction
I 1:
I '-. . .1 ,.---- 1234ABCDh B5
I I B6
I
00005000h
+20h I I
0OOO5000h
I
B7
'-v-'! I ~~4
1
00005020h ~:111!1'
I
SP
~=======_N-_-_-_-_-_-_---,-I PC pC' = N+ 2
Figure 12-5. An Example of Register-Indirect with Offset
Addressing
12-8
Instruction Set - Addressing Modes
12.2.6 Register-Indirect with Postincrement
An instruction syntax may use one of these symbols to indicate a register-
indirect operand that is postincremented:
* Rs+ is a register that contains the address of the source data.
* Rd+ is a register that contains the destination address.
After the operation is performed, the contents of the specified source or des-
tination register are incremented by the field size used for the operation.
Note that the * and + characters are entered as part of the operand.
Figure 12-6 illustrates a MOVE (move field) instruction; both the source and
the destination operands are postincremented register-indirect operands. The
syntax for this MOVE is:
MOVE *Rs+, *Rd+ [, FJ
The example shows this instruction:
MOVE *B4+ I *B14+
Figure 12-6 shows the object code (at address N) in memory and the effect
of the instruction on the destination location and the CPU registers. The
contents of register B4 are the address of the source data; the contents of re-
gister B14 specify the destination address. Assume that the field size for the
move is 16 bits; the 16 bits of data at the source address are copied into the
destination location. After the move, both registers are incremented by 16 bits
(1 word). (Note that this is a 1-word instruction; the next instruction to be
executed is at address N=1.)
15
Memory
,,"
_,0 CPU Registers
o
MOVE *B4+ ,*B14+ < N
N+1
r--
989Eh
next
31
~ ____--IIA~
I :
~------------------~1~4
instruction
o0 0 0 1 0 2 0 h IB4
10h"w.,.,
I--~;...;;.....::.......;.....;:;....;;...;;....;.;....---t .
~
.•.eH·.,.,W
+
After Move
I .
1---=0-::C:-:O:-:O:-:O~0::-2=-0=-=-0":'""h--t Bi 4 + 10h'E.,•.•,.,fi',iM
I--------------------~Sp
ST ~ After Move
~______~N~______~PC PC'=N+1
coo 0 0 2 0 0 h.ma.~--.J
Figure 12-6. An Example of Register-Indirect with Postincrement
Addressing
12-9
Instruction Set - Addressing Modes
12.2.7 Register-Indirect with Predecrement
An instruction syntax may use one of these symbols to indicate a register-
indirect operand that is predecremented.
Before the operation is performed, the contents of the specified source or
destination register are decremented by the field size used for the operation.
* -Rs the decremented register contents are the address of the source data.
* -Rd the decremented register contents specify the destination address.
Note that the * and - characters are entered as part of the operand.
Figure 12-7 illustrates a MOVE (move field) instruction; the source operand
is a register-direct operand the the destination operand is a predecremented
register-indirect operand. The syntax for this MOVE is:
MOVE Rs, *-Rd r FJ
The example shows this instruction:
MOVE A4, *-A3
Figure 12-7 shows the object code (at address N) in memory and the effect
of the instruction on the destination location and the CPU registers. Assume
that the field size for the move is 16 bits. Register A4 contains the source data.
The contents of register A3, minus the field size (16 bits, or 1 word) form the
destination address - 5150h. The 16 LSBs in A4 are copied to address 5150h.
(Note that this is a 1 -word instruction; the next instruction to be executed is
at address N=1.)
Memory
o
15 .,,/~' CPU Registers
MOVE A4,*A3 <
J.
N+1
N
1--
A083h
next
instruction
l
A3LI~o~o~O~O~5~1~6~O~h~
31
••••
0
IA~
A3
Before Move ABCD2222h A4
I~-
I
N
lE- PC'=N+1
Figure 12-7. An Example of Register-Indirect with Predecrement
Addressing
12-10
Instruction Set - Addressing Modes
12.2.8 Register-Indirect in XV Mode
An instruction syntax may use one of these symbols to indicate that the a re-
gister operands contains an XY address.
*Rs.XV is a register that contains the XY address of the source data.
* Rd.XV is a register that contains the XY destination address.
Note that the * and .XV characters are entered as part of the operand. Here's
an example that uses an indirect-XV destination operand:
PIXT AO, *A6.XY
This instruction moves the contents of register AO into the XY address speci-
fied by the contents of register A6.
12-11
Instruction Set - Summary Table
12.3 Instruction Set Summary Table
Arithmetic, Logical, and Compare Instructions
Machine 16-Bit Opcode
Syntax and Description Words States MSB LSB
ABSRd 1 1,4 0000 0011 100R DODD
Store absolute value
ADD Rs, Rd 1 1,4 0100 0005 SSSR DODD
Add registers
ADDC Rs, Rd 1 1,4 0100 001S SSSR DODD
Add registers with carry
ADDIIW, Rd 2 2,8 0000 1011 OOOR DODD
Add immediate (16 bits)
ADDIIL, Rd 3 3,12 0000 1011 001R DODD
Add immediate (32 bits)
ADDK K, Rd 1 1,4 0001 OOKK KKKR DODD
Add constant (5 bits)
ADDXY Rs, Rd 1 1,4 1110 0005 SSSR DODD
Add registers in XY mode
AND Rs, Rd 1 1,4 0101 OOOS SSSR DODD
AND registers
ANDIIL, Rd 3 3,12 0000 1011 100R DODD
AND immediate (32 bits)
ANON Rs, Rd 1 1,4 0101 001S SSSR DODD
AND register with complement
ANDNIIL, Rd 3 3,12 0000 1011 100R DODD
AND not immediate (32 bits)
BTST K, Rd 1 1,4 0001 11 KK KKKR DODD
Test register bit, constant
BTST Rs, Rd 1 2,5 0100 101S SSSR DODD
Test register bit, register
CLR Rd 1 1,4 0101 011 D DO DR DODD
Clear register
CLRC 1 1,4 0000 0011 0010 0000
Clear carry
CMP Rs, Rd 1 1,4 0100 100S SSSR DODD
Compare registers
CMPI/W, Rd 2 2,8 0000 101 1 010R DODD
Compare immediate (16 bits)
CMPI/L, Rd 3 3,12 0000 1011 011 R DODD
Compare immediate (32 bits)
CMPXY Rs, Rd 1 3,6 1110 010S SSSR DDDD
Compare X and Y halves of registers
DECRd 1 1,4 0001 0100 001R DDDD
Decrement register
12-12
Instruction Set - Summary Table
Arithmetic. Logical. and Compare Instructions (Continued)
Machine 16- Bit Opcode
Syntax and Description Words States MSB LSB
DIVS Rs, Rd 1 40,43 II 0101 100S SSSR DODD
Divide registers signed 39,42
DIVU Rs, Rd 1 37,40 0101 101 S SSSR DODD
Divide registers unsigned
LMO Rs, Rd 1 1,4 0110 101 S SSSR DODD
leftmost one
MODS Rs, Rd 1 40,43 0110 110S SSSR DODD
Modulus signed
MODU Rs, Rd 1 35,38 0110 111 S SSSR DODD
Modulus unsigned
MPYS Rs, Rd 1 20,23 0101 110S SSSR DODD
Multiply registers (signed)
MPYU Rs, Rd 1 21,24 0101 111 S SSSR DODD
Multiply registers (unsigned)
NEG Rd 1 1,4 0000 0011 101 R DODD
Negate register
NEGB Rd 1 1,4 0000 0011 110 R DODD
Negate register with borrow
NOTRd 1 1,4 0000 0011 111 R DODD
Complement register
OR Rs, Rd 1 1,4 0101 010S SSSR DODD
OR registers
ORIIL, Rd 3 3,12 0000 1011 101 R DODD
OR immediate (32 bits)
SETC 1 1,4 0000 1101 11 1 0 0000
Set carry
SEXT Rd, F 1 3,6 0000 01 F 1 OOOR DODD
Sign extend to long
SUB Rs, Rd 1 1,4 0100 010S SSSR DODD
Subtract registers
SUBB Rs, Rd 1 1,4 0100 011S SSSR DODD
Subtract registers with borrow
SUBI/W, Rd 2 2,8 0000 1011 111 R DODD
Subtract immediate (16 bits)
SUBIIL, Rd 3 3,12 0000 1101 OOOR DODD
Subtract immediate (32 bits)
SUBK K, Rd 1 1,4 0001 01KK KKKR DODD
S.ubtract constant (5 bits)
SUBXY Rs, Rd 1 1,4 1110 001S SSSR DODD
Subtract registers in XY mode
XOR Rs, Rd 1 1,4 0101 011S SSSR DODD
Exclusive OR registers
XORIIL, Rd 3 3,12 0000 1011 1100 DODD
Exclusive OR immediate value (32 bits)
ZEXT Rd, F 1 1,4 0000 01 F 1 001R DODD
Zero extend to long
II Rd even/Rd odd
12-13
Instruction Set - Summary Table
Move Instructions
Machine 16- Bit Opcode
Syntax and Description Words States MSB LSB
MMFM Rs [, List} 2 t 0000 1001 101 R DODD
Move multiple registers from memory
M MTM Rs {, List} 2 t 0000 1001 100R DODD
Move multiple registers to memory
MOVB Rs, *Rd 1 11' 1000 110S SSSR DODD
Move byte, register to indirect
MOVB *Rs, Rd 1 11' 1000 111 S SSSR DODD
Move byte, indirect to register
*
MOVB Rs, Rd * 1 11' 1001 110S SSSR DODD
Move byte, indirect to indirect
MOVB Rs, *Rd(offsetj 2 11' 1010 110S SSSR DODD
Move byte, register to indirect with offset
MOVB *Rs(offsetj, Rd 2 11' 1010 111 S SSSR DODD
Move byte, indirect with offset to register
* *
MOVB Rs(SOffset), Rd(DOffsetj 3 11' 1011 110S SSSR DODD
Move byte, indirect with offset to
indirect with offset
MOVB Rs, @DAddress 3 11' 0000 0101 111 R SSSS
Move byte, register to absolute
MOVB @SAddress, Rd 3 11' 0000 0111 111 R DODD
Move byte, absolute to register
MOVB @SAddress, @DAddress 5 11' 0000 0011 0100 0000
Move byte, absolute to absolute
MOVE Rs, Rd 1 1,4 0100 11MS SSSR DODD
Move register to register
*
MOVE Rs, Rd {, F} 1 11' 1000 OOFS SSSR DODD
Move field, register to indirect
MOVE Rs, -*Rd {, F}
Move field, register to indirect (predecrement)
1
'" 1010 OOFS SSSR DODD
* OOFS SSSR DODD
MOVE Rs, Rd+ {, F}
Move field, register to indirect (postincrement)
1
'" 1 001
MOVE * Rs, Rd {, F} 1 11' 1000 01FS SSSR DODD
Move field, indirect to register
MOVE -*Rs, Rd {, F} 1 11' 1010 01FS SSSR DODD
Move field, indirect (predecrement) to register
01FS SSSR DODD
MOVE *Rs+, Rd {, F}
Move field, indirect (postincrement) to register
1
'" 1 001
t See instruction
'" See Section 13.2, MOVE and MOVB Instructions Timing
12-14
Instruction Set - Summary Table
Move Instructions (Continued)
Machine 16- Bit Opcode
Syntax and Description Words States MSB LSB
MOVE *Rs, *Rd FJ r 1 11' 1000 10FS SSSR DODD
Move field, indirect to indirect
MOVE -*Rs, -*Rd [, FJ 1 11' 1010 10FS SSSR DODD
Move field, indirect (predecrement) to
indirect (predecrement)
MOVE * Rs+, * Rd+ [, FJ 1 11' 1001 10FS SSSR DODD
Move field, indirect (postincrement) to
indirect (postincrement)
MOVE Rs, * Rd(offset) [, FJ 2 11' 1011 OOFS SSSR DODD
Move field, register to indirect with offset
MOVE *Rs(offset), Rd [, FJ 2 11' 1011 01FS SSSR DODD
Move field, indirect with offset to register
MOVE *Rs(offset), *Rd+ [, FJ 2 11' 1101 OOFS SSSR DODD
Move field, indirect with offset to
indirect (postincrement)
MOVE * Rs(SOffset), * Rd(DOffset) [, FJ 3 11' 1011 10FS SSSR DODD
Move field, indirect with offset to
indirect with offset
MOVE Rs, @DAddress [, FJ 3 11' 0000 01 F 1 100R SSSS
Move field, register to absolute
MOVE @SAddress, Rd [, FJ 3 11' 0000 01 F1 101 R DODD
Move field, absolute to register
MOVE @SAddress, * Rd+ [, FJ 3 11' 1101 01FO OOOR DODD
Move field, absolute to indirect (postincrement
MOVE @SAddress, @DAddress [, FJ 5 11' 0000 01 F 1 1100 0000
Move field, absolute to absolute
MOVI/W, Rd 2 2,8 0000 1001 110 R DODD
Move immediate (16 bits)
MOVIIL, Rd 3 3,12 0000 1001 111 R DODD
Move immediate (32 bits)
MOVKK, Rd 1 1,4 0001 10KK KKKR DODD
Move constant (5 bits)
MOVX Rs, Rd 1 1,4 1110 110S SSSR DODD
Move X half of register
MOVY Rs, Rd 1 1,4 1110 111 S SSSR DODD
Move Y half of register
t See instruction
11' See Section 13.2, MOVE and MOVB Instructions Timing
12-15
Instruction Set - Summary Table
Graphics Instructions
Machine 16-Bit Opcode
Syntax and Description Words States MSB LSB
CPW Rs, Rd 1 1.4 1110 0115 555R DODD
Compare point to window
CVXVLRs, Rd 1 3,6 1110 1005 55SR DODD
Convert XV address to linear address
DRAV Rs, Rd 1 t 1111 0115 SSSR DODD
Draw and advance
FILL L 1 + 0000 1111 1100 0000
Fill array with processed pixels, linear
FILL XV 1 + 0000 111 1 1110 0000
Fill array with processed pixels, XV
LINE [0. 1] 1 t 1101 1111 Z001 1010
Line draw
PIXBLT B. L 1 ++ 0000 111 1 1000 0000
Pixel block transfer, binary to linear
PIXBLT B. XV 1 ++ 0000 1111 1010 0000
Pixel block transfer and expand, binary to XV
PIXBLT L. L 1 § 0000 1 11 1 0000 0000
Pixel block transfer, linear to linear
PIXBLT L. XV 1 § 0000 11 1 1 0010 0000
Pixel block transfer, linear to XV
PIXBLT XV, L 1 § 0000 1111 0100 0000
Pixel block transfer, XV to linear
PIXBLT XV, XV 1 § 0000 1 1 1 1 0110 0000
Pixel block transfer, XV to XV
PIXT Rs, *Rd 1 t 1111 1005 SSSR DODD
Pixel transfer, register to indirect
*
PIXT Rs, Rd.XY 1 t 1111 OOOS SSSR DODD
Pixel transfer, register to indirect XV
PIXT *Rs, Rd 1 t 11 1 1 101S SSSR DDDD
Pixel transfer, indirect to register
*
PIXT Rs, Rd * 1 t 11 1 1 1105 5SSR DODD
Pixel transfer, indirect to indirect
*
PIXT Rs.XY, Rd 1 t 1111 001S SSSR DODD
Pixel transfer, indirect XV to register
*
PIXT Rs.XY, Rd.XY * 1 t 11 1 1 010S SSSR DODD
Pixel transfer, indirect XV to indirect XV
t See instruction
+ See Section 13.3, FILL Instructions Timing
++ See Section 13.5, PIXB LT Expand Instructions Timing
§ See Section 13.4, PIXBLT Instructions Timing
12-16
Instruction Set - Summary Table
Program Control and Context Switching Instructions
Machine 16- Bit Opcode
Syntax and Description Words States MSB LSB
CALL Rs 1 3+(3),9 0000 1001 001 R DODD
Call subroutine indirect 3+(9),150
CALLA Address 3 4+(2),15 0000 1101 0101 1111
Call subroutine address 4+(8),21 0
CALLR Address 2 3+(2),11 0000 1101 0011 1111
Call subroutine relative 3+(8),1r0
DINT 1 3,6 0000 0011 0110 0000
Disable interrupts
EINT 1 3,6 0000 1101 0110 0000
Enable interrupts
EMU 1 6,9 0000 0001 0000 0000
Initiate emulation
EXGF Rd, F 1 1,4 1101 01 F1 OOOR DODD
Exchange field size
EXGPC Rd 1 2,5 0000 0001 001 R DODD
Exchange program counter with register
GETPC Rd 1 1,4 0000 0001 010R DODD
Get program counter into register
GETST Rd 1 1,4 0000 0001 100R DODD
Get status register into register
NOP 1 1,4 0000 0011 0000 0000
No operation
POPST 1 8,11 0000 0001 1100 0000
Pop status register from stack 10,130
PUSHST 1 2+(3),8 0000 0001 111 0 0000
Push status register onto stack 2+(8),130
PUTST Rs 1 3,6 0000 0001 101 R DODD
Copy register into status
RETI 1 11,1~ 0000 1001 0100 0000
Return from interrupt 15,1
RETS [NJ 1 7,1~ 0000 1001 011 N NNNN
Return from subroutine 9,1
REV Rd 1 1,4 0000 0000 001R DODD
Find TMS3401 0 revision level
SETF FS, FE, F 1 1,4 0000 01 F 1 01FS SSSS
Set field parameters 2,5 :I:
TRAPN 1 16,19 0000 1001 OOON NNNN
Software interrupt 0
30,33-
t See instruction
e First values for SP aligned, second values for SP nonaligned
12-17
Instruction Set - Summary Table
Jump Instructions
Machine 16-Bit Opcode
Syntax and Description Words States MSB LSB
DSJ Rd, Address 2 3,9 n 0000 1101 100R DODD
Decrement register and skip jump 2,8
DSJEQ Rd, Address 2 3,9 n 0000 1101 101 R DODD
Conditionally decrement register and 2,8
skip jump
DSJNE Rd, Address 2 3,9 n 0000 1101 110 R DODD
Conditionally decrement register and 2,8
skip jump
DSJS Rd, Address \
1 2,5 n 0011 lDxx xxxR DODD
Decrement register and skip jump short 3,6
JAcc Address 3 3,6 n 1100 code 1000 0000
Jump absolute conditional 4,7
JRcc Address 2 3,6 n 1100 code 0000 0000
Jump relative conditional 1,4
JRcc Address 1 2,5 n 1100 code xxxx xxxx
Jump relative conditional short 2,5
JUMP Rs 1 2,5 0000 0001 011R DODD
Jump indirect
Shift Instructions
Machine 16-Bit Opcode
Syntax and Description Words States MSB LSB
RLK, Rd 1 1,4 0011 OOKK KKKR DODD
Rotate left, constant
RL Rs, Rd 1 1,4 0110 100S SSSR DODD
Rotate left, register
SLAK, Rd 1 3,6 0010 OOKK KKKR DODD
Shift left arithmetic, constant
SLARs, Rd 1 3,6 0110 OOOS SSSR DODD
Shift left arithmetic, register
SLLK, Rd 1 1,4 0010 01KK KKKR DODD
Shift left logical, constant
SLL Rs, Rd 1 1,4 0110 001S SSSR DODD
Shift left logical, register
SRAK, Rd 1 1,4 0010 10KK KKKR DODD
Shift right arithmetic, constant
SRARs, Rd 1 1,4 0110 010S SSSR DODD
Shift right arithmetic, register
SRLK, Rd 1 1,4 0010 11 KK KKKR DODD
Shift right logical, constant
SRL Rs, Rd 1 1,4 0110 011S SSSR DODD
Shift right logical, register
n First values for jump, second values for no jump
12-18
Instruction Set - Arithmetic, Logical, and Compare Instructions
12.4 Arithmetic, Logical, and Compare Instructions
The TMS3401 0 supports a full range of arithmetic, logical, and compare in-
structions. Most of these instructions use register-direct operands; some use
a combination of immediate and register-direct operands. Some instructions
have several versions; each uses a different operand format. For example, the
ADD instruction has several versions:
• The ADD instruction uses register-direct operands for both the source
and destination operands.
• The ADDI instruction uses an immediate source with a destination reg-
ister.
• The ADDK instruction uses a 5-bit constant as the source operand with
a destination register.
• The ADDXV instruction is similar to the ADD instruction - both oper-
ands are register-direct operands - however, the registers contain XY
values.
Some instructions that have immediate values as source operands (such as the
ADDI instruction) have two forms: a short form and a long form. In the short
form, the source operand is a 16-bit immediate value and the instruction oc-
cupies two words. In the long form, the source operand is a 32-bit immediate
value and the instruction occupies three words. Each form of the instruction
has an optional third operand: W for short and L for long. If you don't use the
W or L operand, the assembler chooses the short or the long form, depending
on the size of the source operand. Using W or L forces the assembler to use
the short or long form, respectively. If you use Wand the source value is
greater than 16 bits, the assembler discards all but the 16 LSBs and issues a
warning message. If you use L and the source value is less than 32 bits, the
assembler sign-extends the value to 32 bits.
Some instructions that use immediate operands have only one version. In this
case, the operand is long (32-bits).
Note:
When an instruction's source and destination operands are both regis-
ter-direct operands, the registers must be in the same file. (The MOVE
Rs, Rd instruction is an exception to this rule.)
12-19
Instruction Set - Move Instructions
12.5 Move Instructions Summary
The TMS3401 0 supports a variety of move instructions, allowing you to move
immediate values into registers, move data between registers, and move data
between registers and memory. Table 12-2 summarizes the various types of
move instructions.
Table 12-2. Summary of Move Instructions
Move Type Mnemonic Description
Register MOVE Move register to register
Constant MOVK Move constant (5 bits)
MOVI Move immediate (16 bits)
MOVI Move immediate (32 bits)
XY MOVX Move 16 LSBs of register (X half)
MOVY Move 16 MSBs of register (Y half)
Multiple register MMFM Move multiple registers from memory
MMTM Move multiple registers to memory
Byte MOVB Move byte (8 bits, 9 addressing modes)
Field MOVE Move field to/from memory/register
(15 addressing modes)
12.5.1 Register-to-Register Moves
The MOVE Rs,Rd instruction is a register-to-register move; it moves a full 32
bits of data between any two general-purpose registers. This is the only
MOVE instruction that allows you to move data between register files A and
B.
12.5.2 Value-to-Register Moves
The MOVI and MOVK instructions move immediate values into registers.
MOVK moves a zero-extended value into a register; the value must be in the
range of 1 to 32. The MOVI instruction has two forms; it can move a 16-bit
or a 32-bit immediate value.
12.5.3 XV Moves
The MOVX and MOVY instructions move values into the 16 LSBs or 16
MSBs, respectively, of a register.
12-20
Instruction Set - Move Instructions
12.5.4 Multiple-Register Moves
The MMTM and MMFM instructions use register-direct operands. MMTM
allows you ,to save several register values in memory; MMFM allows you to
retrieve register values from memory. Both instructions have two types of
operands:
• The Rp operand is a register pointer. For the M MTM instruction, Rp
contains the memory address where MMTM stores the register values.
For the MMFM instruction, Rp contains the memory address from which
MMFM loads the stored register values.
• The register list operand is an optional list of registers. It specifies which
registers are stored or retrieved, and also indicates the storing or retrieval
order.
Note that Rp and all the registers in the list must be in the same register file.
12.5.5 Byte Moves
The MOVe instruction is a special form of the MOVE instruction; when you
use MOVB, the field size is restricted to 8 bits. MOVB supports nine combi-
nations of operand formats. There are three basic combinations:
• Register to memory (requires a field insertion),
• Memory to register (requires a field extraction), and
• Memory to memory (requires both field insertion and extraction).
Note that the MOVB instruction does not move data between registers.
The MOVB instruction allows a byte to begin on any bit boundary in memory.
The byte's memory address points to the LS B of the byte. When a byte is
moved into a register, the byte's LSB coincides with the register's LSB; the
byte is sign-extended into the 24 MSBs of the register.
Table 12-3 lists the valid combinations of operand formats for the MOVB in-
struction.
Table 12-3. Summary of Operand Formats for the MOVe
Instruction
Destination
Source Rd *Rd * Rd(DOffset @DAddress
Rs J J J
*Rs J J
* Rs(SOffset) J J
/
@SAddress 'V J
Sequences of byte moves are more efficient if the byte addresses are aligned
on even 8-bit boundaries. Twice as many memory cycles are required to ac-
cess a byte that straddles a word boundary.
12-21
Instruction Set - Move Instructions
12.5.6 Field Moves
The MOVE instruction supports eighteen combinations of operand formats.
There are four basic combinations:
• Register to register,
• Register to memory,
• Memory to register, and
• Memory to memory.
The MOVE instruction moves a field. A field is a configurable data structure
that is identified by its starting address and its length. Field lengths can range
from 1 to 32 bits. A field's memory address points to the LS B of the field; the
field occupies contiguous bits. A field in a register is right-justified within the
register; the field's LSB coincides with the register's LSB.
Note that a" forms of the MOVE instruction have an optional F parameter.
(MOVE Rs,Rd is an exception to this; it doesn't have an F parameter because
it always moves 32 bits.) F selects the field size and field extension for the
MOVE:
• If F=O, FSO and FEO determine the field size and extension.
• If F=1, FS1 and FE1 determine the field size and extension.
If you don't specify 0 or 1, 0 is used as the default. The selected field size
determines the size of the field that is moved. A moved field is either sign-
extended or zero-extended, depending on the value of the appropriate field
extension bit. You can use the SETF instruction to set the field size and ex-
tension.
Table 12-4 summarizes the valid combinations of operand formats for the
MOVE instruction.
Table 12-4. Summary of Operand Formats for the MOVE Instruction
Destination
Source Rd *Rd *Rd+ -*Rd * Rd(DOffset\ @DAddress
Rs J J J J J J
*Rs J J
*Rs+ J J
-*Rs J J
* Rs(SOffset) J J J
@SAddress J J J
12-22
Instruction Set - Move Instructions
12.5.6.1 Register-fa-Memory Field Moves
Figure 12-8 illustrates the register-to-memory move operation. In this type
of move, the source register contains the right-justified field data (width is
specified by the field size). The destination location is the bit position pointed
to by the destination memory address. The address consists of a portion de-
fining the starting word in which the field is to be written and an offset into
that word, the bit address. Depending on the bit address within this word and
the field size, the destination location may extend into two or more words.
Move from Register to Memory
31 4 3 0
Destination Memory Addr888 I..______w_o_r_d_A_dd_r_888_ _ _ _ _ _.......I...:.:,:Ad::.;r::.;re::.;88=--.111
31 0
Source Register
~ A~DaIa~
I+---; Reid Size
Word Addre.. + 18 \ ~rJr'" \
Dest~natlon Memory Location
Reid Size =1 to 32 bits
Figure 12-8. Register-to-Memory Moves
12-23
Instruction Set - Move Instructions
12.5.6.2 Memory-to-Register Field Moves
Figure 12-9 shows the memory-to-register move operation. The source me-
mory location is the bit position pointed to by the source address. The address
consists of a portion defining the starting word in which the field is to be
written and an offset into that word, the bit address. Depending on the bit
address Within this word and the field size, the source location may extend
into two or more words. After the move, the destination register LSBs contain
the right-justified field data (width is specified by the field size). The MSBs
of the register contain either all 1s or all Os.
Move from Memory to Register
31 4 3 0
Source Memory Addr888 1______w_o_rd_Ad_dr_888_ _ _ _ _ _'"""'-,~Ad::;r;;.re::;88-....,,1
...
Source Memory Location
0
DestInation Register, FE=O Field Data I
SlglBIt
31 0
DestInation Register, FE=1 14 Sign BIt
~ Field Data
I
Field IIze =1 to 32 bits
Figure 12-9. Memory-to-Register Moves
12-24
Instruction Set - Move Instructions
12.5.6.3 Memory-to-Memory Field Moves
Figure 12-10 shows a memory-to-memory field move operation. The source
memory location is the bit position pointed to by the source address. The
destination location is the bit position pointed to by the destination memory
address. Depending on the bit addresses within the respective words and the
field size, either the source location or destination locations may extend into
two or more words. After the move, the destination location contains the field
data from the source memory location.
Move from Memory to Memory
31 4 3 0
Souroe Memory Address Word Address A
Word Addreaa A+16
Souroe Memory Looatlon
31
DestInation Memory Address
Word Address 8+16 Word Addr•• B " \
15 o
Destination Memory Looatlon
Destination
- t M - - - BIt Addre.----tI
Field size = 1 to 32 bits
Figure 12-10. Memory-to-Memory Moves
12-25
Instruction Set - Graphics Instructions
12.6 Graphics Instructions Summary
The TMS3401 0 instruction set supports several fundamental graphics drawing
operations.
12.6.1 Comparing a Point to a Window
The CPW instruction compares a point to the window limits defined by the
WSTART and WEND registers. The source operand Rs contains an XY ad-
dress. After the compare operation is performed, bits 5-8 contain a code that
indicate the point's location with respect to the window limits. The de-
scription of the CPW instruction shows these point codes.
12.6.2 Converting an XV Address to a Linear Address
The CVXVL instruction converts an XY address to a 32-bit linear address. The
source register contains the XY address; the linear address is put in the desti-
nation register.
12.6.3 Drawing a Pixel and Advancing to the Next Pixel Address
The DRAV instruction draws the pixel value in the COLOR1 register to the
XY address specified by the destination register. After the pixel is drawn, the
Y half of Rs is added to the Y half of Rd, and the X half of Rs is added to the
X half of Rd.
12.6.4 Draw a Line
The LINE instruction performs the inner loop of Bresenham's line-drawing
algorithm to draw an arbitrarily oriented, straight line. The optional operand
may be a 0 or a 1; this selects one of two algorithms. The default for this op-
erand is O.
12.6.5 Filling a Pixel Block
The FILL instruction fills a two-dimensional pixel array with the value in the
COLOR1 register. Note that L and XV are not actually operands; they are part
of the instruction mnemonic, identifying the form of the FILL instruction. FILL
L specifies that the array has a linear starting address; FI LL XY specifies that
the array has an XY starting address.
12-26
Instruction Set - Graphics Instructions
12.6.6 Moving a Single Pixel
The PIXT instruction transfers a pixel from one location to another. PIXT can
transfer a pixel:
• From a register to memory,
• From memory to a register, or
• From memory to memory.
Table 12-5 summarizes the valid combinations of operand formats for the PIXT
instruction. Note that all addresses are linear unless the operand is suffixed
with .XV.
Table 12-5. Summary of Operand Formats for the PIXT Instruction
Destination Pixel
Source Rd *Rd *Rd.XV
Pixel
Rs J J
*Rs J J
*Rs.XV J J
12.6.7 Moving a Two-Dimensional Block of Pixels
The PIXBLT instruction moves a two-dimensional block of pixels from one
memory location to another. Note that B, L, and XV are not actually
operands; instead, they identify the source or destination array starting ad-
dresses as binary, linear, or XV addresses. The source and destination ad-
dresses of the arrays are designated by the SADDR and DADDR registers,
respectively.
Table 12-6 summarizes the various combinations of pixel block transfers.
Table 12-6. Summary of Array Types for the PIXBLT Instruction
Destination Array
Source Linear XV
Array
Binary J J
Linear J J
XV J J
The graphics instructions use the B-file registers and several I/O registers as
implied operands. These registers must be loaded with appropriate values
before the instruction is executed. The TMS3401 0 obtains information from
these registers during instruction execution. Table 12-7 summarizes the im-
plied operands that are used by the graphics instructions. The TMS34010
User's Guide contains a complete discussion of these registers and describes
the types of information they should contain.
12-27
Instruction Set - Graphics Instructions
12.6.8 Implied Operands
The graphics instructions require additional information that you supply by
loading appropriate values into specific B registers and I/O registers. When
these registers are used for this purpose, they are called implied operands.
Section 5 discusses the functions of B registers as implied operands; Section
5 discusses the functions of I/O registers as implied operands.
Note that the LINE instruction uses registers B1 o-B13 as implied operands;
as implied operands, these registers have the following functions:
B10: COUNT register B12: INC2 register
B11: INC1 register B13: PATTRN register
Table 12-7 identifies the implied operands that each graphics instruction uses.
Table 12-7. Implied Operands Used by Graphics Instructions
~:
}::::::::::::::: Changed by instruction execution t Changed as a result of common rectangle func-
J Used; no particular format tion with window hit operation (W=1)
XY Register is in XY format (1) CONTROL bits used: PP, W, T
L Register is in linear format (2) CONTROL bits used: PP, T
P Register is in pixel format (3) CONTROL bits used: pp, W, T, PBH, PBV
pat Register is in pattern format (4) CONTROL bits used: pp, T, PBH, PBV
(5) Used when PBV=1
12-28
Instruction Set - Program Control and Context Switching Instructions
12.7 Program Control and Context Switching Instructions
The TMS34010 supports a variety of instructions that allow you to control
program flow and to save and restore information by letting you:
• CaH and return from subroutines,
• Enable or disable interrupts,
• Set software interrupts,
• Set, save, or restore status information, and
• Use jump instructions to redirect program flow.
Most of these instructions use register-direct or absolute operands; however,
several of them have no operands.
12.7.1 Subroutine Calls and Returns
The TMS3401 0 allows you to call a subroutine in three ways:
• Indirectly, by loading an address into a register;
• Directly, by using an absolute address; and
• Relatively, by specifying an address that is an offset.
These CALL instructions automatically save status information on the stack.
The RETS (return from subroutine) instruction pops status information off of
the stack and returns control to the program or routine that called the sub-
routine.
12.7.2 Interrupt Handling
The TMS3401 O's EINT and DINT instructions allow you to enable or disable
hardware interrupts by providing control of the IE (global interrupt enable)
status bit. The TMS3401 0 also supports a TRAP instruction that provides you
with control over 32 software interrupts.
12.7.3 Setting, Saving, and Restoring Status Information
Although some instructions automatically save or restore status information,
you will often want explicit control over these functions. The TMS34010
supports several instructions that allow you to save and restore PC and ST
information. The TMS3401 0 also supports a SETF instruction that allows you
to set field-0/field-1 information in the status register.
12-29
Instruction Set - Program Control and Context Switching Instructions
12.7.4 Jump Instructions
The TMS34010 supports both conditional and unconditional jumps. The
conditional jumps use absolute operands or a combination of register-direct
and absolute operands.
• There are four DSJ instructions:
DSJ and DSJS decrement the contents of a register and jump to
the specified address if the new contents of Rd do not equal o. If
Rd is decremented to 0, then execution continues with the next
instruction.
DSJ provides a jump range of -32,768 to +32,767 words; DSJS
provides a jump range of ±32 words (excluding 0).
The operation of DSJ EO and DSJ N E depends on the value of the
Z (zero) status bit.
DSJEO decrements the contents of Rd when Z=1 and jumps to
the specified address if the new contents of Rd do not equal O. If
Rd is decremented to 0, then execution continues with the next
instruction. If Z=O, DSJEQ skips the jump and execution contin-
ues with the next instruction.
DSJNE decrements the contents of Rd when Z=O and jumps to
the specified address if the new contents of Rd do not equal O. If
Rd is decremented to 0, then execution continues with the next
instruction. If Z=O, DSJNE skips the jump and execution contin-
ues with the next instruction.
The address specified for the DSJ instructions is relative; the assembler
uses this address automatically to calculate a displacement, and then it
inserts the displacement into the instruction.
• The JUMP instruction is unconditional. The source register contains
the address for the jump.
• The conditional jump instructions, JAee and J Ree, use the condition
codes listed Table 12-8.
The J Ree instruction has a long and a short form. The short form sup-
ports a jump range of ±127 words (excluding 0). The long form sup-
ports a jump range of ±32K words (excluding 0).
The 32-bit address specified for the JAee instruction is absolute; the assembler
inserts this address into words 2 and 3 of the instruction. The address speci-
fied for the JRee instructions is relative; the assembler uses this address auto-
matically to calculate a displacement, and then it inserts the displacement into
the instruction. The short form has an 8-bit displacement that is inserted into
bits 0-7 of the opcode; the opcode is 1 word long. The long form has 16-bit
displacement; the opcode is 2 words long, and the displacement occupies the
entire 16 bits of the second word.
Table 12-8 lists the condition codes used with the J Ree and JAee in-
structions. (To use the codes, replace the ee with the appropriate mnemonic
code; for example, JRUC, JALS, JRYGT, etc.) Before using one of these jump
instructions, use the CMP, CMPI, or CMPXY instruction; the compare in-
structions set the condition codes for the jump by subtracting a source value
12-30
Instruction Set - Program Control and Context Switching Instructions
from a destination value. The first mnemonics code column in Table 12-8 lists
the codes that can be used for a jump following a CMP or CMPI. The second
mnemonics code column list codes that can be used for a jump following a
CMPXY (codes that are preceded with an X can be used with the result of the
X comparison and codes that are preceded with a Y can be used with the result
of the Y comparison).
Table 12-8. Condition Codes for JRcc and JAcc Instructions
Mnemonic
Code Result of Compare Status Bits Code
Unconditional
Compares
UC - Unconditional don't care 0000
Unsigned La (C) - Dst lower than Src C 0001
Compares LS YLE Dst lower or same as Src C+Z 0010
HI YGT Dst higher than Src CoZ 0011
HS (NC) - Dst higher or same as Src C 1001
EO (Z) - Dst = Src Z 1010
NE (NZ) - Dst ¢ Src Z 1011
Signed LT XLE Dst < Src (N o_V) +_( NoV) 0100
Compares LE - Dst S Src (N 0V_+ (N __V).± Z _ 0110
GT - Dst > Src (N 0 V Z) + ( £:! y.. Z)
0 0 0 0111
GE XGT Dst > Src (N V) + (N
0 V) 0 0101
EO (Z) - Dst ~ Src Z 1010
NE (NZ) - Dst ¢ Src Z 1011
Compare to Z YZ Result = zero Z 0101
Zero NZ YNZ Result ¢ zero Z 1011
P - Result is positive NoZ 0001
N XZ Result is negative N 1110
NN XNZ Result is nonnegative N 1111
General Z YZ Result is zero Z 1010
Arithmetic NZ YNZ Result is nonzero Z 1011
C YN Carry set on resu It C 1000
NC YNN No carryon result C 1001
B (C) - Borrow set on result C 1000
NB (NC) - No borrow on result C 1001
vt XN Overflow on result V 1100
NVt XNN No overflow on result V 1101
Note: A mnemonic code in parentheses is an alternate code for the preceding code.
t Also used for window clipping
+ Logical OR
o Logical AN D
Logical NOT
12-31
Instruction Set - Shift Instructions
12.8 Shift Instructions
The TMS3410 supports several instructions that left-rotate, left-shift, or
right-shift the contents of the destination register. These instructions use re-
gister-direct operands or a combination of register-direct and immediate op-
erands; the shift amount is specified by the value of a 5-bit constant or by the
value specified in the 5 LSBs of a source register. (Note that the SRA Rs, Rd
and SRL Rs, Rd use the 2s complement value of the 5 LSBs in Rs.)
• The RL instruction left-rotates the contents of the destination register
by. (This rotation is a barrel shift.) The bits shifted out of the MSB are
shifted into the LSB. The C (carry) bit is set to the final value shifted
out of the MSB.
• The SLA instruction left shifts the contents of the destination register.
Os are shifted into the LSBs. The MSBs are shifted out through the C
(carry) bit so that the C bit is set to the final value shifted out of the
MSB. If either the N (sign) bit or any of the bits shifted out differ from
the original sign bit, the V (overflow) bit is set.
• The SLL instruction left shifts the contents of the destination register.
Os are shifted into the LSBs. The MSBs are shifted out through the C
(carry) bit so that the C bit is set to the final value shifted out of the
MSB. The main difference between SLL and SLA is that SLL does not
check to see if the sign bit changes.
• The SRA instruction right shifts the contents of the destination register.
The value of the sign bit is shifted into the MSBs; this sign-extends the
value and preserves the original value of the sign bit. The LSBs are
shifted out through the C (carry) bit so that the C bit is set to the final
value shifted out of the LSB.
• The SRL instruction right shifts the contents of the destination register.
Os are shifted into the MSBs, beginning with bit 31. The LSBs are
shifted out through the C (carry) bit so that the C bit is set to the final
value shifted out of the LSB. The main difference between SRL and SRA
is that SRL does not preserve the original value of the sign bit.
12-32
Instruction Set - XV Instructions
12.9 XV Instructions
The TMS3401 0 allows you to use XV addresses. This is useful for specifying
pixel addresses on the screen. Many of the graphics instructions use XV ad-
dressing; the TMS34010 instruction set also supports several other in-
structions that allow you to manipulate XV addresses.
An XV address is a 32-bit address that is divided into two parts. The 16 LSBs
of the address are the X half of the address or register; the 16 MSBs of the
address are the V half of the address or register. The two parts are treated as
completely separate values; for example, using the ADDXV instruction, the X
half does not propagate into the V half.
Table 12-9 summarizes the instructions that use XV addresses.
Table 12-9. Summary of XV Instructions
Instruction Description Instruction Description
ADDXY Rs, Rd Add registers in XV PIXBLT B,XY Pixel block transfer
(binary to XV)
CPW Rs, Rd Compare point to window PIXBLT L, XV Pixel block transfer
(linear to XV)
CMPXY Rs, Rd Compare registers in XV PIXBLT XV, L Pixel block transfer (XV
mode to linear)
CVXVL Rs, Rd Convert XV address to PIXBLT XV, XV Pixel block transfer (XV
linear address to XV)
DRAV Rs, Rd Draw and advance PIXT Rs, *Rd.XY Pixel transfer (register to
indirect XV)
FILL XV Fill array with processed PIXT *Rs.XV, Rd Pixel transfer (indirect XV
pixels to register)
LINE [0, 1] Line draw with XV PIXT * Rs.XV, * Rd.XV Pixel transfer (indirect XV
addressing to indirect XV)
MOVX Rs, Rd Move X half of Rs to X SUBXV Rs, Rd Subtract registers in XV
half of Rd mode
MOVV Rs, Rd Move V half of Rs to V
half of Rd
• The PIXBlT and Fill instructions in Table 12-9 use XV source and/or
destination addresses.
• The PIXT instructions in Table 12-9 use the contents of registers as XV
addresses.
• The LINE instruction draws a line along points that are calculated as XV
addresses.
• The move instructions in Table 12-9 (MOVX and MOVV) move the X
or Y half of a source register into the X or Y half of a destination register.
• The arithmetic and logical instructions in Table 12-9 (ADDXY, SU BXY,
and eM PXV) add, subtract, or compare the X and V halves of the regis-
ters separately.
12-33
Instruction Set - Alphabetical Reference
12.10 Alphabetical Reference of Instructions
The remainder of this section is an alphabetical reference of the TMS34010
assembly language instructions. Each instruction discussion begins on a new
page, and contains the following information:
• Syntax: Shows you how to enter an instruction. (Section 12.1, page
12-2, describes the symbols used in instruction syntaxes.)
• Execution: Illustrates the effects of instruction execution on CPU reg-
isters and memory.
• Instruction Words: Shows the object code generated by an in-
struction.
• Description: Discusses the purpose of the instruction and any other
general information related to the instruction.
• Machine States: Lists the instruction cycle timing. Two timings are
listed for each instruction; the first number is the cache-enabled case, the
second number is the cache-disabled case.
• Status Bits: Lists the effects of instruction execution on the status bits
(N, C, Z, and V).
• Examples: Show the effects of the instruction on memory and registers
using various sets of data and initial conditions.
Several instructions discuss additional topics; for example, the conditional
jump instructions list the conditions codes and mnemonics for various jumps,
and the graphics instructions list the implied operands that they use.
12-34
Store Absolute Value ABS
Syntax ABS Rd
Execution IRdl -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I 0 0 0 0 0 0 0 o IR Rd I
Description ABS stores the absolute value of the contents of the destination register
back into the destination register. This is accomplished by:
• Subtracting the contents of the destination register data from 0 and
• Storing the result back into Rd if status bit N indicates that the result
is positive.
If the result of the subtraction is negative, then the original contents of the
destination register are retained.
Machine
States 1,4
Status Bits N Set to the sign of the result of 0 - Rd; typically, N =0 if the original
contents of Rd are negative (unless Rd = 80000000h), 1 otherwise
C Unaffected
Z 1 if the original data is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise; an overflow occurs if Rd contains
80000000h (80000000h is returned)
Examples Code Before After
A1 NCZV A1
ABS Al 7FFFFFFFh 1xOO 7FFFFFFFh
ABS Al FFFFFFFFh OxOO 00000001h
ABS Al 80000000h 1 x01 80000000h
ABS Al 80000001h OxOO 7FFFFFFFh
ABS Al 00000001h 1xOO 00000001h
ABS Al OOOOOOOOh Ox10 OOOOOOOOh
ABS Al FFFA0011h OxOO 0005FFEFh
12-35
ADD Add Registers
Syntax ADD Rs, Rd
Execution Rs + Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 0 0 0 01 Rs 1R Rd I
Description ADD adds the contents of the source register to the contents of the desti-
nation register, and stores the result in the destination register.
You can is the ADD instruction with the ADDC instruction to perform
multiple-precision arithmetic.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a carry, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
A1 AO NCZV AO
ADD Al,AO FFFFFFFFh FFFFFFFFh 1100 FFFFFFFEh
ADD Al,AO FFFFFFFFh 00000001h 0110 OOOOOOOOh
ADD Al,AO FFFFFFFFh 00000002h 0100 00000001h
ADD Al,AO FFFFFFFFh 80000000h 0101 7FFFFFFFh
ADD Al,AO FFFFFFFFh 80000001h 1100 80000000h
ADD Al,AO 7FFFFFFFh 80000001h 0110 OOOOOOOOh
ADD Al,AO 7FFFFFFFh 80000000h 1000 FFFFFFFFh
ADD Al,AO 7FFFFFFFh 00000001h 1001 80000000h
ADD Al,AO 00000002h 00000002h 0000 00000004h
12-36
Add Register with Carry ADDC
Syntax ADDC Rs, Rd
Execution Rs + Rd + C -+ Rd
Instruction
Words 15 14 ,13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 Rs R Rd
Description ADDC adds the contents of the source register, the carry bit, and the con-
tents of the destination register, and then stores the result in the destination
register. Note that the status bits are set on the final result.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a carry, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
C A1 AO NCZV AO
ADDC Al,AO 1 FFFFFFFFh FFFFFFFFh 1100 FFFFFFFFh
ADDC Al,AO 1 FFFFFFFFh 00000001h 0100 0OOOOO01h
ADDC Al,AO 1 FFFFFFFFh 00000002h 0100 0OOOOO02h
ADDC Al,AO 1 FFFFFFFFh 80000000h 1100 80000000h
ADDC Al,AO 1 FFFFFFFFh 80000001h 1100 80000001h
ADDC Al,AO 1 FFFFFFFFh 80000001h 0100 80000001h
ADDC Al,AO 1 FFFFFFFFh 80000000h 0110 OOOOOOOOh
ADDC Al,AO 1 7FFFFFFFh 00000001h 1001 80000001h
ADDC Al,AO 1 000OOO02h 00000002h 0000 0OOOOO05h
ADDC Al,AO 0 FFFFFFFFh FFFFFFFFh 1100 FFFFFFFEh
ADDC Al,AO 0 FFFFFFFFh 00000001h 0110 OOOOOOOOh
ADDC Al,AO 0 FFFFFFFFh 00000002h 0100 0000000lh
ADDC Al,AO 0 FFFFFFFFh 80000000h 0101 7FFFFFFFh
ADDC Al,AO 0 FFFFFFFFh 80000001h 1100 80000000h
ADDC Al,AO 0 7FFFFFFFh ~0000001h 0110 OOOOOOOOh
ADDC Al,AO 0 7FFFFFFFh 80000000h 1000 FFFFFFFFh
ADDC Al,AO 0 7FFFFFFFh 00000001h 1001 80000000h
ADDC Al,AO 0 00000002h 00000002h 0000 0OOOOO04h
12-37
ADDI Add Immediate - 16 Bits
Syntax ADDI IW, Rd [, W}
Execution IW + Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 987 6 5 4 3 2 o
o o 0 o R Rd
16-bit value
Description This ADDI instruction adds a sign-extended, 16-bit immediate value to the
contents of the destination register, and stores the result in the destination
register. (The symbol IW in the syntax above represents a 16-bit, sign-
extended immediate value.)
The assembler uses the short (16-bit) add if the immediate value is previ-
ously defined and is in the range -32,768 to 32,767. You can force the
assembler to use the short form by following the register operand with a
W:
ADDI IW,Rd,W
If you use the W parameter and the value is outside the legal range, the
assembler discards all but the 16 LSBs and issues an appropriate warning
message.
You can use the ADDI instruction with the ADDC instruction to perform
multiple-precision arithmetic.
Machine
States 2,8
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a carry, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
AO NCZV AO
ADDI l,AO FFFFFFFFh 0110 OOOOOOOOh
ADDI 2,AO FFFFFFFFh 0100 00000001h
ADDI l,AO 7FFFFFFFh 1001 80000000h
ADDI 2,AO 00000002h 0000 00000004h
ADDI 32767,AO 00000002h 0000 00008001h
ADDI OFFFFOO1Oh,AO,W FFFFFFFOh 0110 OOOOOOOOh
12-38
Add Immediate - 32 Bits ADDI
Syntax ADDI IL, Rd [, lJ
Execution IL + Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 1 0 1 1 0 0 1 IR I Rd
16 LSBs of IL
16 MSBs of IL
Description This ADDI instruction adds a 32-bit, signed immediate value to the con-
tents of the destination register, and stores the result in the destination re-
gister. (The symbol IL in the syntax above represents a 32-bit, signed
immediate value.)
The assembler uses the long (32-bit) ADDI if it cannot use the short form.
You can force the assembler to use the long form by following the register
operand with an L:
ADDI IL,Rd,L
Machine
States 3,12
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a carry, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
AO NCZV AO
ADDI OFFFFFFFFh,AO FFFFFFFFh 1100 FFFFFFFEh
ADDI 80000000h,AO FFFFFFFFh 0101 7FFFFFFFh
ADDI 80000000h,AO 7FFFFFFFh 1000 FFFFFFFFh
ADDI 32768,AO 7FFFFFFFh 1001 80007FFFh
ADDI 2,AO,L FFFFFFFFh 0100 00000001h
12-39
ADDK Add Constant (5 Bits)
Syntax ADDK K,Rd
Execution K + Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 0 0 01 K 1R Rd 1
Description ADDK adds a 5-bit constant to the contents of the destination register and
stores the result in the destination register. (The symbol K in the syntax
above represents a 5-bit constant.)
The constant is treated as an unsigned number in the range 1-32; if the or-
iginal value of K=32, then K is converted to 0 in the opcode. The assembler
issues an error if you try to add 0 to a register.
You can use the ADDK instruction with the ADDC instruction to perform
multiple-precision arithmetic.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a carry, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
AO NCZV AO
ADDK l,AO FFFFFFFFh 0110 OOOOOOOOh
ADDK 2,AO FFFFFFFFh 0100 0OOOOO01h
ADDK l,AO 7FFFFFFFh 1001 80000000h
ADDK l,AO 80000000h 1000 80000001h
ADDK 32,AO 80000000h 1000 80000020h
ADDK 32,AO 00000002h 0000 0OOOO022h
12-40
Add Registers in XV Mode ADDXV
Syntax ADDXY Rs, Rd
Execution RsX + RdX ~ RdX
RsY + RdY ~ RdY
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
1 1 0 0 0 01 Rs Rd
Description ADDXY adds the signed source X value to the signed destination X value,
adds the signed source Y value to the signed destination Y value, and stores
the result in the destination register. The source and destination registers
are treated as if they contained separate X and Y values. Any carry out from
the lower (X) half of the register does not propagate into the upper (Y) half.
If you only want to add the X halves together, then one of the Y values must
be 0 (the method for adding the Y halves is similar).
You can use this instruction to manipulate XY addresses in the register file;
ADDXY is also useful for incremental figure drawing.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N 1 if resulting X field is all Os, 0 otherwise
C The sign bit of the Y half of the result
Z 1 if Y field is all Os, 0 otherwise
V The sign bit of the X half of the result
Examples Code Before After
A1 AO AO NCZV
ADDXY AI,AD OOOOOOOOh OOOOOOOOh OOOOOOOOh 1010
ADDXY AI,AD OOOOOOOOh 00000001h 00000001h 0010
ADDXY AI,AD OOOOOOOOh 00010000h 00010000h 1000
ADDXY AI,AD OOOOOOOOh 00010001h 00010001h 0000
ADDXY AI,AD OOOOFFFFh 00000001h OOOOOOOOh 1010
ADDXY AI,AD OOOOFFFFh 00010001h 00010000h 1000
ADDXY AI,AD OOOOFFFFh 00000002h 00000001h 0010
ADDXY AI,AD OOOOFFFFh 00010002h 00010001h 0000
ADDXY AI,AD FFFFOOOOh 00010000h OOOOOOOOh 1010
ADDXY AI,AD FFFFOOOOh 00010001h 00000001h 0010
ADDXY AI,AD FFFFOOOOh 00020000h 00010000h 1000
ADDXY AI,AD FFFFOOOOh 00020001h 00010001h 0000
ADDXY AI,AD FFFFFFFFh 00010001h OOOOOOOOh 1010
ADDXY AI,AD FFFFFFFFh 00010002h 00000001h 0010
ADDXY AI,AD FFFFFFFFh 00020001h 00010000h 1000
ADDXY AI,AD FFFFFFFFh 00020002h 00010001h 0000
12-41
AND AND Registers
Syntax AND Rs, Rd
Execution Rs AND Rd ~ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 0 0 01 Rs 1R Rd 1
Description AND bitwise-ANDs the contents of the source register with the contents
of the destination register and stores the result in the destination register.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z 1 if the result is 0, a otherwise
V Unaffected
Examples Code Before After
A1 AO NCZV AO
AND Al,AO FFFFFFFFh FFFFFFFFh xxOx FFFFFFFFh
AND Al,AO FFFFFFFFh OOOOOOOOh x x 1x OOOOOOOOh
AND Al,AO OOOOOOOOh OOOOOOOOh x x1x OOOOOOOOh
AND Al,AO AAAAAAAAh 55555555h x x1x OOOOOOOOh
AND Al,AO AAAAAAAAh AAAAAAAAh xxOx AAAAAAAAh
AND Al,AO 55555555h 55555555h xxOx 55555555h
AND Al,AO 55555555h AAAAAAAAh xx1 x OOOOOOOOh
12-42
AND Immediate (32 Bits) ANDI
Syntax ANDI IL, Rd
Execution IL AND Rd .... Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 1 0 1 1 1 0 oI R I Rd
1s complement of 16 LSBs of IL
1s complement of 16 MSBs of IL
Description ANDI bitwise-ANDs the value of a 32-bit immediate value with the con-
tents of the destination register, and stores the result in the destination re-
gister. (The symbol IL in the syntax above represents a 32-bit immediate
value.)
This is an alternate mnemonic for ANDNI IL,Rd. Note that the assembler
stores the 1 s complement of I L in the two extension words.
Machine
States 3,12
Status Bits N Unaffected
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
AO NCZV AO
ANDI OFFFFFFFFh,AO FFFFFFFFh xxOx FFFFFFFFh
ANDI OFFFFFFFFh,AO OOOOOOOOh xx1x OOOOOOOOh
ANDI oOOOOOOOh,AO OOOOOOOOh xx1x OOOOOOOOh
ANDI OAAAAAAAAh,AO 55555555h xx1x OOOOOOOOh
ANDI OAAAAAAAAh,AO AAAAAAAAh xxOx AAAAAAAAh
ANDI 55555555h,AO 55555555h xxOx 55555555h
ANDI 55555555h,AO AAAAAAAAh xx1x OOOOOOOOh
12-43
ANON AND Register with Complement
Syntax ANON Rs, Rd
Execution (NOT Rs) AND Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 Rs IR Rd I
Description ANON bitwise-ANDs the 1s complement of the contents of Rs with the
contents of Rd, and stores the result in the qestination register.
Rs and Rd must be in the same register file. Note that ANDN Rn, Rn has the
same effect as CLR Rn.
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
A1 AO NC ZV AO
ANON Al,AO FFFFFFFFh FFFFFFFFh xx 1 x OOOOOOOOh
ANDN Al,AO FFFFFFFFh OOOOOOOOh xx 1 x OOOOOOOOh
ANON Al,AO OOOOOOOOh OOOOOOOOh xx 1 x OOOOOOOOh
ANDN Al,AO AAAAAAAAh 55555555h x x Ox 55555555h
ANON Al,AO AAAAAAAAh AAAAAAAAh x x 1 x OOOOOOOOh
ANON Al,AO 55555555h 55555555h xx 1 x OOOOOOOOh
ANON Al,AO 55555555h AAAAAAAAh x x Ox AAAAAAAAh
12-44
AND Not Immediate (32 Bits) ANONI
Syntax ANONI IL, Rd
Execution (NOT IL) AND Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 1 0 1 1 1 0 oIR I Rd
16 LSBs of IL
16 MSBs of IL
Description ANDNI bitwise-ANDs the 1s complement of a 32-bit immediate value with
the contents of the destination register, and stores the result in the desti-
nation register. (The symbol IL in the syntax above represents a 32-bit
immediate value.) ANDI also uses this opcode.
Machine
States 3,12
Status Bits N Unaffected
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
AO NCZV AO
ANDNI OFFFFFFFFh,AO FFFFFFFFh xx1x OOOOOOOOh
ANDNI OFFFFFFFFh,AO OOOOOOOOh xx1x OOOOOOOOh
ANDNI oOOOOOOOh,AO OOOOOOOOh xx1x OOOOOOOOh
ANDNI OAAAAAAAAh,AO 55555555h xxOx 55555555h
ANDNI OAAAAAAAAh,AO AAAAAAAAh xx1x OOOOOOOOh
ANDNI 55555555h,AO 55555555h xx1x OOOOOOOOh
ANDNI 55555555h,AO AAAAAAAAh xxOx AAAAAAAAh
12-45
BTST Test Register Bit - Constant
Syntax BTST K, Rd
Execution Set status on value of bit K in Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I0 0 0 1 I R Rd
Description BTST tests a bit in the destination register bit and sets status bit Z accord-
ingly. This form of the BTST instruction uses a 5-bit constant to specify the
bit in Rd that is tested (the symbol K in the syntax above represents a 5-bit
constant). The K value must be an absolute expression that evaluates to a
number in the range 0 to 31; if the value is greater than 31, the assembler
issues a warning and truncates the K operand value to the five LSBs.
Note that the assembler 1s-complements the value of K before inserting it
into the opcode.
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z 1 if the bit tested is 0, 0 if the bit tested is 1 .
V Unaffected
Examples Code Before After
AO NCZV
BTST O,AO 55555555h xxOx
BTST 15,AO 55555555h xx1x
BTST 31,AO 55555555h xx1x
BTST O,AO AAAAAAAAh xx1x
BTST 15,AO AAAAAAAAh xxOx
BTST 31,AO AAAAAAAAh xxOx
BTST O,AO FFFFFFFFh xxOx
BTST 15,AO FFFFFFFFh xxOx
BTST 31,AO FFFFFFFFh xxOx
BTST O,AO OOOOOOOOh xx1x
BTST 15,AO OOOOOOOOh xx1x
BTST 31,AO OOOOOOOOh xx1x
12-46
Test Register Bit - Register BTST
Syntax BTST Rs, Rd
Execution Set status on value of specified bit in Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I0 0 0 0 Rs IR Rd
Description BTST tests a bit in the destination register bit and sets status bit Z accord-
ingly. This form of the BTST instruction uses the 5 LSBs of the source re-
gister to specify the bit in Rd that is tested (the symbol Rs in the syntax
above represents the source register). Note that the 27 MSBs of Rs are
ignored.
Rs and Rd must be in the same register file.
Machine
States 2,5
Status Bits N Unaffected
C Unaffected
Z 1 if the bit tested is 0, 0 if the bit tested is 1
V Unaffected
Examples Code Before After
A1 AO NCZV
BTST Al,AO OOOOOOOOh 55555555h xxOx
BTST Al,AO OOOOOOOFh 55555555h xx1x
BTST Al,AO 0000001Fh 55555555h xx1x
BTST Al,AO OOOOOOOOh AAAAAAAAh xx1x
BTST Al,AO OOOOOOOFh AAAAAAAAh xxOx
BTST Al,AO 0000001Fh AAAAAAAAh xxOx
BTST Al,AO FFFFFF8Fh FFFF7FFFh xxOx
BTST Al,AO OOOOOOOOh FFFFFFFFh xxOx
BTST Al,AO OOOOOOOFh FFFFFFFFh xxOx
BTST Al,AO 0000001Fh FFFFFFFFh xxOx
BTST Al,AO OOOOOOOOh OOOOOOOOh xx1x
BTST Al,AO OOOOOOOFh OOOOOOOOh xx1x
BTST Al,AO 0000001Fh OOOOOOOOh xx1x
12-47
CALL Call Subroutine - Indirect
Syntax CALL Rs
Execution PC' -+ TOS
Rs -+ PC
SP - 32 -+ SP
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 R Rs I
Description CALL pushes the address of the next instruction (PC') onto the stack, then
jumps to a subroutine whose address is contained in the source register.
You can use this instruction for indexed subroutine calls. Note that when
Rs is the SP, Rs is decremented after being written to the PC (the PC
contains the original value of Rs).
The TMS3401 0 always sets the four LSBs of the program counter to 0, so
instructions are always word aligned.
The stack pointer (SP) points to the top of the stack; the stack is located
in external memory. The stack grows in the direction of decreasing linear
addresses. PC' is pushed onto the stack and the SP is predecremented by
32 before the return address is loaded onto the stack. Stack pointer align-
ment affects timing as indicated in Machine States, below.
Use the RETS instruction to return from a subroutine.
Machine
States 3+ (3),9 (SP aligned)
3+ (9),15 (SP nonaligned)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Example CALL AO
Before After
AO PC SP PC SP
01234560h 04442210h F000020h 01 234560h FOOOOOOh
Memory contains the following values after instruction execution:
Address Data
F000010h 2220h
F000020h 0444h
12-48
Call Subroutine - Absolute CALLA
Syntax CALLA Address
Execution PC' -+ TOS
Address -+ PC
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 1
16 LSBs of Address
16 MSBs of Address
Description CALLA pushes the address of the next instruction (PC') onto the stack,
then jumps to the address contained in the two extension words. The Ad-
dress operand is a 32-bit absolute address. This instruction is used for long
(greater than ±32K words) or externally referenced calls.
The lower four bits of the program counter are always set to 0, so in-
structions are always word-aligned.
The stack pointer (SP) points to the top of the stack; the stack is located
in external memory. The stack grows in the direction of decreasing linear
address. PC' is pushed onto the stack and the SP is predecremented by 32
before the return address is loaded onto the stack. Stack pointer alignment
affects timing as indicated in Machine States, below.
Use the RETS instruction to return from a subroutine.
Machine
States 4+(2),15 (SP aligned)
4+ (8),21 (SP nonaligned)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Example CALLA 01234560h
Before After
PC SP PC SP
04442210h OF000020h 01234560h OFOOOOOOh
Memory contains the following values after instruction execution:
Address Data
F000010h 2240h
F000020h 0444h
12-49
CALLR Call Subroutine - Relative
Syntax CALLR Address
Execution PC' -+ TOS
PC' + (offset x 16) -+ PC
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0
0 0 0 0 0
offset
0
1 I
Description CALLR pushes the address of the next instruction (PC') onto the stack,
then jumps to the subroutine at the address specified by the sum of the next
instruction address and the signed word offset. This instruction is used for
calls within a specified module or section.
The Address operand is a 32-bit address within ±32K words (-32,768 to
32,767) of the PC. The address must be defined within the current section;
the assembler does not accept an address value that is externally defined
or defined within a different section than PC'. The assembler calculates the
offset value for the opcode as (Address - PC') /16.
The lower four bits of the program counter are always set to 0, so in-
structions are always word aligned.
The stack pointer (SP) points to the top of the stack; the stack is located
in external memory. The stack grows in the direction of decreasing linear
address. The PC is pushed on to the stack and the S P is predecremented
by 32 before the return address is loaded onto the stack. Stack pointer
alignment affects timing as indicated in Machine States, below.
Use the RETS instruction to return from a subroutine.
Machine
States 3+ (2),11 (SP aligned)
3+ (8),17 (SP nonaligned)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
PC SP PC SP
CALLR 0447FFFOh 04400000h OF000020h 0447FFFOh OFOOOOOOh
CALLR 04480000h 04400000h OF000020h 04480000h OFOOOOOOh
Memory contains the following values after instruction execution:
Address Data
F000010h OOOOh
F000020h 0440h
12-50
Clear Register CLR
Syntax CLR Rd
Execution Rd XOR Rd -. Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 Rd IR Rd I
Description CLR clears the destination register by XORing the contents of the register
with itself. This is an alternate mnemonic for XOR Rd,Rd.
Machine
States 1,4
Status Bits NUn affected
C Unaffected
Z 1
V Unaffected
Examples Before After
AO AO NCZV
CLR AO FFFFFFFFh OOOOOOOOh xx1x
CLR AO 00000001h OOOOOOOOh xx1x
CLR AO 80000000h OOOOOOOOh xx1x
CLR AO AAAAAAAAh OOOOOOOOh xx1x
12-51
CLRC Clear Carry
Syntax CLRC
Execution o -. C
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 0 0 0 0 01
Description CLRC sets the C (carry) bit in the status register to 0; the rest of the status
register is unaffected. (Note that the SETC instruction sets the C bit.)
This instruction is useful for returning a true/false value (in the carry bit)
from a subroutine without using a general-purpose register.
Machine
States 1,4
Status Bits N Unaffected
C 0
Z Unaffected
V Unaffected
Examples Code Before After
ST NCZV ST NCZV
CLRC FOOOOOOOh 1111 BOOOOOOOh 1011
CLRC 40000010h 0100 00000010h 0000
CLRC BOOOO01Fh 1011 BOOOO01Fh 1011
12-52
Compare Registers CMP
Syntax CMP Rs, Rd
Execution Set status bits on the result of Rd - Rs
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
10 0 0 0 01 Rs R Rd
Description CMP sets the status bits on the result of subtracting the contents of Rs from
the contents of Rd. This is a nondestructive compare; the contents of the
registers are not affected. This instruction is often used in conjunction with
the JAcc or J Rcc conditional jump instructions.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if a there is a borrow, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After Jumps Taken
A1 AO NCZV
eMP Al,AO 00000001h 00000001h 0010 UC,NN,NC,Z,NV,LS,GE,LE,HS
eMP Al,AO 00000001h 00000002h 0000 UC,NN,NC,NZ,NV,P,HI,GE,GT,HS
eMP Al,AO 00000001h FFFFFFFFh 1000 UC,N,NC,NZ,NV,P,HI,LT,LE,HS
eMP Al,AO 00000001h 80000000h 0001 UC,NN,NC,NZ,V,HI,LT,LE,HS
eMP Al,AO FFFFFFFFh 7FFFFFFFh 1101 UC,N,C,NZ,V,LS,GE,GT,LO
eMP Al,AO FFFFFFFFh 80000000h 1100 UC,N,C,NZ,NV,LS,LT,LE,LO
eMP Al,AO 80000000h 7FFFFFFFh 1101 UC,N,C,NZ,V,LS,GE,GT,LO
12-53
CMPI Compare Immediate - 16 Bits
Syntax CM PI IW, Rd [, WJ
Execution Set status bits on the resu It of Rd - IW
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
o 0 0 IR Rd
1 s complement of IW
Description CMPI sets the status bits on the result of subtracting a 16-bit, sign-
extended immediate value from the contents of the destination register.
(The symbol IW in the syntax above represents a 16-bit, signed immediate
value.) This is a nondestructive compare; the contents of the destination
register are not affected. This instruction is often used in conjunction with
the JAee or J Ree conditional jump instructions.
Note that the assembler inserts the 1 s complement of the 16-bit value into
the second instruction word.
The assembler uses the short form of the CMPI instruction if the immediate
value is previously defined and is in the range -32,768 to 32,767. You can
force the assembler to use the short form by following the register operand
withW:
eMP! !W,Rd,W
The assembler truncates the upper bits and issues an appropriate warning
message if the value is greater than 16 bits.
Machine
States 2,8
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a borrow, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After Jumps Taken
AO NCZV
eMP! 1,AO 00000002h 0000 UC,NN,NC,NZ,NV,P,HI,GE,GT,HS
eMP! 1,AO 00000001h 0010 UC,NN,NC,Z,NV,LS,GE,LE,HS
eMP! 1,AO OOOOOOOOh 1100 UC,N,C,NZ,NV,LS,LT,LE,LO
eMP! 1,AO FFFFFFFFh 1000 UC,N,NC,NZ,NV,P,HI,LT,LE,HS
eMP! 1,AO 80000000h 0001 UC,NN,NC,NZ,V,HI,LT,LE,HS
eMP! -2,AO OOOOOOOOh 0100 UC,NN,C,NZ,NV,P,LS,GE,GT,LO
eMP! -2,AO FFFFFFFFh 0000 UC,NN,NC,NZ,NV,P,LI,GE,GT,HS
eMP! -2,AO FFFFFFFEh 0010 UC,NN,NC,Z,NV,LS,GE,LE,HS
eMP! -2,AO FFFFFFFDh 1100 UC,N,C,NZ,NV,LS,LT,LE,LO
eMP! -l,AO 7FFFFFFFh 1101 UC,N,C,NZ,V,LS,GE,GT,LO
12-54
Compare Immediate - 32 Bits CMPI
Syntax CM PilL, Rd [, LJ
Execution Set status bits on the resu It of Rd - I L
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 1 0 1 1 0 1 1 IR I Rd
1s complement of 16 LSBs of IL
1 s complement of 16 MSBs of IL
Description CMPI sets the status bits on the result of subtracting a 32-bit, signed im-
mediate value from the contents of the destination register. (The IL symbol
in the syntax above represents a 32-bit, signed immediate value.) This is a
nondestructive compare; the contents of the destination register are not af-
fected.
Note that the assembler inserts the 1 s complement of the 16 LSBs of the
value into the second instruction word, and inserts the 1s complement of
the 16 MSBs of the value into the third instruction word.
The assembler uses this form of the CMPI instruction if it cannot use the
short form. You can force the assembler to use the long form by following
the register operand with an L:
CMPI IL,Rd,L
This instruction is often used in conjunction with the JAcc or J Rcc condi-
tional jump instructions.
Machine
States 3,12
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a borrow, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Before After Jumps Taken
AO NCZV
CMPI 8000h,AO 00008001h 0000 UC, N N, NC, NZ, NV, p, H I,G E,GT, HS
CMPI 8000h,AO 00008000h 0010 UC,NN,NC,Z,NV,LS,GE,LE,HS
CMPI 8000h,AO 00007FFFh 1100 UC,N,C,NZ,NV,LS,LT,LE,LO
CMPI 8000h ,AO FFFFFFFFh 1000 UC,N,NC,NZ,NV,P,HI,LT,LE,HS
CMPI 8000h,AO 80007FFFh 0001 UC,NN,NC,NZ,V,HI,LT,LE,HS
CMPI OFFFF7FFFh,AO OOOOOOOOh 0100 UC,NN,C,NZ,NV,P,LS,GE,GT,LO
CMPI OFFFF7FFEh,AO FFFF7FFFh 0000 UC,NN,NC,NZ,NV,P,HI,GE,GT,HS
CMPI OFFFF7FFEh,AO FFFF7FFEh 0010 UC,NN,NC,Z,NV,LS,GE,LE,HS
CMPI OFFFF7FFEh, AO FFFF7FFDh 1100 UC,N,C,NZ,NV,LS,LT,LE,LO
CMPI OFFFF7FFFh,AO 7FFF7FFFh 1101 UC,N,C,NZ,V,LS,GE,GT,LO
12-55
CMPXY Compare X and V Halves of Registers
Syntax CMPXV Rs, Rd
Execution Set status bits on the results of:
RdX - RsX
RdV - RsV
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
11 0 0 01 Rs R Rd
Description CMPXY compares the source register to the destination register in XY mode
and sets the status bits as if a subtraction had been performed. This is a
nondestructive compare; the contents of the register are not affected. The
source and destination registers are treated as signed XY registers. Note
that no overflow detection is provided.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N 1 if source X field = destination X field, 0 otherwise
C Sign bit of Y half of the result
Z 1 if source Y field = destination Y field, 0 otherwise
V Sign bit of X half of the result
Examples Code Before After Jumps Taken
A1 AO NCZV
CMPXY Al,AO 00090009h 00010001 h 0101 NN,C,NZ,V,LS,LT
CMPXY Al,AO 00090009h 00090001 h 0011 NN,NC,Z,V,LS,LT
CMPXY Al,AO 00090009h 00010009h 1100 N,C,NZ,NV,LS,LT
CMPXY Al,AO 00090009h 00090009h 1010 N,NC,Z,NV,LS,LT
CMPXY Al,AO 00090009h 00000010h 0100 NN,C,NZ,NV,LS,GE
CMPXY Al,AO 00090009h 00090010h 0010 NN,NC,Z,NV,LS,GE
CMPXY Al,AO 00090009h 00100000h 0001 NN,NC,NZ,V,HI,LT
CMPXY Al,AO 00090009h 00100009h 1 000 N,NC,NZ,NV,HI,LT
CMPXY Al,AO 00090009h 001 0001 Oh 0000 NN,NC,NZ,NV,HI,GE
12-56
Compare Point to Window CPW
Syntax CPW Rs, Rd
Execution point code -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I1 0 0 Rs R Rd
Description CPW compares a point represented by an XY value in the source register to
the window limits in the WSTART and WEND registers. The contents of
the source register are treated as an XY address that consists of 16-bit
signed X and Y values. WSTART and WEN 0 are also treated as signed
XY -format registers. WST ART and WEN 0 must contain positive values;
negative values produce unpredictable results. The location of the point
with respect to the window is encoded as shown below; the code is loaded
into the destination register.
Codes:
0101 0100 0110
~1UI= 1~10
31 98 5.. 0
1000....000 ICODe I000001 Rd
1001 1000 1010
The following list describes the contents of the destination register after
CPWexecution:
Bit Postion: Contents:
0-4 Os
5 1 if WST ART.X > Rs.X, 0 otherwise
6 1 if Rs.X > WEND.X, 0 otherwise
7 1 if WSTART.Y > Rs.Y, 0 otherwise
8 1 if Rs.Y > WEND.Y, 0 otherwise
9-31 Os
This instruction can also be used to trivially reject lines that do not intersect
with a window. The CPW codes for the two points defining the line are
AN Oed together. If the result is nonzero, then the line must lie completely
outside the window (and does not intersect it). A 0 result indicates that the
line may intersect the window, and a more rigorous test must be applied.
Rs and Rd must be in the same register file.
Implied
Operands B Fi Ie Reg isters
Register Name Format Description
85 WSTART XY Window start. Defines inclusive starting
corner of window (lesser value corner).
86 WEND XY Window end. Defines inclusive ending
corner of window (greater value corner).
12-57
CPW Compare Point to Window
Machine
States 1,4
Status Bits NUn affected
C Unaffected
Z Unaffected
V 1 if point lies outside window, a otherwise
Examples You must select appropriate implied operand values before executing the
CPW instruction. In this example, the implied operands are set up as fol-
lows, specifying a block of 36 pixels.
WSTART = 5,5
WEND = A,A
CPW Al/AO
Before After
A1 NCZV AO NCZV
0OO40004h xxxO OOOOOOAOh xxx1
0OO40005h xxxO 0OOOOO80h xxx1
0OO4000Ah xxxO 0OOOOO80h xxx1
0OO4000Bh xxx1 OOOOOOCOh xxx1
0OO50004h xxx1 0OOOOO20h xxx1
0OO50005h xxxO OOOOOOOOh xxxO
0OO5000Ah xxxO OOOOOOOOh xxxO
0OO5000Bh xxxO 0OOOOO40h xxx1
OOOAOOO4h xxxO 0OOOOO20h xxx1
OOOAOOO5h xxx1 OOOOOOOOh xxxO
OOOAOOOAh xxx1 OOOOOOOOh xxxO
OOOAOOOBh xxxO 0OOOOO40h xxx1
OOOBOOO4h xxxO 0OOOO120h xxx1
OOOBOOO5h xxxO 0OOOO100h xxx1
OOOBOOOAh xxxO 0OOOO100h xxx1
OOOBOOOBh xxxO 0OOOO140h xxx1
12-58
Convert XV Address to Linear Address CVXVL
Syntax CVXVl Rs, Rd
Execution RsXV ..... linear address in Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I 1 0 0 01 Rs R Rd
Description CVXYL converts an XY address to a linear address:
• The source register contains an XY address. The signed X value oc-
cupies the 16 LSBs of the register and the signed Y value occupies
the 16 MSBs. The X value must be positive.
• The XY address is converted into a 32-bit linear address which is
stored in the destination register.
The following conversion formula is used:
Address = [(V x Display Pitch) OR (X x Pixel Size)] + Offset
Since the TMS3401 0 restricts the screen pitch and pixel size to powers of
two (for XY addressing), the multiply operations in this conversion are ac-
tually shifts. The offset value is in the OFFSET register. The CONVDP value
is used to determine the shift amount for the Y value, while the PSIZE reg-
ister determines the X shift amount.
Rs and Rd must be in the same register file.
Implied
Operands B File Registers
Register Name Format Description
B3 DPTCH Linear Destination pitch
B4 OFFSET Linear Screen origin (location 0,0)
I/O Registers
Address Name Description and Elements (Bits)
COOO0140h CONVDP XY-to-linear conversion (destination pitch)
COOO0150h PSIZE Pixel size (1,2,4,8,16)
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
CVXYL instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Machine
States 3,6
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
12-59
CVXVL Convert XV Address to Linear Address
Examples
Before After
AO OFFSET PSIZE CONVDP A1
CVXYL AD,Ai 00400030h OOOOOOOOh 0010h 0014h 00020300h
CVXYL AD,Ai 00400030h OOOOOOOOh 0008h 0014h 00020180h
CVXYL AD,Ai 00400030h OOOOOOOOh 0004h 0014h 00020000h
CVXYL AO,Al 00400030h 00008000h 0004h 0014h 00028000h
CVXYL AO,Al 00400030h oFOOOOOOh 0004h 0014h OF020000h
CVXYL AO,Al 00400030h OOOOOOOOh 0002h 0014h 00020060h
CVXYL AO,Al 00400030h OOOOOOOOh 0001h 0014h 00020030h
CVXYL AO,Al 00400030h OOOOOOOOh 0001h 0013h 00040030h
CVXYL AO,Al 00400030h OOOOOOOOh 0001h 0015h 00010000h
CONVDP = 0013h corresponds to DPTCH = 00001000h
CONVDP = 0014h corresponds to DPTCH = 00000800h
CONVDP = 0015h corresponds to DPTCH = 00000400h
12-60
Decrement Register DEC
Syntax DEC Rd
Execution Rd - 1 -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 R Rd I
Description DEC subtracts 1 from the contents of the destination register and stores the
result in the destination register. This instruction is an alternate mnemonic
for SUBK 1, Rd.
You can use the DEC instruction with the SUBB instruction to perform
multiple-precision arithmetic.
Machine
States 1,4
Status Bits N a
1 if the result is negative, otherwise
C a
1 if there is a borrow, otherwise
Z a
1 if the result is 0, otherwise
V a
1 if there is an overflow, otherwise
Examples Code Before After
A1 A1 NCZV
DEC Al 00000010h OOOOOOOFh 0000
DEC Al 00000001h OOOOOOOOh 0010
DEC Al OOOOOOOOh FFFFFFFFh 1100
DEC Al FFFFFFFFh FFFFFFFEh 1000
DEC Al 80000000h 7FFFFFFFh 0001
12-61
DINT Disable Interrupts
Syntax DINT
Execution o ~ IE
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 0 0 0 oI
Description DINT disables interrupts by setting the global interrupt enable bit (IE, status
bit 21) to O. All interrupts except reset and NMI are disabled; the interrupt
enable mask in the INTENB register is ignored. The remainder of the status
register is unaffected.
The EINT instruction enables interrupts.
Machine
States 3,6
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
IE 0
Examples Before After
ST ST
DINT 00000010h 00000010h
DINT 00200010h 00000010h
12-62
Divide Registers - Signed DIVS
Syntax DIVS Rs, Rd
Execution Rd Even: Rd:Rd+1/Rs -+ Rd, remainder -+ Rd+1
Rd Odd: Rd/Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 0 01 Rs R Rd
Description DIVS performs a signed 32-bit or 64-bit divide. The source register con-
tains the 32-bit signed divisor. The destination register contains a 32-bit
signed dividend or the most significant half of a 64-bit signed dividend,
depending on whether Rd is an odd register (for example, A1 or 83) or an
even register (for example, A8 or B2):
Rd Even DIVS performs a signed divide of the 64-bit operand contained
in the two consecutive registers, starting at the specified desti-
nation register, by the 32-bit contents of the source register.
The specified even-numbered destination register, Rd, contains
the 32 MSBs of the dividend. The next consecutive register
(which is odd-numbered) contains the 32 LSBs of the divi-
dend. The quotient is stored in the destination register, and the
remainder is stored in the following register (Rd+1). The re-
mainder is always the same sign as the dividend (in Rd:Rd+1).
Avoid using A14 or B14 as the destination register, since this
overwrites the SP; the assembler issues a warning in this case.
Rd Odd DIVS performs a signed divide of the 32-bit operand contained
in the destination register by the 32-bit value in the source re-
gister. The quotient is stored in the destination register; the re-
mainder is not returned.
Rs and Rd must be in the same register file.
Machine
States Rd Odd Rd Even
Normal 39,42 40,43
Result = 80000000h 41,44 41,44
Rs = 0 7,10 7,10
Rd.?:. Rs treated as normal 7,10
Status Bits N 0 if:
• Rs = 0, or
• Rd is even and Rd .?:. Rs, or
• Quotient is nonnegative.
1 if:
• Result = 80000000h or
• Quotient is negative.
C Unaffected
Z 0 if:
• Rs = 0, or
• Rd is even and Rd .?:. Rs, or
12-63
DIVS Divide Registers - Signed
• Result = 80000000h, or
•
1 if:
Quotient ¢ O.
• Quotient = O.
V 1 if quotient overflows (cannot be represented by 32 bits), 0 other-
wise
The following conditions cause an overflow and set the overflow flag:
• Divisor (Rs) is 0
• Quotient cannot be contained within 32 bits
Example 1 This example divides the contents of register AO by the contents of register
A2, and stores the result in register AO. Note that the contents of reg-
ister A2 are not affected by instruction execution.
DIVS A2,AO
Before After
AO A1 A2 AO A1 A2 NCZV
12345678h 87654321h 87654321h D95BC60Ah 15CA1DD7h 87654321h 1xOO
EDCBA987h 789ABCDFh 87654321h 26A439F6h EA35E229h 87654321h OxOO
EDCBA987h 789ABCDFh 789ABCDFh D95BC60Ah EA35E229h 789ABCDFh 1xOO
12345678h 87654321h 789ABCDFh 26A439F6h 15CA1DD7h 789ABCDFh OxOO
12345678h 87654321h OOOOOOOOh 12345678h 87654321h OOOOOOOOh Ox01
OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh Ox01
OOOOOOOOh OOOOOOOOh 87654321h OOOOOOOOh OOOOOOOOh 87654321h Ox10
87654321h OOOOOOOOh 87654321h 87654321h OOOOOOOOh 87654321h Ox01
Example 2 This example divides the contents of register A1 by the contents of of reg-
ister A2, and stores the result in register AO. Note that the contents of
register A2 are not affected by instruction execution.
DIVS A2,Al
Before After
AO A1 A2 AO A1 A2 NCZV
OOOOOOOOh 87654321h 12345678h OOOOOOOOh FFFFFFFAh 12345678h 1xOO
OOOOOOOOh 87654321h OEDCBA988h OOOOOOOOh 0OOOOOO6h EDCBA988h OxOO
OOOOOOOOh 789ABCDFh OEDCBA988h OOOOOOOOh FFFFFFFAh EDCBA988h 1xOO
OOOOOOOOh 789ABCDFh 12345678h OOOOOOOOh 0OOOOOO6h 12345678h OxOO
OOOOOOOOh 87654321h OOOOOOOOh OOOOOOOOh 87654321h OOOOOOOOh Ox01
OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh Ox01
12-64
Divide Registers - Unsigned DIVU
Syntax DIVU Rs, Rd
Execution Rd Even: Rd:Rd+1/Rs -+ Rd, remainder -+ Rd+1
Rd Odd: Rd/Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 Rs R Rd I
Description DIVU performs an unsigned 32-bit or 64-bit divide. The source register
contains the 32-bit divisor. The destination register contains a 32-bit divi-
dend or the most significant half of a 64-bit dividend, depending on
whether Rd is an odd register (for example, A 1 or B3) or an even register
(for example, A8 or B2):
Rd Even DIVU performs an unsigned divide of the 64-bit operand con-
tained in the two consecutive registers, starting at the destina-
tion register, by the 32-bit contents of the source register. The
specified even-numbered destination register, Rd, contains the
32 MSBs of the dividend. The next consecutive register
(which is odd-numbered) contains the 32 LSBs of the divi-
dend. The quotient is stored in the destination register, and the
remainder is stored in the following register (Rd+1). Avoid
using A14 or B14 as the destination register, since this over-
writes the SP; the assembler issues a warning in this case.
Rd Odd DIVU performs an unsigned divide of the 32-bit operand con-
tained in the destination register by the 32-bit value in the
source register. The quotient is stored in the destination regis-
ter; the remainder is not returned.
Rs and Rd must be in the same register file.
Machine
States Rd Odd Rd Even
Normal 37,40 37,40
Rs:;:: 0 5,8, 5,8
Rd ~ Rs treated as normal 5,8
Status Bits N Unaffected
C Unaffected
Z 0 if:
• Rs = 0, or
• Rd is even and Rd ..:::. Rs, or
• Quotient ¢ O.
1 if:
• Quotient = O.
V 1 if quotient overflows (cannot be represented by 32 bits), 0 other-
wise
The following conditions cause an overflow and set the overflow flag:
• Divisor (Rs) is 0
12-65
DIVU Divide Registers - Unsigned
• Quotient cannot be contained within 32 bits
Example 7 This instruction divides the contents of register AO by the contents of reg-
ister A2, and stores the unsigned result in register AO. Note that the
contents of register A2 are not affected by instruction execution.
DIVU A2,AO
Before After
AO A1 A2 AO A1 A2 NCZV
12345678h 87654321h 789ABCDFh 26A439F6h 15CA1DD7h 789ABCDFh xxOO
12345678h 87654321h OOOOOOOOh 12345678h 87654321h OOOOOOOOh xx01
OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh xx01
OOOOOOOOh OOOOOOOOh 87654321h OOOOOOOOh OOOOOOOOh 87654321h xx10
87654321h OOOOOOOOh 87654321h 87654321h OOOOOOOOh 87654321h xx01
Example 2 This instruction divides the contents of register A1 by the contents of reg-
ister A2, and stores the unsigned result in register A1. Note that the
contents of register A2 are not affected by instruction execution.
DIVU A2,Al
Before After
AO A1 A2 AO A1 A2 NCZV
OOOOOOOOh 789ABCDFh 12345678h OOOOOOOOh 0OOOOOO6h 12345678h xxOO
OOOOOOOOh 12345678h OOOOOOOOh OOOOOOOOh 12345678h OOOOOOOOh xx01
OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh OOOOOOOOh xx01
OOOOOOOOh OOOOOOOOh 87654321h OOOOOOOOh OOOOOOOOh 87654321h xx10
OOOOOOOOh 87654321h 87654321h OOOOOOOOh 0OOOOOO1h 87654321h xxOO
12-66
Draw and Advance DRAV
Syntax DRAV Rs, Rd
Execution COLOR1 pixels -+ * Rd
RsX + RdX -+ RdX
RsY + RdY -+ RdY
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I1 0 Rs R Rd
Description DRAV writes the pixel value in the COLOR1 register to the location pointed
to by the XY address in the destination register. Following the write, the
XYaddress in the destination register is incremented by the value in the
source register: the X half of Rs is added to the X half of Rd, and the Y half
of Rs is added to the Y half of Rd. Any carry out from the lower (X) half
of the register does not propagate into the upper (Y) half.
COLOR1 bits 0-15 are output on data bus lines 0-15, respectively. The
pixel data used from COLOR1 is that which aligns to the destination lo-
cation, so 16-bit patterns can be implemented. Rs and Rd must be in the
same register file.
Implied
Operands B File Registers
Register Name Format Description
83 DPTCH Linear Destination pitch
84 OFFSET Linear Screen origin (location 0,0)
85 WSTART XY Window starting corner
86 WEND XY Window ending corner
89 COLOR1 Pixel Pixel color
I/O Registers
Address Name Description and Elements (Bits)
COOOO080h CONTROL PP- Pixel processing operations (22 options)
W - Window checking operation
T - Transparency operation
COOO0140h CONVDP XY -to-linear conversion (destination pitch)
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOO0160h PMASK Plane mask - pixel format
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
DRAV instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Pixel
Processing Set the PPOP field in the CONTROL register to select a pixel processing
operation. This operation is applied to the pixel as it is moved to the des-
tination location. At reset, the default pixel processing operation is replace
(S -+ D). For more information, see Section 7.7, Pixel Processing, on page
7-15.
12-67
DRAV Draw and Advance
Window
Checking Select a window checking mode by setting the W bits in the CONTROL
register. If you select an active window checking mode (W = 1, 2, or 3),
the WSTART and WEND registers define the XY starting and ending corners
of a rectangular window. The X and Y values in both WSTART and WEND
must be positive.
When the TMS3401 0 attempts to write a pixel inside or outside a defined
value, the following actions may occur:
W=O No window operation. The pixel is drawn and the WVP and V bits
are unaffected.
W=1 Window hit. No pixels are drawn. The V bit is set to 0 if the pixel lies
within the window; otherwise, it is set to 1. The WVP bit is set to 1
if the pixel lies within the window; otherwise, it is not affected.
W=2 Window miss. If the pixel lies outside the window, the WVP and V
bits are set to 1 and the instruction is aborted (no pixel is drawn).
Otherwise, the pixel is drawn, the V bit is set to 0, and the WVP bit
is unaffected.
W=3 Window clip. If the pixel lies outside the window, the V bit is set to
1 and the instruction is aborted (no pixels are drawn). Otherwise,
the pixel is drawn and the V bit is set to O.
For more information, see Section 7.10, Window Checking, on page 7 -27.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
Shift Register
Transfers When this instruction is executed and the SRT bit is set, normal memory
read and write operations become SRT reads and writes. Refer to Section
9.10.2, Video Memory Bulk Initialization, on page 9-28 for more informa-
tion.
Machine
States The states consumed depend on the operation selected, as indicated below.
Pixel Processing Operation Window
Violation
PSIZE Replace Boolean ADD ADDS SUB SUBS MIN/MAX W=1 W=2 W=3
1,2,4,8 4+(3).10 6+(3),12 7+(3),13 7+(3),13 7+(3),13 8+(3),14 7+(3),13 5,8 3,6 5,8
16 4+(1 ),8 6+(1 ),10 6+(1),10 7+(1),11 7+(1 ),11 8+(1),12 7+(1),11 5,8 3,6 5,8
Status Bits NUn affected
C Unaffected
Z Unaffected
V 1 if a window violation occurs, 0 otherwise; unaffected if window
clipping is not used.
12-68
Draw and Advance DRAV
Examples These DRAV examples use the following implied operand setup.
Register File B: I/O Registers:
DPTCH (83) = 200h CONVDP = 0016h
OFFSET (84) = 00010000h
WST ART (85) = 001 OOOOOh
WEND (86) = 003C0040h
COLOR1 (89) = FFFFFFFFh
Assume that memory contains the following values before instruction exe-
cution:
Address Data
00018040h 8888h
Code Before After
AO A1 PSIZE PP W PMASK AO @18040h
DRAV Al,AO 00400040h 00100010h 0001h 00000 00 OOOOh 00500050h 8889h
DRAV Al,AO 00400020h 00100010h 0002h 00000 00 OOOOh 00500030h 888Bh
DRAV Al,AO 00400010 00100010h 0004h 00000 00 OOOOh 00500020h 888Fh
DRAV Al,AO 00400008 00100010h 0008h 00000 00 OOOOh 00500018h 88FFh
DRAV Al,AO 00400004 00100010h 0010h 00000 00 OOOOh 00500014h FFFFh
DRAV Al,AO 00400004 OOOOFFFFh 0010h 01010 00 OOOOh 00400003h OOOOh
DRAV Al,AO 00400004 FFFFOOOOh 0010h 10011 00 OOOOh 003FOO04h OOOOh
DRAV Al,AO 00400004 00010001h 0010h 00000 11 OOOOh 00410005h OOOOh
DRAV Al,AO 00400004h 00400004h 0010h 00000 00 OOFFh 00800008h FFOOh
12-69
DSJ Decrement Register and Skip Jump
Syntax DSJ Rd, Address
Execution Rd - 1 -+ Rd
If Rd ¢ 0, then (offset x 16) + PC' -+ PC
If Rd = 0, then go to next instruction
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
o o oIR Rd
offset
Description DSJ decrements the contents of the destination register by 1. Depending
on the decremented value of Rd, the TMS3401 0 either jumps or skips the
jump:
• Rd - 1 ¢ 0
The TMS3401 0 jumps. The current PC points to the instruction word
that immediately follows the second word of the DSJ instruction. The
signed word offset is converted to a bit offset by multiplying by 16.
The new PC address is then obtained by adding the resulting signed
offset (offset x 16) to the address of the next instruction.
• Rd - 1 = 0
The TMS3401 0 skips the jump and continues and program execution
with the next sequential instruction.
The Address operand is a 32-bit address. The assembler calculates the
offset as (Address - PC')/16; this results in a jump range of -32,768 to
+32,767 words. (The offset is the second instruction word of the opcode.)
The DSJ instruction is useful for large loops involving a counter. For
shorter loops, the assembler translates this into a DSJS instruction.
Machine
States 3,9 (Jump)
2,8 (No jump)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
A5 A5 Jump taken?
DSJ A5,LOOP 00000009h 00000008h Yes
DSJ A5,LOOP 00000001h OOOOOOOOh No
DSJ A5,LOOP OOOOOOOOh FFFFFFFFh Yes
12-70
Conditionally Decrement Register
and Skip Jump DSJEQ
Syntax DSJ EQ Rd, Address
Execution If Z = 1, then Rd - 1 -+ Rd
If Rd ¢ 0, then PC' + (offset x 16) -+ PC
If Rd = 0, then go to next instruction
If Z = 0, then go to next instruction
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
o o R Rd
offset
Description The DSJ EO instruction evaluates the status Z bit. Depending on the value
of that bit, the TMS3401 0 either skips the jump, or decrements Rd and then
makes a decision to jump or skip the jump:
• Z :::: 1
The TMS34010 decrements the contents of the destination register
by 1.
Rd - 1 ¢ 0
The TMS34010 jumps relative to the current PC. The current
PC points to the instruction word that immediately follows the
second word of the DSJ EO instruction. The signed word offset
is converted to a bit offset by multiplying by 16. The new PC
address is then obtained by adding the resulting signed offset
(offset x 16) to the address of the next instruction.
Rd - 1 :::: 0
The TMS34010 skips the jump and continues program exe-
cution at the next sequential instruction.
• Z:::: 0
The TMS3401 0 skips the jump and continues program execution at
the next sequential instruction.
The Address operand is a 32-bit address. The assembler calculates the
offset as (Address - PC')/16; this results in a jump range of -32,768 to
+32,767 words. (The offset is the second instruction word of the opcode.)
You can use this instruction after an explicit or implicit compare to O. Ad-
ditional information on these types of compares can be obtained in the
CMP and CMPI, and MOVE-to-register instructions, respectively.
Machine
States 3,9 (Jump)
2,8 (No jump)
Status Bits NUn affected
C Unaffected
Z Unaffected
V Unaffected
12-71
Conditionally Decrement Register
DSJEQ and Skip Jump
Examples Before After
A5 NCZV A5 Jump taken?
DSJEQ AS,LOOP 00000009h xx1x 00000008h Yes
DSJEQ AS,LOOP 00000001h xx1x OOOOOOOOh No
DSJEQ AS,LOOP OOOOOOOOh xx1x FFFFFFFFh Yes
DSJEQ AS,LOOP 00000009h xxOx 00000009h No
DSJEQ AS,LOOP 00000001h xxOx 00000001 h No
DSJEQ AS,LOOP OOOOOOOOh xxOx OOOOOOOOh No
12-72
Conditionally Decrement Register
and Skip Jump DSJNE
Syntax DSJNE Rd. Address
Execution If Z = 0, then Rd - 1 -+ Rd
If Rd ¢ 0, then PC' + (offset x 16) -+ PC
If Rd = 0. then go to next instruction
If Z = 1, then to to next instruction
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
o oIR Rd
offset
Description The DSJ N E instruction evaluates the status Z bit. Depending on the value
of that bit, the TMS3401 0 either skips the jump, or decrements Rd and then
makes a decision to jump or skip the jump:
• Z == 0,
The TMS34010 decrements the contents of the destination register
by 1.
Rd - 1 ¢ 0
The TMS34010 jumps relative to the current PC. The current
PC points to the instruction word that immediately follows the
second word of the DSJ N E instruction. The signed word offset
is converted to a bit offset by mUltiplying by 16. The new PC
address is then obtained by adding the resulting signed offset
(offset x 16) to the address of the next instruction.
Rd - 1 == 0
The TMS34010 skips the jump and continues program exe-
cution at the next sequential instruction.
• Z == 1
The TMS3401 0 skips the jump and continues program execution at
the next sequential instruction.
The Address operand is a 32-bit address. The assembler calculates the
offset as (Address - PC')/16; this results in a jump range of -32,768 to
+32,767 words. (The offset is the second instruction word of the opcode.)
You can use this instruction after an explicit or implicit compare to O. Ad-
ditional information on these types of compares can be obtained in the
CMP, CMPI, and MOVE-to-register instructions.
Machine
States 3,9 (Jump)
2,8 (Nojump)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
12-73
Conditionally Decrement Register
DSJNE and Skip Jump
Examples Code Before After
A5 NCZV A5 Jump taken?
DSJNE AS,LOOP 00000009h xx1x 00000009h No
DSJNE AS,LOOP 00000001h xx1x 00000001 h No
DSJNE AS,LOOP OOOOOOOOh xx1x OOOOOOOOh No
DSJNE AS,LOOP 00000009h xxOx 00000008h Yes
DSJNE AS,LOOP 00000001h xxOx OOOOOOOOh No
DSJNE AS,LOOP OOOOOOOOh xxOx FFFFFFFFh Yes
12-74
Decrement Register and Skip Jump - Short DSJS
Syntax OSJS Rd, Address
Execution Rd - 1 -+ Rd
If Rd :to 0, then PC' + (offset x 16) -+ PC
If Rd = 0, then go to next instruction
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I0 0 ID I offset IR Rd
Fields o is a 1 -bit direction bit (from PC' to Address):
0=0 - forward jump
0=1 - backward jump
Description DSJS decrements the contents of the destination register by 1. Depending
on the result, the TMS3401 0 either jumps or skips the jump:
• Rd - 1 :to 0
The TMS34010 jumps relative to PC'. PC' points to the instruction
word that immediately follows the DSJS instruction. Internally, the
5-bit offset is multiplied by 16 to convert it to a bit offset. This allows
a jump range of -30 to +32 words from the PC.
If direction bit 0 = 0
The new PC address is obtained by adding the resulting offset
to PC'.
If direction bit 0 = 1
The new PC address is obtained by subtracting the resulting
offset from PC'.
• Rd - 1 = 0
The TMS34010 skips the jump and continues program execution at
the next sequential instruction.
The Address operand is a 32-bit address. The assembler calculates the
offset as (Address - PC')/16; this results in a jump range of -30 to +32
words from the PC. (The offset is encoded as part of the instruction word.)
This instruction is useful for coding tight loops for cache-resident routines.
Machine
States 2,5 (Jump)
3,6 (No jump)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
A5 A5 Jump taken?
DSJS A5,LOOP 00000009h 00000008h Yes
DSJS A5,LOOP 00000001h OOOOOOOOh No
DSJS A5,LOOP OOOOOOOOh FFFFFFFFh Yes
12-75
EINT Enable Interrupts
Syntax EINT
EXBcution 1 -+ IE
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
1 0 0 0 0 0 0 0 0 0 0 01
Description EINT sets the global interrupt enable bit (IE) to 1, allowing interrupts to be
enabled. When IE=1, individual interrupts are enabled by setting the ap-
propriate bits in the INTENB interrupt mask register. The rest of the status
register is unaffected.
The DINT instruction disables interrupts.
Machine
States 3,6
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
IE 1
Examples Code Before After
ST ST
EINT 00000010h 00200010h
EINT 00200010h 00200010h
12-76
Initiate Emulation EMU
Syntax EMU
Execution ST -+ Rd and conditionally enter emulator mode
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
Description The EMU instruction pulses the EMUA pin and samples the RUN/EMU pin.
If the RUN/EMU pin is in the RUN state, the EMU instruction acts as a NOP.
If the pin is in the EMU state, emulation mode is entered. This instruction
is not intended for general use; refer to the TMS34010 XDS/22 User's
Guide for more information.
Machine
States 8,11 (or more if EMU mode is entered)
Status Bits N Indeterminate
C Indeterminate
Z Indeterminate
V Indeterminate
12-77
EXG F Exchange Field Definition
Syntax EXGF Rd [, FJ
Execution Rd -+ FSO, FEO or Rd -+ FS1, FE1
FSO, FEO -+ Rd or FS1, FE1 -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
11 0 0 1 1F 0 0 01 Rd 1
Description EXGF exchanges the six LSBs of the destination register with the selected
six bits of field information (field size and field extension). Bit 5 of the 6-bit
quantity in Rd is exchanged with the field extension value. The upper 26
bits of Rd are cleared.
Status Register
EXG F's F parameter is optional:
F::O selects FSO, FEO to be exchanged
F::1 selects FS1, FE1 to be exchanged
If you do not specify an F parameter, the default is O.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before
A5 ST A5 ST
EXGF AS,O FFFFFFCOh FOOOOFFFh 0000003Fh FOOOOFCOh
EXGF AS,l FFFFFFCOh FOOOOFFFh 0000003Fh F000003Fh
12-78
Exchange Program Counter EXGPC
Syntax EXGPC Rd
Execution Rd --+ PC, PC' --+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 0 1 IR Rd
I
Description EXGPC exchanges the next program counter value with the destination re-
gister contents. After this instruction has been executed, the destination
register contains the address of the instruction immediately following the
EXG PC instruction.
Note that the TMS34010 sets the four LSBs of the program counter to 0
(word aligned).
This instruction provides a "quick call" capability by saving the return ad-
dress in a register (rather than on the stack). The return from the call is
accomplished by repeating the instruction at the end of the "subroutine."
Note that the subroutine address must be reloaded following each call-
return operation.
Machine
States 2,5
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Before After
A1 PC A1 PC
EXGPC Al 00001C10h 00002080h 00002090h 00001C10h
EXGPC Al 00001C50h 00002080h 00002090h 00001C50h
12-79
FILL Fi II Array with Processed Pixels - Linear
Syntax FILL L
Execution COLOR1 pixels -+ pixel array (with processing)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
10000 0000 o 01
Description FILL processes a set of source pixel values (specified by the COLOR1 reg-
ister) with a destination pixel array.
This instruction operates on a two-dimensional array of pixels using pixels
defined in the COLOR1 register. As the FILL proceeds, the source pixels
are combined with destination pixels based on the selected graphics oper-
ations.
Note that the L parameter in the instruction syntax does not represent a
value or a register - the L is entered as part of the instruction and identifies
the starting address of the pixel array as an L address. That is, the in-
struction is entered as FILL L.
The following set of implied operands govern the operation of the in-
struction and define both the source pixels and the destination array.
Implied
Operands B File Registers
Register Name Format Description
92t DADDR Linear Pixel array starting address
93 DPTCH Linear Pixel array pitch
97 DYDX XY Pixel array dimensions (rows:columns)
99 COLOR1 Pixel Fill color or 16-bit pattern
91o-914t Reserved registers
I/O Registers
Address Name Description and Operations
COOOO090h CONTROL PP- Pixel processing operations (22 options)
T - Transparency operation
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOO0160h PMASK Plane mask - pixel format
t Changed by FI LL during execution.
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
FILL instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Destination
Array The contents of the DADDR, DPTCH, and DYDX registers define the lo-
cation of the destination pixel array:
• At the outset of the instruction, DADDR contains the linear address
. of the pixel with the lowest address in the array.
12-80
Fi II Array with Processed Pixels - Linear FILL
During instruction execution, DADDR points to the next pixel (or
word of pixels) to be modified in the destination array. When the ar-
ray transfer is complete, DADDR points to the linear address of the
pixel following the last pixel written.
• DPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the destination array. DPTCH must be a multiple of
16, except when a single pixel-width line is drawn (DY=1). In this
case, DPTCH may be any value.
• DYDX specifies the dimensions of the destination array in pixels. The
DY portion of DYDX contains the number of rows in the array, while
the DX portion contains the number of columns.
Pixel
Processing Set the PPOP field in the CONTROL register to select a pixel processing
operation. This operation is applied to the pixel as it is moved to the des-
tination location. There are 16 Boolean and e arithmetic operations; the
default operation at reset is replace (S ... D). Note that the destination data
is read through the plane mask and then processed. The 6 arithmetic op-
erations do not operate with pixel sizes of one or two bits per pixel. For
more information, see Section 7.7, Pixel Processing, on page 7-15.
Window
Checking Window checking cannot be used with this instruction. The contents of
the WSTART and WEN D registers are ignored.
Corner Adjust There is no corner adjust for this instruction. The direction of the FI LL is
fixed as increasing linear addresses.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Interrupts This instruction can be interrupted at a word or row boundary of the desti-
nation array. When the FILL is interrupted, the TMS34010 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH and B1 o-B14 contain intermediate values. DADDR
points to the linear address of the next word of pixels to be modified after
the interrupt is processed.
Before executing the RETI instruction to return from the interrupt, restore
any B-file registers that were modified (also restore the CONTROL register
if it was modified). This allows the TMS34010 to resume the FILL cor-
rectly.
Plane Mask The plane mask is enabled for this instruction.
Shift Register
Transfers If the SRT bit in the DPYCTL register is set, each memory read or write in-
itiated by the FI LL generates a shift reg ister transfer read or write cycle at
the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.) See Section 9.10.2,
Video Memory Bulk Initialization, on page 9-28 for more information.
Machine
States See Section 13.3, FILL Instructions Timing.
12-81
FILL Fill Array with Processed Pixels - Linear
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples These FILL examples use the following implied operand setup.
Register File B: I/O Registers:
DADDR (B2) = 00002010h PSIZE = 0008h
DPTCH (B3) = 00000080h
DYDX (B7) = 0002000Dh
COLOR1 (B9) = 30303030h
Assume that memory contains the following values before instruction exe-
cution.
Linear Data
Address
02000h 1100h, 3322h, 5544h, 7766h, 9988h, BBAAh, DDCCh, FFEEh
02080h 1100h, 3322h, 5544h, 7766h, 9988h, BBAAh,DDCCh, FFEEh
Example 1 This example uses the pixel processing replace (S -+ D) operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h 1100h, 3030h, 3030h, 3030h, 3030h, 3030h, 3030h, FF30h
02080h 1100h, 3030h, 3030h, 3030h, 3030h, 3030h, 3030h, FF30h
Example 2 This example uses the (S and 0) -+ 0 pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = 2COOh (T=O,
PP=01 01 0).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h 1100h, 0302h, 4544h, 4746h, 8988h, 8B8Ah, CDCCh,FFCEh
02080h 1100h, 0302h, 4544h, 4746h, 8988h, 8B8Ah, CDCCh,FFCEh
Example 3 This example uses transparency and the (S and D) -+ 0 pixel processing
operation. Before instruction execution, PMASK = OOOOh and CONTROL
= 0420h (T=1, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h 1100h, 3020h, 1 044h, 3020h, 1 088h, 3020h, 10CCh, FF20h
02080h 1100h, 3020h, 1044h, 3020h, 1088h, 3020h, 10CCh, FF20h
12-82
Fill Array with Processed Pixels - Linear FILL
Example 4 This example uses plane masking - the four MSBs are masked. Before in-
struction execution, PMASK = OFOFOh and CONTROL = OOOOh (T=O,
PP=OOOOO).
After instruction execution, memory contains the following values:
linear Data
Address
02000h 1100h, 3020h, 5040h, 7060h, 9080h, BOAOh, DOCOh, FFEOh
02080h 1100h, 3020h, 5040h, 7060h, 9080h, BOAOh, DOCOh, FFEOh
12-83
FILL Fill Array with Processed Pixels - XY
Syntax FILL XV
Execution COLOR1 pixels ~ pixel array (with processing)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 432 o
I0 0 0 0 000 o 0
Description FILL processes a set of source pixel values (specified by the COLOR1 reg-
ister) with a destination pixel array.
This instruction operates on a two-dimensional array of pixels using pixels
defined in the COLOR1 register. As the FILL proceeds, the source pixels
are combined with destination pixels based on the selected graphics oper-
ations.
Note that the XV parameter in the instruction syntax does not represent a
value or a register - it is entered as part of the instruction and identifies the
starting address of the pixel array as an XY address. That is, the instruction
is entered as FILL L, XY.
The following set of implied operands govern the operation of the in-
struction and define both the source pixels and the destination array.
Implied
Operands B File Registers
Register Name Format Description
82tt: DADDR XV Pixel array starting address
83 DPTCH Linear Pixel array pitch
84 OFFSET Linear Screen origin (address of 0,0)
85 WSTART XV Window starting corner
86 WEND XV Window ending corner
87tt: DVDX XV Pixel array dimensions (rows:columns)
89 COLOR1 Pixel Fill color or 16-bit pattern
81o-814t Reserved registers
I/O Registers
Address Name Description and Elements (Bits)
COOOO080h CONTROL PP- Pixel processing operations (22 options)
W - Window checking operation
T - Transparency operation
COOO0140h CONVDP XV -to-linear conversion (destination pitch)
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOO0160h PMASK Plane mask - pixel format
t Changed by FI LL during execution.
t: Used for common rectangle function with window hit operation (W=1).
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
FILL instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
12-84
Fill Array with Processed Pixels - XY FILL
Destination
Array The location of the destination pixel array is defined by the contents of the
DADDR, DPTCH, CONVDP, OFFSET, and DYDX registers. At the outset
of the instruction, DADDR contains the XV address of the pixel with the
lowest address in the array. It is used with OFFSET and CONVDP to cal-
culate the linear address of the starting location of the array. DPTCH con-
tains the linear difference in the starting addresses of adjacent rows of the
destination array (typically this is the screen pitch). DPTCH must be a
power of two (greater than or equal to 16) and CONVDP must be set to
correspond to the DPTCH value. CONVDP is computed by operating on
the DPTCH register with the LMO instruction; it is used for the XY calcu-
lations involved in XY addressing and window clipping. DYDX specifies
the dimensions of the destination array in pixels. The DY portion of DYDX
contains the number of rows in the array, while the DX portion contains the
number of columns. During instruction execution, DADDR points to the
next pixel (or word of pixels) to be modified in the destination array. When
the array transfer is complete, DADDR points to the linear address of the
pixel following the last pixel written. This is that pixel on the last row that
would have been written had the array transfer been wider in the X dimen-
sion.
Pixel
Processing Pixel processing can be used with this instruction. The PPOP field of the
CONTROL register specifies the pixel processing operation that is applied
to pixels as they are processed with the destination array. There are 16
Boolean and 6 arithmetic operations; the default case at reset is the replace
(S -+ D) operation. Note that the destination data is read through the plane
mask and then processed. The 6 arithmetic operations do not operate with
pixel sizes of one or two bits per pixel. For more information, see Section
7.7, Pixel Processing, on page 7-15.
Window
Checking The window operations described in Section 7.10, Window Checking, on
page 7-27. can be used with this instruction. You can select window pick,
violation detect, or preclipping by setting the W bits in the CONTROL reg-
ister to 1, 2, or 3, respectively. Window pick modifies the DADDR and
DYDX registers to correspond to the common rectangle formed by the
destination array and the clipping window defined by WSTART and WEND.
DADDR is set to the XY address of the pixel with the lowest address in the
common rectangle, while DYDX is set to the X and Y dimensions of the
rectangle. If no window operations are selected, the WSTART and WEN D
registers are ignored. At reset, no window operations are enabled.
Corner Adjust There is no corner adjust for this instruction. The direction of the FILL is
fixed as increasing linear addresses.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Interrupts This instruction can be interrupted at a word or row boundary of the desti-
nation array. When the FI LL is interrupted, the TMS34010 sets the PBX
bit in the status register and then pushes the status register on At this time,
DPTCH and B1 o-B14 contain intermediate values. DADDR points to the
linear address of the next word of pixels to be modified after the interrupt
is processed.
12-85
FILL Fill Array with Processed Pixels - XY
Before executing the RETI instruction to return from the interrupt, restore
any B-file registers that were modified (also restore the CONTROL register
if it was modified). This allows the TMS34010 to resume the FI LL cor-
rectly.
Plane Mask The plane mask is enabled for this instruction.
Shift Register
Transfers If the SRT bit in the DPYCTL register is set, each memory read or write in-
itiated by the FI LL generates a shift register transfer read or write cycle at
the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.) See Section 9.10.2,
Video Memory Bulk Initialization, on page 9-28 for more information.
Machine
States See Section 13.3, FILL Instructions Timing.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V 1 if a window violation occurs, 0 otherwise; unaffected if window
clipping is not enabled
Examples These FILL examples use the following implied operand setup.
Register File B: I/O Registers:
DADDR (B2) = 00520007h CONVDP = 0017h
DPTCH (B3) = 00000100h PSIZE = 0004h
OFFSET (B4) = 00010000h PMASK = OOOOh
WSTART (B5) = 0030000Ch CONTROL = OOOOh
WEND (B6) = 00530014h (W=OO, T=O, PP=OOOOO)
DYDX (B7) = 00030012h
COLOR1 (B9) = FFFFFFFFh
Assume that memory contains the following values before instruction exe-
cution.
linear Data
Address
15200h 3210h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, BA98h, FEDCh
15300h 3210h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, BA98h, FEDCh
15400h 3210h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, BA98h, FEDCh
Example 1 This example uses the replace (S -+ D) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
linear Data
Address
15200h 3210h, F654h, FFFFh, FFFFh, FFFFh, FFFFh, BA9Fh, FEDCh
15300h 3210h, F654h, FFFFh, FFFFh, FFFFh, FFFFh, BA9Fh, FEDCh
15400h 3210h, F654h, FFFFh, FFFFh, FFFFh, FFFFh, BA9Fh, FEDCh
12-86
Fill Array with Processed Pixels - XY FILL
XV Addressing
X Address
Y 0 0 0 0 0 000 000 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 111
0123456789ABCDEF0123456789ABCDEF
A
d 52 0 1 2 3 4 5 6 F F F F F F F F F F F F F F F F F F 9 ABC 0 E F
d
r 53 0 1 2 3 4 5 6 F F F F F F F F F F F F F F F F F F 9 ABC 0 E F
e
s 54 0 1 2 3 4 5 6 F F F F F F F F F F F F F F F F F F 9 ABC 0 E F
s
Example 2 This example uses the (D XOR S) -+ D pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = 2800h (T=O,
W=OO, PP=01 01 0).
After instruction execution, memory contains the following values:
X Address
Y 0 0 0 000 0 0 0 0 000 000 1 1 1 1 1 1 1 1 1 111 1 111
0123456789ABCDEF0123456789ABCDEF
A
d 52 0 1 2 3 4 5 6 8 7 6 5 4 3 2 1 0 FED C B A 9 8 7 9 ABC 0 E F
d
r 53 0 1 2 3 4 5 6 8 7 6 5 4 3 2 1 0 FED C B A 9 8 7 9 ABC 0 E F
e
s 54 0 1 2 3 4 5 6 8 7 6 5 4 3 2 1 0 FED C B A 9 8 7 9 ABC 0 E F
s
Example 3 This example uses transparency, the (D subs S) -+ D pixel processing op-
eration. Before instruction execution, COLOR1 = 88888888h, PMASK =
OOOOh, and CONTROL = 4C20h (T=1, W=OO, PP=1 0011).
After instruction execution, memory contains the following values:
X Address
Y 0 0 0 000 0 0 0 0 000 0 0 0 1 111 1 1 1 1 1 1 1 1 1 111
0123456789ABCDEF0123456789ABCDEF
A
d 52 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 ABC D E F
d
r 53 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 ABC D E F
e
s 54 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 ABC D E F
s
12-87
FILL Fill Array with Processed Pixels - XY
Example 4 This example uses window operation 3 - the destination is clipped. Before
instruction execution, PMASK = OOOOh and CONTROL = OOCOh (T=O,
W=11, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
Y 0 0 000 0 0 0 0 0 0 0 0 000 1 1 111 111 1 1 1 1 1 1 1 1
0123456789ABCDEF0123456789ABCDEF
A
d 520123456789ABFFFFFFFFF56789ABCDEF
d
r ~0123456789ABFFFFFFFFF56789ABCDEF
e
s 540123456789ABCDEF0123456789ABCDEF
s
Example 5 This example uses plane masking - the most significant bit is masked. Be-
fore instruction execution, PMASK = 8888h and CONTROL = OOOOh
(T=O, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
Y 0 0 0 0 0 0 0 0 0 0 000 000 1 1 1 1 1 1 1 1 1 1 111 1 1 1
0123456789ABCDEF0123456789ABCDEF
A
d 52 0 1 2 3 4 5 6 7 F F F F F F F F 7 7 7 7 7 7 7 7 F 9 ABC D E F
d
r 53 0 1 2 3 4 5 6 7 F F F F F F F F 7 7 7 7 7 7 7 7 F 9 ABC D E F
e
s 54 0 1 2 3 4 5 6 7 F F F F F F F F 7 7 7 7 7 7 7 7 F 9 ABC D E F
s
12-88
Get Program Counter into Register GETPC
Syntax GETPC Rd
Execution PC' -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
1 0 0 0 0 0 0 0 0 01 R Rd I
Description GETPC increments the PC contents by 16 to point past the GETPC in-
struction, and copies the value into the destination register. Execution
continues with the next instruction. You can use GETPC with the EXGPC
and JUMP instructions for quick call on jump operations. You can also use
G ETPC to access relocatable data areas whose position relative to the code
area is known at assembly time.
Machine
States 1,4
Status Bits NUn affected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
PC A1
GETPC Al 00001 BDOh 00001BEOh
GETPC Al 00001C10h 00001C20h
12-89
GETST Get Status Register into Register
Syntax GETST Rd
Execution ST -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 oIR Rd I
Description GETST copies the contents of the status register into the destination regis-
ter.
Status Register
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
PC A1
GETST Al 20200010h 20200010h
GETST Al 00000010h 00000010h
12-90
Increment Register INC
Syntax INC Rd
Execution Rd + 1 -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 0 R Rd I
Description INC adds 1 to the contents of the destination register and stores the result
in the destination register. This instruction is an alternate mnemonic for
ADDK 1,Rd.
You can accomplish multiple-precision arithmetic by using INC in con-
junction with the ADDC instruction.
Machine
States 1,4
Status Bits N a
1 if the result is negative, otherwise
C 1 if there is a carry, 0 otherwise
Z a
1 if the result is 0, otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
A1 A1 NCZV
INC Al OOOOOOOOh 00000001h 0000
INC Al OOOOOOOFh 00000010h 0000
INC Al FFFFFFFFh OOOOOOOOh 0110
INC Al FFFFFFFEh FFFFFFFFh 1000
INC Al 7FFFFFFFh 80000000h 1001
12-91
JAcc Jump Absolute Conditional
Syntax JAcc Address
Execution If condition true, then Address ~ PC
If condition false, then go to next instruction
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
1 1 0 01 code 1 1 0 0 0 0 0 0 0
16 LSBs of Addre.ss
16 MSBs of Address
Fields code is a 4-bit digit that identifies the condition for the jump within
the opcode. (See the conditioncodes table below.)
Description The JAcc instruction conditionally jumps to an absolute address. The cc
is part of a mnemonic that represents the condition for the jump; for exam-
ple, if cc is UC, then the instruction is JAUC. (See the condition mne-
monics and codes listed below.) If the specified condition is true, the
TMS34010 jumps to the address and continues execution from that point.
If the specified condition is false, the TMS3401 0 skips the jump and con-
tinues execution at the next sequential instruction. Note that the lower four
bits of the program counter are set to 0 (word aligned).
The Address operand in the syntax represents the 32-bit absolute address.
Note that the second and third instruction words contain the address for the
jump.
The JAcc instructions are usually used in conjunction with the CMP and
CMPI instructions. The JAV and JANV instructions can also be used to
detect window violations or CPW status.
Condition
Codes Mnemonic Result of Compare Status Bits Code
Unconditional JAUC - Unconditional don't care 0000
Compares
Unsigned JALO - Ost lovverthan Src C 0001
Compares (JAC)
JALS JAYLE Ost lovver or same as Src C+Z 0010
JAHI JAYGT Ost higher than Src CoZ 0011
JAHS - Ost higher or same as Src C 1001
JANC
JAEO
(JAZ)
- Ost = Src Z 1010
JANE - Ost ¢ Src Z 1011
(JANZ) .
Signed JALT JAXLE Ost < Src (N o_V) +_( NoV) 0100
Compares JALE - Ost :S Src (N ° V + (N ° V) + Z 0110
JAGT - Ost> Src (N ° V Z) + ( N ° y ° Z)
0 0111
JAGE JAXGT Ost> Src (N ° V) + (N ° V) 0101
JAEO - Ost ~ Src Z 1010
(JAZ)
JANE - Ost ¢ Src Z 1011
(JANZ)
Compare to JAZ JAYZ Result = zero Z 0101
Zero JANZ JAYNZ Result ¢ zero Z 1011
JAP - Result is positive i'Joz 0001
JAN JAXZ Result is negative N 1110
JANN JAXNZ Result is nonnegative i'J 1111
12-92
Jump Absolute Conditional JAcc
Condition
Codes
(continued) Mnemonic Result of Compare Status Bits Code
General JAZ JAYZ Result is zero Z 1010
Arithmetic JANZ JAYNZ Result is nonzero Z 1011
JAC JAYN Carry set on resu It C 1000
JANC JAYNN No carryon result C 1001
JAB - Borrow set on result C 1000
(JAC)
JANB - No borrow on result C 1001
JANC
JAVt JAXN Overflow on result V 1100
JANVt JAXNN No overflow on result V 1101
Note: A mnemonic code in parentheses is an alternate code for the preceding code.
t Also used for window clipping
+ Logical OR
.: Logical AND
Logical NOT
Machine
States 3,6 (Jump)
4,7 (No jump)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Flags for Branch Code Flags for Branch
NCZV NCZV NCZV NCZV NCZV NCZV
JAUC HERE xxxx JAV HERE xxx1
JAP HERE OxOx JANZ HERE xxOx
JALS HERE xx1x x1xx JANN HERE Oxxx
JAHI HERE xOOx JANV HERE xxxO
JALT HERE Oxx1 1xxO JAN HERE 1xxx
JAGE HERE OxxO 1xx1 JAB HERE x1xx
JALE HERE Oxx1 1xxO xx1x JANB HERE xOxx
JAGT HERE OxOO 1 x01 JALO HERE x1xx
JAC HERE x1xx JAHS HERE xOOx xx1x
JANC HERE xOxx JANE HERE xxOx
JAZ HERE xx1x JAEQ HERE xx1x
Note that the TMS34010 jumps when anyone or more of the Flags for
Branch listed above are set as indicated.
12-93
JRcc Jump Relative Conditional - ± 127 Words
Syntax J Ree Address
Execution If condition true, then offset + PC' ~ PC
If condition false, then go to next instruction
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I1 0 0 I code offset
Fields code is a 4-bit digit that identifies the condition for the jump within
the opcode. (See the condition codes table below.)
Description The J Ree instruction conditionally jumps to an address that is relative to the
current PC. The ee is part of a mnemonic that represents the condition for
the jump; for example, if ee is UC, then the instruction is JAUC. (See the
condition mnemonics and codes listed below.) If the specified condition
is true, the TMS3401 0 jumps to a new location. The assembler calculates
the address of this location by adding the address of the next instruction
(PC') to the signed word offset. The TMS3401 0 then continues execution
from this point. If the specified condition is false, the TMS3401 0 skip the
jump and continues execution at the next sequential instruction.
The Address operand in the syntax represents the 32-bit relative address.
The assembler calculates the offset as (Address - PC')/16 and inserts the
resulting 8-bit offset into the opcode. The range for this form of the JRee
instruction is ± 127 words (excluding 0).
If the offset is outside the range of ±127 words, the assembler automat-
ically substitutes the longer form of the J Ree instruction. If the offset is 0,
the assembler substitutes a NOP instruction. The assembler does not ac-
cept an address which is externally defined or an address which is relative
to a different section than the PC. Note that the four LSBs of the program
counter are always 0 (word aligned).
The JRee instructions are usually used in conjunction with the CMP and
CMPI instructions. The JRV and JRNV instructions can also be used to
detect window violations or CPW status.
Condition
Codes Mnemonic Result of Compare Status Bits Code
Unconditional JRUC - Unconditional don't care 0000
Compares
Unsigned JRLO - Ost lower than Src C 0001
Compares (JRC)
JRLS JRYLE 05t lower or same as Src C+Z 0010
JRHI JRYGT 05t higher than Src CoZ 0011
JRHS - 05t higher or same as Src C 1001
JRNC
JREQ - 05t = Src Z 1010
(JRZ)
JRNE - 05t ¢: Src Z 1011
(JRNZ)
12-94
Jump Relative Conditional - ±127 Words JRcc
Condition
Codes
(continued) Mnemonic Result of Compare Status Bits Code
Signed JRLT JRXLE Dst < Src (N ·_V) "t....( N • V) 0100
Compares JRLE - Ost S Src (N • V_+ (N __V)..± Z_ 0110
JRGT - Ost > Src (N • V • Z) + ( N . Y.. • Z) 0111
JRGE JRXGT Ost > Src (N • V) + (N • V) 0101
JREQ - Ost ;;- Src Z 1010
(JRZ)
JRNE - Ost ¢ Src Z 1011
(JRNZ)
Compare to JRZ JRYZ Result = zero Z 0101
Zero JRNZ JRYNZ Result ¢ zero Z 1011
JRP - Result is positive N·Z 0001
JRN JRXZ Result is negative N 1110
JRNN JRXNZ Result is nonnegative N 1111
General JRZ JRYZ Result is zero Z 1010
Arithmetic JRNZ JRYNZ Result is nonzero Z 1011
JRC JRYN Carry set on resu It C 1000
JRNC JRYNN No carryon result C 1001
JRB - Borrow set on result C 1000
(JRC)
JRNB - No borrow on result C 1001
JRNC
JRVt JRXN Overflow on result V 1100
JRNVt JRXNN No overflow on result V 1101
Note: A mnemonic code in parentheses is an alternate code for the preceding code.
t Also used for window clipping
+ Logical OR
• Logical ANO
- Logical NOT
Machine
States 2,5 (Jump)
1,4 (No jump)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Flags for Branch Code Flags for Branch
NCZV NCZV NCZV NCZV NCZV NCZV
JRUC HERE xxxx JRC HERE x1xx
JRP HERE OxOx JRNC HERE xOxx
JRLS HERE xx1x x1xx JRZ HERE xx1x
JRHI HERE xOOx JRNZ HERE xxOx
JRLT HERE Oxx1 1xxO JRV HERE xxx1
JRGE HERE OxxO 1 xx1 JRNV HERE xxxO
JRLE HERE Oxx1 1xxO xx1x JRN HERE 1xxx
JRGT HERE OxOO 1 x01 JRNN HERE Oxxx
Note that the TMS34010 jumps when anyone or more of the Flags for
Branch listed above are set as indicated.
12-95
JRcc Jump Relative Conditional - ±32K Words
Syntax J Rcc Address
Execution If condition true, then offset + PC' - PC
If condition false, then go to next instruction
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
code o o o o o o o
offset
Fields code is a 4-bit digit that identifies the condition for the jump within
the opcode. (See the condition codes table below.)
Description The J Rce instruction conditionally jumps to an address that is relative to the
current PC. The cc is part of a mnemonic that represents the condition for
the jump; for example, if cc is UC, then the instruction is JAUC. (See the
condition mnemonics and codes listed below.) If the specified condition
is true, the TMS3401 0 jumps to a new location. The assembler calculates
the address of this location by adding the address of the next instruction
(PC') to the signed word offset. The TMS3401 0 then continues execution
from this point. If the specified condition is false, the TMS3401 0 skips the
jump and continues execution at the next sequential instruction.
The Address operand in the syntax represents the 32-bit relative address.
The assembler calculates the offset as (Address - PC')/16 and inserts the
resulting offset into the second instruction word of the opcode. The range
for this form of the JRcc instruction is -32,768 to +32,767 words (ex-
cluding 0).
If the offset is 0, the assembler substitutes a NOP instruction. If the address
is out of range, the assembler uses the JAcc instruction instead. The as-
sembler does not accept an address which is externally defined or an ad-
dress which is relative to a different section than the PC. Note that the four
LSBs of the program counter are always 0 (word aligned).
The JRcc instructions are usually used in conjunction with the CMP and
CMPI instructions. The JRV and JRNV instructions can also be used to
detect window violations or CPW status.
Condition
Codes Mnemonic Result of Compare Status Bits Code
Unconditional JRUC - Unconditional don't care 0000
Compares
Unsigned JRLO - Ost lower than Src C 0001
Compares (JRC)
JRLS JRYLE Ost lower or same as Src C+Z 0010
JRHI JRYGT Ost higher than Src CoZ 0011
JRHS - Ost higher or same as Src C 1001
JRNC
JREQ - Ost = Src Z 1010
(JRZ)
JRNE - Ost ¢ Src Z 1011
(JRNZ)
12-96
Jump Relative Conditional - ±32K Words JRcc
Condition
Codes
(continued) Mnemonic Result of Compare Status Bits Code
Signed JRLT JRXLE Dst < Src (N "_V) "t..( N " V) 0100
Compares JRLE - Ost S Src (N " V_+ (N :.Y).:!: Z _ 0110
JRGT - Ost> Src (N " V " Z) + ( N " Y.. " Z) 0111
JRGE JRXGT Ost> Src (N " V) + (N " V) 0101
JREQ - Ost -;;- Src Z 1010
(JRZ)
JRNE - Ost ¢ Src Z 1011
(JRNZ)
Compare to JRZ JRYZ Result = zero Z 0101
Zero JRNZ JRYNZ Result ¢ zero Z 1011
JRP - Result is positive N"Z 0001
JRN JRXZ Result is negative N 1110
JRNN JRXNZ Result is nonnegative N 1111
General JRZ JRYZ Result is zero Z 1010
Arithmetic JRNZ JRYNZ Result is nonzero Z 1011
JRC JRYN Carry set on resu It C 1000
JRNC JRYNN No carryon result C 1001
JRB - Borrow set on result C 1000
(JRC)
JRNB - No borrow on result C 1001
JRNC
JRVt JRXN Overflow on result V 1100
JRNVt JRXNN No overflow on result V 1101
Note: A mnemonic code in parentheses is an alternate code for the preceding code.
t Also used for window clipping
+ Logical OR
" Logical AN 0
- Logical NOT
Machine
States 3,6 (Jump)
4,7 (No jump)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Flags for Branch Code Flags for Branch
NCZV NCZV NCZV NCZV NCZV NCZV
JRUC HERE xxxx JRV HERE xxx1
JRP HERE OxOx JRNZ HERE xxOx
JRLS HERE xx1x x1xx JRNN HERE Oxxx
JRHI HERE xOOx JRNV HERE xxxO
JRLT HERE Oxx1 1xxO JRN HERE 1xxx
JRGE HERE OxxO 1 xx1 JRB HERE x1xx
JRLE HERE Oxx1 1xxO xx1x JRNB HERE xOxx
JRGT HERE OxOO 1 x01 JRLO HERE x1xx
JRC HERE x1xx JRHS HERE xOOx xx1x
JRNC HERE xOxx JRNE HERE xxOx
JRZ HERE xx1x JREQ HERE xx1x
Note that the TMS34010 jumps when anyone or more of the Flags for
Branch listed above are set as indicated.
12-97
JUMP Jump Indirect
Syntax JUMP Rs
Execution Rs -+ PC
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 1 IR Rs I
Description JUMP jumps to the address contained in the source register. The
TMS34010 sets the four LSBs of the program counter to 0 (word aligned).
This instruction can be used in conjunction with the GETPC and/or EXGPC
instructions.
Machine
States 2,5
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
A1 PC PC
JUMP Al 00001EEOh 00555550h 00001EEOh
JUMP Al 00001EE5h 00555550h 00001EEOh
JUMP Al FFFFFFFFh 00555550h FFFFFFFOh
12-98
Line Draw with XV Addressing LINE
Syntax LINE {O,1}
Execution The two execution algorithms for the LINE instruction are explained below.
These algorithms are similar, varying only in their treatment of d=O.
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
11 0 zoo 0 o
Fields The assembler sets bit 7 in the instruction word (the Z bit) to 0 or 1, de-
pending on which LINE algorithm you select:
Z=O selects algorithm 0
Z=1 selects algorithm 1
Description LINE performs the inner loop of Bresenham's line-drawing algorithm. This
type of line draw plots a series of points (Xj,yj) either diagonally or laterally
with respect to the previous point. Movement from pixel to pixel always
proceeds in a dominant lateral direction. The algorithm mayor may not also
increment in the direction with the smaller dimension (this produces a di-
agonal movement). Two XV -format registers supply the XV increment val-
ues for the two possible movements. The LINE instruction maintains a
decision variable, d, that acts as an error term, controlling movement in ei-
ther the dominant or diagonal direction. The algorithm operates in one of
two modes, depending on how the condition d=O is treated.
During LINE execution, some portion of a line [(XO,yO)(X1,y1)] is drawn.
The line is drawn so that the axis with the largest extent has dimension a
and the axis with the least extent has dimension b. Thus, a is the larger (in
absolute terms) of Y1 - YO or x1 - Xo and b is the smaller of the two. This
means that a .?: b .?: O.
The following values must be supplied to draw a line from (XO,YO) to
(X1,Y1):
1) Set the XV pointer (Xi,Yi) in the DADDR register to the initial value
of (xO'YO).
2) Use the line endpoints to determine the major and minor dimensions
(a and b, respectively) for the line draw; then set the DVDX register
to this value (b:a).
3) Place the signed XV increment for a movement in the diagonal (or
minor) direction (d .?: 0 for Z=O, d > 0 for Z=1) in the I NC1 register.
4) Place the signed XV increment for a movement in the dominant (or
major) direction (d < 0 for Z=O, d S 0 for Z=1) in the INC2 register.
5) Set the initial value of the decision variable in register BO to 2b - a.
6) Set the initial count value in the COUNT register to a + 1.
7) Set the LINE color in the COLOR1 register.
8) Set the PATTRN register to all 1s.
12-99
LINE Line Draw with XV Addressing
The LINE instruction may use one of two algorithms, depending on the
value of Z:
Algorithm 0 (Z=O):
While COUNT> 0
COUNT = COUNT - 1
Draw the next pixel
If d > 0
-d = d + 2b - 28
POINTER = POINTER + INC1
Else d = d + 2b;
POINTER = POINTER + INC2
Algorithm 1 (Z=1):
While COUNT> 0
COUNT = COUNT - 1
Draw the next pixel
If d > 0
d = d + 2b - 2a
POINTER = POINTER + INC1
Else d = d + 2b;
POINTER = POINTER + INC2
LINE 1 is commonly used to draw lines with decreasing y values; LINE 0
is used to draw lines with increasing y values. For horizontal lines, use FILL
or LINE O.
Implied
Operands B File Registers
Register Name Format Description
BOt SADDR Integer Decision variable, d
B2t DADDR XY Starting point (Yj:Xj), usually (YO:xO)
B4 OFFSET Linear Screen origin (0,0)
B5 WSTART XY Window starting corner
B6 WEND XY Window ending corner
B7 DYDX XY b:a minor:major line dimensions
B9 COLOR1 Pixel Pixel color to be replicated
B10t COUNT Integer Loop count
B11 INC1 XY Minor axis (diagonal) increment, INC1
B12 INC2 XY Major axis (dominant) increment, INC2
B13t PATTRN Pattern Future pattern register, must be set to all 1s
B14 TEMP - Temporary reg ister
I/O Registers
Address Name Description and Elements (Bits)
COOOOOBOh CONTROL PP- Pixel processing operations
W - Window clipping operation
T - Transparency operation
COOO0140h CONVDP XY-to-linear conversion (destination pitch)
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOOO160h PMASK Plane mask - pixel format
t These registers are changed by instruction execution
12-100
Line Draw with XV Addressing LINE
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
LINE instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Pixel
Processing The PP field in the CONTROL I/O register specifies the operation to be
applied to the pixel as it is written. There are 22 operations; the default case
at reset is the pixel processing replace (S -+ D) operation. For more infor-
mation, see Section 7.7, Pixel Processing, on page 7-15.
Window
Checking Window clipping or pick is selected by setting the W bits in the CONTROL
I/O register to the appropriate value. The WSTART and WEND registers
define the window in XY -coordinate space.
Options include:
o No window clipping. LINE draws the entire line. Neither the WVP or
V bit are affected. WSTART and WEN D are ignored.
1 Window hit. The instruction calculates points but no pixels are actually
drawn. As soon as the pixel to be drawn lies inside the window, the
WVP bit is set, the V bit is cleared, and the instruction is aborted. At
this point, registers BO, B2, B10, B13, and B14 are set so as to draw
the next pixel in the line; BO is set to the value for the pixel beyond the
next pixel on the line. If the line lies entirely outside the window, then
the WVP bit is not affected, the V bit in the status is set, and the in-
struction completes execution.
2 Clip and set WVP. LINE draws pixels until the pixel to be drawn lies
outside the window. At this point, the WVP bit is set, the V bit is set,
and the instruction is aborted. At this point, registers BO, B2, B10, B13,
and B14 are set so as to draw the next pixel in the line; BO is set to the
value for the pixel beyond the next pixel on the line. If the entire line
lies within the window, then the WVP bit is not affected, the V bit
is cleared and the instruction completes execution. The initial value of
WVP does not affect instruction execution.
3 Clip. LINE calculates all the points, but only draws the points that lie
inside the window. The V bit tracks the state of the last pixel. If the
pixel was outside the window, V is set to 1; otherwise, it is O. The in-
struction traverses the entire line.
The default case at reset is no window clipping. For more information, see
Section 7.10, Window Checking, on page 7-25.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register t01. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
Interrupts LINE may be interrupted after every pixel in the line draw except for the last
pixel. If the instruction is interrupted, the PC is decremented by 16 to point
back to the LINE instruction (the one being executed) before the PC is
12-101
LINE Line Draw with XV Addressing
pushed on the stack. Thus, the LINE instruction is resumed upon return
from the interrupt. In order for the LINE to be resumed correctly, any B-file
registers that are modified by the interrupting routine must be restored, and
the RETI instruction must be executed. Note that a LINE instruction that
is aborted because of window checking options 1 or 2 does not decrement
the PC before pushing it on the stack. In this case, the LINE is not resumed
after returning from the interrupt service routine.
Machine
States The total LINE instruction timing is obtained by adding a setup time to a
transfer time:
LINE time = LINE setup time + LINE transfer time
• LINE setup time is the overhead incurred from initiating the LINE
instruction. The setup sequence executes an initialization sequence,
performing any necessary setup operations and translations. The
setup time is a/ways 4 machine states.
• The transfer sequence performs the actual data transfer from the
source register to the destination pixels. Table 12-10 shows LINE
transfer timing. LI N E transfer timing may be influenced by window
and pixel processing operations; their affects are discussed in the list
that follows Table 12-10.
Table 12-10. LINE Transfer Timing
Window Option
W=1 W=2, Interrupt W=3
Instruction W=O (Off) Window Hit On Clip Clipping
LlNEO (3+P)E 5q + 5 (3+ P)E t (3+ P)E + 5q
LINE 1 (3+P)E 5q + 5 (3+ P)E t (3+ P)E + 5q
t Add 5 for a window violation
Key:
E Number of pixels written
q Number of pixels calculated, but not written
P Selected pixel processing operation
Although window operations affect the setup time of most instructions,
they are performed during transfer execution of the LINE instruction, af-
fecting it on a per-pixel basis. Window operations that affect the LINE in-
struction include:
• No window checking
• Window clip: V flag set, LINE aborted on first write outside window
• Window hit: WVP flag set, V flag cleared, abort LINE on first write
inside window
Pixel processing operations influence the LINE transfer timing. (The effects
of other graphics operations, such as plane masking and transparency, are
already included.) Pixel processing consumes 2, 4, 5, or 6 machine states
per pixel, depending on the operation selected. Table 12-11 shows the
effects of pixel processing on LINE timing.
12-102
Line Draw with XV Addressing LINE
Table 12-11. Per-Word Timing Values for Pixel Processing (P)
Other ADDS,SUBS
Replace Booleans SUBS
or ADD MAX or MIN
2 4 5 6
Figure 12-11 illustrates timing for a LIN E 0, drawing a line from (3h,52h)
to (19h,55h).
**************************************************
* Implied operand setup for LINE example (assume *
* that B register and I/O register names are *
* equated with the proper registers) *
**************************************************
MOVI OFFFFFFFOh, BO Decision variable d=2b-a=-16
MOVI 00S20003h, B2 DADDR
MOVI 00000800h, B3 DPTCH (CONVDP=14)
MOVI 00000100h, B4 OFFSET
MOVI 00300003h, BS WSTART
MOVI 00SS002Sh, B6 WEND
MOVI 00030016h, B7 b:a; b=3 and a=22
MOVI 44444444h, B9 COLORI (color of the line)
MOVI 00000017h, BI0 COUNT (a+l)
MOVI 00010001h, Bll Diagonal increment (+1,+1)
MOVI 00000001h, B12 Nondiagonal increment (0,+1)
MOVI OFFFFFFFFh, B13 PATTRN (all Is)
MOVI OOCOh, AO
MOVE AO, @CONTROL W=3, T=O, PP=O,
CLR AO
MOVE AO, @PMASK No plane masking
Figure 12-11. Implied Operand Setup for LINE Timing Example
Figure 12-12. LINE Timing Example
Follow these steps to determine the number of machine states consumed
by this LINE example:
1) The setup time for a LINE instruction is always 4 machine states.
2) Determine the transfer time. Transfer time comprehends window-
ing, the number of pixels drawn, and graphi,cs operations.
a) Windowing: is on for this LINE 0 instruction; as Table 12-10
shows, the transfer timing is (3+P)E + 5Q.
b) Graphics operations: The pixel processing replace operation has
been selected; according to Table 12-11, P=2.
12-103
LINE Line Draw with XV Addressing
c) Number of pixels drawn: Register B10 indicates the total num-
ber of pixels in the line (23). Since the line fits within the win-
dow, all pixels calculated are drawn; thus, E = 23 and 0=0.
The total machine states required for this instruction are:
LINE time = LINE setup time + LI N E transfer time
= 4 + (3+P)E + 50
= 4 + (3+2) x 23 + 0
= 119 states
119 states are needed to draw these 23 pixels.
The LINE instruction may be interrupted on any pixel boundary during the
transfer portion of the algorithm. The context of the LI N E is saved in re-
served registers; the PC is decremented before it is pushed on the stack, so
that execution returns to the LINE opcode. This operation takes 20 ma-
chine states for the interrupt to be recognized. The time for the context
switch must be added; see the TRAP instruction for context switch timing.
Status Bits N Undefined
C Undefined
Z Undefined
V Set depending upon window operation.
12-104
Line Draw with XV Addressing LINE
Linedraw Code
The following code segment shows setup and execution of the LINE in-
struction.
*********************************************************************
* Draw a line from point (xs,¥s) to point (xe,¥e) using Bresenham's *
* algorithm. When -draw_line ~s called, xs is ~n the 16 LSBs of B2, *
* ¥s is in the 16 MSBs of B2, xe is in the 16 LSBs of BO, and ye is *
* ~n the 16 MSBs of BO. *
*********************************************************************
. global -draw-line
-draw_line:
SUBXY B2, BO ; Calculate a and b
* Now set up B7 (a,b) and B11 = (dx-diag,dy-diag). Assume that
* a < 0 and b < 0; if a >= 0 or b >= 0, make corrections later.
* Register B11 (INC1) contains dy-diag::dx-diag
* Register B12 (INC2) contains dy-nondiag::dx-nondiag
MOVI -1, B11 dx-diag = dy-diag- - 1
MOVK 1, B12 Constant = 1
CLR B7
SUBXY BO, B7 B7 = (-a,-b)
JRNC L1 Jump if b < 0
* Handle case where b >= 0:
MOVY BO, B7 Make a in B7 positive
SRL 15, B11 Change dy-diag to +1
L1:
JRNV L2 Jump if a < 0
* Handle case where a >= 0:
MOVX BO, B7 Take absolute value of a
MOVX B12, B11 Change dx-diag to +1
L2:
MOVX B11, B12 dx-nondiag=dx-diag, dy-nondiag=O
* Compare magnitudes of a and b:
MOVE B7, BO Copy a and b
SRL 16, BO Move b into 16 LSBs
CMPXY BO, B7 Compare a and b
JRNV L3 Jump if a )= b
* Handle case where a < b; must swap a and b so that a >= b:
MOVX B7, BO Copy b into BO
RL 16, B7 Swap a and b halves of B7
CLR B12
MOVY B11, B12 dx_nondiag=O, dy-nondiag=dy_diag
* Calculate initial values of decision variable (d) and
* loop counter:
L3: ADD BO, BO BO = 2 x b
MOVX B7, BID BID = a
SUB BID, BO BO = d (2 x b - a)
ADDK I, BID Loop count = a + I (in BID)
* Draw line and return to caller:
LINE 0 ; Inner loop of line algorithm
RETS 0 ; Return to caller
12-105
LINE Line Draw with XV Addressing
Example 1 This example draws a line from (3,52) to (19,55). Window checking is off,
transparency and the pixel processing replace operation are selected, and
plane masking is disabled. Assume the following registers have been
loaded with these values:
BO = FFFFFFF1 h Decision variable d = 2b - a = -1 5
B2 = 00520003h DADDR
B3 = 00000800h DPTCH (CONVDP=13)
B4 = 00000100h OFFSET
B5 = 00300003h WSTART
B6 = 00550025h WEND
B7 = 00030016h b:a; b=3 and a=22
B9 = 44444444h COLOR1 (color of the line)
B10 = 00000017h COUNT (a+1)
B11 = 00010001 h Diagonal increment (+ 1, + 1 )
B1 2 = 00000001 h Nondiagonal increment (0, +1 )
B13 = FFFFFFFFh PATTRN (all 1 s)
This line is shown in Figure 12-13, represented by.s.
Before LINE execution, DADDR contains the first pixel to be drawn. During
LINE execution, DADDR is updated so that it always points to the next
pixel to be drawn. After this example is completed, DADDR equals
0055001 Ah. Register B7 contains the X and Y dimensions of the line.
Register B10 indicates the number of pixels that are drawn; if you want the
endpoint to be drawn (in this case, (19,55)), B10 should equal a+1.
B11 contains the XY increment for diagonal moves. You can see the line
progressing in a diagonal direction when it moves from (6,52) to (7,53); it
is incremented by 1 in both the X and the Y dimensions. B12 contains the
XY increment for nondiagonal moves. You can see the line progressing in
a nondiagonal direction when it moves from (3,52) to (4,52); it is incre-
mented by 1 in the X dimension.
~--------------~v~------------~
a=22
Figure 12-13. LINE Examples
12-106
Line Draw with XV Addressing LINE
Example 2 This example draws a line from (19,52) to (3,55). Window checking is off,
transparency and the pixel processing replace operation are selected, and
plane masking is disabled. Assume the following registers have been
loaded with these values:
BO = FFFFFFF1 h Decision variable d = 2b - a = -1 5
B2 = 00520019h DADDR
B3 = 00000800h DPTCH (CONVDP=13)
B4 = 000001 OOh OFFSET
B5 = 00300003 h WSTART
B6 = 00550025h WEND
B7 = 00030016h b:a; b=3 and a=22
B9 = 22222222h COLOR1 (color of the line)
B10 = 00000017h COUNT (a+1)
B11 = 0001 FFFFh Diagonal increment (+1,-1)
B12 = OOOOFFFFh Nondiagonal increment (0,-1 )
B13 = FFFFFFFFh PATTRN (all 1s)
This line is shown in Figure 12-13, represented by Xs.
Before LINE execution, DADDR contains the first pixel to be drawn. During
LINE execution, DADDR is updated so that it always points to the next
pixel to be drawn. After this example is completed, DADDR equals
00550002h. Register B7 contains the X and Y dimensions of the line.
Register B10 indicates the number of pixels that are drawn; if you want the
endpoint to be drawn (in this case, (3,55)), B10 should equal a+1.
B11 contains the XY increment for diagonal moves. You can see the line
progressing in a diagonal direction when it moves from (F,53) to (E,54); it
is decremented by 1 in the X dimension and incremented by 1 in the Y di-
mension. B12 contains the XY increment for nondiagonal moves. You can
see the line progressing in a nondiagonal direction when it moves from
(14,53) to (13,53); it is decremented by 1 in the X dimension.
12-107
LMO Find Leftmost One
Syntax LMO Rs, Rd
Execution 31 - (bit number of leftmost 1 in Rs) -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 Rs R Rd I
Description LMO locates the leftmost (most significant) 1 in the source register. It then
loads the 1s complement of the bit number of the leftmost-1 bit into me
five LSBs of the destination register. The 27 MSBs of the destination reg-
ister are loaded with Os. Bit 31 of Rs is the MSB (leftmost) and bit 0 is the
LSB. If the source register contains all Os, then the destination register is
loaded with all Os and status bit Z is set.
You can normalize the contents of the source register by following the LMO
instruction with an RL Rs,Rd instruction, where Rs is the destination reg-
ister of the LMO instruction and Rd is the source register.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z 1 if the source register contents are 0, 0 otherwise
V Unaffected
Examples Code Before After
AO NCZV A1
LMO AO,Al OOOOOOOOh xx1x OOOOOOOOh
LMO AO,Al 00OOOOO1h xxOx 0OOOOO1Fh
LMO AO,Al 00OOOO10h xxOx 0OOOOO1Bh
LMO AO,Al 08000000h xxOx 0OOOOO04h
LMO AO,Al 80000000h xxOx OOOOOOOOh
12-108
Move Multiple Registers from Memory MMFM
Syntax M M FM Rp, register list
Execution For each register Rn in the register list,
32 bits of data at the address specified in Rp -+ Rn
Rp + 32 -+ Rp
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2
000 0 o 0 o R Rs °
binary representation of the register list
Description MMFM loads the contents of a specified list of either A or B file registers
(not both) from a block of memory.
• The Rp operand is a register that points to the first location in the
block of memory.
• The register list is a list of registers separated by commas (such as AO,
A1, A9). These are the registers that MMFM loads new values into.
The MMTM and MMFM instructions are "stack" instructions for storing
multiple registers in memory and then retrieving their values. Both in-
structions use Rp as a "stack pointer" that contains the bit address of the
top of the stack. The stack grows toward lower addresses so that the bot-
tom of the stack is the highest address in the stack. M MTM stores the re-
gisters in memory. MMFM reverses the action of the MMTM instruction
by "popping" register values from memory. At the outset of the MMFM
instruction, Rp must contain the address of the 16 LS Bs of the highest or-
der register in the list. The LSW is moved into the register, and then the
contents of the next consecutive word are moved into the MSW of the re-
gister. After a register is "popped", the contents of Rp are incremented by
32 to point to the address of the LSW of the next register to be restored.
Rp and the registers in the list must all be in the same register file. The re-
gisters in the list can be specified in any order; the highest order register is
always restored first (that is, the value at the top of the stack - the lowest
address in the stack - is loaded into the highest order register). Don't in-
clude Rp as one of the registers in the register list, because this produces
unpredictable results. The original contents of Rp should be aligned on a
word-boundary; the alignment of Rp affects the instruction timing as indi-
cated in Machine States, below.
The second word of the MMFM instruction is a binary-mask representation
of the registers in the list. The R bit (bit 4) in the first word indicates which
register file is affected; the bits that are set to 1 in the mask indicate which
registers are restored. The bit assignments in the mask are:
12-109
MMFM Move Multiple Registers from Memory
Machine
States Cache Enabled Cache Disabled
Rp Aligned: 3 + 4n + (2) 11 + 4n
Rp Nonaligned: 3 + 6n + (4) 13 + 6n
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples This example restores several B-file registers:
MMFM BO,Bl,B2,B3,B7,B12,B13,B14,SP
This instruction uses register BO as the stack pointer. Assume that BO =
00010000h; this is the address of the top of the stack. MMFM moves the
data at this location into the LSW of the SP (which is the highest order
register listed in this example). Assume that memory contains the following
values before instruction execution:
Address Data Address Data
000100FOh 1111h 00010070h CCCCh
000100EOh 01 B1 h 00010060h BCBCh
000100DOh 2222h 00010050h DDDDh
000100COh OB2B2h 00010040h BDBDh
000100BOh 3333h 00010030h EEEEh
000100AOh 03B3h 00010020h BEBEh
00010090h 7777h 00010010h FFFFh
00010080h B7B7h 00010000h BFBFh
After the MMFM instruction is executed, the registers in the list have the
following values:
BO = 000101 OOh B12 = CCCCBCBCh
B1 = 1111 B1 B1 h B13 = DDDDBDBDh
B2 = 2222B2B2h B14 = EEEEBEBEh
B4 = 3333B3B3h SP = FFFFBFBFh
B8 = 7777B7B7h
The other B-file registers (which weren't specified in the register list) are
not affected by this instruction. Note that 80 now contains the value
10100h; the last part of the data that was restored was for B1, and BO
points to the word past that data.
12-110
Move Multiple Registers to Memory MMTM
Syntax M MTM Rp, register list
Execution For each register Rnin the register list,
Rp - 32 -+ Rp
32 bits of data at the address specified in Rn -+ Rp
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2
o 0 0 0 o 0 o 0 R Rd °
binary representation of the register list
Description M MTM stores the contents of a specified list of either A or B file registers
(not both) in memory.
• The Rp operand is a register that points to the first location in a block
of memory.
• The register list is a list of registers that are separated by commas
(such as AO, A1, A9). These are the registers that MMTM stores in
memory.
The MMTM and MMFM instructions are "stack" instructions for storing
multiple registers in memory and then retrieving their values. Both in-
structions use Rp as a "stack pointer" that contains the bit address of the
top of the stack. The stack grows toward lower addresses so that the bot-
tom of the stack is the highest address in the stack. MMTM stores the re-
gisters in memory. Before a register's contents are "pushed" onto the stack,
the Rp is decremented by 32 bits; the register is then pushed, LSW first.
Thus, at the outset of the M MTM instruction, Rp must contain an incre-
mented value. This value is the address where you want to store the LSW
of the lowest-order register, plus 32 bits; this assures that Rp is predecre-
mented to point to the correct location in memory.
When MMTM execution is complete, the contents of the lowest-order reg-
ister in the list reside at the highest address in the memory "stack," and Rp
points to the address of the highest-order register in the list.
Rp and the registers in the list must all be in the same register file. The re-
gisters in the list can be specified in any order; the lowest order register is
always saved first. Don't include Rp as one of the registers in the register
list, because this produces unpredictable results. The original contents of
Rp should be aligned on a word boundary; the alignment of Rp affects the
instruction timing as shown in Machine States, below.
The second word of the MMFM instruction is a binary-mask representation
of the registers in the list. The R bit (bit 4) in the first word indicates which
register file is affected; the bits that are set to 1 in the mask indicate which
registers are restored. The bit assignments in the mask are:
12-111
MMTM Move Multiple Registers to Memory
Machine
States Cache Enabled Cache Disabled
Rp Aligned: 2 + 4n + (2) 8 + 4n + 2
Rp Nonaligned: 2 + 10n + (8) 10(n+1)
Status Bits N Set to the sign of the result of 0 - Rp. (This value is typically 1 if the
original contents of Rp are positive; otherwise, it is O. The only ex-
ceptions to this are when Rp=80000000h, N is set to 0, and when
Rp=O, N is set to 1.)
C Unaffected
Z Unaffected
V Unaffected
Examples This example saves the values of several A-file registers in memory:
MMTM Al,AO,A2,A4,A8,A12,A13,A14,SP
This instruction uses register A1 as the stack pointer. Assume that A1
100000h before instruction execution; this value is decremented by 32 to
point to the address where the contents of AO (the lowest order register in
the list) are stored. Assume that the registers in the list contain the fol-
lowing values before instruction execution:
AO = OOOOAOAOh A 12 = CCCCACACh
A2 = 2220A2A2h A13 = DDDDADADh
A4 = 4444A4A4h A14 = EEEEAEAEh
A8 = 8888A8A8h SP = FFFFAFAFh
M MTM saves these register values in memory as shown below:
Address Data Address Data
OOOFFFOOh AFAFh 000FFF80h A8A8h
000FFF10h FFFFh 000FFF90h 8888h
000FFF20h AEAEh OOOFFFAOh A4A4h
000FFF30h EEEEh OOOFFFBOh 4444h
000FFF40h ADADh OOOFFFCOh A2A2h
000FFF50h DDDDh OOOFFFDOh 2222h
OOOFFF60h ACACh OOOFFFEOh AOAOh
00OFFF70h CCCCh OOOFFFFOh OOOOh
After instruction execution, register A1 = OOOFFFOOh. Note that A1 now
contains the value OFFFOOh; this is the address of the last portion of register
data that is saved.
12-112
Modulus - Signed MODS
Syntax MODS Rs, Rd
Execution Rd mod Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 01 Rs IR Rd I
Description MODS performs a 32-bit signed divide of the 32-bit dividend in the desti-
nation register by the 32-bit value in the source register, and returns a
32-bit remainder in the destination register. The remainder is the same sign
as the dividend. The original contents of the destination register are always
overwritten.
Rs and Rd must be in the same register file.
Machine
States 40,43 (normal case)
41,44 if result = 80000000
3,6 if Rs = 0
Status Bits N Unaffected
C Unaffected
Z Unaffected if RS=O, 1 if quotient is 0, 0 otherwise
V 1 if the quotient overflows (cannot be represented by 32 bits), 0 oth-
erwise
The following conditions set the overflow flag:
• The divisor is 0
• The quotient cannot be contained within 32 bits
Examples Code Before After
AO A1 NCZV AO
MODS AD,AI OOOOOOOOh OOOOOOOOh Ox01 OOOOOOOOh
MODS AD,AI OOOOOOOOh 00000007h Ox01 00000OO7h
MODS AD,AI OOOOOOOOh FFFFFFF9h Ox01 FFFFFFF9h
MODS AD,AI 00OOOO04h 00000008h Ox10 OOOOOOOOh
MODS AD,AI 00000004h 000OOO07h OxOO 000OOOO3h
MODS AD,AI 00000004h OOOOOOOOh Ox10 OOOOOOOOh
MODS AD,AI 00000004h FFFFFFF9h 1xOO FFFFFFFDh
MODS AD,AI 00000004h FFFFFFF8h Ox10 OOOOOOOOh
MODS AD,AI FFFFFFFCh 000OOO08h Ox10 OOOOOOOOh
MODS AD,AI FFFFFFFCh 000OOO07h OxOO 000OOOO3h
MODS AD,AI FFFFFFFCh OOOOOOOOh Ox10 OOOOOOOOh
MODS AD,AI FFFFFFFCh FFFFFFF9h 1xOO FFFFFFFDh
MODS AD,AI FFFFFFFCh FFFFFFF8h Ox10 OOOOOOOOh
12-113
MODU Modulus - Unsigned
Syntax MODU Rs, Rd
Execution Rd mod Rs ~ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 1 I Rs IR Rd I
Description MODU performs a 32-bit unsigned divide of the 32-bit dividend in the
destination register by the 32-bit value in the source register, and returns a
32-bit remainder in the destination register. The original contents of the
destination register are always overwritten.
Rs and Rd must be in the same register file.
Machine
States 35,38
3,6 if Rs = 0
Status Bits N Unaffected
C Unaffected
Z Unaffected if RS=O, 1 if quotient is 0, 0 otherwise
V 1 if divisor Rs equals 0,0 otherwise
Examples Code Before After
AO A1 NCZV A1
MODU AO,AI OOOOOOOOh OOOOOOOOh xx01 OOOOOOOOh
MODU AO,AI OOOOOOOOh 00000007h xx01 00OOOOO7h
MODU AO,AI OOOOOOOOh FFFFFFF9h xx01 FFFFFFF9h
MODU AO,AI 0000OOO4h 0OOOOOO8h xx10 OOOOOOOOh
MODU AO,AI 0000OO04h 00000OO7h xxOO 00OOOO03h
MODU AO,AI 00OOOOO4h OOOOOOOOh xx10 OOOOOOOOh
MODU AO,AI 0OOOOOO4h FFFFFFF9h xxOO 00OOOOO1h
12-114
Move Byte - Register to Indirect MOVB
Syntax MOVB Rs, *Rd
Execution 8 LSBs of Rs -+ *Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
11 0 0 0 01 Rs IR Rd I
Description MOVB moves a byte from the source register to the memory address con-
tained in the destination register. The source operand byte is right justified
in the source register; only the 8 LSBs of the register are moved. The me-
mory address is a bit address and the field size for the move is 8 bits.
Rs and Rd must be in the same register file.
Machine
States 1 + (3),7 (when the destination address is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
5000h OOOOh
5010h OOOOh
Code Before After
AO A1 @5000h @5010h
MOVB AO,*Al 89ABCDEFh 00005000h OOEFh OOOOh
MOVB AO,*Al 89ABCDEFh 00005001h 01 DEh OOOOh
MOVB AO, *Al 89ABCDEFh 00005009h ODEOOh 0001h
MOVB AO, *Al 89ABCDEFh 0000500Ch FOOOh OOOEh
12-115
MOVB Move Byte - Register to Indirect with Offset
Syntax MOVB Rs, *Rd(offset)
Execution 8 LSBs of Rs ~ *Rd + offset
Instruction
Words 15 14 13 12 11 10 987 6 5 4 3 2 o
o oI Rs R Rd
offset
Description MOVB moves a byte from the source register to the destination memory
address. The source operand byte is right justified in the source register;
only the 8 LSBs of the register are moved. The destination memory address
is a bit address and is formed by adding the contents of the specified reg-
ister to the signed 16-bit offset. This is a field move, and the field size for
the move is 8 bits.
Rs and Rd must be in the same register file.
Machine
States 3+ (3),9 (when the destination address is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
10000h OOOOh
10010h OOOOh
Before After
AO A1 @1 OOOOh @1 001 Oh
MOVB AO, *Al( 0) 89ABCDEFh 00010000hOOEFh OOOOh
MOVB AO, *A1 (1) 89ABCDEFh 00010000h01DEh OOOOh
MOVB AO,*A1(9) 89ABCDEFh 0001 OOOOh DEOOh 0001h
MOVB AO, *Al( 12) 89ABCDEFh 0001 OOOOh FOOOh OOOEh
MOVB AO,*A1(32767) 89ABCDEFh 00008001hOOEFh OOOOh
MOVB AO,*A1(-32768) 89ABCDEFh 00018000hOOEFh OOOOh
12-116
Move Byte - Register to Absolute MOVB
Syntax MOVB Rs, *DAddress
Execution 8 LSBs of'Rs ~ DAddress
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 0 1 0 1 1 1 1 IR I Rs
1 6 LS Bs of destination address
16 MSBs of destination address
Description MOVB moves a byte from the source register to the destination memory
address. The source operand byte is right justified in the source register;
only the 8 LSBs of the register are moved. The specified destination mem-
ory address is a bit address and the field size for the move is 8 bits.
Rs and Rd must be in the same register file.
Machine
States 1 + (3),7 (when the destination address is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits NUn affected
C Unaffected
Z Unaffected
V Unaffected
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
5000h OOOOh
5010h OOOOh
Code Before After
AO @5000h @5010h
MOVB AO,@5000h 89ABCDEFh OOEFh OOOOh
MOVB AO,@5001h 89ABCDEFh 01 DEh OOOOh
MOVB AO,@5009h 89ABCDEFh DEOOh 0001h
MOVB AO,@500Ch 89ABCDEFh FOOOh OOOEh
12-117
MOVB Move Byte - Indirect to Register
Syntax MOVB *Rs, Rd
Execution byte at *Rs -. Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I1 0 0 0 Rs R Rd I
Description MOVB moves a byte from the memory address contained in the source re-
gister to the destination register. The source memory address is a bit ad-
dress and the field size for the move is 8 bits. When the byte is moved into
the destination register, it is right justified and sign extended to 32 bits.
This instruction also performs an implicit compare to 0 of the field data.
Rs and Rd must be in the same register file.
Machine
States 3,6 (when the source data is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N 1 if the sign-extended data moved into register is negative, 0 otherwise
C Unaffected
Z 1 if the sign-extended data moved into register is 0, 0 otherwise
V 0
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
5000h OOEFh
5010h 89ABh
Code Before After
AO A1 NCZV
MOVB *AO,Al 00005000h FFFFFFEFh 1xOO
MOVB *AO,Al 00005001h 00000077h OxOO
MOVB *AO,Al 00005008h OOOOOOOOh Ox10
MOVB *AO,Al 0000500Ch FFFFFFBOh 1xOO
12-118
Move Byte - Indirect to Indirect MOVB
Syntax MOVB *Rs, *Rd
Execution byte at *Rs -+ *Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
Rs Rd
11
° ° 01 1R 1
Description MOVB moves a byte from the source memory address to the destination
memory address. The source address is specified by the contents of Rs, and
the destination address is specified by the contents of Rd. Both memory
addresses are bit addresses and the field size for the move is 8 bits.
Rs and Rd must be in the same register file.
Machine
States 3+(3),7 (when the source data and destination address are aligned on byte
boundaries)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
5000h CDEF
5010h 89AB
6000h 0000
6010h 0000
Code Before After
AO A1 @6000h @6010h
MOVB *AO,*Al 00005000h 00006000h OOEFh OOOOh
MOVB *AO, *Al 00005000h 00006001h 01 DEh OOOOh
MOVB *AO,*Al 00005000h 00006009h DEOOh 0001h
MOVB *AO,*Al 00005000h 0000600Ch FOOOh OOOEh
MOVB *AO,*Al 0OO05001h 0OOO6000h 00F7h OOOOh
MOVB *AO,*Al 0OO05001h 00006001h 01EEh OOOOh
MOVB *AO,*Al 00005001h 0OOO6009h EEOOh 0001h
MOVB *AO,*Al 0OO05001h 0OOO600Ch 7000h OOOFh
MOVB *AO, *Al 0OO05009h 0OOO6000h OOE6h OOOOh
MOVB *AO,*Al 0OO05009h 0OOO6001h 01CCh OOOOh
MOVB *AO,*Al 0OOO5009h 0OOO6009h CCOOh 0001h
MOVB *AO,*Al 0OOO5009h 0OOO600Ch 6000h OOOEh
MOVB *AO,*Al 0OOO500Ch 0OOO6000h OOBCh OOOOh
MOVB *AO,*Al 0OO0500Ch 0OO06001h 0178h OOOOh
MOVB *AO,*Al 0OO0500Ch 0OOO6009h 7800h 0001h
MOVB *AO,*Al 0OO0500Ch 0OOO600Ch COOOh OOOBh
12-119
MOVB Move Byte - Indirect with Offset to Register
Syntax MOVB *Rs(offset), Rd
Execution byte at (*Rs + offset) -+ Rd
Instruction
Words 15 14 13 12 11 10 9 876 5 4 3 2 o
o Rs R Rd
offset
Description MOVB moves a byte from the source memory address to the destination
register. The source memory address is a bit address and is formed by ad-
ding the contents of the specified register to the signed 16-bit offset. The
field size is 8 bits. When the byte is moved into the destination register, it
is right justified and sign extended to 32 bits. This instruction also performs
an implicit compare to 0 of the field data.
Rs and Rd must be in the same register file.
Machine
States 5,11 (when the source data is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N 1 if the sign-extended data moved into register is negative, a otherwise
C Unaffected
Z 1 if the sign-extended data moved into register is 0, a otherwise
V a
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
10000h OOEFh
10010h 89ABh
Code Before After
AO A1 NCZV
MOVB *AO (0) ,Al 00010000h FFFFFFEFh 1xOO
MOVB *AO(l) ,Al 0OO10000h 0OOOOO77h OxOO
MOVB *AO(8) ,Al 00010000h OOOOOOOOh Ox10
MOVB *AO(12) ,Al 0OO10000h FFFFFFBOh 1xOO
MOVB *AO(32767) ,Al 00OO8001h FFFFFFEFh 1xOO
MOVB *AO(-32768),Al 00018000h FFFFFFEFh 1xOO
12-120
Move Byte - Indirect with Offset
to Indirect with Offset MOVB
Syntax MOVB *Rs(SOffset), *Rd(DOffset)
Execution byte at (* Rs + SOffset) -+ (* Rd + DOffset)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
1 0 1 1 1 1 01 Rs 1R 1 Rd
source offset
destination offset
Description MOVB moves a byte from the source memory address to the destination
memory address. Both the source and destination memory addresses are
bit addresses and are formed by adding the contents of the specified regis-
ter to its respective signed 16-bit offset. The field size is 8 bits.
Rs and Rd must be in the same register file.
Machine
States 5+ (3),9 (when the source data and destination address are aligned on byte
boundaries)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits NUn affected
C Unaffected
Z Unaffected
V Unaffected
12-121
Move Byte - Indirect with Offset
MOVB to Indirect with Offset
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
10000h CDEFh
10010h 89ABh
11000h OOOOh
11010h OOOOh
Code Before After
AO A1 @11000h @11010h
MOVB *AO(O) ,*A1(O) 00010000h 00011000h OOEFh OOOOh
MOVB *AO(O) ,*A1(l) 00010000h 00011 OOOh 01 DEh OOOOh
MOVB * AO ( 0) , * A1 ( 9 ) 00010000h 00011000h DEOOh 0001h
MOVB *AO(O) ,*A1(l2) 00010000h 00011000h FOOOh OOOEh
MOVB *AO(O),*A1(32767) 00010000h 00009001h OOEFh OOOOh
MOVB *AO(O),*A1(-32768) 00010000h 00019000h OOEFh OOOOh
MOVB *AO(12) ,*A1(O) 00010000h 00011000h OOBCh OOOOh
MOVB *AO(l2) ,*Al(l) 00010000h 00011000h 0178h OOOOh
MOVB *AO(12) ,*A1(9) 00010000h 00011000h 7800h 0001h
MOVB *AO (12) , *A1 (12) 00010000h 00011 OOOh COOOh OOOBh
MOVB *AO(12),*A1(32767) 00010000h 00009001 h OOBCh OOOOh
MOVB *AO(12),*A1(-32768) 00010000h 00019000h OOBCh OOOOh
MOVB *AO(32767),*A1(O) 00008001h 00011000h OOEFh OOOOh
MOVB *AO(32767),*A1(l) 00008001h 00011000h 01 DEh OOOOh
MOVB *AO(32767),*A1(9) 00008001h 00011 OOOh DEOOh 0001h
MOVB *AO(32767),*A1(12) 00008001h 00011 OOOh FOOOh OOOEh
MOVB *AO(32767),*A1(32767) 00008001h 00009001h OOEFh OOOOh
MOVB *AO(32767),*A1(-32678) 00008001h 00019000h OOEFh OOOOh
MOVB *AO(-32768),*A1(O) 00018000h 00011000h OOEFh OOOOh
MOVB *AO(-32768),*A1(l) 00018000h 00011000h 01 DEh OOOOh
MOVB *AO(-32768),*A1(9) 00018000h 00011000h DEOOh 0001h
MOVB *AO(-32768),*A1(12) 00018000h 00011000h FOOOh OOOEh
MOVB *AO(-32768),*A1(32767) 00018000h 00009001h OOEFh OOOOh
MOVB *AO(-32768),*A1(-32678) 00018000h 00019000h OOEFh OOOOh
12-122
Move Byte - Absolute to Register MOVB
Syntax MOVB @SAddress, Rd
Execution byte at SAddress -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 0 1 1 1 1 1 1 IR I Rd
16 LSBs of source address
16 MSBs of source address
Description MOVB moves a byte from the source memory address to the destination
register. The specified source memory address is a bit address and the field
size for the move is 8 bits. When the byte is moved into the destination
register, it is right justified and sign extended to 32 bits. This instruction
also performs an implicit compare to 0 of the field data.
Rs and Rd must be in the same register file.
Machine
States 5,14 (when the source data is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N 1 if the sign-extended data moved into register is negative, 0 otherwise
C Unaffected
Z 1 if the sign-extended data moved into register is 0, 0 otherwise
V 0
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
10000h OOEFh
10010h 89ABh
Code After
A1 NCZV
MOVB @lOOOOh,Al FFFFFFEFh 1xOO
MOVB @lOOOlh,Al 00000077h OxOO
MOVB @lOOO8h,Al OOOOOOOOh Ox10
MOVB @lOOOCh,Al FFFFFFBOh 1xOO
12-123
MOVB Move Byte - Absolute to Absolute
Syntax MOVB @SAddress, @DAddress
Execution byte at SAddress -+ DAddress
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0
16 LSBs of source address
16 MSBs of source address
16 LSBs of destination address
16 MSBs of destination address
Description MOVB moves a byte from the source memory address to the destination
memory address. Both the source and destination addresses are interpreted
as bit addresses and the field size for the move is 8 bits.
Machine
States 7 + (3) ,25 (when the source data and destination address are aligned on
byte boundaries)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
10000h CDEFh
10010h 89ABh
11000h OOOOh
11010h OOOOh
12-124
Move Byte - Absolute to Absolute MOVB
Code After
@11000h @11010h
MOVB @lOOOOh,@llOOOh OOEFh OOOOh
MOVB @l{)OOOh,@llOOlh 01DEh OOOOh
MOVB @lOOOOh,@11OO9h DEOOh 0001h
MOVB @lOOOOh,@llOOCh FOOOh OOOEh
MOVB @lOOOlh,@llOOOh 00F7h OOOOh
MOVB @lOOOlh,@llOOlh 01EEh OOOOh
MOVB @lOOOlh,@11OO9h EEOOh 0001h
MOVB @lOOOlh,@llOOCh 7000h OOOFh
MOVB @lOOO9h,@11OOOh 00E6h OOOOh
MOVB @lOOO9h,@11OOlh 01CCh OOOOh
MOVB @lOOO9h,@11OO9h CCOOh 0001h
MOVB @lOOO9h,@11OOCh 6000h OOOEh
MOVB @lOOOCh,@llOOOh OOBCh OOOOh
MOVB @lOOOCh,@llOOlh 0178h OOOOh
MOVB @lOOOCh,@11OO9h 7800h 0001h
MOVB @lOOOCh,@llOOCh COOOh OOOBh
12-125
MOVE Move - Register to Register
Syntax MOVE Rs, Rd
Execution Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 1 IM I Rs R Rd I
Description MOVE moves the 32 bits of data from the source register to the destination
register. Note that this is not a field move; therefore, the field size has no
effect. The source and destination registers can be any of the 31 locations
in the on-chip register file. Note that this is the only MOVE instruction that
allows the source and destination registers to be in different files. This in-
struction also performs an implicit compare to 0 of the register data.
Fields The assembler sets bit 9 (the M bit) in the instruction word to specify
whether the move is within a register file or if it crosses the register files.
The assembler sets M to 0 if the source and destination registers are in the
same file; it sets M to 1 if the registers are in different files.
The assembler sets bit 4 (the R bit) in the instruction word to specify which
file the registers are in. The assembler sets R to 0 if the registers are in file
A; it sets R to 1 if the registers are in file B.
Note that when M=O, R specifies the register file for both registers; if M=1,
R specifies the register file for the source register
Machine
States 1,4
Status Bits N 1 if the 32-bit data moved is negative, a otherwise
C Unaffected
Z 1 if the 32-bit data moved is 0, a otherwise
V a
Examples Code Before After
AO A1 B1 NCZV
MOVE AO,AI OOOOFFFFh OOOOFFFFh xxxxxxxxh OxOO
MOVE AO,AI OOOOOOOOh OOOOOOOOh xxxxxxxxh Ox10
MOVE AO,AI FFFFFFFFh FFFFFFFFh xxxxxxxxh 1xOO
MOVE AO,BI OOOOFFFFh xxxxxxxxh OOOOFFFFh OxOO
MOVE AO,BI OOOOOOOOh xxxxxxxxh OOOOOOOOh Ox10
MOVE AO,BI FFFFFFFFh xxxxxxxxh FFFFFFFFh 1xOO
12-126
Move Field - Register to Indirect MOVE
Syntax MOVE Rs, *Rd [, FJ
Execution field in Rs -+ *Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I1 0 0 0 0 01 F Rs IR Rd 1
Description MOVE moves a field from the source register to the memory address con-
tained in the destination register. This memory address is a bit address.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F param-
eter determines the field size and extension for the move:
F =0 selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.
Machine
States The following typical cases assume that the destination address is aligned
on a 16-bit boundary:
16- Bit Field 32- Bit Field
1 +(1 ),5 1+(3),7
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15500h OOOOh
15510h OOOOh
15520h OOOOh
Register AO = FFFFFFFFh
Code Before After
A1 FSO/1 @15500h @15510h @15520h
MOVE AO,*Al,O 00015500h 5/x 001Fh OOOOh OOOOh
MOVE AO,*Al,l 00015503h x/8 07F8h OOOOh OOOOh
MOVE AO,*Al,O 00015508h 13/x FFOOh 001Fh OOOOh
MOVE AO,*Al,l 0001550Bh x/16 F800h 07FFh OOOOh
MOVE AO,*Al,O 0001550Dh 19/x EOOOh FFFFh OOOOh
MOVE AO,*Al,l 0001550Ch x/24 FOOOh FFFFh OOOFh
MOVE AO,*Al,O 00015512h 27/x OOOOh FFFCh 1 FFFh
MOVE AO,*Al,l 00015510h x/32 OOOOh FFFFh FFFFh
12-127
Move Field - Register to
MOVE Indirect (Postincrement)
Syntax MOVE Rs, *Rd+ [, FJ
Execution field in Rs -+ * Rd
Rd + field size -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
11 0 0 0 01 F Rs R Rd I
Description MOVE moves a field from the source register to the memory address COFt--
tained in the destination register. This memory address is a bit address.
After the move, the contents of the destination register are postincremented
by the selected field size. The field size for the move is 1-32 bits, depending
on the selected field size; the field is right justified within the source regis-
ter. The optional F parameter determines the field size and extension for the
move:
F =0 selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.
Machine
States The following typical cases assume that the destination address is aligned
on a 16-bit boundary:
16-Bit Field 32- Bit Field
1+(1),5 1+(3),7
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15500h OOOOh
15510h OOOOh
15520h OOOOh
Register AO = FFFFFFFFh
12-128
Move Field - Register to
Indirect (Postincrement) MOVE
Code Before After
A1 FSO/1 A1 @15500h @15510h @15520h
MOVE AO,*Al+,O 0OO15528h 5/x 0OO1552Dh OOOOh OOOOh 1 FOOh
MOVE AO,*Al+,l 0OO15525h x/8 0OO1552Dh OOOOh OOOOh 1FEOh
°
MOVE AO, *Al+,
MOVE AO,*Al+,l
0OO15520h
0OO1551Dh
13/x
x/16
0OO1552Dh
0OO1552Dh
OOOOh
OOOOh
OOOOh
EOOOh
1 FFFh
1 FFFh
°
MOVE AO, *Al+,
MOVE AO,*Al+,l
0OO15516h
0OO15507h
19/x
x/24
0OO15529h
0OO1551Fh
OOOOh
FF80h
FFCOh
7FFFh
01 FFh
OOOOh
MOVE AO,*Al+,O 0OO15507h 27/x 0OO1551Fh FF80h FFFFh 0OO3h
MOVE AO,*Al+,l 0OO15500h x/32 0OO15520h FFFFh FFFFh OOOOh
12-129
Move Field - Register to
MOVE Indirect (Predecrement)
Syntax MOVE Rs, -*Rd [, FJ
Execution Rd - field size -+ Rd
field in Rs -+ * Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I1 0 0 0 o IF Rs R Rd
Description MOVE moves a field from the source register to the memory address con-
tained in the destination register; the destination address is predecremented
by the field size. The memory address is a bit address. Before the move,
the field size is subtracted from the contents of the destination register to
determine the location that the field is moved to. (This value is also the fi-
nal value for the register.)
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F param-
eter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the sam,e register file.
Machine
States The following typical cases assume that the destination address is aligned
on a 16-bit boundary:
16- Bit Field 32-Bit Field
2+(1),6 2+(3),8
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15500h OOOOh
15510h OOOOh
15520h OOOOh
Register AO = FFFFFFFFh
12-130
Move Field - Register to
Indirect (Predecrement) MOVE
Code Before After
A1 FSO/1 A1 @15500h @15510h @15520h
MOVE AO,-*Al,O 0OO1530h 5/x 0OO152Bh OOOOh OOOOh F800h
MOVE AO,-*Al,l 0OO152Dh x/B 0OO1525h OOOOh OOOOh 1FEOh
MOVE AO,-*Al,O 0OO1528h 13/x 0OO151Bh OOOOh FBOOh OOFFh
MOVE AO,-*Al,l 0OO152Bh x/16 0OO1518h OOOOh FFOOh OOFFh
MOVE AO,-*Al,O 0OO1523h 19/x 0OO1510h OOOOh FFFFh 0OO7h
MOVE AO,-*Al,l 0OO1520h x/24 0OO1508h FFOOh FFFFh OOOOh
MOVE AO,-*Al,O 0OO1524h 27/x 0OO1509h FEOOh FFFFh OOOFh
MOVE AO,-*Al,l 0OO1520h x/32 0OO1500h FFFFh FFFFh OOOOh
12-131
Move Field - Register to
MOVE Indirect with Offset
Syntax MOVE Rs, *Rd(offset) [, FJ
Execution field in Rs -+ * (Rd + offset)
Instruction
Words 15 14 13 12 11 10 9 876 5 4 3 2 o
o o oIF Rs Rd
offset
Description MOVE moves a field from the source register to the destination memory
memory address. The destination memory address is a bit address and is
formed by adding the contents of the destination register to the signed
16-bit offset. The field size for the move is 1-32 bits, depending on the
selected field size; the field is right justified within the source register. The
optional F parameter determines the field size and extension for the move:
F =0 selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.
Machine
States The following typical cases assume that the destination address is aligned
on a 16-bit boundary:
16- Bit Field 32-Bit Field
3+ (1 ),7 3+(3),9
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
12-132
Move Field - Register to
Indirect with Offset MOVE
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15530h OOOOh
15540h OOOOh
15550h OOOOh
Register AO = FFFFFFFFh
Code Before After
A1 FSO/1 @15530h @15540h @15550h
MOVE AO,*Al(OOOOh),1 00015530h x/1 0001h OOOOh OOOOh
MOVE AO,*Al(OOOlh),O 0001552Fh 5/x 001Fh OOOOh OOOOh
MOVE AO,*Al(OOOFh),O 00015520h 8/x FOOOh OOOFh OOOOh
MOVE AO,*Al(0020h),1 0001551Ch x/13 FOOOh 01FFh OOOOh
MOVE AO,*Al(OOFFh),O 00015435h 16/x FFFOh OOOFh OOOOh
MOVE AO,*Al(OFFFh),O 00014531h 19/x FFFFh 0007h OOOOh
MOVE AO,*Al(7FFFh),1 00000531 h x/22 FFFFh 003Fh OOOOh
MOVE AO,*Al(OFFF2h),1 00015540h x/25 FFFCh 07FFh OOOOh
MOVE AO,*Al(8000h),0 00010530h 27/x FFFFh 07FFh OOOOh
MOVE AO,*Al(OFFFOh),O 00015540h 31/x FFFFh 7FFFh OOOOh
MOVE AO,*Al(OFFECh),l 00015548h x/31 FFFOh FFFFh 0007h
MOVE AO,*Al(OFFECh),O 00015540h 32/x FEOOh FFFFh 01FFh
MOVE AO,*Al(OOIDh),O 00015520h 32/x EOOOh FFFFh 1 FFFh
MOVE AO,*Al(0020h),1 00015520h x/32 OOOOh FFFFh FFFFh
12-133
MOVE Move Field - Register to Absolute
Syntax MOVE Rs, @DAddress [, FJ
Execution field in Rs -+ DAddress
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 0 1 IF I 1 1 0 oIR I Rs
16 LSBs of destination address
16 MSBs of destination address
Description MOVE moves a field from the source register to the destination memory
address. The specified destination memory address is a linear bit address.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F param-
eter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
SETF sets the field size and extension.
Machine
States The following typical cases assume that the destination address is aligned
on a 16-bit boundary:
16- Bit Field 32- Bit Field
3+(1),7 3+(3),9
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Assume that memory contains these values before instruction execution:
Address Data
15500h OOOOh
15510h OOOOh
15520h OOOOh
Register AO = FFFFFFFFh
Code Before After
FSO/1 @15500h @15510h @15520h
MOVE AO,@15500h,O 5/x 001Fh OOOOh OOOOh
MOVE AO,@15503h,1 x/8 07F8h OOOOh OOOOh
MOVE AO,@15508h,O 13/x FFOOh 001 Fh OOOOh
MOVE AO,@1550Bh,1 x/16 F800h 07FFh OOOOh
MOVE AO,@1550Dh,O 19/x EOOOh FFFFh OOOOh
MOVE AO,@15510h,1 x/24 OOOOh FFFFh OOFFh
MOVE AO,@15512h,O 27/x OOOOh FFFCh 1 FFFh
MOVE AO,@1550Ch,1 x/32 FOOOh FFFFh OFFFh
12-134
Move Field - Indirect to Register MOVE
Syntax MOVE *Rs, Rd [, FJ
Execution field at * Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I1 0 0 0 0 1 IF Rs R Rd I
Description MOVE moves a field from the source memory address to the destination
register. The contents of the source register specify the address of the field.
When the field is moved into the destination register, it is right justified and
sign extended or zero extended to 32 bits, according to the value of FE.
This instruction also performs an implicit compare to 0 of the field data.
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.
Machine
States The following typical cases assume that the source data is aligned on a
16-bit boundary:
16-Bit Field 32- Bit Field
3,6 5,8
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N 1 if the field-extended data moved to register is negative, 0 otherwise
C Unaffected
Z 1 if the field-extended data moved to register is 0, 0 otherwise
V 0
12-135
MOVE Move Field - Indirect to Register
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15500h 7770h
15510h 7777h
Register AO = 0001 5500h
Code Before After
FSO/1 FEO/1 A1 NCZV
MOVE *AO,Al,l x/1 x/1 OOOOOOOOh Ox10
MOVE *AO,Al,O 5/x O/x 00000010h OxOO
MOVE *AO,Al,l x/5 x/1 FFFFFFFOh 1xOO
MOVE *AO,Al,O 12/x 1/x 00OOO770h OxOO
MOVE *AO,Al,l x/12 x/O 00000770h OxOO
MOVE *AO,Al,O 18/x O/x 00037770h OxOO
MOVE *AO,Al,l x/18 x/1 FFFF7770h 1xOO
MOVE *AO,Al,O 27/x 1/x FF777770h 1xOO
MOVE *AO,Al,l x/27 x/O 07777770h OxOO
MOVE *AO,Al,O 31/x O/x 77777770h OxOO
MOVE *AO,Al,l x/31 x/1 F7777770h 1xOO
MOVE *AO,Al,O 32/x x/x 77777770h OxOO
12-136
Move Field - Indirect to Indirect MOVE
Syntax MOVE *Rs, *Rd [, FJ
Execution field at *Rs ~ *Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
11 0 0 0 01 F Rs R Rd
Description MOVE moves a field from a source address to a destination address. Both
memory addresses are bit addresses; the source register contains the ad-
dress of the field and the destination register specifies the address that the
field is moved to. The field size for the move is 1-32 bits, depending on the
selected field size; the optional F parameter determines the field size and
extension for the move:
F =0 selects FSO
F=1 selects FS1
SETF sets the field size and extension. Rs and Rd must be in the same re-
gister file.
Machine
States The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:
16- Bit Field 32-Bit Field
3+(1 ),7 5+(3),11
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits NUn affected
C Unaffected
Z Unaffected
V Unaffected
12-137
MOVE Move Field - Indirect to Indirect
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data Address Data
15500h FFFFh 15530h OOOOh
15510h FFFFh 15540h OOOOh
15520h FFFFh 15550h OOOOh
Code Before After
AO A1 FSO/1 @15530h @15540h @15550h
MOVE *AO,*Al,l 0OO15500h 0OO15530h x/1 0OO1h OOOOh OOOOh
MOVE *AO,*Al,O 0OO15500h 0OO15534h 5/x 01FOh OOOOh OOOOh
MOVE *AO,*Al,l 0OO15500h 0OO1553Ah x/10 FCOOh OOOFh OOOOh
MOVE *AO,*Al,O 0OO15500h 0OO1553Fh 19/x 8000h FFFFh 0OO3h
MOVE *AO,*Al,l 0OO15504h 0OO15530h x/7 007Fh OOOOh OOOOh
MOVE *AO,*Al,O 0OO1550Ah 0OO15530h 13/x 1 FFFh OOOOh OOOOh
MOVE *AO,*Al,l 0OO1550Dh 0OO15534h x/8 OFFOh OOOOh OOOOh
MOVE *AO,*Al,O 0OO1550Dh 0OO15530h 28/x FFFFh OFFFh OOOOh
MOVE *AO,*Al,l 0OO15505h 0OO15535h x/23 FFEOh OFFFh OOOOh
MOVE *AO,*Al,O 0OO15508h 0OO15536h 31/x FFCOh FFFFh 001Fh
MOVE *AO,*Al,l 0OO15508h 0OO15531h x/31 FFFEh FFFFh OOOOh
MOVE *AO,*Al,O 0OO1550Ah 0OO15530h 32/x FFFFh FFFFh OOOOh
MOVE *AO,*Al,O 0OO15500h 0OO1553Ah x/32 FCOOh FFFFh 03FFh
12-138
Move Field - Indirect
(Postincrement) to Register MOVE
Syntax MOVE *Rs+, Rd [, FJ
Execution field at * Rs -+ Rd
Rs + field size -+ Rs
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I1 0 0 0 1 I F Rs R Rd
Description MOVE moves a field from memory to the destination register. The source
register contains the address of the field; after the move, the contents of the
source register are incremented by the field size. When the field is moved
into the destination register, it is right justified and sign extended or zero
extended, as specified by the selected field extension. This instruction also
performs an implicit compare to 0 of the field data.
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.
Machine
States The following typical cases assume that the source data is aligned on a
16-bit boundary: .
16- Bit Field 32-Bit Field
3,6 5,8
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N 1 if the field-extended data moved to register is negative, 0 otherwise
C Unaffected
Z 1 if the field-extended data moved to register is 0,0 otherwise
V 0
12-139
Move Field - Indirect
MOVE (Postincrement) to Register
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15500h 7770h
15510h 7777h
Register AO = 00015500h
Code Before After
FSO/1 FEO/1 AO A1 NCZV
MOVE *AO+,Al,l x/1 x/O 00015501h OOOOOOOOh Ox10
MOVE *AO+,Al,l x/5 x/O 00015505h 00000010h OxOO
MOVE *AO+,Al,O 5/x 1/x 00015505h FFFFFFFOh 1xOO
MOVE *AO+,Al,O 12/x O/x 0001550Ch 00000770h OxOO
MOVE *AO+,Al,l x/12 x/1 0001550Ch 00000770h OxOO
MOVE *AO+,Al,O 18/x 1/x 00015512h FFFF7770h 1xOO
MOVE *AO+,Al,l x/18 x/O 00015512h 00037770h OxOO
MOVE *AO+,Al,O 27/x O/x 0001551Bh 07777770h OxOO
MOVE *AO+,Al,l x/27 x/1 0001551 Bh FF777770h 1xOO
MOVE *AO+,Al,O 31/x 1/x 0001551Fh F7777770h 1xOO
MOVE *AO+,Al,l x/31 x/O 0001551Fh 77777770h OxOO
MOVE *AO+,Al,O 32/x x/x 00015520h 77777770h OxOO
12-140
Move Field - Indirect (Postincrement)
to Indirect (Postincrement) MOVE
Syntax MOVE *Rs+, *Rd+ [, F]
Execution field at * Rs -+ *Rd
Rs + field size -+ Rs
Rd + field size -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
11 0 0 01 F Rs R Rd
Description MOVE moves a field from one memory address to another. The source re-
gister contains the bit address of the field; the destination register contains
the bit address of field's destination. After the move, the contents of both
instructions are incremented by the field size.
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F =0 selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
If Rs and Rd specify the same register, the data read from the location
pointed to by the original contents of Rs is written to the location pointed
to by the incremented value of Rs(Rd). Rs and Rd must be in the same
register file.
Machine
States The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:
16-Bit Field 32-Bit Field
4,7 6+(2),11
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits NUn affected
C Unaffected
Z Unaffected
V Unaffected
12-141
Move Field - Indirect (Postincrement)
MOVE to Indirect (Postincrement)
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data Address Data
15500h FFFFh 15530h OOOOh
15510h FFFFh 15540h OOOOh
15520h FFFFh 15550h OOOOh
MOVE *AO+,*Al+,F
Before After
F AO A1 FSO/1 AO A1 @15530h @15540h @15550h
1 0OO15500h 0OO1553Dh x/1 0OO15501h 0OO1553Eh 2000h OOOOh OOOOh
0 0OO15505h 0OO1553Bh 5/x 0OO1550Ah 0001553Dh 1 FOOh OOOOh OOOOh
1 0OO1550Ah 0OO1553Fh x/10 0OO15514h 0OO15549h BOOOh 01FFh OOOOh
0 0OO1550Dh 0OO15530h 19/x 0OO15520h 0OO15543h FFFFh 0OO7h OOOOh
1 0OO15510h 0OO15532h x/7 0OO15517h 0OO15539h 01FCh OOOOh OOOOh
0 0OO15511h 0001553Ah 13/x 0OO1551Eh 0OO15547h FCOOh 007Fh OOOOh
1 0OO15513h 0OO1553Fh x/B 0OO1551Bh 0OO15547h BOOOh 007Fh OOOOh
0 0OO15510h 0001553Ah 2B/x 0OO1552Ch 0OO15556h FCOOh FFFFh 003Fh
1 0OO1551Bh 0OO15534h x/23 0OO1552Fh 0001554Bh FFFOh 07FFh OOOOh
0 0OO15510h 0OO15530h 31/x 0OO1552Fh 0OO1554Fh FFFFh 7FFFh OOOOh
1 0OO15511h 0001553Dh x/31 0OO15530h 0001555Ch EOOOh FFFFh OFFFh
0 0OO15510h 0OO1553Fh 32/x 0OO15530h 0OO1555Fh BOOOh FFFFh 7FFFh
1 0OO15500h 0OO15530h x/32 0OO15520h 0OO15550h FFFFh FFFFh OOOOh
12-142
Move Field - Indirect
(Predecrement) to Register MOVE
Syntax MOVE -*Rs, Rd [, F}
Execution Rs - field size -+ Rs
field at * Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I1 0 0 0 1 IF Rs R Rd
Description MOVE moves a field from memory to the destination register. The source
register contains a bit address; before the move, the contents of the source
register are decremented by the field size to form the address of the field.
(This value is also the final value for the register.)
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
When the field is moved into the destination register, it is right justified and
sign extended or zero extended to 32 bits according to the value of FE for
the particular F bit selected. This instruction also performs an implicit
compare to 0 of the field data.
Rs and Rd must be in the same register file. If Rs and Rd are the same re-
gister, the pointer information is overwritten by the data fetched.
Machine
States The following typical cases assume that the source data is aligned on a
16-bit boundary:
16- Bit Field 32-Bit Field
4,7 6,9
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N 1 if the field-extended data moved to register is negative, 0 otherwise
C Unaffected
Z 1 if the field-extended data moved to register is 0, 0 otherwise
V 0
12-143
Move Field - Indirect
MOVE (Predecrement) to Register
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15500h 7770h
15510h 7777h
Register AO = 00015520h
Code Before After
FSO/1 FEO/1 AO A1 NCZV
MOVE -*AO,Al,l x/1 x/O 0001551Fh OOOOOOOOh Ox10
MOVE -*AO,Al,O 5/x 1/x 0001551Bh OOOOOOOEh OxOO
MOVE -*AO,Al,l x/5 x/O 0001551Bh OOOOOOOEh OxOO
MOVE -*AO,Al,O 12/x O/x 00015514h 00000777h OxOO
MOVE -*AO,Al,l x/12 x/1 00015514h 00000777h OxOO
MOVE -*AO,Al,O 18/x 1/x 0001550Eh 0001 DDDDh OxOO
MOVE -*AO,Al,l x/18 x/O 0001550Eh 0001 DDDDh OxOO
MOVE -*AO,Al,O 27/x O/x 00015505h 03BBBBBBh OxOO
MOVE -*AO,Al,l x/27 x/1 00015505h 03BBBBBBh OxOO
MOVE -*AO,Al,O 31/x 1/x 00015501h 3BBBBBB8h OxOO
MOVE -*AO,Al,l x/31 x/O 00015501h 3BBBBBB8h OxOO
MOVE -*AO,Al,O 32/x x/x 00015500h 77777770h OxOO
12-144
Move Field - Indirect (Predecrement)
to Indirect (Predecrement) MOVE
Syntax MOVE -*Rs, -*Rd [, FJ
Execution Rs - field size -+ Rs
Rd - field size -+ Rd
(field) * Rs -+ (field) * Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I1 0 0 01 F Rs R Rd I
Description MOVE moves a field from one memory address to another. Both registers
contain bit addresses; before the move, the contents of both registers are
decremented by the field size. The source register then contains the address
of the field, and the destination register specifies the destination address for
the move.
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F =0 selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file. If Rs and Rd are the same re-
gister, then the final contents of the register are its original contents decre-
mented by twice the field size.
Machine
States The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:
16-Bit Field 32- Bit Field
4+ (1 ),8 6+(3),12
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
12-145
Move Field - Indirect (Predecrement)
MOVE to Indirect (Predecrement)
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data Address Data
15500h FFFFh 15530h OOOOh
15510h FFFFh 15540h OOOOh
15520h FFFFh 15550h OOOOh
MOVE -*AO,-*Al,F
Before After
F AO A1 FSO/1 AO A1 @15530h @15540h @15550h
1 0OO15501h 0OO15531h x/1 0OO15500h 0OO15530h 0OO1h OOOOh OOOOh
0 0OO15505h 0OO15539h 5/x 0OO15500h 0OO15534h 01FOh OOOOh OOOOh
1 0OO1550Ah 0OO15544h x/10 0OO1550hO 0OO1553Ah FCOOh OOOFh OOOOh
0 0OO15513h 0OO15552h 19/x 0OO15500h 0OO1553Fh 8000h FFFFh 0OO3h
1 0OO1550Bh 0OO15537h x/7 0OO15504h 0OO15530h 007Fh OOOOh OOOOh
0 0OO15517h 0OO1553Dh 13/x 0OO1550Ah 0OO15530h 1 FFFh OOOOh OOOOh
1 0OO15515h 0OO1553Ch x/8 0OO1550Dh 0OO15534h OFFOh OOOOh OOOOh
0 0OO15529h 0OO1554Ch 28/x 0OO1550Dh 0OO15530h FFFFh OFFFh OOOOh
1 0OO1551Ch 0OO1554Ch x/23 0OO15505h 0OO15535h FFEOh OFFFh OOOOh
0 0OO15527h 0OO15555h 31/x 0OO15508h 0OO15536h FFCOh FFFFh 001Fh
1 0OO15527h 0OO15550h x/31 0OO15508h 0OO15531h FFFEh FFFFh OOOOh
0 0OO1552Ah 0OO15550h 32/x 0OO1550Ah 0OO15530h FFFFh FFFFh OOOOh
1 0OO15520h 0OO1555Ah x/32 0OO15500h 0OO1553Ah FCOOh FFFFh 03FFh
12-146
Move Field - Indirect with Offset to Register MOVE
Syntax MOVE *Rs(offset), Rd [, FJ
Execution field at (* Rs + offset) -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
11
0 0
I F Rs R Rd
offset 1
Description This MOVE instruction moves a field from a memory address to the desti-
nation register. The address of the source data is formed by adding a
signed, 16-bit offset to the contents of Rs. When the field is moved into
the destination register, it is right justified and sign extended or zero ex-
tended to 32 bits, according to the value of the current FE bit. This in-
struction also performs an implicit compare to 0 of the field data.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F param-
eter determines the field size and extension for the move:
F ==0 selects FSO
F==1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file.
Machine
States The following typical cases assume that the source data is aligned on a
16-bit boundary:
16-Bit Field 32- Bit Field
5,11 7,13
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N 1 if the field-extended data moved to register is negative, 0 otherwise
C Unaffected
Z 1 if the field-extended data moved to register is 0, 0 otherwise
V 0
12-147
MOVE Move Field - Indirect with Offset to Register
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15530h 3333h
15540h 4444h
15550h 5555h
Code Before After
AO FSO/1 FEO/1 A1 NCZV.
MOVE *AO(OOOOh),Al,l 00015530h x/1 x/1 FFFFFFFFh 1xOO
MOVE *AO(OOO3h),Al,1 0001552Fh x/2 x/O OOOOOOOOh Ox10
MOVE *AO(OOOlh),Al,O 0001552Fh 5/x O/x 00000013h OxOO
MOVE *AO(OOOFh),Al,O 0001552Dh 8/x 1/x 00000043h OxOO
MOVE *AO(OO20h),Al,1 0001551Ch x/13 x/O 00000443h OxOO
MOVE *AO(OOFFh) ,Al,O 00015435h 16/x 1/x 00004333h OxOO
MOVE *AO(OFFFh) ,Al,O 00014531h 19/x 1/x FFFC3333h 1xOO
MOVE *AO (7FFFh) ,Al, 1 0000D531 h x/22 x/1 00043333h OxOO
MOVE *AO(OFFF2h),Al,1 00015540h x/25 x/O 01110CCCh OxOO
MOVE *AO(8000h),Al,O 0001 D530h 27/x 1/x FC443333h 1xOO
MOVE *AO(OFFFOh),Al,O 00015540h 31/x O/x 44443333h OxOO
MOVE *AO(OFFEOh),Al,l 00015558h x/31 x/1 D5444433h 1xOO
MOVE *AO(OFFECh),Al,O 0001554Dh 32/x O/x AAA22219h 1xOO
MOVE *AO(OOlDh),Al,O 00015520h 32/x 1/x AAAA2221 h 1 xOO
MOVE *AO(OO20h),Al,1 00015520h x/32 x/O 55554444h OxOO
12-148
Move Field - Indirect with Offset
to Indirect (Postincrement) MOVE
Syntax MOVE *Rs(offset), *Rd+ [, FJ
Execution field at (*Rs + offset) ... *Rd
Rd + field size ... Rd
Instruction
Words 15 14 13 12 11 10 9 876 5 4 3 2 o
o o oIF Rs R Rd
offset
Description MOVE moves a field from the one memory location to another. Both the
source and destination registers contain bit addresses. The source memory
address is formed by adding the contents of the source register to the
signed 16-bit offset. The destination register contains the address of the
field's destination; after the move, the contents of Rd are incremented by
the selected field size.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F param-
eter determines the field size and extension for the move:
F =0 selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file.
Machine
States The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:
16-Bit Field 32- Bit Field
5+(1),12 7+(3),16
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
12-149
Move Field - Indirect with Offset
MOVE to Indirect (Postincrement)
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data Address Data
15500h OOOOh 15530h 3333h
15510h OOOOh 15540h 4444h
15520h OOOOh 15550h 5555h
Before After
@15500h @15520h
AO A1 FSO/1 A1 @15510h
MOVE *AO(OOOOh),*Al+,l 00015530h 0015500h x/1 00015501h 0001h OOOOh OOOOh
MOVE *AO(OOOlh),*Al+,l 0001552Fh 00015504h 5/x 00015509h 0130h OOOOh OOOOh
MOVE *AO(OOOFh),*Al+,l 00015520h 0001550Ch 8/x 00015514h 3000h 0004h OOOOh
MOVE *AO(0020h),*Al+,1 0001551 Ch 00015E )Oh x/13 0001551 Ah 6000h 0088h OOOOh
MOVE *AO(OOFFh),*Al+,l 00015535h 0001550Ch16/x 0001551Ch3000h 0433h OOOOh
MOVE *AO(OFFFh),*Al+,l 00015531 h 00015510h 19/x 00015523h OOOOh 3333h 0004h
MOVE *AO(7FFFh),*Al+,1 00000531 h 00015508h x/22 0001551Eh 3300h 0433h OOOOh
MOVE *AO(OFFF2h),*Al+,1 0001 5540h 0015500h x/25 00015519h OCCCh 0111 h OOOOh
MOVE *AO(8000h),*Al+,1 0001 0530h 00015503h 27 Ix 0001551Eh 9998h 2221h OOOOh
MOVE *AO(OFFFOh),*Al+,l 00015540h 00015501 h 31 Ix 0001552Ah 6666h 8888h OOOOh
MOVE *AO(OFFEOh),*Al+,l 00015558h 00015508h x/31 00015527h 3300h 4444h 0055h
MOVE *AO(OFFECh),Al+,l 00015540h 0001550Ah 32/x 00015528h 3200h 4444h 0155h
MOVE *AO(OOlDh),Al+,l 00015520h 00015510h 32/x 00015530h OOOOh 2221 h AAAAh
MOVE *AO(0020h),Al+,1 00015520h 00015510h x/32 00015530h OOOOh 4444h 5555h
12-150
Move Field - Indirect with Offset
to Indirect with Offset MOVE
Syntax MOVE *Rs(SOffset), *Rd(DOffset) [, FJ
Execution field at (*Rs + SOffset) -+ (*Rd + DOffset)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
1 0 1 1 1 oI F I Rs IR I Rd
source offset
destination offset
Description This MOVE instruction moves a field from one memory location to another.
Both the source and destination registers contain bit addresses. The ad-
dress of the source address is formed by adding a signed 16-bit offset to
the contents of the source register. The address of the destination location
is formed by adding a signed 16-bit offset to the contents of the destination
register.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F param-
eter determines the field size and extension for the move:
F =0 selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file.
Machine
States The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:
16- Bit Field 32-Bit Field
5+(1),15 7+(3),19
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
12-151
Move Field - Indirect with Offset
MOVE to Indirect with Offset
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data Address Data
15500h OOOOh 15530h 3333h
15510h OOOOh 15540h 4444h
15520h OOOOh 15550h 5555h
Code Before After
@15500h @15520h
AO A1 FSO/1 @15510h
MOVE *AO(OOOOh),*Al(OOOOh),l 00015530h 0015500h x/1 0001h OOOOh OOOOh
MOVE *AO(OOOlh),*Al(OOOOh),O 0001552Fh 00015504h 5/x 0130h OOOOh OOOOh
MOVE *AO(OOOFh),*Al(OOOFh),O 00015520h 000154FOh 8/x 3000h 0004h OOOOh
MOVE *AO(OO20h),*Al(OOlDh),1 0001551Ch 000154FOh x/13 5000h 0088h OOOOh
MOVE *AO(OOFFh),*Al(OFFF8h),O 00015435h 00015514h 16/x 3000h 0433h OOOOh
MOVE *AO(OFFFh),*Al(OFFFh),O 00014531h 00014511 h 19/x OOOOh 3333h 0004h
MOVE *AO(7FFFh),*Al(8000h),1 00000531 h 0001 0508h x/22 3300h 0433h OOOOh
MOVE *AO(OFFF2h),*Al(7FFFh),1 00015540h 00000501 h x/25 OCCCh 0111 h OOOOh
MOVE *AO(8000h),*Al(0020h),O 0001D530h 000154E3h 27/x 9998h 2221h OOOOh
MOVE *AO(OFFFOh),*Al(OOlOh),O 0OO15540h 000154F1 h 31/x 6666h 8888h OOOOh
MOVE *AO(OFFEOh),*Al(OFFEOh),l 00015558h 00015528h x/31 3300h 4444h 0055h
MOVE *AO(OFFECh),*Al(OFFECh),O 00015540h 00015510h 32/x 3200h 4444h 0155h
MOVE *AO(OOlDh),*Al(0020h),O 00015520h 000154FOh 32/x OOOOh 2221h ~Ah
MOVE *AO(OO20h),*Al(0020h),1 00015520h 000154FOh x/32 OOOOh 4444h 5555h
12-152
Move Field - Absolute to Register MOVE
Syntax MOVE. @SAddress, Rd [, FJ
Execution field at SAddress -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 0 1 IF I 1 1 0 1 IR I Rd
16 LSBs of source address
16 MSBs of source address
Description This MOVE instruction moves a field from memory to the destination reg-
ister. The field data for the move is contained at a source-memory bit ad-
dress. When the field is moved into the destination register, it is right
justified and sign extended or zero extended to 32 bits according to the
selected value of FE. This instruction also performs an implicit compare to
o of the field data.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F param-
eter determines the field size and extension for the move:
F =0 selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Machine
States The following typical cases assume that the source data is aligned on a
16-bit boundary:
16- Bit Field 32-Bit Field
5,15 7,13
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N 1 if the field-extended data moved to register is negative, 0 otherwise
C Unaffected
Z 1 if the field-extended data moved to register is 0, 0 otherwise
V 0
12-153
MOVE Move Field - Absolute to Register
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15500h 7770h
15510h 7777h
Code Before After
FEO/1 FSO/1 A1 NCZV
MOVE @15500h,Al,1 x/O x/1 OOOOOOOOh Ox10
MOVE @15500h,Al,O O/x 5/x 0OOOOO10h OxOO
MOVE @15503h,Al,1 x/1 x/5 OOOOOOOEh OxOO
MOVE @15500h,Al,O O/x 12/x 0OOOO770h OxOO
MOVE @1550Dh,Al,1 x/1 x/12 FFFFFBBBh 1xOO
MOVE @15504h,Al,O 1/x 18/x FFFF7777h 1xOO
MOVE @15500h,Al,1 x/O x/18 0OO37770h OxOO
MOVE @15500h,Al,O O/x 27/x 07777770h OxOO
MOVE @15500h,Al,1 x/1 x/27 FF777770h 1xOO
MOVE @15501h,Al,O O/x 30/x 3BBBBBB8h OxOO
MOVE @15501h,Al,1 x/1 x/30 FBBBBBB8h 1xOO
MOVE @15500h,Al,O x/x 32/x 77777770h OxOO
12-154
Move Field - Absolute to Indirect (Postincrement) MOVE
Syntax MOVE @SAddress, *Rd+ [, FJ
Execution field at SAddress ... * Rd
Rd + field size ... Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
1 1 0 1 0 1 I Flo 0 0 oIR I Rd
16 LSBs of source address
16 MSBs of source address
Description This MOVE instruction moves a field from one location in memory to an-
other. The source address is a 32-bit address; the destination address is
specified by the contents of Rd. After the move, the contents of the desti-
nation register are incremented by the field size.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F param-
eter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file.
Machine
States The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:
16-Bit Field 32-Bit Field
5+(1),15 7+(3),19
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
12-155
MOVE Move Field - Absolute to Indirect (Postincrement)
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data Address Data
15500h FFFFh 15530h OOOOh
15510h FFFFh 15540h OOOOh
15520h FFFFh 15550h OOOOh
Code Before After
@15500h @15526h
AO A1 FEO!1 A1 @15510h
MOVE @15500,*Al+,1 0OO15530h 0OO15531h x/1 0OO15531h 0001h OOOOh OOOOh
MOVE @15500,*Al+,O 0OO15534h 0OO15539h 5/x 0OO15539h 01FOh OOOOh OOOOh
MOVE @15500,*Al+,1 0OO1553Ah 0OO15544h x/10 0OO15544h FCOOh OOOFh OOOOh
MOVE @15500,*Al+,O 0OO1553Fh 0OO15552h 19/x 0OO15552h 8000h FFFFh 0OO3h
MOVE @15504,*Al+,1 0OO15530h 0OO15537h x/7 00015537h 007Fh OOOOh OOOOh
MOVE @1550A,*Al+,O 0OO15530h 0OO1553Dh 13/x 0001553Dh 1FFFh OOOOh OOOOh
MOVE @1550D,*Al+,1 0OO15534h 0OO15536h x/8 00015536h OFFOh OOOOh OOOOh
MOVE @1550D,*Al+,O 0OO15530h 0OO1554Ch 28/x 0001554Ch FFFFh OFFFh OOOOh
MOVE @15505,*Al+,1 0OO15535h 0OO1554Dh x/23 0001554Dh FFEOh OFFFh OOOOh
MOVE @15508,*Al+,O 0OO15536h 0OO15555h 31/x 00015555h FFCOh FFFFh 001Fh
MOVE @15508,*Al+,1 0OO15531h 0OO15548h x/31 00015548h FFFEh FFFFh OOOOh
MOVE @1550A,*Al+,O 0OO15530h 0OO15550h 32/x 00015550h FFFFh FFFFh OOOOh
MOVE @15500,*Al+,1 0OO1553Ah 0OO1555Ah x/32 0001555Ah FCOOh FFFFh 03FFh
12-156
Move Field - Absolute to Absolute MOVE
Syntax MOVE @SAddress, @DAddress [, FJ
Execution field at SAddress -+ DAddress
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 0 1 JF I 1 1 1 0 0 0 0 0 0
16 LSBs of source address
16 MSBs of source address
16 LSBs of destination address
16 MSBs of destination address
Description This MOVE instruction moves a field from one location in memory to an-
other. Both memory addresses are 32-bit addresses.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F param-
eter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Machine
States The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:
16-Bit Field 32-Bit Field
7+(1),12 9+(3),27
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
12-157
MOVE Move Field - Absolute to Absolute
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
15500h FFFFh
15510h FFFFh
15520h FFFFh
15530h OOOOh
15540h OOOOh
15550h OOOOh
Code Before After
FSO/1 @15530h @15540h @15550h
MOVE @15500h,@15530h,1 x/1 0OO1h OOOOh OOOOh
MOVE @15500h,@15534h,O 5/x 01FOh OOOOh OOOOh
MOVE @15500h,@1553Ah,1 x/10 FCOOh OOOFh OOOOh
MOVE @15500h,@1553Fh,O 19/x 8000h FFFFh 0OO3h
MOVE @15504h,@15530h,1 x/7 007Fh OOOOh OOOOh
MOVE @1550Ah,@15530h,O 13/x 1 FFFh OOOOh OOOOh
MOVE @1550Dh,@15534h,1 x/8 OFFOh OOOOh OOOOh
MOVE @1550Dh,@15530h,O 28/x FFFFh OFFFh OOOOh
MOVE @15505h,@15535h,1 x/23 FFEOh OFFFh OOOOh
MOVE @15508h,@15536h,O 31/x FFCOh FFFFh 001Fh
MOVE @15508h,@15531h,1 x/31 FFFEh FFFFh OOOOh
MOVE @1550Ah,@15530h,O 32/x FFFFh FFFFh OOOOh
MOVE @15500h,@1553Ah,O x/32 FCOOh FFFFh 03FFh
12-158
Move Immediate - 16 Bits MOVI
Syntax MOVI IW, Rd [, W}
Execution IW -+ Rd
Instruction
Words 15 14 13 12 11 10 987 6 5 4 3 2 o
o o o o o oIR Rd
16-bit value
Description MOVI stores a 16-bit, sign-extended immediate value in the destination
register. (/W in the instruction syntax represents the 16-bit value.)
The assembler uses the short form if the immediate value has been previ-
ously defined and is in the range -32,768 through 32,767. You can force
the assembler to use the short form by following the register operand with
,W:
MOVI IW,Rd,W
The assembler truncates the upper bits and issue an appropriate warning
message.
Machine
States 2,8
Status Bits N 1 if the data being moved is negative, 0 otherwise
C Unaffected
Z 1 if the data being moved is 0, 0 otherwise
V 0
Examples Code After
AO NCZV
MOVI 32767,AO 00007FFFh OxOO
MOVI 1,AO 00OOOO01h OxOO
MOVI O,AO OOOOOOOOh Ox10
MOVI -l,AO FFFFFFFFh 1xOO
MOVI -32768,AO FFFF8000h 1xOO
MOVI OOOOh,AO OOOOOOOOh Ox10
MOVI 7FFFh,AO 0OO07FFFh OxOO
12-159
MOVI Move Immediate - 32 Bits
Syntax MOVI IL, Rd {, l]
Execution IL -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 1 0 0 1 1 1 1 IR I Rd
16 LSBs of IL
16 MSBs of IL
Description MOVI stores a 32-bit immediate value in the destination register. (lL in the
instruction syntax represents the 32-bit value.)
The assembler uses this opcode if it cannot use the MOVI IW, Rd opcode,
or if the long opcode is forced by following the register operand with ,l:
MOVI IL,Rd,L
Machine
States 3,12
Status Bits N 1 if the data being moved is negative, 0 otherwise
C Unaffected
Z 1 if the data being moved is 0, 0 otherwise
V 0
Examples Code After
AO NCZV
MOVI 2147483647,AO 7FFFFFFFh OxOO
MOVI 32768,AO 00008000h OxOO
MOVI -32769,AO FFFF7FFFh 1xOO
MOVI -2147483648,AO 80000000h 1xOO
MOVI 8000h,AO 0OOO8000h OxOO
MOVI OFFFFFFFFh,AO FFFFFFFFh 1xOO
MOVI OFFFFh,AO,L FFFFFFFFh 1xOO
12-160
Move Constant (5 Bits) MOVK
Syntax MOVK K,Rd
Execution K -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 0 01 K R Rd I
Description MOVK stores a 5-bit constant in the destination register. (K in the in-
struction syntax represents the constant.) The constant is treated as an
unsigned number in the range 1-32, where K = 0 in the opcode corre-
sponds to a value of 32. The resulting constant value is zero extended to
32 bits.
Note that you cannot set a register to 0 with this instruction. You can clear
a register by XORing the register with itself; use CLR Rd (an alternate
mnemonic for XOR) to accomplish this. Both these methods alter the Z bit
(set it to 1 ).
Machine
States 1,4
Status Bits NUn affected
C Unaffected
Z Unaffected
V Unaffected
Examples Code After
AO
MOVK 1,AO 00000001h
MOVK S,AO 00000008h
MOVK 16,AO 00000010h
MOVK 32,AO 00000020h
12-161
MOVX Move X Half of Register
Syntax MOVX Rs,Rd
Execution RsX -+ RdX
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
11 0 01 Rs IR Rd
Description MOVX moves the X half of the source register (16 LSBs) to the X half of
the destination register. The Y halves of both registers are unaffected.
You an also use the MOVX and MOVY instructions for handling packed
16-bit quantities and XY addresses. You can use the RL instruction to
swap the contents of X and Y.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
AO A1 A1
MOVX AO,Al OOOOOOOOh FFFFFFFFh FFFFOOOOh
MOVX AO,Al 12345678h OOOOOOOOh 00005678h
MOVX AO,Al FFFFFFFFh OOOOOOOOh OOOOFFFFh
12-162
Move Y Half of Register MOVY
Syntax MOVV Rs, Rd
Execution RsV -+ RdV
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I1 0 Rs R Rd I
Description MOVY moves the Y half of the source register (16 MSBs) to the Y half of
the destination register. The X halves of both registers are unaffected.
You an also use the MOVX and MOVY instructions for handling packed
16-bit quantities and XY addresses. You can use the RL instruction to
swap the contents of X and Y.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
AO A1 A1
MOVY AO,Al OOOOOOOOh FFFFFFFFh OOOOFFFFh
MOVY AO,Al 12345678h OOOOOOOOh 12340000h
MOVY AO,Al FFFFFFFFh OOOOOOOOh FFFFOOOOh
12-163
MPYS Multiply Registers - Signed
Syntax MPYS Rs, Rd
Execution Rd Even: Rs x Rd -+ Rd:Rd+1
Rd Odd: Rs x Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 01 Rs R Rd 1
Description MPYS performs a signed multiply of a variably-sized field in the source re-
gister by the 32 bits in the destination register. This produces a 32-bit to
a 64-bit result, depending on the register and field definitions. Note that
Rs and Rd must be in the same register file.
The value of field size 1 (FS1) defines the size of the multiplier in Rs. FS1
may have any even value n from 2 to 32 (that is, n = 2, 4, 6 ... 30, 32).
The instruction executes a 32-bit-by-n-bit multiply - multiplying the 32 bits
in Rd by the n bits in Rs. All values are signed. The MSB of the source field
(bit n - 1 in Rs) defines the sign of the field; the bits to the left of bit n are
ignored. The MSB of Rd defines the sign of the multiplicand.
Contents of Rs (n = FS1): Contents of Rd:
31 n n-1 o 31 o
n-bit multiplier 32-bit multiplicand
sign bit sign bit
M PYS has two modes, depending on whether Rd is even or odd:
• Rd Even:
M PYS multiplies the contents of Rd by the n-bit field in Rs, and stores
the result in two consecutive registers, Rd and Rd+1. (For example,
if Rd = B4, the result is stored in registers B4 and B5.) The result is
sign extended and right justified; the 32 MSBs are stored in Rd and
the 32 LSBs are stored in Rd+1. Note that all 32 bits of both registers
are used, regardless of the field size of the mUltiply.
Do not use A14 or B14 as the destination register, because Rd+1
(A15 or B15) is the stack pointer register (SP). It is not desirable to
write over the contents of the SP.
Contents of Rd (even register): Contents of Rd+1 (odd register):
~ 0 ~ 0
I sign I n MSBs of result I 32 LSBs of result I
• Rd Odd:
MPYS multiplies the contents of Rd by the n-bit field in Rs, and stores
the 32 LSBs of the result in Rd; Rs is not changed. If the result is
greater than 32 bits, the extra MSBs are discarded, regardless of the
field size.
Contents of Rd (odd register):
31 0
32 MSBs are discarded I 32 LSBs of result I
12-164
Multiply Registers - Signed MPYS
Machine
States 5 + FS1/2, 8 + FS1/2
Status Bits N 1 if the result is negative, a otherwise
C Unaffected
Z 1 if the result is 0, a otherwise
V Unaffected
Example 1 MPYS AI, AD
Before After
AO A1 FS1 AO A1 NCZV
OOOOOOOOh OOOOOOOOh 32 OOOOOOOOh OOOOOOOOh Ox1x
7FFFFFFFh 7FFFFFFFh 32 3FFFFFFFh 0000OOO1h OxOx
7FFFFFFFh FFFFFFFFh 32 FFFFFFFFh 80000001h 1xOx
FFFFFFFFh 7FFFFFFFh 32 FFFFFFFFh 80000001h 1xOx
FFFFFFFFh FFFFFFFFh 32 OOOOOOOOh 000OOO01h OxOx
80000000h 7FFFFFFFh 32 COOOOOOOh 80000000h 1xOx
80000000h 80000000h 32 40000000h OOOOOOOOh OxOx
80000001h 80000000h 32 3FFFFFFFh 80000000h OxOx
8040156Fh 7FF3B074h 32 C0262CDCh 53E486F8h 1xOx
8040156Fh 7FF3B074h 24 000624B1h 53E486F8h OxOx
8040156Fh 7FF3B074h 20 FFFE28B2h 594486F8h 1xOx
8040156Fh 7FF3B074h 16 0OOO27B2h 17EC86F8h OxOx
8040156Fh 7FF3B074h 14 0OOOO7C2h 1 C0206F8h OxOx
8040156Fh 7FF3B074h 8 FFFFFFC6h 1 D0766F8h 1 xOx
8040156Fh 7FF3B074h 6 0OOOOO05h FCFF3BF8h OxOx
8040156Fh 7FF3B074h 4 FFFFFFFEh 01004158h 1xOx
8040156Fh 7FF3B074h 2 OOOOOOOOh OOOOOOOOh Ox1x
Example 2 MPYS AD,AI
Before After
AO A1 FS1 AO A1 NCZV
OOOOOOOOh OOOOOOOOh 32 unchanged OOOOOOOOh Ox1x
7FFFFFFFh 7FFFFFFFh 32 unchanged 000OOO01h OxOx
7FFFFFFFh 7FFFFFFFh 32 unchanged 80000001h 1 xOx
FFFFFFFFh 7FFFFFFFh 32 unchanged 80000001h 1 xOx
FFFFFFFFh FFFFFFFFh 32 unchanged 0OOOOO01h OxOx
80000000h 7FFFFFFFh 32 unchanged 80000000h 1xOx
80000000h 80000000h 32 unchanged OOOOOOOOh OxOx
80000001h 80000000h 32 unchanged 80000000h OxOx
7FF3B074h 80401056h 32 unchanged 53E486F8h 1xOx
7FF3B074h 80401056h 24 unchanged 53E486F8h OxOx
7FF3B074h 80401056h 20 unchanged 594486F8h 1xOx
7FF3B074h 80401056h 16 unchanged 17EC86F8h OxOx
7FF3B074h 80401056h 14 unchanged 1 C0206F8h OxOx
7FF3B074h 80401056h 8 unchanged 1 D0766F8h 1 xOx
7FF3B074h 80401056h 6 unchanged FCFF3BF8h OxOx
7FF3B074h 80401056h 4 unchanged 01004158h 1xOx
7FF3B074h 80401056h 2 unchanged OOOOOOOOh Ox1x
12-165
MPYU Multiply Registers - Unsigned
Syntax MPYU Rs, Rd
Execution Rd Even: Rs x Rd
Rd Odd: Rs x Rd -- Rd:Rd+1
Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 Rs R Rd I
Description MPYU performs an unsigned multiply of a variably-sized field in the source
register by the 32 bits in the destination register. This produces a 32-bit to
a 54-bit result, depending on the register and field definitions. Note that
Rs and Rd must be in the same register file.
The value of field size 1 (FS1) defines the size of the multiplier in Rs. FS1
may have any even value n from 2 to 32 (that is, n = 2, 4, 6 ... 30, 32).
The instruction executes a 32-bit-by-n-bit multiply - multiplying the 32 bits
in Rd by the n bits in Rs. All values are unsigned.
Contents of Rs (n = FS1): Contents of Rd:
31 n n-1 o 31 o
I ignored I n-bit multiplier I 32-bit multiplicand
MPYS has two modes, depending on whether Rd is even or odd:
• Rd Even:
MPYU multiplies the contents of Rd by the n-bit field in Rs, and
stores the result in two consecutive registers, Rd and Rd+1. (For
example, if Rd=B4, the result is stored in registers B4 and B5.) The
result is zero extended and right justified; the 32 MSBs are stored in
Rd and the 32 LSBs are stored in Rd+1. Note that all 32 bits of both
registers are used, regardless of the field size of the mUltiply.
Do not use A14 or B14 as the destination register, because Rd+1
(A15 or B15) is the stack pointer register (SP). It is not desirable to
write over the contents of the S P.
Contents of Rd (even register): Contents of Rd+1 (odd register):
~ O~ 0
I Os I n MSBs of result I 32 LSBs of result I
• Rd Odd:
MPYU multiplies the contents of Rd by the n-bit field in Rs, and
stores the 32 LSBs of the result in Rd; Rs is not changed. If the result
is greater than 32 bits, the extra MSBs are discarded, regardless of the
field size.
Contents of Rd (odd register):
~ 0
32 MSBs are discarded I 32 LSBs of result I
12-166
Multiply Registers - Unsigned MPYU
Machine
States Rs nonnegative: 5 + FS1/2, 8 + FS1/2
Rs negative: 6 + FS1 /2, 9 + FS1/2
Status Bits N Unaffected
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Example 1 MPYU Al,AO
Before After
AO A1 FS1 AO A1 NCZV
FFFFOOOOh 10000000h 32 OFFFFOOOh OOOOOOOOh xxOx
FFFFOOOOh 10001 01 Oh 32 1000000Fh EFFOOOOOh xxOx
FFFFOOOOh 10001 01 Oh 16 0000100Fh EFFOOOOOh xxOx
FFFFOOOOh 10001010h 8 OOOOOOOFh FFFOOOOOh xxOx
FFFFOOOOh 10001010h 4 OOOOOOOOh OOOOOOOOh xx1x
08001056h 0003B074h 32 00001D83h DC4486F8h xxOx
08001056h 0003B074h 16 00000583h AB4286F8h xxOx
08001056h 0003B074h 14 00000183h A31786F8h xxOx
08001056h 0003B074h 8 00000003h A00766F8h xxOx
08001056h 0003B074h 6 00000001h A0035178h xxOx
08001056h 0003B074h 4 OOOOOOOOh 20004158h xxOx
08001056h 0003B074h 2 OOOOOOOOh OOOOOOOOh xx1x
Example 2 MPYU AO,Al
Before After
AO A1 FS1 AO A1 NCZV
10000000h FFFFOOOOh 32 unchanged OOOOOOOOh xxOx
10001010h FFFFOOOOh 32 unchanged EFFOOOOOh xxOx
10001 010h FFFFOOOOh 16 unchanged EFFOOOOOh xxOx
10001 010h FFFFOOOOh 8 unchanged FFFOOOOOh xxOx
10001 010h FFFFOOOOh 4 unchanged OOOOOOOOh xx1x
0003B074h 08001056h 32 unchanged DC4486F8h xxOx
0003B074h 08001056h 16 unchanged AB4286F8h xxOx
0003B074h 08001056h 14 unchanged A31786F8h xxOx
0003B074h 08001056h 8 unchanged A00766F8h xxOx
0003B074h 08001056h 6 unchanged A0035178h xxOx
0003B074h 08001056h 4 unchanged 20004158h xxOx
0003B074h 08001056h 2 unchanged OOOOOOOOh xx1x
12-167
NEG Negate Register
Syntax NEG Rd
Execution 2s complement of Rd - Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 1 IR Rd
I
Description NEG stores the 2s complement of the contents of the destination register
back into the destination register.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a borrow (Rd '¢ 0), 0 otherwise
Z a
1 if the result is 0, otherwise
V 1 if there is an overflow (Rd = 80000000h), 0 otherwise
Examples Code Before After
AO NCZV AO
NEG AD OOOOOOOOh 0010 OOOOOOOOh
NEG AD 55555555h 1100 AAAAAAABh
NEG AD 7FFFFFFFh 1100 80000001h
NEG AD 80000000h 1101 80000000h
NEG AO 80000001h 0100 7FFFFFFFh
NEG AD FFFFFFFFh 0100 00000001h
12-168
Negate Register with Borrow NEGB
Syntax NEGB Rd
Execution (2s complement of Rd) - C -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 oIR Rd I
Description NEG B takes the 2s complement of the destination register's contents and
decrements by 1 if the borrow bit (C) is set; the result is stored in the des-
tination register. This instruction can be used in sequence with itself and
with the NEG instruction for negating multiple-register quantities.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a borrow, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
AO C NCZV AO
NEGB AO OOOOOOOOh 0 0010 OOOOOOOOh
NEGB AO OOOOOOOOh 1 1100 FFFFFFFFh
NEGB AO 55555555h 0 1100 AAAAAAABh
NEGB AO 55555555h 1 1100 AAAAAAAAh
NEGB AO 7FFFFFFFh 0 1100 80000001h
NEGB AO 7FFFFFFFh 1 1100 80000000h
NEGB AO 80000000h 0 1101 80000000h
NEGB AO 80000000h 1 0100 7FFFFFFFh
NEGB AO 80000001h 0 0100 7FFFFFFFh
NEGB AO 80000001h 1 0100 7FFFFFFEh
NEGB AO FFFFFFFFh 0 0100 00000001h
NEGB AO FFFFFFFFh 1 0110 OOOOOOOOh
12-169
NOP No Operation
Syntax NOP
Execution No operation
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I0 0 0 0 0 0 0 0 0 0 0 0 0 01
Description The program counter is incremented to point to the next instruction. The
processor status is otherwise unaffected.
You an use the NOP instruction to pad loops and perform other timing
functions.
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Example Before After
PC PC
NOP 00020000h 00020010h
12-170
Complement Register NOT
Syntax NOT Rd
Execution NOT Rd ... Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 1 I R Rd I
Description NOT stores the 1s complement of the destination register's contents back
into the destination register.
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
AO NCZV AO
NOT AO OOOOOOOOh xxOx FFFFFFFFh
NOT AO 55555555h xxOx AAAAAAAAh
NOT AO FFFFFFFFh xx1x OOOOOOOOh
NOT AO 80000000h xxOx 7FFFFFFFh
12-171
OR OR Registers
Syntax OR Rs, Rd
Execution Rs OR Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 0 01 Rs 1R Rd I
Description This instruction bitwise-ORs the contents of the source register with -the
contents of the destination register; the result is stored in the destination
register.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
AO A1 A1 NCZV
OR AD,Al FFFFFFFFh OOOOOOOOh FFFFFFFFh xxOx
OR AD,Al OOOOOOOOh FFFFFFFFh FFFFFFFFh xxOx
OR AD,Al 55555555h AAAAAAAAh FFFFFFFFh xxOx
OR AD,Al OOOOOOOOh OOOOOOOOh OOOOOOOOh xx1x
12-172
OR Immediate (32 Bits) ORI
Syntax ORI IL, Rd
Execution IL DR Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 1 0 1 1 1 0 1 IR I Rd
16 LSBs of IL
16 MSBs of IL
Description This instruction bitwise-DRs a 32-bit immediate value with the contents of
the destination register and stores the result in the destination register. (lL
in the syntax represents the 32-bit value.)
Machine
States 3,12
Status Bits N Unaffected
C Unaffected
Z 1 if the result is 0, a otherwise
V Unaffected
Examples Code Before After
AO AO NCZV
ORI OFFFFFFFFh,AO OOOOOOOOh FFFFFFFFh xxOx
ORI oOOOOOOOh,AO FFFFFFFFh FFFFFFFFh xxOx
ORI OAAAAAAAAh,AO 55555555h FFFFFFFFh xxOx
ORI oOOOOOOOh,AO OOOOOOOOh OOOOOOOOh xx1x
12-173
PIXBLT Pixel Block Transfer - Binary to Linear
Syntax PIXBLT B, L
Execution binary pixel array -+ linear pixel array (with processing)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 543 2 o
I0 0 0 0 00000 o 0
Description This PIXBLT instruction expands, transfers, and processes a binary source
pixel array with a destination pixel array.
This instruction operates on two-dimensional arrays of pixels using linear
starting addresses for both the source and the destination. The source pixel
array is treated as a one bit per pixel array. As the PixBlt proceeds, the
source pixels are expanded and then combined with the corresponding
destination pixels based on the selected graphics operations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT B, L. The first parameter, B, indi-
cates that the starting address of the source array is a linear address but the
source array is a binary array. The second parameter, L, indicates that the
starting address of the destination array is a linear address. The foilowing
set of implied operands govern the operation of the instruction and define
the source and destination arrays.
Implied
Operands B File Registers
Register Name Format Description
BOt SADDR Linear Source pixel array starting address
B1 SPTCH Linear Source pixel array pitch
B2t DADDR Linear Destination pixel array starting address
B3 DPTCH Linear Destination pixel array pitch
B7 DYDX XY Pixel array dimensions (rows:columns)
B8 COlORO Pixel Background expansion color
B9 COlOR1 Pixel Foreground expansion color
B1<rB14t Reserved registers
1/0 Registers
Address Name Description and Elements (Bits)
COOOOOOBOh CONTROL PP- Pixel processing operations (22 options)
T - Transparency operation
COOOO150h PSIZE Pixel size (1,2,4,8,16)
COOOO160h PMASK Plane mask - pixel format
t These registers are changed by PIXBlT execution.
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXBLT instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
12-174
Pixel Block Transfer - Binary to Linear PIXBLT
Source Array The source pixel array for the expand operation is defined by the contents
of the SADDR, SPTCH, and DYDX registers:
• At the outset of the instruction, SADDR contains the linear address
of the pixel with the lowest address in the array. During instruction
execution, SADDR points to the address of the next set of 32 pixels
to be read from the source array. When the transfer is complete,
SADDR points to the linear address of the first pixel on the next row
of pixels that would have been moved if the block transfer continued.
• SPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the source array. For this PIXBLT instruction, SPTCH
can be any value.
• DYDX specifies the dimensions, in pixels, of both the source and
destination arrays. The DY portion of DYDX contains the number of
rows in the array; the DX portion contains the number of pixels per
row.
Source
Expansion The actual values of the source pixels are determined by the interaction of
the source array with the contents of the COLOR1 and COLORO registers.
In the expansion operation, a 1 bit in the source array selects a pixel from
the COLOR1 register for operation on the destination array. A 0 bit in the
source array selects a COLORO pixel for this purpose. The pixels selected
from the COLOR1 and COLORO registers are those that align directly with
their intended position in the destination array word.
Destination
Array The location of the destination pixel block is defined by the contents of the
DADDR, DPTCH, and DYDX registers:
• At the outset of the instruction, DADDR contains the linear address
of the pixel with the lowest address in the array. During instruction
execution, DADDR points to the next pixel (or word of pixels) to be
modified in the destination array. When the block transfer is com-
plete, DADDR points to the linear address of the first pixel on the
next row of pixels that would have been moved if the block transfer
continued.
• DPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the destination array (typically this is the screen pitch).
DPTCH must be a multiple of 16. '
• DYDX specifies the dimensions, in pixels, of both the source and
destination arrays. The DY portion of DYDX contains the number of
rows in the array; the DX portion contains the number of pixels per
row.
Corner Adjust No corner adjust is performed for this instruction
PBH and PBV are' ignored. The pixel transfer simply proceeds in the order
of increasing linear addresses.
Window
Checking You cannot use window checking with this PixBlt instruction. The con-
tents of the WSTART and WEND registers are ignored.
12-175
PIXBLT Pixel Block Transfer - Binary to Linear
Pixel
Processing You can select a pixel processing option for this instruction by setting the
PPOP bits in the CONTROL register. The pixel processing operation is
applied to expanded pixels as they are processed with the destination array;
that is, the data is first expanded and then processed. There are 1 6 Boolean
and 6 arithmetic operations; the default case at reset is the replace (S -.
D) operation. The 6 arithmetic operations do not operate with pixel sizes
of one or two bits per pixel. For more information, see Section 7.7, Pixel
Processing, on page 7 -15.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
pixels after it expands and processes the source data. At reset, the default
case for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
Interrupts This instruction can be interrupted at a word or row boundary of the desti-
nation array. When the PixBlt is interrupted, the TMS3401 0 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH, SPTCH, and B1 o-B14 contain intermediate values.
DADDR points to the linear address of the next word of pixels to be modi-
fied after the interrupt is processed. SADDR points to the address of the
next 32 pixels to be read from the source array after the interrupt is proc-
essed.
The PIXBLT instruction uses several I/O and B-file registers as implied op-
erands. If an interrupt service routine modifies a register that the PIXBLT
uses as an implied operand, you must restore that register to the value it had
when the routine began, before returning from the routine. (You can use
the MMFM and MMTM instructions to save and restore the B-file regis-
ters.) In order to maintain compatibility with future TMS340 devices, use
only the RETI instruction to return from an interrupt routine.
Shift Register
Transfers If the SRT bit in the DPYCTL I/O register is set, each memory read or write
initiated by the PixBlt generates a shift register transfer read or write cycle
at the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.)
Machine
States See PIXBLT Expand Instructions Timing, Section 13.5.
Status Bits N Undefined
C Undefined
Z Undefined
V Undefined
Examples Before executing the PIXBLT instruction, load the implied operand registers
with appropriate values. These PIXBLT examples use the following implied
operand setup:
Register File B: I/O Registers:
SADDR (BO) 00002030h PSIZE = 0010h
SPTCH (B1) 00000100h
DADDR (B2) 00033000h
12-176
Pixel Block Transfer - Binary to Linear PIXBLT
DPTCH (B3) 00001000h
DYDX (B7) 00020010h
COlORO (B8) FEDCFEDCh
COlOR1 (BS) BAS8BAS8h
Additional implied operand values are listed with each example.
For this example, assume that memory contains the following data before
instruction execution.
Linear Data
Address
02000h xxxxh, xxxxh, xxxxh, 1234h, xxxxh, xxxxh, xxxxh, xxxxh
02080h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, 5678h, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
33000h FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
33080h FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
34000h FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
34080h FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
Example 1 This example uses the rep/ace (S ..... 0) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
33000h FEDCh,FEDCh,BAS8h,FEDCh,BAS8h, BAS8h, FEDCh,FEDCh
33080h FEDCh, BAS8h, FEDCh, FEDCh, BAS8h, FEDCh, FEDCh, FEDCh
34000h FEDCh,FEDCh,FEDCh,BAS8h, BAS8h,BAS8h,BAS8h, FEDCh
34080h FEDCh,BAS8h, BAS8h,FEDCh,BAS8h,FEDCh,BAS8h,FEDCh
Example 2 This example uses the (0 - S) ..... 0 pixel processing operation. Before in-
struction execution, PMASK = OOOOh and CONTROL = 4800h (T=O,
PP=1 001 0).
After instruction execution, memory contains the following values:
Linear Data
Address
33000h 0123h, 0123h, 4567h, 0123h, 4567h, 4567h, 0123h, 0123h
33080h 0123h, 4567h, 0123h, 0123h, 4567h, 0123h, 0123h, 0123h
34000h 0123h, 0123h, 0123h, 4567h, 4567h, 4567h, 4567h, 0123h
34080h 0123h, 4567h, 4567h, 0123h, 4567h, 0123h, 4567h, 0123h
12-177
PIXBLT Pixel Block Transfer - Binary to Linear
Example 3 This example uses transparency with COLORO = OOOOOOOOh. Before in-
struction execution, PMASK = OOOOh and CONTROL = 0020h (T=1,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
33000h FFFFh, FFFFh, BA98h, FFFFh, BA98h, BA98h, FFFFh, FFFFh
33080h FFFFh, BA98h, FFFFh, FFFFh, BA98h, FFFFh, FFFFh, FFFFh
34000h FFFFh, FFFFh, FFFFh, BA98h, BA98h, BA98h, BA98h, FFFFh
34080h FFFFh, BA98h, BA98h, FFFFh, BA98h, FFFFh, BA98h, FFFFh
Example 4 This example uses plane masking
the four LSBs are masked. Before instruction execution, PMASK = OOOFh
and CONTROL = OOOOh (T=O, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
33000h FEDFh, FEDFh, BA9Fh,FEDFh, BA9Fh, BA9Fh, FEDFh, FEDFh
33080h FEDFh, BA9Fh,FEDFh, FEDFh, BA9Fh,FEDFh, FEDFh, FEDFh
34000h FEDFh, FEDFh, FEDFh, BA9Fh, BA9Fh, BA9Fh, BA9Fh, FEDFh
34080h FEDFh, BA9Fh,BA9Fh,FEDFh, BA9Fh,FEDFh, BA9Fh,FEDFh
12-178
Pixel Block Transfer - Binary to XY PIXBLT
Syntax PIXBLT B, XV
Execution binary pixel array -+ XY pixel array (with processing)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
10000 0 000 o 0
Description This PIXBLT instruction expands, transfers, and processes a binary source
pixel array with a destination pixel array.
This instruction operates on two-dimensional arrays of pixels using a linear
starting address for the source and an XY address for the destination. The
source pixel array is treated as a one bit per pixel array. As the PixBlt pro-
ceeds, the source pixels are expanded and then combined with the corre-
sponding destination pixels based on the selected graphics operations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT B,XY. The first parameter, B, indi-
cates that the starting address of the source array is a linear address but the
source array is a binary array. The second parameter, XV, indicates that the
starting address of the destination array is an XY address.
The following set of implied operands govern the operation of the in-
struction and define the source and destination arrays.
Implied
Operands B File Registers
Register Name Format Description
BOt SADDR Linear Source pixel array starting address
B1 SPTCH Linear Source pixel array pitch
B2t+ DADDR XV Destination pixel array starting address
B3 DPTCH Linear Destination pixel array pitch
B4 OFFSET Linear Screen origin (0,0)
B5 WSTART XV Window starting corner
B6 WEND XV Window ending corner
B7+ DVDX XV Pixel array dimensions (rows:columns)
B8 COLORO Pixel Background expansion color
B9 COLOR1 Pixel Foreground expansion color
B1O-B14t Reserved registers
I/O Registers
Address Name Description and Elements (Bits)
COOOOOOBOh CONTROL PP- Pixel processing operations (22 options)
W - Window clipping or pick operation
T - Transparency operation
COOO0130h CONVSP XV -to-linear conversion (source pitch)
Used for source preclipping.
COOO0140h CONVDP XV -to-linear conversion (destination pitch)
COOO0150h PSIZE Pixel size (1,2.4,6,8,16)
COOO0160h PMASK Plane mask - pixel format
t These registers are changed by PIXBLT execution.
+ Used for common rectangle function with window hit operation (W=1).
12-179
PIXBlT Pixel Block Transfer - Binary to XY
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXBLT instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Source Array The source pixel array for the expand operation is defined by the contents
of the SADDR, SPTCH, DYDX, and (possibly) CONVSP registers:
• At the outset of the instruction, SADDR contains the linear address
of the pixel with the lowest address in the array. During instruction
execution, SADDR points to the address of the next set of 32 pixels
to be read from the source array. When the block transfer is complete,
SADDR points to the linear address of the first pixel on the next row
of pixels that would have been moved if the block transfer continued.
• SPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the source array. SPTCH can be any value for this
PIXBLT. For window clipping, SPTCH must be a power of two, and
CONVSP must be set to correspond to the SPTCH value.
• CONVSP is calculated by taking the LMO of SPTCH; this value is
used for the XY calculations involved in XY addressing and window
clipping.
• DYDX specifies the dimensions, in pixels, of both the source and
destination arrays in pixels. The DY portion of DYDX contains the
number of rows in the array; the the DX portion contains the number
of pixels per row.
Source
Expansion The actual values of the source pixels are determined by the interaction of
the source array with contents of the COLOR1 and COLORO registers. In
the expansion operation, a 1 bit in the source array selects a pixel from the
COLOR1 register for operation on the destination array. A 0 bit in the
source array selects a COLORO pixel for this purpose. The pixels selected
from the COLOR1 and COLORO registers are those that align directly with
their intended position in the destination array word.
Destination
Array The location of the destination pixel block is defined by the contents of the
DADDR, DPTCH, CONVDP, OFFSET, and DYDX registers:
• At the outset of the instruction, DADDR contains the XV address of
the pixel with the lowest address in the array; it is used with OFFSET
and CONVDP to calculate the linear address of the array. During in-
struction execution, DADDR points to the linear address of next
pixel (or word of pixels) to be modified in the destination array. When
the block transfer is complete, DADDR points to the linear address
of the first pixel on the next row of pixels that would have been
moved if the block transfer continued.
• DPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the destination array (typically this is the screen pitch).
DPTCH must be a power of two (greater than or equal to 16) and
CONVDP must be set to correspond to the DPTCH value.
12-180
Pixel Block Transfer - Binary to XY PIXBLT
• CONVOP is determined by taking the LMO of the OPTCH register;
this value is used for the XY calculations involved in XY addressing
and window clipping.
• OYOX specifies the dimensions, in pixels, of both the source and
destination arrays. The OY portion of OYOX contains the number of
rows in the array; the OX portion contains the number of pixels per
row.
Corner Adjust No corner adjust is performed for this instruction. The transfer executes in
the order of increasing linear addresses. PBH and PBV are ignored.
Window
Checking You can use window checking with this instruction by setting the W bits
in the CONTROL register to the desired value. If you select window
checking mode 1, 2, or 3, the WSTART and WEN 0 registers define the XY
starting and ending corners of a rectangular window.
o No windowing. The entire pixel array is drawn and the WVP and V bits
are unaffected.
1 Window hit. No pixels are drawn. The V bit is set to 0 if any portion of
the destination array lies within the window. Otherwise, the V bit is set
to 1.
If the V bit is set to 0, the OAOOR and OYOX registers are modified to
correspond to the common rectangle formed by the intersection of the
destination array with the rectangular window. OAOOR is set to the XY
address of the pixel in the starting corner of the common rectangle.
OYOX is set to the X and Y dimensions of the common rectangle.
If the V bit is set to 1, the array lies entirely outside the window, and the
values of OAOOR and OYOX are indeterminate.
2 Window miss. If the array lies entirely within the active window, it is
drawn and the V bit is set to O. Otherwise, no pixels are drawn, the V
and WVP bits are set to 1, and the instruction is aborted.
3 Window clip. The source and destination arrays are preclipped to the
window dimensions. Only those pixels that lie within the common rec-
tangle (corresponding to the intersection of the specified array and the
window) are drawn. If any preclipping is required, the V bit is set to 1.
Pixel
Processing You can select a pixel processing option for this instruction by setting the
PPOP bits in the CONTROL register. The pixel processing operation is
applied to expanded pixels as they are processed with the destination array;
that is, the data is first expanded and then processed. There are 16 Boolean
and 6 arithmetic operations; the default case at reset is the S ..... 0 operation.
The 6 arithmetic operations do not operate with pixel sizes of one or two
bits per pixel. For more information, see Section 7.7, Pixel Processing, on
page 7-15.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
pixels after it expands and processes the source data. At reset, the default
case for transparency is off.
12-181
PIXBLT Pixel Block Transfer - Binary to XY
Plane Mask The plane mask is enabled for this instruction.
Interrupts This instruction can be interrupted at a word or row boundary of the desti-
nation array. When the PixBlt is interrupted, the TMS3401 0 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH, SPTCH, and B1 o-B14 contain intermediate values.
DADDR points to the linear address of the next word of pixels to be modi-
fied after the interrupt is processed. SADDR points to the address of the
next 32 pixels to be read from the source array after the interrupt is proc-
essed.
The PIXBLT instruction uses several I/O and B-file registers as implied op-
erands. If an interrupt service routine modifies a register that the PIXBLT
uses as an implied operand, you must restore that register to the value it had
when the routine began, before returning from the routine. (You can use
the MMFM and MMTM instructions to save and restore the B-file regis-
ters.) In order to maintain comnatibility with future TMS340 devices, use
only the RETI instruction to return from an interrupt routine.
Shift Register
Transfers If the SRT bit in the DPYCTL I/O register is set, each memory read or write
initiated by the PixBlt generates a shift register transfer read or write cycle
at the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.)
Machine
States See PIXBLT Expand Instructions Timing, Section 13.5.
Status Bits N Undefined
C Undefined
Z Undefined
V 1 if a window violation occurs, 0 otherwise; undefined if window
checking is not enabled (W=OO)
12-182
Pixel Block Transfer - Binary to XY PIXBLT
Examples Before executing a PIXBLT instruction, load the implied operand registers
with appropriate values. These PIXBLT examples use the following implied
operand setup.
Register File B: I/O Registers:
SADDR (BO) = 00002010h PSIZE = 0008h
SPTCH (B1) = 00000010h CONVSP = 001 Bh
DADDR (B2) = 00300022h CONVDP = 0013h
DPTCH (B3) = 00001000h
OFFSET (B4) = 00010000h
WSTART (B5) = 00000026h
WEND (B6) = 00400050h
DYDX (B7) = 00040010h
COLORO (B8) = OOOOOOOOh
COLOR1 (B9) = 7C7C7C7Ch
Additional implied operand values are listed with each example.
For this example, assume that memory contains the following data before
instruction execution.
Linear Data
Address
2000h xxxxh, 0123h, 4567h, 89ABh, CDEFh, xxxxh, xxxxh, xxxxh
40000hto
43200h FFFFh
Example 1 This example uses the rep/ace (S - D) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
40100h FFFFh, 7C7Ch,0000h, 7COOh, OOOOh, 007Ch, OOOOh, OOOOh
40180h OOOOh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
41100h FFFFh, 7C7Ch,007Ch, 7COOh, 007Ch, 007Ch, 007Ch, OOOOh
41180h 007Ch, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
42100h FFFFh, 7C7Ch,7COOh, 7COOh, 7COOh, 007Ch, 7COOh, OOOOh
42180h 7COOh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
43100h FFFFh, 7C7Ch, 7C7Ch, 7COOh, 7C7Ch,007Ch, 7C7Ch,OOOOh
43180h 7C7Ch, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
12-183
PIXBLT Pixel Block Transfer - Binary to XY
XV Addressing
X Address
Y 222222222222222233333
0123456789ABCDEF01234
A
d ~FFFF7C7C0000007C00007COOOOOOOOOOOOOOFFFFFF
d
r 31 FF F F 7 C 7 C 7 C 00 00 7 C 7 C 00 7 C 00 7 C 00 00 00 7 C 00 FF FF F F
e
s 32 FF F F 7 C 7 C 00 7 C 00 7 C 00 7 C 7 C 00 00 7 C 00 00 00 7 C F F FF FF
s
33 FF FF 7 C 7 C 7 C 7 C 00 7 C 7 C 7 C 7 C 00 7 C 7 C 00 00 7 C 7 C FF FF FF
Example 2 This example uses the XOR pixel processing operation. Before instruction
execution, PMASK = OOOOh and CONTROL = 2800h (T=O, W=OO,
PP=01 01 0).
After instruction execution, memory contains the following values:
X Address
Y 222222222222222233333
o 1 234 5 678 9 ABC 0 E F 0 1 234
A
d 30 FF FF 83 83 FF FF FF 83 FF FF 83 FF FF FF FF FF FF FF FF FF FF
d
r 31 FF FF 83 83 83 FF FF 83 83 FF 83 FF 83 FF FF FF 83 FF FF FF FF
e
s 32 FF FF 83 83 FF 83 FF 83 FF 83 83 FF FF 83 FF FF FF 83 FF FF FF
s
33 FF FF 83 83 83 83 FF 83 83 83 83 FF 83 83 FF FF 83 83 FF FF FF
Example 3 This example uses transparency. Before instruction execution, PMASK =
OOOOh and CONTROL = 0020h (T=1, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
Y 222222222222222233333
o 1 2 345 6 7 8 9 ABC 0 E F 0 1 234
A
d 30 FF FF 7C 7C FF FF FF 7C FF FF 7C FF FF FF FF FF FF FF FF FF FF
d
r 31 F F FF 7 C 7 C 7 C FF FF 7 C 7 C FF 7 C FF 7 C FF FF F F 7 C F F FF FF FF
e
s 32 FF FF 7 C 7 C FF 7 C F F 7 C F F 7 C 7 C FF FF 7 C FF FF FF 7 C FF FF FF
s
33 FF FF 7C 7C 7C 7C FF 7C 7C 7C 7C FF 7C 7C FF FF 7C 7C FF FF FF
12-184
Pixel Block Transfer - Binary to XY PIXBLT
Example 4 This example uses window operation 3 (clipped destination). Before in-
struction execution, PMASK = OOOOh and CONTROL = OOCOh (T=O,
W=11, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
V 222222222222222233333
o 1 2 3 4 5 6 7 8 9 ABC D E F 0 1 2 3 4
A
d 30 FF FF FF FF FF FF 00 7C 00 00 7C 00 00 00 00 00 00 00 FF FF FF
d
r 31 FF FF FF FF FF FF 00 7C 7C 00 7C 00 7C 00 00 00 7C 00 FF FF FF
e
s 32 FF FF FF FF FF FF 00 7C 00 7C 7C 00 00 7C 00 00 00 7C FF FF FF
s
33 FF F F FF F F FF FF 00 7 C 7 C 7 C 7 C 00 7 C 7 C 00 00 7 C 7 C FF FF F F
Example 5 This example uses plane masking; the four LSBs of each pixel are masked.
Before instruction execution, PMASK = OFOFh and CONTROL = 0020h
(T=1, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
V 222222222222222233333
o 1 2 3 4 5 6 7 8 9 ABC D E F 0 1 2 3 4
A
d 30 FF FF 7 F 7 F FF FF FF 7 F F F FF 7 F F F FF FF FF FF FF FF FF FF FF
d
r 31 FF FF 7F 7F 7F FF FF 7F 7F FF 7F FF 7F FF FF FF 7F FF FF FF FF
e
s 32 FF FF 7 F 7 F FF 7 F F F 7 F F F 7 F 7 F F F FF 7 F FF FF FF 7 F FF FF FF
5
33 FF F F 7 F 7 F 7 F 7 F FF 7 F 7 F 7 F 7 F F F 7 F 7 F F F FF 7 F 7 F FF FF F F
12-185
PIXBLT Pixel Block Transfer - Binary to XY
Example 6 This example shows how to use the PIXBLT B,XY instruction's window
preclipping capabilitied when the source pitch is not a power of 2.
*-----------------------------------------------------------------------
* Assume that the registers have been loaded as follows:
* BO linear start address of source bitmap
* B1 SPTCH (no restrictions)
* B2 start X coord. ytop in 16 MSBs, start x coord.
* xleft 1n 16 LSBs
* B3 DPTCH (must be power of 2)
* B4 OFFSET
* B5 WSTART
* B6 WEND
* B7 DY::DX (array height in 16 MSBs, array width in 16 LSBs)
* B8 COLORO
* B9 COLOR1
* FS1 >= 16 (assume multiplier for MPYS below is less than 16 bits)
* CONVSP will not be used.
* Implied operands in other I/O registers (incl. CONVDP) are valid.
* Window option = 3
*-----------------------------------------------------------------------
-color-expand:
MOVY B2,B10 ;copy ytop
SUBXY B5,B10 ;window y overlap = ytop - ystart
JRYNN INWINDOW ;jump if ytop below top of window
* Need to clip destination array to top edge of clippin9 window
MOVY B5,B2 ;clip ytop to top of w1ndow
SRA 16,B10 ;shift y overlap to 16 LSBs
MOVE B1,B11 ;copy SPTCH
MPYS B10,B11 ;(yoverlap) * SPTCH
SUB B11,BO ;clip SADDR to top of window
SLL 16,B10 ;shift y overlap to 16 MSBs
ADDXY B10,B7 ;clip DY to top of window
JRLS DONE ;done if DY<=O (completely
;above window)
* PIXBLT instruction will do any additional clipping required
INWINDOW:
PIXBLT B,XY ;color expand bitmap to screen
* Restore registers and return
DONE:
RETS o ;done
.end
12-186
Pixel Block Transfer - Linear to Linear PIXBLT
Syntax PIXBlT l, l
Execution linear pixel array -+ linear pixel array (with processing)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
10000 000000 o 0
Description The PIXB LT instruction transfers and processes a source pixel array with a
destination pixel array.
This instruction operates on two-dimensional arrays of pixels using linear
starting addresses for both the source and the destination. As the PixBlt
proceeds, the source pixels are combined with the corresponding destina-
tion pixels based on the selected graphics operations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT L, L. The first parameter, l, indi-
cates that the starting address of the source array is a linear address; the
second parameter, l, indicates that the starting address of the destination
array is also a linear address.
The following set of implied operands govern the operation of the in-
struction and define the source and destination arrays.
Implied
Operands B File Registers
Register Name Format Description
BOt+ SADDR Linear Source pixel array starting address
B1t SPTCH Linear Source pixel array pitch
B2t+ DADDR Linear Destination pixel array starting address
B3 DPTCH Linear Destination pixel array pitch
B7 DYDX XY Pixel array dimensions
(rows:columns)
B1Q-B14t Reserved registers
I/O Registers
Address Name Description and Elements (Bits)
COOOOOOBOh CONTROL PP- Pixel processing operations (22 options)
T - Transparency operation
PBH- PixBlt horizontal direction
PBV- PixBlt vertical direction
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOO0160h PMASK Plane mask - pixel format
t These registers are changed by PIXBLT execution.
+ You must adjust SADDR and DADDR to correspond to the corner selected by the
values of PBH and PBV. See Corner Adjust below for additional information.
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXBLT instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
12-187
PIXBLT Pixel Block Transfer - Linear to Linear
Source Array The source pixel array for the processing operation is defined by the con-
tents of the SADDR, SPTCH, and DYDX registers:
• At the outset of the instrl.Jction, SADDR contains the linear address
of the pixel at the appropriate starting corner of the array as deter-
mined by the PBH and PBV bits in the CONTROL I/O register. (See
Corner Adjust below.) During instruction execution, SADDR
points to the next pixel (or word of pixels) to be read from the source
array. When the block transfer is complete, SADDR points to the
starting address of the next set of 32. pixels that would have been
moved had the block transfer continued.
• SPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the source array. SPTCH must be a mUltiple of 16.
• DYDX specifies the dimensions, in pixels, of both the source and
destination arrays. The DY portion of DYDX contains the number of
rows in the array; the DX portion contains the number of pixels per
row.
Destination
Array The location of the destination pixel array is defined by the contents of the
DADDR, DPTCH, and DYDX registers:
• At the outset of the instruction, DADDR contains the linear address
of the pixel at the appropriate starting corner of the array as deter-
mined by the PBH and PBV bits in the CONTROL I/O register. (See
Corner Adjust below.) During instruction execution, DADDR
points to the next pixel (or word of pixels) to be modified in the des-
tination array. When the block transfer is complete, DADDR points
to the linear address of the first pixel on the next row of pixels that
would have been moved had the block transfer continued.
• DPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the destination array. DPTCH must be a multiple of
16.
• DYDX specifies the dimensions, in pixels, of both the source and
destination arrays in pixels. The DY portion of DYDX contains the
number of rows in the array, while the DX portion contains the num-
ber of columns.
Corner Adjust The PBH and PBV bits in the CONTROL I/O register govern the direction
of the PixBlt. If the source and destination arrays overlap, then PBH and
PBV should be set to prevent any portion of the source array from being
overwritten before it is moved.
Note that this PIXBLT's corner adjustment is unique. The PBH and PBV
bits control the direction of the PIXBLT; however, the adjustment of
SADDR and DADDR to point to the appropriate starting corner is not au-
tomatic. You must explicitly set these two registers to point to the selected
starting corners of the source and destination arrays, respectively, as indi-
cated by PBH and PBV. This facility allows you to use corner adjust for
screen definitions that do not lend themselves to XY addressing (those not
binary powers of two). In effect, you supply your own corner adjust oper-
ation in software and the PixBlt instruction provides directional control.
12-188
Pixel Block Transfer - Linear to Linear PIXBLT
• For PBH = 0 and PBV = 0, set SADDR and DADDR as they are
normally set for linear PixBlts. Set both registers to correspond to the
linear address of the first pixel on the first line of the array (that is,
the pixel with the lowest address).
• For PBH = 0 and PBV = 1, set SADDR and DADDR to correspond
to the linear address of the first pixel on the last line of the array.
In other words,
SADDR = (linear address of 1st source pixel) + [(DY-1) x SPTCH)]
and
DADDR = (linear address of 1 st destination pixel) + [(DY -1) x DPTCH)]
• For PBH = 1 and PBV = 0, set SADDR and DADDR to correspond
to the linear address of the pixel fol/owing the last pixel on the first
line of the array. In other words,
SADDR = (linear address of 1st source pixel) + (OX x PSIZE)
and
DADDR- = (linear address of 1st destination pixel) + (OX x PSIZE)
• For PBH = 1 and PBV = 1, set SADDR and DADDR to correspond
to the linear address of the pixel fol/owing the last pixel on the last
line of the array. In other words,
SADDR = (linear address of 1st source pixel) + [(DY-1) x SPTCH)]
+ (OX x PSIZE)
and
DADDR = (linear address of 1st destination pixel) + [(DY-1) x
DPTCH)] + (OX x PSIZE)
Window
Checking Window operations are not enabled for this instruction. The contents of the
WSTART and WEND registers are ignored.
Pixel
Processing You can select a pixel processing option for this instruction by setting the
PPOP bits in the CONTROL register. The pixel processing option is applied
to pixels as they are processed with the destination array. Note that the
data is read through the plane mask and then processed. There are 16
Boolean and 6 arithmetic operations; the default case at reset is the replace
(S .... D) operation. The 6 arithmetic operations do not operate with pixel
sizes of 1 or 2 bits per pixel. For more information, see Section 7.7, Pixel
Processing, on page 7 -15.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
pixels after it expands and processes the source data. At reset, the default
case for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
12-189
PIXBLT Pixel Block Transfer - Linear to Linear
Interrupts This instruction can be interrupted at a word or row boundary of the desti-
nation array. When the PixBlt is interrupted, the TMS3401 0 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH, SPTCH, and B10-B14 contain intermediate values.
DADDR points to the linear address of the next word of pixels to be modi-
fied after the interrupt is processed. SADDR points to the address of the
next 32 pixels to be read from the source array after the interrupt is proc-
essed.
The PIXBLT instruction uses several I/O and B-file registers as implied op-
erands. If an interrupt service routine modifies a register that the PIXBLT
uses as an implied operand, you must restore that register to the value it had
when the routine began, before returning from the routine. (You can use
the MMFM and MMTM instructions to save and restore the B-file regis-
ters.) In order to maintain compatibility with future TMS340 devices, use
only the RETI instruction to return from an interrupt routine.
Shift Register
Transfers If the SRT bit in the DPYCTL I/O register is set, each memory read or write
initiated by the PixBlt generates a shift register transfer read or write cycle
at the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.)
Machine
States See Section 13.4, PIXBLT Instructions Timing.
Status Bits N Undefined
C Undefined
Z Undefined
V Undefined
Examples Before executing a PIXBLT instruction, load the implied operand registers
with appropriate values. These PIXBLT examples use the following implied
operand setup.
Register File B: I/O Registers:
SADDR (BO) = 00002004h PSIZE = 0004h
SPTCH (B1) = 00000080h
DADDR (B2) = 00002228h
DPTCH (B3) = 00000080h
OFFSET (B4) = OOOOOOOOh
DYDX (B7) = 0002000Dh
Additional implied operand values are listed with each example.
For these examples, assume that memory contains the following data before
instruction execution.
linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, FFxxh, FFFFh, FFFFh, xFFFh, xxxxh, xxxxh
02280h xxxxh, xxxxh, FFxxh, FFFFh, FFFFh, xFFFh, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
12-190
Pixel Block Transfer - Linear to Linear PIXBLT
Example 1 This example uses the replace (S -+ 0) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, OOxxh, 1110h, 2221 h, x332h, xxxxh, xxxxh
02280h xxxxh, xxxxh, OOxxh, 1110h, 2221 h, x332h, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
Example 2 This example uses the (0 - S) -+ 0 pixel processing operation. Before in-
struction execution, PMASK = OOOOh and CONTROL = 4800h (T=O,
W=OO, PP=1 001 0).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, FFxxh, EEEFh, DDDEh,xCCDh,xxxxh, xxxxh
02280h xxxxh, xxxxh, FFxxh, EEEFh, DDDEh,xCCDh, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
Example 3 This example uses transparency. Before instruction execution, PMASK =
OOOOh and CONTROL = 0020h (T=1, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, OFFxxh, 111 Fh, 2221 h, x332h, xxxxh, xxxxh
02280h xxxxh, xxxxh, OFFxxh, 111 Fh, 2221 h, x332h, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
12-191
PIXBLT Pixel Block Transfer - Linear to Linear
Example 4 This example uses plane masking (the MSB of each pixel is masked). Be-
fore instruction execution, PMASK = 8888h and CONTROL = OOOOh
(T=O, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, 88xxh, 9998h, AAA9h, xB BAh, xxxxh, xxxxh
02280h xxxxh, xxxxh, 88xxh, 9998h, AAA9h, xBBAh, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
12-192
Pixel Block Transfer - Linear to XY PIXBLT
Syntax PIXBLT L, XV
Execution linear pixel array --. XV pixel array (with processing)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10000 00 00000
Description The PIXBLT instruction transfers and processes a source pixel array with a
destination pixel array.
This instruction operates on two-dimensional arrays of pixels using a linear
starting address for the source array and an XV address for the destination
array. As the PixBlt proceeds, the source pixels are combined with the
corresponding destination pixels based on the selected graphics operations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT L, XY. The first parameter, l, indi-
cates that the starting address of the source array is a linear address; the
second parameter, XV, indicates that the starting address of the destination
array is an XV address.
The following set of implied operands govern the operation of the in-
struction and define the source and destination arrays.
Implied
Operands B File Registers
Register Name Format Description
BOt SADDR Linear Source pixel array starting address
B1 SPTCH Linear Source pixel array pitch
B2t:l: DADDR XV Destination pixel array starting address
B3 DPTCH Linear Destination pixel array pitch
B4 OFFSET Linear Screen origin (0,0)
B5 WSTART XV Window starting corner
B6 WEND XV Window ending corner
B7:1: DVDX XV Pixel array dimensions (rows:columns)
B1 D-B14t Reserved registers
I/O Registers
Address Name Description and Elements (Bits)
COOOOOOBOh CONTROL PP- Pixel processing operations (22 options)
W -Window operations
T - Transparency operation
PBH- PixBlt horizontal direction
PBV- PixBlt vertical direction
COOOO130h CONVSP XV -to-linear conversion (source pitch)
Used for preclipping and corner adjust
COOOO140h CONVDP XV -to-linear conversion (destination pitch)
COOOO150h PSIZE Pixel size (1,2,4,8,16)
COOOO160h PMASK Plane mask - pixel format
t These registers are changed by PIXBLT execution.
:I: Used for common rectangle function with window pick.
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
12-193
PIXBLT Pixel Block Transfer - Linear to XY
PIXBLT instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Source Array The source pixel array for the processing operation is defined by the con-
tents of the SADDR, SPTCH, DYDX, and (possibly) CONVSP registers:
• At the outset of the instruction, SADDR contains the linear address
of the pixel with the lowest address in the array. During instruction
execution, SADDR points to the next pixel (or word of pixels) to be
accessed in the source array. When the block transfer is complete,
SADDR points to the linear address of the first pixel on the next row
of pixels that would have been moved had the block transfer contin-
ued.
• SPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the source array. SPTCH must be a multiple of 16.
For window clipping or corner adjust, SPTCH must be a power of two
and CONVSP must be set to correspond to the SPTCH value.
• CONVSP is determined by taking the LMO of the SPTCH register; this
value is used for the XY calculations involved in window clipping and
corner adjust.
• DYDX specifies the dimensions, in pixels, of both the source and
destination arrays. The DY portion of DYDX contains the number of
rows in the array; the DX portion contains the number of pixels per
row.
Destination
Array The location of the destination pixel array is defined by the contents of the
DADDR, DPTCH, CONVDP, OFFSET, and DYDX registers:
• At the outset of the instruction, DADDR contains the XV address of
the pixel with the lowest address in the array; it is used with OFFSET
and CONVDP to calculate the linear address of the starting location
of the array. During instruction execution, DADDR points to the lin-
ear address of next pixel (or word of pixels) to be accessed in the
destination array. When the block transfer is complete, DADDR
points to the linear address of the first pixel on the next row of
pixels that would have been moved had the block transfer continued.
• DPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the destination array (typically this is the screen pitch).
DPTCH must be a power of two (greater than or equal to 16).
• CONVDP must be set to correspond to the DPTCH value. CONVDP
is determined by taking The LMO of the DPTCH register; this value
is used for the XY calculations involved in XY addressing, window
clipping and corner adjust.
12-194
Pixel Block Transfer - Linear to XY PIXBLT
• DYDX specifies the dimensions of both the source and destination
arrays in pixels. The DY portion of DYDX contains the number of
rows in the array, while the DX portion contains the number of col-
umns.
Corner Adjust The PBH and PBV bits in the CONTROL I/O register govern the direction
of the PixBlt. If the source and destination arrays overlap, then PBH and
PBV should be set to prevent any portion of the source array from being
overwritten before it is moved. This PixBlt performs the corner adjust
function automatically under the control of the PBH and PBV bits. If
PBV=1, SPTCH must be a power of two and CONVSP should be valid.
The SADDR and DADDR registers should be set to correspond to the ap-
propriate format address of the first pixel on the first line of the source
(linear) and destination (XY) arrays, respectively.
Window
Checking You can use window checking with this instruction by setting the W bits
in the CONTROL register to the desired value. If you select window
checking mode 1, 2, or 3, the WSTART and WEN D registers define the XY
starting and ending corners of a rectangular window.
o No windowing. The entire pixel array is drawn and the WVP and V bits
are unaffected.
1 Window hit. No pixels are drawn. The V bit is set to 0 if any portion of
the destination array lies within the window. Otherwise, the V bit is set
to 1.
If the V bit is set to 0, the DADDR and DYDX registers are modified to
correspond to the common rectangle formed by the intersection of the
destination array with the rectangular window. DADDR is set to the XY
address of the pixel in the starting corner of the common rectangle.
DYDX is set to the X and Y dimensions of the common rectangle.
If the V bit is set to 1, the array lies entirely outside the window, and the
values of DADDR and DYDX are indeterminate.
2 Window miss. If the array lies entirely within the active window, it is
drawn and the V bit is set to O. Otherwise, no pixels are drawn, the V
and WVP bits are set to 1, and the instruction is aborted.
3 Window clip. The source and destination arrays are preclipped to the
window dimensions. Only those pixels that lie within the common rec-
tangle (corresponding to the intersection of the specified array and the
window) are drawn. If any preclipping is required, the V bit is set to 1.
Pixel
Processing You can select a pixel processing option to use with this instruction by
setting the PPOP bits in the CONTROL register. The pixel processing op-
eration is applied to pixels as they are processed with the destination array.
Note that the data is read through the plane mask and then processed.
There are 16 Boolean and 6 arithmetic operations; the default case at reset
is the replace (S -+ D) operation. The 6 arithmetic operations do not op-
erate with pixel sizes of 1 or 2 bits per pixel. For more information, see
Section 7.7, Pixel Processing, on page 7 -15.
12-195
PIXBLT Pixel Block Transfer - Linear to XY
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
pixels after it expands and processes the source data. At reset, the default
case for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
Interrupts This instruction can be interrupted at a word or row boundary of the desti-
nation array. When the PixBlt is interrupted, the TMS3401 0 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH, SPTCH, and B1 o-B14 contain intermediate values.
DADDR points to the linear address of the next word of pixels to be modi-
fied after the interrupt is processed. SADDR points to the address of the
next 32 pixels to be read from the source array after the interrupt is proc-
essed.
The PIXBLT instruction uses several I/O and B-file registers as implied op-
erands. If an interrupt service routine modifies a register that the PIXBLT
uses as an implied operand, you must restore that register to the value it had
when the routine began, before returning from the routine. (You can use
the MMFM and MMTM instructions to save and restore the B-file regis-
ters.) In order to maintain compatibility with future TMS340 devices, use
only the RETI instruction to return from an interrupt routine.
Shift Register
Transfers If the SRT bit in the DPYCTL I/O register is set, each memory read or write
initiated by the Pix Bit generates a shift register transfer read or write cycle
at the selected address. This operation can be used for bulk memory clears
or transfers (the TMS4461 VRAM supports this capability).
Machine
States See PIXBLT Instructions Timing, Section 13.4.
Status Bits N Undefined
C Undefined
Z Undefined
V If window clipping is enabled - 1 if a window violation occurs, 0 oth-
erwise; undefined if window clipping not enabled (W=002)
12-196
Pixel Block Transfer - Linear to XY PIXBLT
Examples Before executing a PIXBLT instruction, load the implied operand registers
with appropriate values. These PIXBLT examples use the following implied
operand'setup.
Register File B: I/O Registers:
SADDR (BO) = 00002004h CONVDP = 0017h
SPTCH (B1) = 00000080h PS IZE = 0004h
DADDR (B2) = 00520007h PMASK = OOOOh
DPTCH (B3) = 00000100h CONTROL = OOOOh
OFFSET (B4) = 00010000h (W=OO, T=O, PP=OOOOO)
WSTART (B5) = 0030000Ch
WEND (B6) = 00530014h
DYDX (B7) = 00030016h
Additional implied operand values are listed with each example.
For this example, assume that memory contains the following data before
instruction execution.
Linear Data
Address
02000h 3210h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, BA98h, FEDCh
02080h 3210h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, BA98h, FEDCh
02100h 3210h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, BA98h, FEDCh
15200h to
15480h 8888h
Example 1 This example uses the replace (S -+ D) pixel processing operation. Before
instruction execution, PMASK = 7777h and CONTROL = OOOOh (T=O,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
15200h 8888h, 1888h, 5432h, 9876h, DCBAh,10FEh, 5432h, 8886h
15300h 8888h, 1888h, 5432h, 9876h, DCBAh,10FEh, 5432h, 8886h
15400h 8888h, 1888h, 5432h, 9876h, DCBAh,10FEh, 5432h, 8886h
XV Addressing
X Address
y 0 0 000 0 0 0 0 0 0 0 0 000 1 111 1 1 1 1 1 1 1 1 1 111
0123456789ABCDEF0123456789ABCDEF
A
d 52 8 8 8 8 8 8 8 1 2 3 4 5 6 7 8 9 ABC D E F 0 1 2 3 4 5 8 8 8 8
d
r 53 8 8 8 8 8 8 8 1 2 3 4 5 6 7 8 9 ABC D E F 0 1 2 3 4 5 8 8 8 8
e
s 548888888123456789ABCDEF0123458888
s
12-197
PIXBLT Pixel Block Transfer - Linear to XY
Example 2 This example uses the (D subs S) -+ D pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = 4COOh (T=O,
W=OO, PP=1 0011).
After instruction execution, memory contains the following values:
X Address
Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 111 1 111
0123456789ABCDEF0123456789ABCDEF
A
d 52 8 8 8 8 8 8 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 8 8 8
d
r 53 8 8 8 8 8 8 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 8 8 8
e
s ~88888887654321000000008765432888
s
Example 3 This example uses transparency with the (D subs S) -+ D pixel processing
operation. Before instruction execution, PMASK = OOOOh and CONTROL
= 4C20h (T=1, W=OO, PP=1 0011).
After instruction execution, memory contains the following values:
X Address
Y 0 0 0 0 0 0 0 0 000 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 111
0123456789ABCDEF0123456789ABCDEF
A
d 52 8 8 8 8 8 8 8 7 6 5 4 3 2 1 8 8 8 8 8 8 8 8 8 7 6 5 4 3 2 8 8 8
d
r 53 8 8 8 8 8 8 8 7 6 5 4 3 2 1 8 8 8 8 8 8 8 8 8 7 6 5 4 3 2 8 8 8
e
s ~88888887654321888888888765432888
s
Example 4 This example uses window operation 3 (the destination is clipped). Before
instruction execution, PMASK = OOOOh and CONTROL = OOCOh (T=O,
W=11, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 111 111
0123456789ABCDEF0123456789ABCDEF
A
d 52 8 8 8 8 8 8 8 8 8 8 8 8 6 7 8 9 ABC 0 E 8 8 8 8 8 8 8 8 8 8 8
d
r 53 8 8 8 8 8 8 8 8 8 8 8 8 6 7 8 9 ABC 0 E 8 8 8 8 8 8 8 8 8 8 8
e
s ~88888888888888888888888888888888
s
12-198
Pixel Block Transfer - Linear to XY PIXBLT
Example 5 This example uses plane masking (the most significant bit is masked). Be-
fore instruction execution, PMASK = 8888h and CONTROL = OOOOh
(T=O, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
Y 000 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 111
0123456789ABCDEF0123456789ABCDEF
A
d 52 8 8 8 8 8 8 8 9 ABC 0 E F 8 9 ABC 0 E F 8 9 ABC 0 E 8 8 8
d
r 53 8 8 8 8 8 8 8 9 ABC 0 E F 8 9 ABC 0 E F 8 9 ABC 0 E 8 8 8
e
s M 88888889ABCDEF89ABCDEF89ABCDE888
s
12-199
PIXBLT Pixel Block Transfer - XY to Linear
Syntax PIXBLT XV, L
Execution XY pixel array -+ linear pixel array (with processing)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
10000 0 0000 o 0
Description The PIXBLT instruction transfers and processes a source pixel array with a
destination pixel array.
This instruction operates on two-dimensional arrays of pixels using an XY
starting address for the source pixel array and a linear address for the des-
tination array. As the PixBlt proceeds, the source pixels are combined with
the corresponding destination pixels based on the selected graphics oper-
ations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT XY, L. The first parameter, XV, in-
dicates that the starting address of the source array is an XY address; the
second parameter, L, indicates that the starting address of the destination
array is a linear address.
The following set of implied operands govern the operation of the in-
struction and define the source and destination arrays.
Implied
Operands B File Registers
Register Name Format Description
BOt SADDR XY Source pixel array starting address
B1 SPTCH linear Source pixel array pitch
B2t DADDR linear Destination pixel array starting address
B3 DPTCH linear Destination pixel array pitch
B4 OFFSET linear Screen origin (0,0)
B7 DYDX XY Pixel array dimensions (rows:columns)
B1 Q-B14t Reserved registers
I/O Registers
Address Name Description and Elements (Bits)
COOOOOOBOh CONTROL PP - Pixel processing operations (22 options)
T - Transparency operation
PBH - PixBlt horizontal direction
PBV - PixBlt vertical direction
COOO0130h CONVSP XY-to-linear conversion (source pitch)
Used for XY operations
COOO0140h CONVDP XY -to-linear conversion (destination pitch)
Used for XY operations
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOO0160h PMASK Plane mask - pixel format
t These registers are changed by PIXBLT execution.
12-200
Pixel Block Transfer - XY to Linear PIXBLT
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXBLT instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Source Array The source pixel array for the processing operation is defined by the con-
tents of the SADDR, SPTCH, CONVSP, OFFSET, and DYDX registers:
• At the outset of the instruction, SADDR contains the XV address of
the pixel with the lowest address in the array; it is used with OFFSET
and CONVSP to calculate the linear address of the starting location
of the array. During instruction execution, SADDR points to the next
pixel (or word of pixels) to be accessed from the source array. When
the block transfer is complete, SADDR points to the linear address
of the first pixel on the next row of pixels that would have been
moved had the block transfer continued.
• SPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the source array (typically this is the screen pitch).
SPTCH must be a power of two (greater than or equal to 16) unless
only one line is moved and CONVSP must be set to correspond to the
SPTCH value.
• CONVSP is determined by taking the LMO of the SPTCH register; this
value is used for the XY calculations involved in XY addressing, win-
dow clipping and corner adjust.
• DYDX specifies the dimensions, in pixels, of both the source and
destination arrays. The DY portion of DYDX contains the number of
rows in the array, while the OX portion contains the number of col-
umns.
Destination
Array The location of the destination pixel array is defined by the contents of the
DADDR, DPTCH, DYDX, and (potentially) CONVDP registers:
• At the outset of the instruction, DADDR contains the linear address
of the pixel with the lowest address in the array. During instruction
execution, DADDR points to the next pixel (or word of pixels) to be
modified in the destination array. When the block transfer is com-
plete, DADDR points to the linear address of the first pixel on the
next row of pixels that would have been moved had the block trans-
fer continued.
• DPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the destination array. DPTCH must be a multiple of
16. For window clipping or corner adjust, DPTCH must be a power
of two and CONVDP must be set to correspond to the DPTCH value.
12-201
PIXBLT Pixel Block Transfer - XY to Linear
• CONVDP is determined by taking the LMO of the DPTCH register;
this value is used for the XY calculations involved in window clipping
and corner adjust.
• DYDX specifies the dimensions of both the source and destination
arrays in pixels. The DY portion of DYDX contains the number of
rows in the array; the DX portion contains the number of columns.
Corner Adjust The PBH and PBV bits in the CONTROL I/O register govern the direction
of the PixBIt. If the source and destination arrays overlap, then PBH and
PBV should be set to prevent any portion of the source array from being
overwritten before it is moved. This PixBlt performs the cornel' adjust
function automatically under the control of the PBH and PBV bits. If
PBV=1, DPTCH must be a power of two and CONVDP must be valid. The
SADDR and DADDR registers should be set to correspond to the appro-
priate format address of the first pixel on the first line of the source (XY)
and destination (linear) arrays, respectively.
Window
Checking Window operations are not enabled for this instruction. The contents of the
WSTART and WEN D registers are ignored.
Pixel
Processing You can select a pixel processing option to use with this instruction by
setting the PPOP bits in the CONTROL register. The pixel processing op-
eration is applied to pixels as they are processed with the destination array.
Note that the data is read through the plane mask and then processed.
There are 16 Boolean and 6 arithmetic operations; the default case at reset
is the S -+ D operation. The 6 arithmetic operations do not operate with
pixel sizes of one or two bits per pixel. For more information, see Section
7.7, Pixel Processing, on page 7-15.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
pixels after it expands and processes the source data. At reset, the default
case for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
Interrupts This instruction can be interrupted at a word or row boundary of the desti-
nation array. When the PixBlt is interrupted, the TMS34010 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH, SPTCH, and B1 o-B14 contain intermediate values.
DADDR points to the linear address of the next word of pixels to be modi-
fied after the interrupt is processed. SADDR points to the address of the
next 32 pixels to be read from the source array after the interrupt is proc-
essed.
The PIXBLT instruction uses several I/O and B-file registers as implied op-
erands. If an interrupt service routine modifies a register that the PIXBLT
uses as an implied operand, you must restore that register to the value it had
when the routine began, before returning from the routine. (You can use
the MMFM and MMTM instructions to save and restore the B-file regis-
12-202
Pixel Block Transfer - XY to Linear PIXBLT
ters.) In order to maintain compatibility with future TMS340 devices, use
only the RETI instruction to return from an interrupt routine.
Shift Register
Transfers If the SRT bit in the DPYCTL I/O register is set, each memory read or write
initiated by the PixBlt generates a shift register transfer read or write cycle
at the selected address. This operation can be used for bulk memory clears
or transfers (not all VRAMs support this capability).
Machine
States See PIXBLT Instructions Timing, Section 13.4.
Status Bits N Undefined
C Undefined
Z Undefined
V Undefined
Examples Before executing a PIXBLT instruction, load the implied operand registers
with appropriate values. These PIXBLT examples use the following implied
operand setup.
Register File B: I/O Registers:
SADDR (BO) = 00400001 h CONVSP = 0018h
SPTCH (B1) = 00000080h PSIZE = 0004h
DADDR (B2) = 00002228h
DPTCH (B3) = 00000080h
OFFSET (B4) = OOOOOOOOh
DYDX (B7) = 0002000Dh
Additional implied operand values are listed with each example.
For this example, assume that memory contains the following data before
instruction execution.
Linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, FFxxh, FFFFh, FFFFh, xFFFh, xxxxh, xxxxh
02280h xxxxh, xxxxh, FFxxh, FFFFh, FFFFh, xFFFh, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
12-203
PIXBLT Pixel Block Transfer - XY to Linear
Example 1 This example uses the replace (S -+ D) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, OOxxh, 1110h, 2221 h, x332h, xxxxh, xxxxh
02280h xxxxh, xxxxh, OOxxh, 1110h, 2221 h, x332h, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
Example 2 This example uses the Os -+ D pixel processing operation. Before in-
struction execution, PMASK = OOOOh and CONTROL = OCOOh (T=O,
W=OO, PP=00011).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, OOxxh, OOOOh, OOOOh, xOOOh, xxxxh, xxxxh
02280h xxxxh, xxxxh, OOxxh, OOOOh, OOOOh, xOOOh, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
Example 3 This example uses transparency. Before instruction execution, PMASK =
OOOOh and CONTROL = 0200h (T=1, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, FFxxh, 111 Fh, 2221 h, x332h, xxxxh, xxxxh
02280h xxxxh, xxxxh, FFxxh, 111 Fh, 2221 h, x332h, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh,xxxxh
12-204
Pixel Block Transfer - XY to Linear PIXBLT
Example 4 This example uses plane masking
the two MSBs of each pixel are masked. Before instruction execution,
PMASK = CCCCh and CONTROL = OOOOh (T=O, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
02000h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02080h OOOxh, 1111 h, 2222h, xx33h, xxxxh, xxxxh, xxxxh, xxxxh
02100h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02180h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
02200h xxxxh, xxxxh, CCxxh, DDDCh,EEEDh, xFFEh, xxxxh, xxxxh
02280h xxxxh, xxxxh, CCxxh, DDDCh,EEEDh, xFFEh, xxxxh, xxxxh
02300h xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh, xxxxh
12-205
PIXBLT Pixel Block Transfer - XY to XY
Syntax PIXBLT XV, XV
Execution XY pixel array ~ XY pixel array (with processing)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 432 o
I0 0 0 0 0 000 o 0
Description The PIXBLT instruction transfers and processes a source pixel array with a
destination pixel array.
This instruction operates on two-dimensional arrays of pixels using XY
starting addresses for both the source and destination pixel arrays. As the
PixBlt proceeds, the source pixels are combined with the corresponding
destination pixels based on the selected graphics operations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT XY, XY. The first XV indicates that
the starting address of the source array is an XV address; the second XV
indicates that the starting address of the destination array is also an XV
address.
The following set of implied operands govern the operation of the in-
struction and define the source and destination arrays.
Implied
Operands B File Registers
Register Name Format Description
BOt SADDR XY Source pixel array starting address
B1 SPTCH Linear Source pixel array pitch
B2t:1: DADDR XY Destination pixel array starting address
B3 DPTCH Linear Destination pixel array pitch
B4 OFFSET Linear Screen origin (0,0)
B5 WSTART XY Window starting corner
B6 WEND XY Window ending corner
BTl: DYDX XY Pixel array dimensions (rows:columns)
B1o-B14t Reserved registers
I/O Registers
Address Name Description and Elements (Bits)
COOOOOBOh CONTROL PP - Pixel processing operations (22 options)
W - Window clipping or pick operation
T - Transparency operation
PBH- PixBlt horizontal direction
PBV- PixBlt vertical direction
COOO0130h CONVSP XY -to-linear conversion (source pitch)
COOO0140h CONVDP XY -to-linear conversion (destination pitch)
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOO0160h PMASK Plane mask - pixel format
t These registers are changed by PIXBLT execution.
:t: Used for common rectangle function with window pick.
12-206
Pixel Block Transfer - XY to XY PIXBLT
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXBLT instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Source Array The source pixel array for the processing operation is defined by the con-
tents of the SADDR, SPTCH, CONVSP, OFFSET, and DYDX registers:
• At the outset of the instruction, SADDR contains the XV address of
the pixel with the lowest address in the array; it is used with OFFSET
and CONVSP to calculate the linear address of the starting location
of the array. During instruction execution, SADDR points to the next
pixel (or word of pixels) to be read from the source array. When the
block transfer is complete, SADDR points to the linear address of
the first pixel on the next row of pixels that would have been moved
had the block transfer continued.
• SPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the source array (typically this is the screen pitch).
SPTCH must be a power of two (greater than or equal to 16) and
CONVSP must be set to correspond to the SPTCH value.
• CONVSP is determined by taking the LMO of the SPTCH register; this
value is used for the XY calculations involved in XY addressing, win-
dow clipping and corner adjust.
• DYDX specifies the dimensions of both the source and destination
arrays in pixels. The DY portion of DYDX contains the number of
rows in the array, while the OX portion contains the number of col-
umns.
Destination
Array The location of the destination pixel array is defined by the contents of the
DADDR, DPTCH, CONVDP, OFFSET, and DYDX registers:
• At the outset of the instruction, DADDR contains the XV address of
the pixel with the lowest address in the array; it is used with OFFSET
and CONVDP to calculate the linear address of the starting location
of the array. During instruction execution, DAD 0 R points to the next
pixel (or word of pixels) to be read from the destination array. When
the block transfer is complete, DADDR points to the linear address
of the first pixel on the next row of pixels that would have been
moved had the block transfer continued.
• DPTCH contains the linear difference in the starting addresses of ad-
jacent rows of the destination array (typically this is the screen pitch).
DPTCH must be a power of two (greater than or equal to 16) and
CONVDP must be set to correspond to the DPTCH value.
12-207
PIXBLT Pixel Block Transfer - XY to XY
• CONVDP is determined by taking the LMO of the DPTCH register;
this value is used for the XY calculations involved in XY addressing,
window clipping and corner adjust.
• DYDX specifies the dimensions of both the source and destination
arrays in pixels. The DY portion of DYDX contains the number of
rows in the array, while the OX portion contains the number of col-
umns.
Window
Checking You can use window checking with this instruction by setting the W bits
in the CONTROL register to the desired value. If you select window
checking mode 1,2, or 3, the WSTART and WEND registers define the XY
starting and ending corners of a rectangular window.
o No windowing. The entire pixel array is drawn and the WVP and V bits
are unaffected.
1 Window hit. No pixels are drawn. The V bit is set to 0 if any portion of
the destination array lies within the window; otherwise, the V bit is set
to 1.
If the V bit is set to 0, the DADDR and DYDX registers are modified to
correspond to the common rectangle formed by the intersection of the
destinatio.n array with the rectangular window. DADDR is set to the XY
address of the pixel in the starting corner of the common rectangle.
DYDX is set to the X and Y dimensions of the common rectangle.
If the V bit is set to 1, the array lies entirely outside the window, and the
values of DADDR and DYDX are indeterminate.
2 Window miss. If the array lies entirely within the active window, it is
drawn and the V bit is set to 0; otherwise, no pixels are drawn, the V and
WVP bits are set to 1, and the instruction is aborted.
3 Window clip. The source and destination arrays are preclipped to the
window dimensions. Only those pixels that lie within the common rec-
tangle (corresponding to the intersection of the specified array and the
window) are drawn. If any preclipping is required, the V bit is set to 1.
Pixel
Processing You can select a pixel processing option to use with this instruction by
setting the PPOP bits in the CONTROL register. The pixel processing op-
eration is applied to pixels as they are processed with the destination array.
Note that the data is read through the plane mask and then processed.
There are 16 Boolean and 6 arithmetic operations; the default case at reset
is the rep/ace (S -+ D) operation. The 6 arithmetic operations do not op-
erate with pixel sizes of one or two bits per pixel. For more information, see
Section 7.7, Pixel Processing, on page 7-15.
Corner Adjust The PBH and PBV bits in the CONTROL I/O register govern the direction
of the PixBlt. If the source and destination arrays overlap, then PBH and
PBV should be set to prevent any portion of the source array from being
overwritten before it is moved. This PixBlt performs the corner adjust
12-208
Pixel B lock Transfer - XY to XY PIXBLT
function automatically under the control of the PBH and PBV bits. The
SADDR and DADDR registers should be set to correspond to the appro-
priate format address of the first pixel on the first line of the source (XY)
and destination (XY) arrays, respectively.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
pixels after it expands and processes the source data. At reset, the default
case for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
Interrupts This instruction can be interrupted at a word or row boundary of the desti-
nation array. When the PixBlt is interrupted, the TMS3401 0 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH, SPTCH, and B1 o-B14 contain intermediate values.
DADDR points to the linear address of the next word of pixels to be modi-
fied after the interrupt is processed. SADDR points to the address of the
next 32 pixels to be read from the source array after the interrupt is proc-
essed.
The PIXBLT instruction uses several I/O and B-file registers as implied op-
erands. If an interrupt service routine modifies a register that the PIXBLT
uses as an implied operand, you must restore that register to the value it had
when the routine began, before returning from the routine. (You can use
the MMFM and MMTM instructions to save and restore the B-file regis-
ters.) In order to maintain compatibility with future TMS340 devices, use
only the RETI instruction to return from an interrupt routine.
Shift Register
Transfers If the SRT bit in the DPYCTL I/O register is set, each memory read or write
initiated by the PixBlt generates a shift register transfer read or write cycle
at the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.)
Machine
States See Section 13.4, PIXBLT Instructions Timing.
Status Bits NUn affected
C Unaffected
Z Unaffected
V If window clipping is enabled - 1 if a window violation occurs, 0 oth-
erwise; unaffected if window clipping not enabled
12-209
PIXBLT Pixel Block Transfer - XY to XY
Examples Before executing a PIXBL T instruction, load the implied operand registers
with appropriate values. These PIXBLT examples use the following implied
operand setup.
Register File B: I/O Registers:
SADDR (BO) = 00200004h CONVSP = 0016h
SPTCH (B1) = 00000200h CONVDP = 0016h
DADDR (B2) = 00410004h PS IZE = 0004h
DPTCH (B3) = 00000200h PMASK = OOOOh
OFFSET(B4) = 00010000h CONTROL = OOOOh
WSTART(B5) = 00300009h (W=OO, T=O, PP=OOOOO)
WEN 0 (B6) = 00420012h
DYDX (B7) = 00030016h
Additional implied operand values are listed with each example. For this
example, assume that memory contains the following data before in-
struction execution.
Linear Data
Address
14000h 3210h, 7654h, OBA98hFEDCh, 321 Oh, 7654h, OBA98hFEDCh
14200h 3210h, 7654h, OBA98hFEDCh, 321 Oh, 7654h, OBA98hFEDCh
14400h 3210h, 7654h, OBA98hFEDCh, 321 Oh, 7654h, OBA98hFEDCh
18200h to
18680h 3333h
Example 1 This example uses the replace (S -+D) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear Data
Address
18200h 3333h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, 3398h, 3333h
18400h 3333h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, 3398h, 3333h
18600h 3333h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, 3398h, 3333h
XV Addressing
X Address
Y 00 0 0 0 0 00 0 0 00 00 0 0 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1
0123456789ABCDEF0123456789ABCDEF
A
d 41 3 3 3 3 4 5 6 7 8 9 ABC 0 E F 0 1 2 3 4 5 6 7 8 9 3 3 3 3 3 3
d
r 42 3333456789ABCDE F01 23456789333333
e
s 433333456789ABCDEF0123456789333333
s
12-210
Pixel Block Transfer - XY to XY PIXBLT
Example 2 This example uses the (D adds S) -+ D pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = 4400h (T=O,
W=OO, PP=1 0001).
After instruction execution, memory contains the following values:
X Address
y 000 0 0 0 0 0 0 0 0 0 0 000 1 1 1 1 1 1 1 1 1 1 1 1 1 111
0123456789ABCDEF0123456789ABCDEF
A
d ~ 3333789ABCDEFFFF3456789ABC333333
d
r 42 3 3 3 3 7 8 9 ABC D E F F F F 3 4 5 6 7 8 9 ABC 3 3 3 3 3 3
e
s 43 3 3 3 3 7 8 9 ABC D E F F F F 3 4 5 6 7 8 9 ABC 3 3 3 3 3 3
s
Example 3 This example uses transparency and the (D SUBS S) -+ D pixel processing
operation. Before instruction execution, PMASK = OOOOh and CONTROL
= 4C20h (T=1, W=OO, PP=1 0011).
After instruction execution, memory contains the following values:
X Address
Y 000 0 0 0 0 0 0 0 0 0 0 000 1 1 1 1 1 1 1 1 1 1 1 1 1 111
0123456789ABCDEF0123456789ABCDEF
A
d 41 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 1 3 3 3 3 3 3 3 3 3 3 3 3 3
d
r 4233333333333333333213333333333333
e
s 4333333333333333333213333333333333
s
Example 4 This example uses window operation 3 (the destination is clipped). Before
instruction execution, PMASK = OOOOh and CONTROL = OOCOh (T=O,
W=11, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
Y 000 0 0 0 0 000 000 000 1 1 1 1 1 1 1 1 1 1 1 1 1 111
0123456789ABCDEF0123456789ABCDEF
A
d 41 3 3 3 3 3 3 3 3 3 9 ABC D E F 0 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3
d
r 423333333339ABCDEF0123333333333333
e
s ~ 33333333333333333333333333333333
s
12-211
PIXBLT Pixel Block Transfer - XY to XY
Example 5 This example uses plane masking
the third least significant bit is masked. 8efore instruction execution,
PMASK = 5555h and CONTROL = OOOOh (T=O, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
Y 0 0 000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 111 1 1 1 111 1
0123456789ABCDEF0123456789ABCDEF
A
d 41 3 3 3 3 1 1 3 3 9 9 8 8 9 9 8 8 1 1 3 3 1 1 3 3 9 9 3 3 3 3 3 3
d
r 42 33331133998899881133113399333333
e
s 4333331133998899881133113399333333
s
12-212
Pixel Transfer - Register to Indirect PIXT
Syntax PIXT Rs, *Rd
Execution pixel in Rs -+ * Rd
(Note that Rd contains a linear address.)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
1 1 0 01 Rs R Rd
Description This PIXT instruction transfers a pixel from a register to memory. The
source pixel is the 1, 2, 4, 8, or 16 LSBs of the source register, depending
on the pixel size specified in the PSIZE I/O register. The destination register
contains a linear address; the source pixel is transferred to this memory lo-
cation.
Rs and Rd must be in the same register file.
Implied
Operands I/O Registers
Address Name Description and Elements (Bits)
COOOOOOBOh CONTROL PP- Pixel processing operations (22 options)
T - Transparency operation
COOO0150h PSIZE Pi)<el size (1,2,4,6,8,16)
COOO0160h PMASK Plane mask - pixel format
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXT instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Pixel
Processing You can select a pixel processing option to use with this instruction by
setting the PPOP bits in the CONTROL register. The pixel processing op-
eration is applied to the pixel as it is transferred to the destination location.
The default case at reset is the replace option. For more information, see
Section 7.7, Pixel Processing, on page 7 -15.
Window
Checking Window checking cannot be used with this instruction. The W bits are
ignored.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
12-213
PIXT Pixel Transfer - Register to Indirect
Machine Pixel Processing Operation
States
PSIZE Replace Boolean ADD ADDS SUB SUBS MIN/MAX
1,2,4,8 2+(3),8 4+(3),10 ~+(3),11 ~+(3),11 5+(3),12 6+(3),11 5+(3),10
16 2+(1 ),6 4+(1 ),8 4+(1 ),8 5+(1 ),9 5+(1 ),9 6+(1),10 5+(1 ),9
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples PIXT AD, *Al
Before After
AO A1 @20500h FSIZE PP T PMASK @20500h
1) OOOOFFFFh 00020500h OOOOh 0001h 00000 0 OOOOh 0001h
1) OOOOFFFFh 00020500h OOOOh 0002h 00000 0 OOOOh 0003h
1) OOOOFFFFh 00020500h OOOOh 0004h 00000 0 OOOOh OOOFh
1) OOOOFFFFh 00020500h OOOOh 0008h 00000 0 OOOOh OOFFh
1) OOOOFFFFh 00020500h OOOOh 0010h 00000 0 OOOOh FFFFh
1) 00000006h 00020508h OOOOh 0004h 00000 0 OOOOh 0600h
2) 00000006h 00020508h 0300h 0004h 01010 0 OOOOh 0500h
3) 00000006h 00020508h 0100h 0004h 00001 0 OOOOh OOOOh
4) 00000006h 00020508h 0100h 0004h 00001 1 OOOOh 0100h
5) 00000006h 00020508h OOOOh 0004h 00000 0 AAAAh 0400h
Notes:
1) S replaces 0
2) (S XOR D) replaces 0
3) (S AND D) = 0, transparency is off, D is replaced
4) (S + D) = 0, transparency is on, 0 is not replaced
5) S replaces unmasked bits of 0
12-214
Pixel Transfer - Register to Indirect XY PIXT
Syntax PIXT Rs, *Rd.XV
(Note that Rd contains an XV address.)
Execution pixel in Rs -+ * Rd.XY
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I1 0 0 0 Rs R Rd
Description This PIXT instruction transfers a pixel from a register to memory. The
source pixel is the 1, 2, 4, 8, or 16 LSBs of the source register, depending
on the pixel size specified in the PSIZE I/O register. The destination register
contains an XY address; the X value occupies the 16 LSBs of the register
and the Y value occupies the 16 MSBs. The source pixel is moved to the
XY address specified in Rd.
Rs and Rd must be in the same register file.
Implied
Operands B File Registers
Register Name Format Description
B3 DPTCH Linear Destination pitch
B4 OFFSET Linear Screen origin (0,0)
B5 WSTART XY Window starting corner
B6 WEND XY Window ending corner
I/O Registers
Address Name Description and Elements (Bits)
COOOOOOBOh CONTROL PP- Pixel processing operations (22 options)
W -Window clipping or pick operation
T - Transparency operation
COOO0140h CONVDP XY-to-linear conversion (destination pitch)
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOO0160h PMASK Plane mask - pixel format
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXT instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Window
Checking You can use window checking with this instruction by setting the W bits
in the CONTROL register to the desired value. If you select window
checking mode 1, 2, or 3, the WSTART and WEND registers define the XY
starting and ending corners of a rectangular window. When an attempt is
made to write a pixel inside or outside a window, the results depend on the
selected window checking mode:
12-215
PIXT Pixel Transfer - Register to Indirect XY
o No window checking. The pixel is drawn and the WVP and V bits are
unaffected.
1 Window hit. No pixels are drawn. The V bit is set to 0 if the pixel lies
within the window; otherwise, it is set to 1 .
2 Window miss. If the pixel lies outside the window, the V and WVP bits
are set to 1 and the instruction is aborted (no pixels are drawn). Other-
wise, the pixel is drawn and the V bit is set to o.
3 Window clip. If the pixel lies outside the window, the V bit is set to 1
and the instruction is aborted (no pixels are drawn). Otherwise, the pixel
is drawn and the V bit is set to O.
For more information, see Section 7.10, Window Checking, on page 7 -26.
Pixel
Processing You can select a pixel processing option to use with this instruction by
setting the PPOP bits in the CONTROL register. The pixel processing op-
eration is applied to the pixel as it is transferred to the destination location.
The default case at reset is the replace option. For more information, see
Section 7.7, Pixel Processing, on page 7 -1 5.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
Machine
States
Pixel Processing Operation Window
Violation
PSIZE Replace Boolean ADD ADDS SUB SUBS MIN/MAX W=1 W=2 W=3
1,2.4.8 4+(3),10 6+(3),12 6+(3),12 7+(3),13 7+(3),13 8+(3),14 7+(3),13 6,9 6,9 4.7
16 4+{1 ),8 6+(1),10 6+(1),10 7+(1),11 7+(1),11 8+(1),12 7+(1),11 6,9 6.9 4,7
Status Bits N Unaffected
C Unaffected
Z Unaffected
V 1 if the pixel lies outside the window and W=1, W=2, or W=3, 0 oth-
erwise. Unaffected if W=O.
12-216
Pixel Transfer - Register to Indirect XY PIXT
Examples 8efore executing a PIXT instruction, load the implied operand registers with
appropriate values. These PIXT examples use the following implied oper-
and setup.
Register File B: I/O Registers:
DPTCH (83) = 00000800h CONVDP = 0014h
OFFSET (84) = OOOOOOOOh
WSTART (85) = 00300020h
WEND (86) = 00500142h
PIXT AO, *A1.XY
Before After
AO A1 @20500h PSIZE PP W T PMASK @20500h
1) OOOOFFFFh 00400500h OOOOh 0001h 00000 00 0 OOOOh 0001h
1) OOOOFFFFh 00400280h OOOOh 0002h 00000 00 0 OOOOh 0003h
1) OOOOFFFFh 00400140h OOOOh 0004h 00000 00 0 OOOOh OOOFh
1) OOOOFFFFh 004000AOh OOOOh 0008h 00000 00 0 OOOOh OOFFh
1) OOOOFFFFh 00400050h OOOOh 0010h 00000 00 0 OOOOh FFFFh
1) 00000006h 00400142h OOOOh 0004h 00000 00 0 OOOOh 0600h
2) 00000006h 00400142h 0300h 0004h 01010 00 0 OOOOh 0500h
3) 00000006h 00400142h 0100h 0004h 00001 00 0 OOOOh OOOOh
4) 00000006h 00400142h 0100h 0004h 00001 00 1 OOOOh 0100h
5) 00000006h 00400142h OOOOh 0004h 00000 00 0 AAAAh 0400h
6) 00000006h 00400142h OOOOh 0004h 00000 11 0 OOOOh 0600h
7) 00000006h 00400143h OOOOh 0004h 00000 11 0 OOOOh OOOOh
8) 00000006h 00400143h OOOOh 0004h 00000 10 0 OOOOh OOOOh
XY Address in A1 = Linear Address 20500h
Notes:
1) S replaces D
2) (S XOR D) replaces D
3) (S AN D D) = 0, transparency is off, 0 is replaced
4) (S + D) = 0, transparency is on, D not replaced
5) S replaces unmasked bits of D
6) Window Option = 3, D inside window, S replaces D
7) Window Option = 3, D outside window, D not replaced, V bit set in
status reg ister
8) Window Option = 2, D outside window, D not replaced, WV interrupt
generated, V bit set in status register
12-217
PIXT Pixel Transfer - Indirect to Register
Syntax PIXT *Rs, Rd
(Note that Rs contains a linear address.)
Execution pixel at * Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I1 0 Rs R Rd
Description This PIXT instruction transfers a pixel from memory to a register. The
source register contains a linear address; the pixel at this address is trans-
ferred into the destination register. When the pixel is moved into Rd, it is
right justified and zero extended to 32 bits according to the pixel size spe-
cified in the PSIZE I/O register.
Rs and Rd must be in the same register file.
Implied
Operands I/O Registers
Address Name Description and Elements (Bits)
COOOO150h PSIZE Pixel size (1,2,4,6,8,16)
COOOO160h PMASK Plane mask - pixel format
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXT instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Window
Checking Window checking cannot be used with this instruction. The W bits are
ignored.
Pixel
Processing Pixel processing cannot be used with this instruction.
Transparency Transparency cannot be used with this instruction.
Plane Mask The plane mask is enabled for this instruction.
Machine
States 4,7
Status Bits N Undefined
C Undefined
Z Undefined
V Set to 1 if the pixel is 1 , set to 0 if the pixel is O.
12-218
Pixel Transfer - Indirect to Register PIXT
Examples Assume that memory contains the following values:
Address Data
@20500h OFFFFh
@20510h 3333h
PIXT *AO,Al
Before After
AO PSIZE PMASK A1
0OO20500h 0OO1h OOOOh 0OOOOOO1h
0OO20500h 0OO1h FFFFh OOOOOOOOh
0OO20500h 0OO2h OOOOh 0OOOOOO3h
0OO20500h 0OO2h 5555h 0OOOOOO2h
0OO20500h 0OO4h OOOOh OOOOOOOFh
0OO20510h 0OO4h 9999h 0OOOOOO2h
0OO20500h 0OO8h OOOOh OOOOOOFFh
0OO20510h 0OO8h 5454h 0OOOOO23h
0OO20500h 0010h OOOOh OOOOFFFFh
0OO20500h 0010h BA98h 0OOO4567h
0OO20510h 0010h BA98h 0OOOO123h
12-219
PIXT Pixel Transfer - Indirect to Indirect
Syntax PIXT *Rs, *Rd
(Note that Rs and Rd contain linear addresses.)
Execution pixel at * Rs -+ * Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
11 01 Rs R Rd
Description This PIXT instruction transfers a pixel from one memory location to another.
The source and destination registers both contain linear addresses. The
address in Rs is the address of the source pixel; the pixel is moved into the
address in Rd.
Rs and Rd must be in the same register file.
Implied
Operands I/O Registers
Address Name Description and Elements (Bits)
COOOOOOBOh CONTROL PP- Pixel processing operations (22 options)
T - Transparency operation
COOO0150h PSIZE Pixel size (1,2.4.6,8,16)
COOOO160h PMASK Plane mask - pixel format
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXT instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Reg isters.
Pixel
Processing You can select a pixel processing option to use with this instruction by
setting the PPOP bits in the CONTROL register. The pixel processing op-
eration is applied to the pixel as it is transferred to the destination location.
The default case at reset is the rep/ace option. For more information, see
Section 7.7, Pixel Processing, on page 7 -1 5.
Window
Checking Window checking cannot be used with this instruction. The W bits are
ignored.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
12-220
Pixel Transfer - Indirect to Indirect PIXT
Machine
States
Pixel Processing Operation Window
Violation
PSIZE Replace Boolean ADD ADDS SUB SUBS MIN/MAX W=1 W=2 W=3
1,2,4,8 4+(3),10 6+(3),12 6+(3),12 7+(3),13 7+(3),13 8+(3),14 7+(3),13 - - -
16 4+(1 ),8 6+(1),10 6+(1),10 7+(1),11 7+(1),11 8+(1),12 7+(1),11 - - -
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples PIXT *AO,*Al
Before After
AO A1 @20500h PSIZE PP T PMASK @20500h @20510h
1) 00020500h 00020508h OOOFh 0001h 00000 o OOOOh 010Fh xxxx
1) 00020500h 00020508h OOOFh 0002h 00000 o OOOOh 030Fh xxxx
1) 00020500h 00020508h OOOFh 0004h 00000 o OOOOh OFOFh xxx x
1) 00020500h 00020508h OOEFh 0008h 00000 o OOOOh EFEFh xxx x
1) 00020500h 00020508h 1234h 0010h 00000 o OOOOh 3434h xx12h
2) 00020500h 00020508h 030Fh 0004h 01010 o OOOOh OCOFh xxxx
3) 00020500h 00020508h 010Eh 0004h 00001 o OOOOh OOOEh xxxx
4) 00020500h 00020508h 020Eh 0004h 00001 1 OOOOh 020Eh xxxx
5) 00020500h 00020508h OOOFh 0004h 00000 o AAAAh 050Fh xxxx
Notes:
1) S replaces D
2) (S XOR D) replaces D
3) (S AN D D) = 0, transparency is off, D is replaced
4) (S + D) = 0, transparency is on, D not replaced
5) S replaces unmasked bits of D
12-221
PIXT Pixel Transfer - Indirect XY to Register
Syntax PIXT *Rs.XV, Rd
(Note that Rs contains an XV address.)
Execution pixel at * Rs.XY -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I1 0 0 Rs R Rd
Description This PIXT instruction transfers a pixel from a memory location to a register.
The source register contains an XY address; the X value occupies the 16
LSBs of the register and the Y value occupies the 16 MSBs. The address
in Rs is the address of the source pixel; this pixel is moved into the desti-
nation register. When the pixel is moved into Rd, it is right justified and
zero extended to 32 bits according to the pixel size specified in the PSIZE
I/O register.
Rs and Rd must be in the same register file.
Implied
Operands B File Registers
Register Name Format Description
81 SPTCH Linear Source pitch
84 OFFSET Linear Screen origin (0,0)
I/O Registers
Address Name Description and Elements (Bits)
COOO0130h CONVSP XV -to-linear conversion (source pitch)
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOO0160h PMASK Plane mask - pixel format
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXT instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Window
Checking Window checking cannot be used with this instruction. The W bits are
ignored.
Pixel
Processing Pixel processing cannot be used with this instruction.
Transparency Transparency cannot be used with this instruction.
Plane Mask The plane mask is enabled for this instruction.
Machine
States 6,9
12-222
Pixel Transfer - Indirect XY to Register PIXT
Status Bits N Undefined
C Undefined
Z Undefined
V Set to 1 if the pixel is 1, set to 0 if the pixel is O.
Examples These PIXT examples use the following implied operand setup.
Register File B: I/O Registers:
DPTCH (83) = BOOh CONVSP = 0014h
OFFSET (84) = OOOOOOOOh
Assume that memory address @20500h contains CF3Fh before instruction
execution.
PIXT *AO.XY,Al
Before After
AO PSIZE PMASK A1
00400500h 0OO1h OOOOh 0OOOOOO1h
00400500h 0OO1h FFFFh OOOOOOOOh
00400280h 0OO2h OOOOh 0OOOOOO3h
00400280h 0OO2h AAAAh 0OOOOOO1h
00400140h 0OO4h OOOOh OOOOOOOFh
00400140h 0OO4h 9999h 0OOOOOO6h
004000AOh 0OO8h OOOOh 0OOOOO3Fh
004000AOh 0OO8h 8989h 0OOOOO36h
00400050h 0010h OOOOh OOOOCF3Fh
00400050h 0010h 7310h 0OOO8C2Fh
Note:
The XY addresses stored in register A 1 in these examples translate to
the linear memory address 20500h. The pitch of the source was not
changed for any of these examples.
12-223
PIXT Pixel Transfer - Indirect XY to Indirect XY
Syntax PIXT *Rs.XV, *Rd.XV
(Note that Rs and Rd contain XV addresses.)
Execution pixel at * Rs.XY ~ * Rd.XY
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
11 0 01 Rs R Rd
Description This PIXT instruction transfers a pixel from one memory location to another.
The source and destination registers both contain XY addresses; the X value
occupies the 16 LSBs of the register and the Y value occupies the 16
MSBs. Rs contains the address of the source pixel; Rd contains the address
where the pixel is moved.
Rs and Rd must be in the same register file.
Implied
Operands B File Registers
Register Name Format Description
B1 SPTCH Linear Source pitch
B3 DPTCH Linear Destination pitch
B4 OFFSET Linear Screen origin (0,0)
B5 WSTART XV Window starting corner
B6 WEND XV Window ending corner
1/0 Registers
Address Name Description and Elements (Bits)
COOOOOOBOh CONTROL PP- Pixel processing operations (22 options)
W - Window clipping or pick operation
T - Transparency operation
COOO0130h CONVSP XV -to-linear conversion (source pitch)
COOO0140h CONVDP XV -to-linear conversion (destination pitch)
COOO0150h PSIZE Pixel size (1,2,4,8,16)
COOO0160h PMASK Plane mask - pixel format
Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXT instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an in-
struction that reads the same location (such as a MOVE SAddress,Rd in-
struction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Window
Checking You can use window checking with this instruction by setting the W bits
in the CONTROL register to the desired value. If you select window
checking mode 1, 2, or 3, the WSTART and WEN D registers define the XY
starting and ending corners of a rectangular window. When an attempt is
made to write a pixel inside or outside a window, the results depend on the
selected window checking mode:
12-224
Pixel Tra nsfer - Indirect XY to Indirect XY PIXT
o No window checking. The pixel is drawn and the WVP and V bits are
unaffected.
1 Window hit. No pixels are drawn. The V bit is set to 0 if the pixel lies
within the window; otherwise, it is set to 1.
2 Window miss. If the pixel lies outside the window, the V and WVP bits
are set to 1 and the instruction is aborted (no pixels are drawn). Other-
wise, the pixel is drawn and the V bit is set to O.
3 Window clip. If the pixel lies outside the window, the V bit is set to 1
and the instructi0r:l is aborted (no pixels are drawn). Otherwise, the pixel
is drawn and the V bit is set to O.
For more information, see Section 7.10, Window Checking, on page 7-25.
Pixel
Processing You can select a pixel processing option to use with this instruction by
setting the PPOP bits in the CONTROL register. The pixel processing op-
eration is applied to the pixel as it is transferred to the destination location.
The default case at reset is the rep/ace option. For more information, see
Section 7.7, Pixel Processing, on page 7-15.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Plane Mask The plane mask is enabled for this instruction.
Machine
States
Pixel Processing Operation Window
Violation
PSIZE Replace Boolean ADD ADDS SUB SUBS MIN/MAX W=1 W=2 W=3
1,2,4,8 7+(3),13 9+(3),15 9+(3),15 0+(3),16 0+(3),16 11+(3),17 10+(3),16 - 8,11 6,9
16 7+(1).11 9+(1),13 9+(1),13 0+(1),14 0+(1),14 11+(1),15 10+(1),14 - 8,11 6,9
Status Bits N Unaffected
C Unaffected
Z Unaffected
V 1 if the pixel lies outside the window and W=1, W=2, or W=3, 0 oth-
erwise. Unaffected if W=O.
Examples These PIXT examples use the following implied operand setup.
Register File B: I/O Registers:
SPTCH (81) = 800h CONVSP = 0014h
DPTCH (83) = 800h CONVDP = 0014h
OFFSET (84) = OOOOOOOOh
WSTART (85) = 00300020h
WEND (86) = 00500142h
PIXT *AO.XY,*Al.XY
12-225
PIXT Pixel Transfer - Indirect XY to Indirect XY
Before After
AO A1 @20500h PSIZE PP W T PMASK @20500h @20510h
1) 00400500h 00400508h OOOFh 0001 h 00000 000 OOOOh 010Fh xxxx
1) 00400280h 00400284h OOOFh 0002h 00000 000 OOOOh 030Fh xxxx
1) 00400140h 00400142h OOOFh 0004h 00000 000 OOOOh OFOFh xxxx
1) 004000AOh 004000A1h OOEFh 0008h 00000 000 OOOOh EFEFh xxxx
1) 00400050h 00400051h CDEFh 0010h 00000 000 OOOOh CDEFh CDEFh
2) 00400140h 00400142h 0306h 0004h 01010 000 OOOOh 0506h xxxx
3) 00400140h 00400142h 0106h 0004h 00001 00 0 OOOOh 0006h xxxx
4) 00400140h 00400142h 0106h 0004h 10001 00 1 OOOOh 0106h xxxx
5) 00400140h 00400142h 0006h 0004h 00000 000 AAAAh 0406h xxxx
6) 00400140h 00400142h 0006h 0004h 00000 11 0 OOOOh 0606h xxxx
7) 00400140h 00400143h 0006h 0004h 00000 11 0 OOOOh 0006h xxx x
8) 00400140h 00400143h 0006h 0004h 00000 10 0 OOOOh 0006h xxxx
XV Address in AO = Linear Address 20500h
Notes:
1) S replaces 0
2) (S XOR 0) replaces 0
3) (S AN 0 D) = 0, transparency is off, 0 is replaced
4) (S + D) = 0, transparency is on, 0 not replaced
5) S replaces unmasked bits of 0
6) Window Option = 3, 0 inside window, S replaces 0
7) Window Option = 3, 0 outside window, 0 not replaced, V bit set in
status register
8) Window Option = 2, 0 outside window, 0 not replaced, WV interrupt
generated, V bit set in status register
12-226
Pop Status Reg ister from Stack POPST
Syntax POPST
Execution *SP+ -. ST
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
1 0 0 0 0 0 0 0 0 0 0 0 0 01
Description POPST pops the status register from the stack and increments the SP by
32 after the status register is removed from the stack.
Status Register
Machine
States 8,11 (SP aligned)
10,13 (SP nonaligned)
Status Bits N Set from bit 31 of stack status.
C Set from bit 30 of stack status.
Z Set from bit 29 of stack status.
V Set from bit 28 of stack status.
IE Set from bit 21 of stack status.
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
OFFOOOOOh 0010h
OFFOO010h COOOh
Code Before After
SP ST SP
POPST OFFOOOOOh COOOO010h OFFOO020h
12-227
PUSHST Push Status Register onto Stack
Syntax PUSHST
Execution ST -+ -*SP
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 0 0 0 01
Description PUSHST writes the status register contents to the address contained in the
SP-32.
Status Register
Machine
States 2+(3),8 (SP aligned)
2+(8),13 (SP nonaligned)
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Example Code Before After
SP ST SP
PUSHST OFF00020h C0000010h OFFOOOOOh
Memory contains the following values after instruction execution:
Address Data
OFF00010h 0010h
OFF00020h COOOh
12-228
Copy Register into Status PUTST
Syntax PUTST Rs
Execution Rs -+ ST
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 R Rs I
Description PUTST copies the contents of the specified register into the status register.
Status Register
Machine
States 3,6
Status Bits N Set to value of bit 31 in source register
C Set to value of bit 30 in source register
Z Set to value of bit 29 in source register
V Set to value of bit 28 in source register
IE Set to value of bit 21 in source register
Example Before After
AO ST ST
PUTST AD C0000010h xxxxxxxxh C0000010h
12-229
RETI Return from Interrupt
Syntax RETI
Execution *SP+ -+ ST
*SP+ -+ PC
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 0 0 0 0 01
Description RETI returns to an interrupted routine from an interrupt service routine. The
instruction restores the ST and PC to their original values that were stored
on the system stack.
The stack is located in external memory and the top is indicated by the stack
pointer (SP). The stack grows in the direction of decreasing linear address.
The ST and PC are popped from the stack and the SP is incremented by
32 after each register is removed from the stack.
Note:
If the PBX status bit is set in the restored ST value, then the bit is
cleared and a PIXBLT or FILL is resumed, depending on the values
stored in the B-file registers.
The CONTROL register and any B-file registers modified by an interrupt
routine should be restored before RETI is executed. Otherwise, inter-
rupted PIXB LT and FI LL instructions may not resume execution cor-
rectly.
Machine
States 11,14 (aligned stack)
15,18 (nonaligned stack)
Status Bits N Copy of corresponding bit in stack location
C Copy of corresponding bit in stack location
Z Copy of corresponding bit in stack location
V Copy of corresponding bit in stack location
IE Copy of corresponding bit in stack location
Interrupts If the IE bit in the restored ST is a 1, interrupts are enabled by the time the
RETI instruction finishes executing. If an interrupt request is active during
the last state of the RETI instruction, and the interrupt is enabled in the
INTENB register, the interrupt will be taken immediately following the RET!.
Since interrupts are level-triggered, the interrupt service routine should
write to the interrupting device to clear the interrupt request before execut-
ing an RET!. The following example shows a typical interrupt service rou-
tine; in this example, the symbol DEVICE is the symbolic address of the
interrupting device.
12-230
Return from Interrupt RETI
CLR AO
MOVE AO, @DEVICE
RETI
In this example, the interrupt request is cleared by the MOVE instruction,
which writes a 0 to the device address.
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
CCCOOOOh 0010h
CCC0010h COOOh
CCC0020h FFFOh
CCC0030h 0044h
Before After
SP ST PC SP
RETI CCCOOOOh C0000010h 0044FFFOh CCC0040h
12-231
RETS Return from Subroutine
Syntax RETS [NJ
Execution *SP -+ PC (N defaults to 0)
S P + 32 + 1 6N -+ S P
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 N
I
Description RETS returns from a subroutine by popping the program counter from the
stack and optionally incrementing the stack pointer.
The N parameter is optional; it can be a value between 0 and 32 that indi-
cates a number of words that are added to the stack pointer. If N is speci-
fied, the stack pointer is incremented by 32 + 16N. If N is not specified,
the stack is incremented by 32. Execution then continues according to the
PC value loaded.
Machine
States 7,10 (Aligned stack)
9,12 (Unaligned stack)
Status Bits N Unaffected
C Unaffected
Z Unaffe<;:ted
V Unaffected
Examples Assume that memory contains the following values before instruction exe-
cution:
Address Data
OFFOOOOOh OFFFOh
OFFOOO10h 0001h
Code Before After
SP PC SP
RETS OFFOOOOOh 0OO1FFFOh OFFOO020h
RETS 1 OFFOOOOOh 0OO1FFFOh OFFOO030h
RETS 2 OFFOOOOOh 0OO1FFFOh OFFOOO40h
RETS 16 OFFOOOOOh 0OO1FFFOh OFF00120h
RETS 31 OFFOOOOOh 0OO1FFFOh OFF00210h
12-232
Store Revision Number REV
Syntax REV Rd
Execution revision number ~ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 0 0 R Rd I
Description REV stores the revision number of the TMS340 family device in the desti-
nation register. The revision number information is stored in the following
format:
31 16 15 3 2 0
undefined 10 0 0 0 0 0 0 0 0 0 0 0 1 lundefinedl
Machine
States 1,4
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
A1 A1
REV A1 OFFFFFFFFh 00000008h
12-233
RL Rotate Left - Constant
Syntax RL K,Rd
Execution left-rotate Rd by K -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 0 01 K R Rd 1
Description RL left-rotates the contents of the destination register by a specified num-
ber of bits. (This rotation is a barrel shift.) The rotate count is specified
by a 5-bit immediate value, or constant; this produces a rotation amount
of 0 to 31 bits. (K in the syntax represents the 5-bit constant.) This is a
circular rotate so that bits shifted out the MSB are shifted into the LSB.
The assembler only accepts absolute expressions for the rotate count. If the
specified rotation value is greater than 31, the assembler issues a warning
and set the K field in the opcode to the 5 LSBs of K.
The carry bit is set to the value of the last bit that is shifted out of the MSB
(this value is the same as the final value of the LSB). You can use a rotate
count of 0 to clear the carry anc:ttest a register for 0 simultaneously.
Machine
States 1,4
Status Bits N Unaffected
C Set to value of last bit rotated out, 0 for rotate count of 0
Z 1 if result is 0, 0 otherwise
V Unaffected
Examples Code Before After
A1 NCZV A1
RL O,AI OOOOOOOFh xOOx OOOOOOOFh
RL I,AI FOOOOOOOh x10x EOOOOO01h
RL 4,AI FOOOOOOOh x10x OOOOOOOFh
RL S,AI FOOOOOOOh xOOx 0OOOO01Eh
RL 30,Al FOOOOOOOh x10x 3COOOOOOh
RL S,AI OOOOOOOOh x01x OOOOOOOOh
12-234
Rotate Left - Register RL
Syntax RL Rs, Rd
Execution left-rotate Rd by 5 LSBs of Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I0 0 0 01 Rs Rd
Operands Rs The five LSBs of the source register specify the left rotate count (a
value from a to 31). The 27 MSBs are ignored.
Description RL left-rotates the contents of the destination register by a specified num-
ber of bits. (This rotation is a barrel shift.) The rotate count is specified
by the 5 LSBs of Rs (the 27 MSBs are ignored); this produces a rotation
amount between 0 and 31 bits. This is a circular rotate; the bits that are
shifted out of the MSB of Rd are shifted into the LSB.
C 31 0
G-Ji------l]
Note that the you must designate Rs with a keyword or symbol which has
been defined to be a register, for example, A9; otherwise, the assembler
uses the RL K,Rd instruction.
The carry bit is set to the value of the last bit that is shifted out of the MSB
(this value is the same as the final value of the LSB).
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits NUn affected
C Set to value of last bit rotated out, 0 for rotate count of 0
Z 1 if result is 0, 0 otherwise
V Unaffected
Examples Code Before After
5 LSBs AO A1 NCZV A1
RL AO,AI 00000 OOOOOOOFh xOOx OOOOOOOFh
RL AO,AI 00100 FOOOOOOOh x10x OOOOOOOFh
RL AO,AI 00101 FOOOOOOOh xOOx 0000001Eh
RL AO,AI 11111 FOOOOOOOh xOOx 78000000h
RL AO,AI xxxxx OOOOOOOOh x01x OOOOOOOOh
12-235
SETC Set Carry
Syntax SETC
Execution 1 -+ C
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 0 0 0 0 01
Description SETC sets the carry bit (C) in the status register to 1. The rest of the status
register is unaffected.
This instruction is useful for returning a true/false value (in the carry bit)
from a subroutine without using a general-purpose register.
Machine
States 1,4
Status Bits N Unaffected
C 1
Z Unaffected
V Unaffected
Examples Code Before After
ST NCZV ST NCZV
SETC OOOOOOOOh 0000 40000000h 0100
SETC BOOOO010h 1011 FOOOO010h 1111
SETC 4000001Fh 0100 4000001Fh 0100
12-236
Set Field Parameters SETF
Syntax SETF FS, FE [, FJ
Execution FS, FE -+ ST
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I0 0 0 0 0 1 IF 0 I FE I FS
Description SETF loads specified field size (FS) and field extension (FE) values into the
status register; depending on the value of the F parameter, this information
sets the field size and extension for either field 0 or field 1. (The remainder
of the status register is not affected.)
Status Reg ister
• The FS parameter is a value between 1 and 32; it selects the field size.
(Note that an FS value of 0 in the opcode corresponds to an actual
selected field size of 32.)
• The FE parameter is a value of 0 or 1 :
FE=O selects zero extension for a field.
FE=1 selects sign extension for a field.
• The F parameter is optional; the default value for F is O. The F value
determines whether the SETF instruction sets the field size and ex-
tension for field 0 or for field 1 .
F=O selects FSO, FEO to be altered.
F=1 selects FS1, FE1 to be altered.
Each MOVE instruction also has an F parameter that selects the field size
and extension of either field 0 or field 1 for the individual move. You can
use the SETF instruction to prepare for MOVE instructions.
Machine
States 1,4 for F=O
2,5 for F=1
Status Bits N Unaffected
C Unaffected
Z Unaffected
V Unaffected
Examples Code Before After
ST ST
SETF 32,0,0 xxxxxOOOh xxxxxOOOh
SETF 32,1,0 xxxxxOOOh xxxxx020h
SETF 31,1,0 xxxxxOOOh xxxxx03Fh
SETF 16,0,0 xxxxxOOOh xxxxx010h
SETF 32,0,1 xxxxxOOOh xxxxxOOOh
SETF 32,1,1 xxxxxOOOh xxxxx800h
SETF 31,1,1 xxxxxOOOh xxxxxFCOh
SETF 16,0,1 xxxxxOOOh xxxxx400h
12-237
SEXT Sign Extend to Long
Syntax SEXT Rd [, FJ
Execution field in Rd .... sign-extended field Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 1 IF I 1 0 0 oIR Rd I
Description SEXT sign extends the right-justified field contained in the destination re-
gister by copying the MSB of the field data into all the non field bits of the
destination register. The size of the field is determined by the current field
size. The optional F parameter, which must be specified as a 0 or a 1, se-
lects the field size:
F =0 selects FSO for the field size.
F =1 selects FS1 for the field size.
The default value for F is O.
Machine
States 3,6
Status Bits N 1 if the result is negative, 0 otherwise
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
FSO/1 AO NCZV AO
SEXT AO,O 17/x 00008000h OxOx 00008000h
SEXT AO,O 16/x 00008000h 1xOx FFFF8000h
SEXT AO,O 15/x 00008000h Ox1x OOOOOOOOh
SEXT AO,l x/17 0OO08000h OxOx 0OOO8000h
SEXT AO,l x/16 0OO08000h 1xOx FFFF8000h
SEXT AO,l x/15 0OO08000h Ox1x OOOOOOOOh
12-238
Shift Left Arithmetic - Constant SLA
Syntax SlA K,Rd
Execution left-shift Rd by K ~ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 01 K R Rd 1
Description SLA left-shifts the contents of the destination register by a specified num-
ber of bits. The shift count is specified by a 5-bit constant (K in the syn-
tax); this is a value between 0 and 31 .
As shown in the diagram, Os are shifted into the least significant bits. The
last bit shifted out of the destination register (the original value of bit
32-K) is shifted into the carry bit. If either the new sign bit (N) or any of
the bits shifted out of the register differ from the original sign bit, the over-
flow bit (V) is set.
o
It---'--t +--- Shift +-- 0
MSB LSB
The assembler accepts only absolute expressions for the shift count. If the
shift count is greater than 31, the assembler issues a warning and sets the
K field in the opcode to the 5 LS Bs of K.
Note that SLA executes slower than SLL because it provides overflow de-
tection.
Machine
States 3,6
Status Bits N a
1 if the result is negative, otherwise
C Set to the value of last bit shifted out, 0 for shift count of 0
Z a
1 if a 0 result generated, otherwise
V a
1 if the MSB changes during shift operation, otherwise
Examples Code Before After
A1 A1 NCZV
SLA O,Al 33333333h 33333333h 0000
SLA O,Al CCCCCCCCh CCCCCCCCh 1000
SLA 1,Al CCCCCCCCh 99999998h 1100
SLA 2,Al 33333333h CCCCCCCCh 1001
SLA 2,Al CCCCCCCCh 33333330h 0101
SLA 3,Al CCCCCCCCh 66666660h 0001
SLA S,Al CCCCCCCCh 99999980h 1101
SLA 30,Al CCCCCCCCh OOOOOOOOh 0111
SLA 3l,Al CCCCCCCCh OOOOOOOOh 0011
SLA 3l,Al OOOOOOOOh OOOOOOOOh 0010
12-239
SLA Shift Left Arithmetic - Register
Syntax SLA Rs,Rd
Executiqn left-shift Rd by 5 LSBs of Rs ~
Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 0 0 01 Rs R Rd I
Description SLA left-shifts the contents of the destination register by a specified num-
ber of bits. The shift count is specified by the 5 LSBs of Rs (the 27 MSBs
are ignored); this produces a shift count from 0 to 31.
The last bit shifted out of the destination register (the original value of bit
32-K) is shifted into the carry bit. If either the new sign bit (N) or anyof
the bits shifted out of the register differ from the original sign bit, the over-
flow bit (V) is set.
V
o
It---..&..-I +--- Shift +---- 0
MSB LSB
Note that you must designate Rs with a keyword or symbol which has
been defined to be a register, for example, A9; otherwise, the assembler
uses uses the SLA K,Rd instruction. Rs and Rd must be in the same register
file.
Note that SLA executes slower than SLL because it provides overflow de-
tection.
Machine
States 3,6
Status Bits N 1 if the result is negative, 0 otherwise
C Set to value of last bit shifted out, 0 for shift count of 0
Z 1 if the result is 0, 0 otherwise
V 1 if the MSB changes during shift operation, 0 otherwise
Examples Code Before After
5 LSBs AO A1 A1 NCZV
SLAAO,Al 00000 33333333h 33333333h 0000
SLA AO,Al 00000 CCCCCCCCh CCCCCCCCh 1000
SLA AO,Al 00001 CCCCCCCCh 99999998h 1100
SLA AO,Al 00010 33333333h CCCCCCCCh 1001
SLA AO,Al 00010 CCCCCCCCh 33333330h 0101
SLA AO,Al 00011 CCCCCCCCh 66666660h 0001
SLA AO,Al 00101 CCCCCCCCh 99999980h 1101
SLA AO,Al 11110 CCCCCCCCh OOOOOOOOh 0111
SLA AO,Al 11111 CCCCCCCCh OOOOOOOOh 0011
SLA AO,Al 11111 OOOOOOOOh \ OOOOOOOOh 0010
12-240
Shift Left Logical - Constant SLL
Syntax SLL K,Rd
Execution left-shift Rd by K ..... Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 1 I K R Rd I
Description SLL left-shifts the contents of the destination register by a specified number
of bits. The shift count is specified by a 5-bit constant (K in the syntax.),
which is a value between 0 and 31.
The last bit shifted out of the destination register (the original value of bit
32-K) is shifted into the carry bit. Os are shifted into the least significant
bits. This instruction differs from the SLA instruction only in its effect on
the overflow (V) bit.
c
~~~------------~~
1+4- - Shift +-4- - 1 + - - 0
9 I
The assembler only accepts absolute expressions for the shift count. If the
specified shift count is greater than 31, the assembler issues a warning and
sets the K field in the opcode to the 5 LSBs of K.
Machine
States 1,4
Status Bits N Unaffected
C 1 to the value of last bit shifted out, 0 for shift count of 0
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
A1 A1 NCZV
SLL O,Al OOOOOOOOh OOOOOOOOh x01x
SLL O,Al 88888888h 88888888h xOOx
SLL 1,Al 88888888h 11111110h x10x
SLL 4,Al 88888888h 88888880h xOOx
SLL 30,Al FFFFFFFCh OOOOOOOOh x11x
SLL 3l,Al FFFFFFFCh OOOOOOOOh x01x
12-241
SLL Shift Left Logical - Register
Syntax SLL Rs, Rd
Execution left-shift Rd by 5 LSBs of Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 Rs IR Rd I
Description SLL left-shifts the contents of the destination register by a specified number
of bits. The shift count is specified by the 5 LSBs of Rs (the 27 MSBs are
ignored); this produces a shift count between 0 and 31.
The last bit shifted out of the destination register (the original value of bit
32 -K) is shifted into the carry bit. Os are shifted into the least significant
bits. This instruction differs from the SLA instruction only in its effect on
the overflow (V) bit.
I~~--------------~~
+-l1li- - t.- o
Shift +-l1li- -
I
Note that you must designate Rs with a keyword or symbol which has been
defined to be a register, for example, A9; otherwise, the assembler uses the
SLA K,Rd instruction.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N Unaffected
C Set to the value of last bit shifted out, 0 for shift value of 0
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
5 LSBs AO A1 A1 NCZV
SLL AO,Al 00000 OOOOOOOOh OOOOOOOOh x01x
SLL AO,Al 00000 88888888h 88888888h xOOx
SLL AO,Al 00001 88888888h 11111110h x10x
SLL AO,Al 00100 88888888h 88888880h xOOx
SLL AO,Al 11110 FFFFFFFCh OOOOOOOOh x11x
SLL AO,Al 11111 FFFFFFFCh OOOOOOOOh x01x
12-242
Shift Right Arithmetic - Constant SRA
Syntax SRA K,Rd
Execution right-shift Rd by K -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 01 28 complement of K 1R Rd I
Description SRA right-shifts the contents of the destination register by a specified
number of bits. The shift count is specified by the 2s complement of a 5-bit
immediate value, or constant; this produces a shift count of 0 to 31. (K in
the syntax represents this 5-bit constant).
The last bit shifted out of the destination register (the original value of bit
K-1) is shifted into the carry bit. The sign bit (MSB) is extended into the
most significant bits.
31 30 0 C
~
.s.
~ l::::_-_-_-_·~_6_hlft___~~~~
L6B
M6B
The assembler only accepts absolute expressions for the shift count. If the
specified shift count is greater than 31, the assembler issues a warning and
sets the K field in the opcode to the 2s complement of the 5 LSBs of K.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C Set to the value of last bit shifted out, 0 for shift count of 0
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
A1 A1 NCZV
SRA O,Al OOOOOOOOh OOOOOOOOh 001x
SRA O,Al FFFFOOOOh FFFFOOOOh 100x
SRA 8,Al 7FFFOOOOh 007FFFOOh OOOx
SRA 8,Al FFFFOOOOh FFFFFFOOh 100x
SRA 30,Al 7FFFOOOOh 0000OO01h 010x
SRA 31,Al 7FFFOOOOh OOOOOOOOh 011x
SRA 31,Al FFFFOOOOh FFFFFFFFh 110x
12-243
SRA Shift Right Arithmetic - Register
Syntax SRA Rs,Rd
Execution right-shift Rd by 2s complement of 5 LSBs in Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
10 0 0 01 Rs 1R Rd I
Description SRA right-shifts the contents of the destination register by a specified
number of bits. The shift amount is specified by the 2s complement of the
5 LSBs of Rs (the 27 MSBs of Rs are ignored); this produces a shift count
between 0 and 31 .
The last bit shifted out of the destination register (the original value of bit
K-1) is shifted into the carry bit. The sign bit (MSB) is extended into the
most significant bits.
31 30 0 C
.--.Is~l::_-_-_-_"_._S_h_Ift__
--_-_-:_~.~
~ LSB
MSB
You must specify Rs with a keyword or a symbol which has been defined
to be a register, for example, A9; otherwise, the assembler uses the SRA
K,Rd instruction. Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C Set to the value of last bit shifted out, 0 for shift count of 0
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
5 LSBs AO A1 A1 NCZV
SRA Ac,AI 00000 OOOOOOOOh OOOOOOOOh 001x
SRA Ac,AI 00000 FFFFOOOOh FFFFOOOOh 100x
SRA Ac,AI 11111 7FFFOOOOh 3FFF8000h OOOx
SRA Ac,AI 11111 FFFFOOOOh FFFF8000h 100x
SRA Ac,AI 11000 7FFFOOOOh 007FFFOOh OOOx
SRA Ac,AI 11000 FFFFOOOOh FFFFFFOOh 100x
SRA Ac,AI 00010 7FFFOOOOh 00000001h 010x
SRA Ac,AI 00001 7FFFOOOOh OOOOOOOOh 011x
SRA Ac,AI 00001 FFFFOOOOh FFFFFFFFh 110x
12-244
Shift Right Logical - Constant SRL
Syntax SRL K,Rd
Execution right-shift Rd by 2s complement of K -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 1 I 25 complement of K R Rd I
Description SRL right-shifts the contents of the destination register by a specified
number of bits. The shift amount is specified by the 2s complement of a
5-bit immediate value; this produces a shift count between 0 and 31. (K
in the syntax represents the immediate value, or constant.)
The last bit shifted out of the destination register (the original value of bit
K-1) is shifted into the carry bit. Os are shifted into the most significant bits.
~ 0 C
o ----1---.~ Shift ----.~ ~
MSB LSB
The assembler accepts only absolute expressions for the shift count. If the
specified shift amount is greater than 31, the assembler issues a warning
and set the K field in the opcode to the 25 complement of the 5 LS Bs of K.
Machine
States 1,4
Status Bits N Unaffected
C Set to the value of last bit shifted out, 0 for shift count of 0
Z 1 if the resu It is 0, 0 otherwise
V Unaffected
Examples Code Before After
A1 A1 NCZV
SRL O,Al OOOOOOOOh OOOOOOOOh x01x
SRL O,Al 7FFFFFFFh 7FFFFFFFh xOOx
SRL 1,Al 7FFFFFFFh 3FFFFFFFh x10x
SRL 8,Al 7FFFOOOOh 007FFFOOh xOOx
SRL 30,Al 7FFFOOOOh 00000001h x10x
SRL 3l,Al 7FFFOOOOh OOOOOOOOh x11x
SRL 3l,Al 3FFFOOOOh OOOOOOOOh x01x
12-245
SRL Shift Right Logical - Register
Syntax SRL Rs, Rd
Execution right-shift Rd by 2s complement of 5 LSBs in Rs ..... Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 1 I Rs IR I Rd I
Description SRL right-shifts the contents of the destination register by a specified
number of bits. The shift amount is specified by the 2s complement of the
5 LSBs of Rs (the 27 MSBs of Rs are ignored); this produces a shift value
of 0 to 31.
The last bit shifted out of the destination register (the original value of bit
K -1) is shifted into the carry bit. Os are shifted into the most significant bits.
31 0 C
o -----.I----+~ Shift ----+~ I----{]
M8B LSB
You must specify Rs with a keyword or symbol which has been defined to
be a register, for example, A9; otherwise, the assembler uses the SRL K,Rd
instruction. Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N Unaffected
C Set to the value of last bit shifted out, 0 for shift count of 0
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Before After
5 LSBs AO A1 A1 NCZV
SRL AO,Al 00000 OOOOOOOOh OOOOOOOOh x01x
SRL AO,Al 00000 7FFFFFFFh 7FFFFFFFh xOOx
SRL AO,Al 11111 7FFFFFFFh 3FFFFFFFh x10x
SRL AO,Al 11000 7FFFOOOOh 007FFFOOh xOOx
SRL AO,Al 00010 7FFFOOOOh 00000001h x10x
SRL AO,Al 00001 7FFFOOOOh OOOOOOOOh x11x
SRL AO,Al 00001 3FFFOOOOh OOOOOOOOh x01x
12-246
Subtract Registers SUB
Syntax SUB Rs, Rd
Execution Rd - Rs -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
1 0 0 0 0 01 Rs IR Rd I
Description SUB subtracts the contents of the source register from the contents of the
destination register and stores the result in the destination register.
You can accomplish multiple-precision arithmetic by using SUB in con-
junction with the SUBB instruction.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a borrow, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
AO A1 NCZV AO
SUB AI,AD 7FFFFFF2h 7FFFFFF1h 0000 00000001h
SUB AI,AD 7FFFFFF2h 7FFFFFF2h 0010 OOOOOOOOh
SUB AI,AD 7FFFFFF1h 7FFFFFF2h 1100 FFFFFFFFh
SUB AI,AD 7FFFFFF1h FFFFFFFFh 0100 7FFFFFF2h
SUB AI,AD 7FFFFFFFh FFFFFFFFh 1101 80000000h
SUB AI,AD FFFFFFFDh FFFFFFFFh 1100 FFFFFFFEh
SUB AI,AD FFFFFFFDh FFFFFFFDh 0010 OOOOOOOOh
SUB AI,AD FFFFFFFEh FFFFFFFDh 0000 00000001h
SUB AI,AD FFFFFFFFh 00000001h 1000 FFFFFFFEh
SUB AI,AD 80000000h 00000001h 0001 7FFFFFFFh
12-247
SUBB Subtract Registers with Borro\
Syntax SUBB Rs, Rd
Execution Rd - Rs - C -+ Rd (the carry bit acts as a borrow)
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I0 0 0 0 1 I Rs IR Rd
Description SUBB subtracts both the contents of the source register and the carry t
from the contents of the destination register, and stores the result in tl
destination register.
You can use this instruction with the SUB, SUBK, and SUBI instructiol
for extended-precision arithmetic.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a borrow, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
C AO A1 NCZV AO
SUBB Al,AO 0 00000002h 00000001h 0000 00000001
SUBB Al,AO 1 00000002h 00000001h 0010 00000000
SUBB Al,AO 0 00000002h 00000002h 0010 00000000
SUBB Al,AO 1 00000002h 00000002h 1100 FFFFFFFF
SUBB Al,AO 0 00000002h 00000003h 1100 FFFFFFFF
SUBB Al,AO 0 7FFFFFFEh FFFFFFFFh 0100 7FFFFFFF
SUBB Al,AO 0 7FFFFFFEh FFFFFFFEh 1101 80000000
SUBB Al,AO 1 7FFFFFFEh FFFFFFFEh 0100 7FFFFFFF
SUBB Al,AO 0 FFFFFFFEh FFFFFFFFh 1100 FFFFFFFF
SUBB Al,AO 0 FFFFFFFEh FFFFFFFEh 0010 00000000
SUBB Al,AO 1 FFFFFFFEh FFFFFFFEh 1100 FFFFFFFF
SUBB Al,AO 0 FFFFFFFEh FFFFFFFDh 0000 00000001
SUBB Al,AO 1 FFFFFFFEh FFFFFFFDh 0010 00000000
SUBB Al,AO 0 80000001h 00000001h 1000 80000000
SUBB Al,AO 1 80000001h 00000001h 0001 7FFFFFFF
SUBB Al,AO 0 80000001h 00000002h 0001 7FFFFFFF
12-248
Subtract Immediate - 16 Bits SUBI
Syntax SU BI IW, Rd [, W}
Execution Rd - IW -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
o 1 IR Rd
1s complement of IW
Description SUBI subtracts a sign-extended, 16-bit immediate value from the contents
of the destination register, and stores the result in the destination register.
(The IW in the syntax represents a sign-extended, 16-bit immediate value.)
The assembler uses this form of the SUBI instruction if the immediate value
was previously defined and is in the range -32,768 to 32,767. You can
force the assembler to use the short form by by following the register op-
erand with, W:
SUBI IW,Rd,W
The assembler truncates any upper bits and issues an appropriate warning
message. You can accomplish mUltiple-precision arithmetic by using SUBI
in conjunction with the SUBB instruction.
Machine
States 2,8
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if a borrow is generated, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
AO AO NCZV
SUBI 32765,AO 00007FFEh 00000001h 0000
SUBI 32766,AO 00007FFEh OOOOOOOOh 0010
SUBI 32767,AO 00007FFEh FFFFFFFFh 1100
SUBI 32766,AO 80007FFEh 80000000h 1000
SUBI 32767,AO 80007FFEh 7FFFFFFFh 0001
SUBI -32766,AO FFFF8001h FFFFFFFFh 1100
SUBI -32767,AO FFFF8001h OOOOOOOOh 0010
SUBI -32768,AO FFFF8001h 00000001h 0000
SUBI -32767,AO FFFF8000h 7FFFFFFFh 0100
SUBI -32768,AO 7FFF8000h 80000000h 1101
12-249
SUBI Subtract Immediate - 32 Bits
Syntax SU BilL, Rd [, LJ
Execution Rd - IL -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 1 1 0 1 0 0 01 R I Rd
1 s complement of 16 LSBs of IL
1s complement of 16 MSBs of IL
Description SUBI subtracts a signed 32-bit immediate value from the contents of the
destination register, and stores the result in the destination register. (The
IL in the syntax represents a signed 32-bit immediate value.)
The assembler uses this version of the SUBI instruction if it cannot use the
SUBI IW,Rd opcode, or if you request the long opcode by following the
register operand with ,L:
SUBI IL,Rd,L
You can accomplish multiple-precision arithmetic by using SUBI in con-
junction with the SUBB instruction.
Machine
States 3,12
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a borrow, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
AO AO NCZV
SUBI 2147483647,AO 7FFFFFFFh OOOOOOOOh 0010
SUBI 32768,AO 00008001h 00000001h 0000
SUBI 32769,AO 00008001h OOOOOOOOh 0010
SUBI 32770,AO 00008001h FFFFFFFFh 1100
SUBI 32768,AO 80008000h 80000000h 1000
SUBI 32769,AO 80008000h 7FFFFFFFh 0001
SUBI -2147483648,AO 80000000h OOOOOOOOh 0010
SUBI -32769,AO FFFF7FFEh FFFFFFFFh 1100
SUBI -32770,AO FFFF7FFEh OOOOOOOOh 0010
SUBI -32771,AO FFFF7FFEh 00000001h 0000
SUBI -32770,AO 7FFF7FFDh 7FFFFFFFh 0100
SUBI -32771,AO 7FFF7FFDh 80000000h 1101
12-250
Subtract Constant SUBK
Syntax SUBK K,Rd
Execution Rd - K -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 1 I K R Rd I
Description SUBK subtracts the 5-bit constant from the contents of the destination re-
gister; the result is stored in the destination register. The K in the syntax
represents a constant that is treated as an unsigned number in the range
1-32. Note that K=O in the opcode corresponds to the value 32; the as-
sembler converts the value 32 to O. The assembler issues an error if you try
to subtract 0 from a register.
You can accomplish multiple-precision arithmetic by using SUBK in con-
junction with the SUBB instruction.
Machine
States 1,4
Status Bits N 1 if the result is negative, 0 otherwise
C 1 if there is a borrow, 0 otherwise
Z 1 if the result is 0, 0 otherwise
V 1 if there is an overflow, 0 otherwise
Examples Code Before After
AO AO Nevz
SUBK S,AO 00000009h 00000004hOOOO
SUBK 9,AO 00000009h 0000000Oh0010
SUBK 32,AO 00000009h FFFFFFE9h1100
SUBK 1,AO 80000000h 7FFFFFFFhOO01
12-251
SUBXV Subtract Registers in XV Mode
Syntax SUBXY Rs, Rd
Execution RdX - RsX ~ RdX
RdY - RsY ~ RdY
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I1 0 0 0 1 I Rs IR Rd I
Description SUBXY subtracts the source X and Y values individually from the destina-
tion X and Y values; the result is stored in the destination register.
You can use this instruction for manipulating XY addresses; it is particularly
useful for incremental figure drawing. These addresses are stored as XY
pairs in the register file.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits N 1 if source X field = destination X field, 0 otherwise
C 1 if source Y field > destination Y field, 0 otherwise
Z 1 if source Y field = destination Y field, 0 otherwise
V 1 if source X field > destination X field, 0 otherwise
Examples Code Before After
AO A1 AO NCZV
SUBXY Al,AO 00090009h 00010001h 00080008h 0000
SUBXY Al,AO 00090009h 00090001h 00000008h 0010
SUBXY Al,AO 00090009h 00010009h 00080000h 1000
SUBXY Al,AO 00090009h 00090009h OOOOOOOOh 1010
SUBXY Al,AO 00090009h 00000010h 0009FFF9h 0001
SUBXY Al,AO 00090009h 00090010h 0000FFF9h 0011
SUBXY Al,AO 00090009h 00100000h FFF90009h 0100
SUBXY Al,AO 00090009h 00100009h FFF90000h 1100
SUBXY Al,AO 00090009h 001 0001 Oh FFF9FFF9h 0101
12-252
Software Interrupt TRAP
Syntax TRAP N
Execution PC -+ -*5P
5T -+ -*5P
trap vector N -+ PC
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
1 0 0 0 0 0 0 0 0 01 N
Description TRAP executes a software interrupt. The N parameter is a trap number from
o to 31 that selects the trap to be executed. During a software interrupt,
• The return address (the address of next instruction) is pushed on the
stack.
• The status register is pushed on the stack.
• The IE (interrupt enable) bit in 5T is set to 0, disabling maskable in-
terrupts, and 5T is set to 00000010h.
• Finally, the trap vector is loaded into the PC.
The TM53401 0 generates the trap vector addresses as shown below:
Trap
Number Addreas
--0-
>FFFF FFEO I-----I~!.P_--I Reset
1 >FFFF FFCO External Interrupt 1
2 >FFFF FFAO External Interrupt 2
3 >FFFF FF80
4 >FFFF FF60
5 >FFFF FF40
6 >FFFF FF20
7 >FFFF FFOO 1----nI'ln----I
8 >FFFF FEEO Non Mukable Interrupt
9 >FFFF FECO Host Interrupt
10 >FFFF FEAO DIsplay Interrupt
11 >FFFF FE80 WIndow Violation
12 >FFFF FE60
13 >FFFF FE40
14 >FFFF FE20
15 >FFFF FEOO
16 >FFFF FDEO
17 >FFFF FDCO
18 >FFFF F[)\O
19 >FFFF FDBO
20 >FFFF FD60 Traps 12-29
21 >FFFF FD40
22 >FFFF FD20
23 >FFFF FDOO
24 >FFFF FCEO
25 >FFFF FCCO
26 >FFFF FCAO
27 >FFFF FCSO
28 >FFFF FCSO
29 >FFFF FC40 I-----,"""~--I
30 >FFFF FC20 Illegal Opcode
31 >FFFF FCOO ti==~~=:;t
The stack, which is located in external memory, grows toward lower ad-
dresses. The PC and 5T are pushed on the stack M5W first, and the 5P is
predecremented before each word is loaded onto the stack.
12-253
TRAP Software Interrupt
Notes:
1. The level 0 trap differs from all other traps; it does not save the old
status register or program counter. This may be useful in cases
where the stack pointer is corrupted or uninitialized; such a situ-
ation could cause an erroneous write.
2. The NMI bit does not affect the operation of TRAP B.
For more information, refer to Section B (Interrupts, Traps, and Reset).
Machine
States 16,19 (SP aligned)
30,33 (SP nonaligned)
Status Bits N 0
C 0
Z 0
V 0
Examples
Code Before After
PC SP PC w- ST
TRAP 0 xxxxxxxxh BOOOOOOOh FFFFFFEOh BOOOOOOOh 00000010h
TRAP 1 xxxxxxxxh BOOOOOOOh FFFFFFCOh 7FFFFFCOh 00000010h
TRAP 30 xxxxxxxxh BOOOOOOOh FFFFFC20h 7FFFFFCOh 00000010h
TRAP 31 xxxxxxxxh BOOOOOOOh FFFFFCOOh 7FFFFFCOh 00000010h
12-254
Exclusive-OR Registers XOR
Syntax XOR Rs, Rd
Execution Rs XOR Rd -+ Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 1 I Rs R Rd I
Description XOR bitwise-exclusive-ORs the contents of the source register with the
contents of the destination register, and stores the result in the destination
register.
You can use this instruction to clear registers (for example, XOR BO ,BO);
the CLR instruction also supports this function.
Rs and Rd must be in the same register file.
Machine
States 1,4
Status Bits NUn affected
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Before
AO A1 NCZV A1
XOR AO,Al FFFFFFFFh OOOOOOOOh xxOx FFFFFFFFh
XOR AO,Al FFFFFFFFh AAAAAAAAh xxOx 55555555h
XOR AO,Al FFFFFFFFh FFFFFFFFh xx1x OOOOOOOOh
12-255
XORI Exclusive-OR Immediate Value
Syntax XORI IL, Rd
Execution IL XOR Rd .... Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
0 0 0 0 1 0 1 1 1 1 oIR I Rd
16 LSBs of IL
16 MSBs of IL
Description XORI bitwise exclusive ORs a 32-bit immediate data with the contents of
the destination register and stores the result in the destination register. (The
IL parameter in the syntax above represents a 32-bit immediate value.)
Machine
States 3,12
Status Bits N Unaffected
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
AO NCZV AO
XORI OFFFFFFFFh,AO OOOOOOOOh xxOx FFFFFFFFh
XORI OFFFFFFFFh,AO AAAAAAAAh xxOx 55555555h
XORI OFFFFFFFFh,AO FFFFFFFFh xx1x OOOOOOOOh
XORI oOOOOOOOh,AO OOOOOOOOh xx1x OOOOOOOOh
XORI oOOOOOOOh,AO FFFFFFFFh xxOx FFFFFFFFh
12-256
Zero Extend to Long ZEXT
Syntax ZEXT Rd [, FJ
Execution field in Rd -+ zero-extended field Rd
Instruction
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
I0 0 0 0 0 1 IF I 1 0 0 1 IR Rd I
Description ZEXT zero extends a right-justified field in the destination register by zero-
ing all the nonfield bits in Rd. The size of the field is determined by the
current field size. The optional F parameter, which must be specified as a
o or a 1, selects the field size:
F =0 selects FSO for the field size.
F=1 selects FS1 for the field size.
The default value for F is O.
Machine
States 1,4
Status Bits NUn affected
C Unaffected
Z 1 if the result is 0, 0 otherwise
V Unaffected
Examples Code Before After
FSO FS1 AO NCZV AO
ZEXT AO,O 32 x FFFFFFFFh xxOx FFFFFFFFh
ZEXT AO,O 31 x FFFFFFFFh xxOx 7FFFFFFFh
ZEXT AO,O 1 x FFFFFFFFh xxOx 00000001h
ZEXT AO,O 16 x FFFFOOOOh xx1x OOOOOOOOh
ZEXT AO,l x 16 FFFFOOOOh xx1x OOOOOOOOh
12-257
Instruction Set
12-258
Section 13
Instruction Timings
Section 12, The TMS34010 Instruction Set, describes each TMS34010 as-
sembly language instruction, including instruction cycle timings. This section
provides details pertaining to instruction timings for the following groups of
instructions:
Section Page
13.1 General Instructions .............................................................................. 13-2
13.2 MOVE and MOVB Instructions ........................................................... 13-4
13.3 FILL Instructions ................................................................................. 13-10
13.4 PIXBLT Instructions ........................................................................... 13-18
13.5 PIXBLT Expand Instructions ............................................................. 13-31
13-1
Instruction Timings - General Instructions
13.1 General Instructions
Note:
General instructions include all TMS34010 instructions except MOVEs,
MOVBs, FILLs, PIXBLTs, and LINE.
Each instruction description in Section 12 contains a Machine States field
that describes the instruction execution time in terms of the machine state. A
machine state is the fundamental time unit of the processor. Logically, it is the
time required to decode, interpret, and execute a single microinstruction in-
ternal to the CPU. Physically, a TMS3401 0 machine state is equal to a single
local clock period (the time from one LCLK1 low-to-high transition to the
next). For example, this value is 160 nanoseconds for a TMS34010 clocked
at 50 M Hz, and 200 nanoseconds for a 40- M Hz TMS3401 O.
The descriptions in the instruction discussions appear as:
Machine
States cache hit case, cache disabled case
These two values represent the number of CPU states required to execute the
instruction for each of two cases:
• The cache hit case gives the number of execution states if the in-
struction and its extension words reside entirely in cache. Thus, only
actual execution states (using the CPU) and external memory cycles for
data transfer are counted with the instruction.
• The cache disabled case gives the number of execution states if the
cache is disabled when the instruction is executed. In this case, external
memory cycles for fetching the instruction word and any extension
words are counted with the instruction in addition to states through the
CPU and memory states for data transfer. Cache is usually only disabled
during debugging.
Cache disabled timing is not necessarily worst case timing. It may sometimes
be exceeded when the cache is enabled but the instruction is not in the cache
(this is known as a cache miss).
13.1.1 Best Case Timing - Considering Hidden States
Best case timing occurs when an instruction is executed entirely in parallel
with the end of a previous instruction. According to some microprocessor
conventions, many TMS3401 0 instructions would have a best case timing of
o states. Since this is unrealistic, the convention used here assigns a finite
(nonzero) timing value but allows for instruction overlap by using the concept
of hidden states.
Hidden states are memory write cycles that occur at the end of a given in-
struction. Parallelism is achieved when the CPU is executing instructions at
the same time the memory controller is writing to memory. The machine states
consumed by the instructions that the CPU is executing hide the machine
13-2
Instruction Timings - General Instructions
states consumed by the write cycles. These hidden machine states are not
counted against the instruction that incurs them, but are counted against
subsequent instructions. If an instruction uses the local bus before all of the
hidden cycles have been overlapped by subsequent instructions, that in-
struction must wait for the hidden cycles to complete. Up to nine machine
states may be hidden by write cycles incurred by a single instruction.
In the timing charts in this section and in the Machine States portions of the
instruction descriptions, hidden states are indicated by parentheses as shown
below:
Machine
States cache hit case + (hidden states),cache disabled case
13.1.2 Other Effects on Instruction Timing
Instruction timing varies, depending on:
• Whether the cache is enabled.
• Whether the instruction and extension words are in cache or not.
• The field size and the word alignment of memory data manipulated
by the instruction.
The timing for some instructions (particularly the MOVE, MOVEB, LINE, FILL,
and PIXBLT instructions) is affected by the values of implied operands and
on the alignment and field sizes of any associated memory accesses.
In addition, several system-dependent factors that are not included in timing
values may further influence the instruction timings:
• Wait states on the local memory bus
• Host accesses via the host port
• Display refresh operations
• D RAM refresh operations
• HOLD/HLDA accesses
13-3
Instruction Timings - MOVE and MOVB Instructions
13.2 MOVE and MOVB Instructions
Timings for MOVE and MOVB instructions are in the following tables:
Table Page
13-1 MOVE and MOVB Memory-to-Register Timings ............................. 13-5
13-2 MOVE and MOVB Register-to-Memory Timings ............................. 13-6
13-4 MOVE Memory-to-Memory Timings .................................................. 13-7
MOVE and MOVB instructions are field operations, so their timings are af-
fected by factors such as memory address, field size, and field extensions.
These factors define the field alignment, which in turn defines the number of
memory states required to insert or extract the field from memory. Figure 13-1
illustrates seven cases of alignment, labelled A-G, that are used in the MOVE
and MOVB timing tables.
Cae A
Caae B
Caae C , Word N+1 I Word N
- 32-B1t field
Cae 0 IWOiCi N+1 I
Ii===Fleid
Caae E
Word N+g;~~QLj
Caae F Word N+1 I Word N
Ii=== field ~i
Caae G Word N+2 Word N+1 Word N
Ie Field ~i
Figure 13-1. Field Alignments in Memory
Case A A 16-bit field is aligned on word boundaries.
Cases B1-B3
The field length is less than 1 6 bits.
• In Case B1, the field starting address is not aligned to a word
boundary, although the end of the field coincides with the end
of the word.
13-4
Instruction Timings - MOVE and MOVB Instructions
• In Case B2, the field starting address is aligned to a word
boundary, but the end of the field does not coincide with the
end of the word.
• In Case B3, the field length is 14 bits or less, and neither the
start nor the end of the field is aligned to a word boundary.
Case C A 32-bit field is aligned on word boundaries.
Case 0 The field size is greater than 16 bits. The field starting address is not
aligned to a word boundary, although the end of the field coincides
with the end of a word.
Case E The field size is greater than 1 6 bits. The field starting address is
aligned to a word boundary, but the end of the field does not coin-
cide with the end of a word.
Case F The field straddles the boundary between two words. Neither the
start nor the end of the field is aligned to a word boundary.
Case G The field size ranges from 18 to 32 bits, and the field straddles two
word boundaries. Neither the start nor the end of the field is aligned
to a word boundary.
13.2.1 Moves Between Registers and Memory
Table 13-1 lists the timing for memory-to-register moves for each case of the
destination alignment in Figure 13-1. Table 13-2 lists the timing for regis-
ter-to-memory moves. Note that there are no hidden states for memory-to-
register moves.
Table 13-1. MOVE and MOVB Memory-to-Register Timings
Field Alignment Type
Instruction
A or B C, 0, E, F G
MOVB *Rs, Rd 3,6 5,8 -
MOVB *Rs(offsetj, Rd 5,11 7,13 -
MOVB @Address, Rd 5,14 7,16 -
MOVE *Rs, Rd 3,6 5,8 7,10
MOVE *Rs+,Rd 3,6 5,8 7,10
MOVE -*Rs, Rd 4,7 6,9 8,11
MOVE *Rs(offsetj, Rd 5,11 7,13 9,15
MOVE @Address, Rd 5,14 7,16 9,18
Notes: 1. Add 1 state to MOVES for sign extension.
2. The first number specifies the number of cycles required when the entire in-
struction is contained within cache (cache hit case). The second number
specifies the number of cycles required when the cache is disabled (cache
disabled case).
13-5
Instruction Timings - MOVE and MOVB Instructions
Table 13-2. MOVE and MOVe Register-to-Memory Timings
Field Alignment Type
Instruction
A B or C D or E F G
MOVB Rs, *Rd - 1 +(3),7 - 1+(7),11 -
MOVB Rs, * Rd(offset) - 3+(3),7 - 3+(7),13 -
MOVB Rs, @Address - 1 +(3),7 - 3+(7),13 -
MOVE Rs, *Rd 1+(1),5 1 +(3),7 1 +(5),9 1+(7),11 1+(9),13
MOVE Rs, *Rd+ 1+(1),5 1 +(3),7 1 +(5),9 1+(7),11 1+(9),13
MOVE Rs, - *Rd 2+(1 ),6 2+(3),8 2+(5),10 2+(7),12 2+(9),14
MOVE Rs, * Rd(offset) 3+{1 ),9 3+(3),12 3+(5),14 3+(7),13 3+(9),18
MOVE Rs, @Address 3+(1),13 3+(3),15 3+(5),17 3+(7),19 3+(9),21
Note: The first number specifies the number of cycles required when the entire instruction is contained
within cache (cache hit case). The second number specifies the number of cycles required when
the cache is disabled (cache disabled case). Hidden states are indicated by parentheses.
13.2.2 Memory-to-Memory Moves
Table 13-4 lists memory-to-memory move timings for each combination of
source and destination alignment. Table 13-3 lists numeric indices which are
used in Table 13-4. The indices are associated with each source and desti-
nation alignment yair (the alignments are shown in Figure 13-1 on page
13-4). To use these tables:
1) Determine the source and destination alignment,
2) Locate the alignment and its index in Table 13-3, and
3) Use the index to select the correct column for a particular MOVE
addressing mode in Table 13-4.
Table 13-3. Alignment Indices for Memory-to-Memory Moves
Source Field Destination Field Alignment
Alignment A B C D E F G
A 1 - - - - 3 -
B - 2 - - - 3 -
C - - 6 - - - 9
D - - - 7 7 8 9
E - - - 7 7 8 9
F 4 5 - 7 7 8 9
G - - 10 11 11 12 13
13-6
Instruction Timings - MOVE and MOVB Instructions
Table 13-4. MOVE Memory-to-Memory Timings
Memory-to-Memory Index - Source to Destination
Instruction
1 2 3 4 5 6 7
Move *Rs, *Rd - 3+(3),7 3+(7),13 - 5+(3),11 - -
Move * Rs(offset),
* Rd(offset)
- 5+(3),7 5+(7),21 - 6+(3),13 - -
Move @SAddr, @DAddr - 7+(3),7 7+(7),29 - 6+(3),12 - -
MOVE *Rs, *Rd 3+(1 ),7 3+(3),9 3+(7),13 5+(1 ),9 5+(3),11 5+(3),11 5+(5),13
MOVE *Rs+, *Rd+ 4,7 4+(2),9 4+(6),13 6,9 6+(2),11 6+(2),11 6+(4),13
MOVE -*Rs, -*Rd 4+(1 ),8 4+(3),10 4+(7),14 6+(1),10 6+(3),12 6+(3),12 6+(5),14
MOVE * Rs(offset), * Rd+ 5+(1),12 5+(3),14 5+(7),18 7+(1 ),14 7+(3),16 7+(3),13 7+(5),15
MOVE * Rs(offset), 5+(1).15 5+(3),17 5+(7),21 7+(1).17 7+(3),19 7+(3),16 7+(5),18
* Rd(offset)
MOVE @SAddr, * Rd+ 5+(1),15 5+(3).17 5+(7),21 7+(1),17 7+(3),19 7+(3),16 7+(5),18
MOVE @SAddr, @DAddr 7+(1),23 7+(3),25 7+(7),29 9+(1),25 9+(3),27 9+(3),24 9+(5),26
Memory-to-Memory Index - Source to Destination
Instruction
8 9 10 11 12 13
Move * Rs, * Rd 5+(7),15 - - - - -
Move * Rs(offset), 7+(7),19 - - - - -
* Rd(offset)
Move @SAddr, @DAddr 9+(7),27 - - - - -
MOVE *Rs, *Rd 5+(7),15 5+(9),17 7+(3),13 7+(5),15 5+(7),17 9+(9),21
MOVE *Rs+, *Rd+ 6+(6),15 6+(8),17 8+(2),13 8+(4),15 6+(6),17 10+(8),21
MOVE -*Rs, -*Rd 6+(7),15 6+(9),18 8+(3),14 8+(5),16 6+(7),18 10+(9),22
MOVE * Rs(offset), * Rd+ 7+(7),16 7+(9),19 9+(3),18 9+(5),20 i+(7),22 11 +(9),26
MOVE * Rs(offset), 7+(7).19 7+(9),22 9+(3),21 9+(5),23 7+(7),25 11 +(9),29
* Rd(offset)
MOVE @SAddr, *Rd+ 7+(7),19 7+(9),22 9+(3),21 9+(5),23 7+(7),25 11 +(9),29
MOVE @SAddr, @DAddr 9+(7),27 9+(9),30 11 +(3),29 11 +(5),31 9+(7),33· 13+(9),37
Note: The number on the left specifies the number of cycles required when the entire instruction is con-
tained within cache (cache hit case). The number on the right specifies the number of cycles re-
quired when the cache is disabled (cache disabled case). Hidden states are indicated by
parentheses.
13-7
Instruction Timings - MOVE and MOVB Instructions
13.2.3 MOVE Timing Example
This example illustrates the timing for the following MOVE instruction:
*************************************************
* Example of a MOVE @SADDR,@DADDR instruction: *
* Source address = OE5h *
* Destination address = 161h *
* Size of field 0 = 31 bits (FEO = don't care) *
*************************************************
SETF 31, 0 ; Set FSO field in ST
MOVE @OESh, @16lh, 0
This example moves 31 bits of data from one memory location to another
memory location (a memory-to-memory move). We know that the field size
is 31 bits because we FSO to 31 and then used field 0 for the move. To de-
termine the timing for this MOVE instruction, follow these steps:
1) Determine the field alignment of the source data.
The 31 bits of source data begin at address OE5h and span three words.
Figure 13-2 below illustrates the alignment of the source data in mem-
ory; if you look at Figure 13-1 on page 13-4, you'll see that this is
alignment G.
T
/
\
Figure 13-2. Source Data, Alignment G
2) Determine the field alignment of the destination location.
The destination location begins at address 161 h and spans two words.
Figure 13-3 illustrates alignment of the destination location; according
to Figure 13-1 (page 13-4), this is alignment E.
Figure 13-3. Destination Location, Alignment E
13-8
Instruction Timings - MOVE and MOVB Instructions
3) Find the alignment index for the combination of the source alignment
and the destination alignment.
Table 13-3 (page 13-6) shows the source-to-destination alignment in-
dices. The correct index for the combination of source alignment G with
destination alignment E is index 11.
4) Find the index for this instruction in Table 13-4 (page 13-7).
The example instruction, MOVE @OE5h I @161h, corresponds to M aVE
@SAddr,@Oaddr in Table 13-4. Follow this row in the table across to
the entry beneath column 11. The timing listed in this entry,
11 +(5),31, is the timing for the example instruction.
Thus, this MOVE example consumes 11 machine states (plus 5 hidden states)
if this code resides in cache. If the instruction cache is not enabled, this ex-
ample consumes 31 machine states. The memory accesses at the end of the
MOVE consume 5 machine states, which may be hidden by subsequent
cache-resident instructions.
This example is for a memory-to-memory move. If you want to determine the
timing for a memory-to-register or a register-to-memory move, use Table 13-2
or Table 13-1 .
13-9
Instruction Timings - FILL Instructions
13.3 FILL Instructions
The total time for the FILL instruction is determined by adding a setup time to
a transfer time:
FILL time = FILL setup time + FILL transfer time
• The setup sequence executes an initialization sequence, performing
any necessary setup operations and translations. (This may include
XV -to-linear conversions and window preclipping.) The result of the
setup includes the dimensions of the array that is to be moved.
• The transfer sequence performs the actual data transfer from the
source register to the destination array.
FILL setup and transfer timings are in the following tables:
Table Page
13-5 FI LL Setup Time ................................................................................. 13-10
13-6 FILL Transfer Timingt ........................................................................ 13-11
13.3.1 FILL Setup Time
FILL setup time is the overhead incurred by the FILL instructions from per-
forming initialization, XV conversions, and window operations. Windowop-
erations are performed before the FI LL transfer begins. Window options that
affect FILL setup timing include:
• No window clipping (W=O)
• A window clip that requires no change (array fits)
• A window clip that affects the starting pointer (start adjust)
• A window clip that affects the array transfer dimensions (dimension
adjust)
• A window clip that affects both the starting and the ending pointers
(adjust both)
• A window miss requesting an interrupt
• A window hit
Table 13-5 illustrates the effects of windowing operations on FILL setup tim-
ing. Corner adjust operations have no effect on FILL setup timing.
Table 13-5. FILL Setup Time
Window Operation Corner Adjust
Array Start Dimens Adjust PBH=1 PBH=O PBH=1
Instruction W=O Fits Adjust Adjust Both Miss Hit PBV=O PBV=1 PBV=1
FILL L 4 - - - - - - - - -
FILL XV 6 9 16 12 20 - - - - -
Note: These timings are for the cache hit case; add 3 machine states for cache disabled timing.
For example, a FI LL XV with preclipping that requires both the starting and
ending array corners to be adjusted would consume 20 states of setup time.
13-10
Instruction Timings - FILL Instructions
13.3.2 FILL Transfer Timing
Table 13-6 lists FILL transfer timings. Transfer timing is the time required (in
addition to the setup time) to execute the actual data transfer to memory.
Transfer timing is based on several parameters such as the number of rows in
the adjusted array (L), the number of words affected per row (N), graphics
operations (G), and four possible destination array alignments (A, B, C, and
D). These factors are described in the list that follows the table.
Table 13-6. FILL Transfer Timingt
Array Alignments
Line Length
A B C 0
Short (N=1) (1 +G)L + 2 (2+G)L + 2 (2+G)L + 1 (2+G)L + 1
Medium (N=2) (2+2G)L + 2 (3+2G)L + 2 (3+2G)L + 2 (4+2G)L + 1
Long (N)3) (1 +NG)L + 2 (2+NG)L + 5 (3+NG)L + 2 (4+NG)L + 1
t Subtract any alignment/graphics adjustment from these values
Key:
L Number of rows (see page 13-11 )
N Number of words per row (see page 13-12)
G Value derived from selected graphics operation (see Table 13-7 on page 13-13)
13.3.2.1 Number of Rows in the Adjusted Array (L)
The working dimensions (L rows x M pixels) for the fill are determined by the
originally supplied destination pointer (DADDR) and dimensions (DYDX) in
conjunction with window preclipping.
13.3.2.2 Alignment of Leading and Trailing Words in Rows
After clipping, the data transfer portion of the FI LL treats the array as a series
of L rows of M pixels. These M pixels are spread across N words in each row
of the destination array. Figure 13-4 illustrates a single row of a destination
array in memory. The FILL algorithm resolves rows into three portions:
1) The leading edge at the beginning of the row
2) The center N-2 words of the row
3) The trailing edge at the end of the row
Word Boundaries
I I
I I
..~-----+---- N words----+------tt~
I
:
I
I
,..---------------------_...... --...... I
:
I
I
:
I
.....-~------------------....,i---' I
:
I
II Leading +--11 Center N-2 Words ---+&11 Trailing II
I
Pixels I I
Plxel8 I
: : M Pixels : :
I I I I
Figure 13-4. Pixel Block Alignment in X
13-11
Instruction Timings - FILL Instructions
As Figure 13-4 shows, a row of N words includes one word each for the
leading and trailing parts of the transfer and N-2 words for the center portion.
The FILL always transfers the center portion of the row as a series of 16-bit
words. Thus, the alignment of the leading and trailing words in the row
characterize the alignment type of the array. Figure 13-5 illustrates the four
possible alignments (A, B, C, and D) of destination array rows within pixel
blocks in memory.
,~If---------N Worda----------tl~,
: :'--Word BoUndarl88~ :
;.'- - - - - - ,---------------------,_ _ _ _-if
AUgnment A I~1--Le-adlng--~14---c~;;;N-2-W~;;--~·I--Tr-al-lIn-g-...I!
ARgnment B
---------------------------
!------:-, -------------------....0:",-...
Leading ~ Center N-2 Worda ~ Tralling
Algnment C
,....---------------------------i
--~,---------------------.;-----...I!
Leading ~Center N-2 Worda ~ TralRng
AlIgnment 0
------------------------
....._'!'"",--------------------;_-..1
Leading ~ Center N-2 Words ---+: Trailing
,~ N Worda----------tr~ ,
Figure 13-5. Pixel Block Alignments
Word alignment is constant from row to row because DPTCH is constrained
to be a mUltiple of 16 for most FILls. If a FILL is only one pixel wide, and all
the rows are contained in single words in memory, DPTCH may be any value.
If DPTCH is not a multiple of 16, word alignment may vary between cases B,
C, and D. Average timing for this situation may be derived using alignment
C. Worst case timing for this situation may be derived using alignment D.
13.3.2.3 Row Length (Number of Words N per Row)
Row length is determined by a combination of the computed array pointer
value in DADDR, the clipped DX dimension, and the pixel size stored in the
PSIZE register. The data transfer algorithm breaks down into one of three
cases, short, medium, or long, according to the number of words N in a row.
These three cases include:
• Short case. The destination array row occupies only one word in me-
mory (N=1). In this case, only one write (or read-modify-write) opera-
tion is required to place the row into the destination array. Alignment
13-12
Instruction Timings - FILL Instructions
for the short case is either type A for exactly aligned arrays or type B, C,
or 0 for nonaligned arrays (which require a read-modify-write).
• Medium case. The destination row occupies two words in memory
(N=2). In this case, the row has no center portion and the array align-
ment is determined by the alignments of the first and last words in the
row.
• Long case. The destination row occupies all or part of at least three
words (N~3). This is the general case for array alignment discussions.
13.3.2.4 Transfer Direction in X
Transfer direction does not apply to FILLs. FILL transfers proceed a single
word of pixels at a time in the order of increasing X and increasing Y. This
corresponds to a transfer from left-to-right and top-to-bottom for the default
screen orientation.
13.3.2.5 Selected Graphics Operations (G)
Graphics operations such as plane masking, transparency, and pixel process-
ing influence FILL transfer timing because the destination pixels must be read
before they are replaced. However, the effects of these operations vary be-
cause they are performed by different portions of the TMS34010 hardware.
For instance, plane masking, transparency, and field insertion are all performed
by the TMS34010 memory controller; any combination of these operations
uses 2 machine states for each word written. Pixel processing, on the other
hand, is performed by the TMS34010 CPU, and requires 2, 4, 5, or 6 states
per word (independently of other operations). The minimum cycle time for
any graphics operation, then, is 2 machine states (one memory cycle) using
the pixel processing replace operation, with plane masking and transparency
disabled. Table 13-7 shows these values.
Table 13-7. Timing Values per Word for Graphics Operations (G)
Pixel Processing Operation
Other ADDS,SUB
Graphics Operation Replace Booleans MAX. or SUBS
orADD MIN
No plane masking or 2 4 5 6
transparency=~
Read-modify-write, plane 4 6 7 8
masking, or transparency
13-13
Instruction Timings - FILL Instructions
13.3.2.6 Alignment/Graphics Adjustment
An additional adjustment may be necessary when plane masking or transpar-
ency are enabled and the alignment type is 8, C, or O. As the second line of
Table 13-7 shows, if a particular word in a destination row has already been
read as part of a read-modify-write operation, no additional states are re-
quired to perform plane masking or transparency for that word. Since the
alignment types with misaligned edges (8, C, and D) already assume a RMW
(read-modify-write) on their respective edges, the effect of plane masking or
transparency can be ignored for these edges. That is, after you have calculated
the timing using the proper value for the graphics operation, you can subtract
2 states (cases 8 and C) or 4 states (case D) per row from the transfer timings
for the respective alignment cases. Case A requires no adjustment.
13.3.3 FILL Timing Examples
To determine the timing for a FILL instruction, add the FILL setup value to the
FILL transfer value and subtract the alignment adjustment:
FILL time = FILL setup time + FILL transfer time - alignment adjustment
FILL setup timings, transfer timings, and the effects of graphics operations are
listed in the following tables:
Table Page
13-5 FILL Setup Time ................................................................................. 13-10
13-6 FILL Transfer Timingt ........................................................................ 13-11
13-7 Timing Values per Word for Graphics Operations (G) .................. 13-13
The following three examples illustrate timing for a Fill XV. The setup and
transfer timings for these examples are the same, except each uses a different
graphics operation. Figure 13-7 illustrates the destination array and window
used in these examples, as defined by the implied operands in Figure 13-6.
Note that the shaded portion is the area of intersection.
****************************************************
* Implied operand setup for FILL examples (assume *
* that the B register names and I/O register names *
* are equated with the proper registers) *
****************************************************
MOVI 004400E4h, DADDR X=228, Y=68
MOVI 800h, DPTCH X extent = 512 pixels
(at 4 bits per pixel)
CLR OFFSET
MOVI 004900EBh, WSTART X=235, Y=73
MOVI 005F0140h, WEND X=320, Y=95
MOVI 0014003Ch, DYDX DX=60, DY=20
MOVI 4h, AO
MOVE AO, @PSIZE Pixel size = 4 bits
MOVI 14h, AO
MOVE AO, @CONVDP (LMO DPTCH)
MOVI OCh, AO
MOVE AO, @CONTROL W=3, T=O, PPOP=O
CLR AO
MOVE AO, @PMASK Disable plane masking
Figure 13-6. Implied Operand Setup for Fill Example
13-14
Instruction Timings - Fill Instructions
Even word Even word
boundary boundary
~I
N= 63 =13.62=14
• pixels per word
WSTART
-~==~~~~~~_d------ (320,73)
20
I ~ ____~~I.w.w~~~~w.w.~
I
I
l .("WEND
(235,95) .-----------------------------. (320,46)
Figure 13-7. FILL XV Timing Example
Follow these steps to determine the number of machine states consumed by
this example:
1) Determine the setup time; refer to Table 13-5 on page 13-10.
Setup time comprehends the time required for windowing operations.
These examples use window preclipping (W bits=3); this option re-
quires the starting corner to be adjusted. As Table 13-5 (page 13-10)
shows, the setup time for a FI LL XY with a starting corner adjust is 16
machine states.
2) Determine the transfer time; refer to Table 13-6 on page 13-11.
Transfer time is affected by the number of words per row, line length,
and graphics operations.
a) Number of words per row: As Figure 13-7 shows, adjusting the
array by clipping it to the window dimensions produc"es a new Y
dimension, so L (the number of rows in the adjusted array) equals
15.
b) Line length: Adjusting the array to fit the window also produces
a new X dimension of 53 pixels. The number of pixels divided by
the pixel size yields the number of words N per row; 53 divided by
4 produces 13.25, so N=14. Since N is greater than 3, this exam-
ple conforms to the long case. The trailing edge is word aligned
but the leading edge is not, so the alignment type is C.
As Table 13-6 shows, the transfer time for a FI LL XY with these char-
acteristics is (3+NG)L + 2. The only variable in the following three
examples is G, which represents the selected graphics operations.
13-15
Instruction Timings - FILL Instructions
Example 13-1. Replace, No Transparency, No Plane Masking
The implied operand setup in Figure 13-6 selects the following graphics
options:
• Pixel processing replace operation (PPOP=O),
• No transparency, and
• No plane masking.
According to Table 13-7 (page 13-13), variable G = 2. The FILL timing
for this instruction is determined as follows:
FILL time = FILL setup time + FILL transfer time
= Adjust pointer + [3+(NxG)]L + 2
= 16 + [(3 + (14x2)]15 + 2
= 483 states
The FILL writes 795 pixels in these 483 states. (The portion of the array
lying within the window contains 795 pixels.)
Example 13-2. MAX, No Transparency, No Plane Masking
Select the pixel processing MAX option (be sure to retain the values of the
W bits and the T bit, which are also in the CONTROL register):
MOVI 50COh, AO
MOVE AO, @CONTROL ; MAX, W=3, T=O
These instructions, in combination with the implied operand setup in Figure
13-6, select the following graphics options:
• Pixel processing MAX operation (PPOP=14h),
• No transparency, and
• No plane masking.
According to Table 13-7, variable G = 5. The FILL timing is now calculated
as:
FILL time = FILL setup time + FILL transfer time
= Adjust pointer + [3+(Nx G)]L + 2
=16 + [3+(5x14)]15+2
= 1,113 states
This FI LL example consumes 1 ,113 machine states.
13-16
Instruction Timings - FILL Instructions
Example 13-3. XNOR with Transparency and Plane Masking
Select the pixel processing XNOR operation and enable transparency and
plane masking:
MOVI 14EDh, AD
MOVE AD, @CONTROL XNOR, W=3, T=l
MOVI llllh, AD
MOVE AD, @PMASK Use a plane mask
These instructions, in combination with the implied operand setup in Figure
13-6, select the following graphics options:
• Pixel processing XNOR operation (PPOP=05h),
• No transparency, and
• No plane masking.
According to Table 13-7, variable G :::: 6.
If plane masking or transparency is enabled, you must consider the array
alignment in the timing. This example conforms to alignment type C (as
shown in Figure 13-5 on page 13-12), which incurs a read-modify-write
at the leading edge of each row. The extra read in the RMW can be used
by the plane masking or transparency hardware, so an alignment/graphics
adjustment is necessary. The adjustment negates the effect of the extra read
cycles in each row that are attributed to the graphics operations. For this
example, the amount subtracted is 2L (the number of machine states for a
read cycle times the number of rows). The FILL timing is now calculated
as:
FI LL time = FI LL setup time + FI LL transfer time - adjustment
= Adjust pointer + [3+(NxG)]L+2 - 2L
= 16 + [3 + (6x14)]15 + 2 - (2x15)
= 1 ,293 states
This FI LL example consumes 1,293 machine states.
13.3.4 Interrupt Effects on FILL Timing
A FILL instruction can be interrupted on a word boundary during the transfer
portion of the FI LL algorithm. It can also be interrupted at the end of each
row. The context of the FILL is saved in reserved registers, and the PBX bit
is set in the copy of the status register that is pushed onto the stack. The worst
case latency caused by an interrupt is 20 machine states for the interrupt to
be recognized. The time for the context switch must be added to this. See
Section 8.5.1, Interrupt Latency (page 8-6) for context switch information.
13-17
Instruction Timings - PIXBLT Instructions
13.4 PIXBLT Instructions
PIXBLT instructions covered in this section include:
• PIXBLT L,L
• PIXBLT XY,L
• PIXBLT L,XY
• PIXBLT XY,XY
(PIXBLT B,L and PIXBLT B,XY are discussed in Section 13.5.)
The total PIXBLT instruction timing is obtained by adding a setup time to a
transfer time:
PIXBLT time = PIXBL T setup time + PIXBL T transfer time
• The setup sequence executes an initialization sequence, performing
any necessary setup operations and translations. (This includes XY-
to-linear conversion and window preclipping.) The result of the setup
includes the dimensions of the source array.
• The transfer sequence performs the actual data transfer from the
source array to the destination array.
PIXBLT setup and transfer timings are in the following tables:
Table Page
13-8 PIXBLT Setup Time ............................................................................ 13-18
13-9 PIXBLT Transfer Timingt ................................................................... 13-20
13.4.1 PIXBLT Setup Time
Table 13-8 lists PIXBLT setup times. Setup time is the overhead incurred by
the PIXBLT instructions in performing initialization, XY conversions, window
options, and corner adjust. Setup time is affected by both the window and
corner adjust operations. The effects of these operations are described in the
list that follows Table 13-8.
Table 13-8. PIXBLT Setup Time
Window Operation Corner Adjust
Array Start Dimens Adjust PBH=1 PBH=O PBH=1
Instruction W=O Fits Adjust Adjust Both Miss Hit PBV=O PBV=1 PBV=1
PIXBLT L, L 7 - - - - - - - - -
PIXBLT XV, L 9 - - - - - - +1 +2 +4
PIXBLT L, XV 9 12 19 15 23 - - +1 +2 +4
PIXBLT XV, XV 12 15 22 18 26 - - +1 +2 +4
For example, consider a PIXBLT XY,XY instruction with preclipping that re-
quires hoth the starting and ending array corners to be adjusted (PBH =1 and
PBV=O). The setup timing for this example would be 26+1 =27 states.
13-18
Instruction Timings - PIXBlT Instructions
13.4.1.1 Window Operations
Window operations are performed before the PIXBLT transfer begins. Win-
dow options that affect PIXBLT setup timing include:
• No window checking (W=O)
• A window clip that requires no change (array fits)
• A window clip that affects the starting pointer (start adjust)
• A window clip that affects the array transfer dimensions (dimension
adjust)
• A window clip that affects both the starting and ending pointers (adjust
both)
• A window miss that requests an interrupt
• A window hit
13.4.1.2 Corner Adjust (PBH and PBV)
The TMS3401 0 may need to adjust the starting corner of the source and des-
tination arrays for the PIXBLT L,XY, PIXBLT XY,L, and PIXBLT XY,XY in-
structions. The default starting corner is the upper left corner of the array. This
can be altered by changing the values of the PBH and PBV (PIXBLT hori-
zontal and vertical) bits. Possible corner adjustments (with default origin
ORG=O) include:
• No corner adjust (PBH=O, PBV=O)
• Adjust to upper right corner (PBH=1, PBV=O)
• Adjust to lower left corner (PBH=O, PBV=1)
• Adjust to lower right corner (PBH=1, PBV=1)
The TMS34010 adjusts corners before PIXBLT execution begins. For each
combination of PBH and PBV, the TMS3401 0 adjusts the source and desti-
nation starting address pointers to point to the appropriate corner of the arrays.
This assures that the same pixel block is moved, despite the difference in X and
Y transfer directions.
The original source and destination pointers must be supplied th-rough soft-
ware. The pointers should indicate the least significant pixel in the array, ex-
cept for PIXBLT L,L. For this instruction, the PBH and PBV bits affect only
the direction of the move; the TMS3401 0 does not adjust the starting corner.
13-19
Instruction Timings - PIXBLT Instructions
13.4.2 PIXBLT Transfer Timing
Table 13-9 lists PIXBLT transfer timings. Transfer timing is the time required
(in addition to the setup time) to execute the actual data transfer to memory.
Transfer timing is affected by several factors, including the number of rows in
the adjusted array (L), the number of words affected per row (N), graphics
operations (G), and four possible destination array alignments (A, B, C, and
D). These factors are described in the list that follows the table.
Table 13-9. PIXBlT Transfer Timingt
PBH= 0
Row Lengths Destination Array Alignment
and Alignment A B C 0
Short (N=1)
O>S (G+4)L + 5 (G+6)L + 3 (G+6)L + 3 (G+6)L + 3
O<S (G+4)L + 5 (G+6)L + 3 (G+6)L + 3 (G+6)L + 3
Medium (N=2
O>S [2+(4+2G)]L + 5 [4+(4+2G)]L + 3 [4+(4+2G)]L + 5 [6+(4+2G)]L + 3
O<S [4+(4+2G)]L + 4 [6+(4+2G)]L + 2 [6+(4+2G)]L + 4 [8+(4+2G)]L + 2
Long (N.::,3)
O>S [(2+G)N]L + 5 [2+(2+G)N]L + 3 [2+(2+G)N]L + 5 [2+(4+G)N]L + 3
O<S [2+(2G)N]L + 4 [4+(2G)N]L + 2 [4+(2G)N]L + 4 [6+(2G)N]L + 2
PBH= 1
Row Lengths Destination Array Alignment
and Alignment A B C 0
Short (N=1)
O>S (G+3)L + 8 (G+4)L + 7 (G+4)L + 7 (G+4)L + 7
O<S (G+3)L + 8 (G+4)L + 7 (G+4)L + 7 (G+4)L + 7
Medium (N=2)
O>S [2+(4+2G)]L + 4 [4+(4+2G)]L + 3 [4+(4+2G)]L + 4 [6+(4+2G)]L + 3
O"<S [4+(4+2G)]L + 5 [5+(4+2G)]L + 4 [6+(4+2G)]L + 5 [7+(4+2G)]L + 4
Long (N.::,3)
O>S [1 +(2+G)N]L + 4 [3+(2+G)N]L + 3 [3+(2+G)N]L + 4 [5+(2+G)N]L + 3
O<S [3+(2+G)N]L + 5 [4+(2+G)N]L + 4 [5+(2+G)N]L + 5 [6+(2+G)N]L + 4
t Subtract any alignment/graphics adjustment from these values
Key:
L Number of rows in the array (see page 13-20)
N Number of destination words per row (see page 13-22)
G Value dependent on selected graphics operation (see Table 13-10 on page 13-24)
O>S First destination to source alignment case (see page 13-22)
O<S Second destination to source alignment case (see page 13-22)
13-20
Instruction Timings - PIXBlT Instructions
13.4.2.1 Number of Rows in the Array (L)
The working dimensions (L rows by N words) for the block transfer are de-
termined by the original destination pointer (DADDR) and dimensions
(DYDX) in conjunction with window preclipping. L represents the number
of rows in the clipped array.
13.4.2.2 Alignment of Leading and Trailing Words in Rows
After clipping, the data transfer portion of the PIXBLT treats the array as a se-
ries of L rows of M pixels. These M pixels are spread across N words in each
row of the destination array. Nand L affect the transfer timing. Alignment
does not vary from row to row because DPTCH is constrained to be a power
of two.
Figure 13-8 illustrates a single row of a destination array in memory. The
PIXBLT algorithm resolves rows into three portions:
1) The leading edge at the beginning of a row
2) The center N-2 words of the row
3) The trailing edge at the end of the row
Word Boundarlaa
I I
I I
~If------lr------ N Words ----+-----......~
r---..:....--------------------:....._.
'---"!""I
I
--------------------1-......
I
Leading
Pixels r - Center N-2 Words ----+:
I
I
I
I
Trailing
Pixels
: M Pixels :
I I
Figure 13-8. Pixel Block Alignment in X
As Figure 13-8 shows, a row of N words includes one word each for the
leading and trailing parts of the transfer and N-2 words for the center portion.
The PIXBLT always transfers the center portion of the row as a series of 16-bit
words. Thus, the alignment of the leading and trailing portions characterize
the alignment type of the array. Figure 13-9 illustrates the four possible
alignments (A, B, C, and D) of a destination array.
13-21
Instruction Timings - PIXBLT Instructions
..~---------N Word8---------tl~
1
I:i-_____I+--Word
____________________
Boundarlea---'+I_____--i
AlIgnment A
I~__~__ ----------------~--~
1 1 1
: Leading :t--Center N-2 Word8~ Trailing
AlIgnment B
---------------------------..
~-----:"I--------------------""!'I-
Leading : t - - Center N-2 Word8 ---+: Trailing
AlIgnment C
,....---------------------------;
"--'!""I --------------------,------I!
Leading ~ Center N-2 Words ----+: TraJUng
AlIgnment 0
r------------------------_
" - - ' ! " " I- - - - - - - - - - - - - - - - - - - - , . , - - - '
Leading ~ Center N-2 Words ----+: Trailing
~
1
N Word8---------tl~
1
Figure 13-9. Pixel Block Alignments
73.4.2.3 Row Length (Number of Words N per Row)
Row length is determined by a combination of the computed array pointer
value in DADDR, the clipped DX dimension, and the pixel size stored in the
PSIZE register. The data transfer algorithm breaks down into one of three
cases, short, medium, or long, according to the number of words N in a row.
These three cases include:
• Short case. The destination array row occupies only one word in me-
mory (N=1). In this case, only one write (or read-modify-write) opera-
tion is required to place the row into the destination array. Alignment
for the short case is either type A for exactly aligned arrays or type B, C,
or D for nonaligned arrays (which require a read-modify-write).
• Medium case. The destination row occupies two words in memory
(N=2). In this case, there is no center portion to the row and the array
alignment is determined by the alignments of the first and last words in
the row.
• Long case. The destination row occupies all or part of at least three
words (N~3). This is the general case for array alignment discussions.
13-22
Instruction Timings - PIXBLT Instructions
73.4.2.4 Relative Alignment of Source Rows to Destination Rows
The alignment of the leading pixels in a source row with respect to a destina-
tion row influences PIXBLT transfer timing. This alignment determines
whether one or two words are required from the source array to fully write the
first word of the destination array. This initial condition can be divided into
two cases:
O~S The four LSBs of the destination address are greater than the four
LSBs of the source address. This implies that the amount of data
available from the first word of the source array exceeds the amount
needed to write to the first word of the destination array. The write to
the destination array can proceed immediately.
O<S The four LSBs of the destination address are less than the four LSBs
of the source address. This implies that the amount of data to be
written to the first word of the destination array exceeds the amount
available from the first word of the source array. Another word must
be read from the source array.
Alignment Case 1 : 0 ). S
, . . -_ _ _ _ _1 _______________ _
Source Array
......
----~--------------
,..--""-------------------
"'-_~DestI--n~~~~~"'!-- _____ _
j4-- Word Boundarles--":
1 !
Alignment Case 2 : 0 < S
,..---11 __________________ _
Source Array
......_------------------
,..----_....._--------------
Destination Array
j4-- Word Boundaries--+!
Increasing bit addreaa
Figure 13-10. Source to Destination Alignments
13-23
Instruction Timings - PIXBlT Instructions
13.4.2.5 Transfer Direction in X (PBH)
PIXBLT transfers proceed a word of data at a time in a consistent direction in
X and Y. The default direction is from the smallest word address to the largest,
corresponding to left-to-right and top-to-bottom for the default screen orien-
tation. The values of the PBH and PBV bits determine the transfer direction
in X and Y.
For the four regular PIXBLTs (without expand), PBH determines the order in
which words are written on each row of the destination array:
PBH=O: Words within rows are written in the order of increasing addresses.
PBH=1: Words are written in the order of decreasing addresses. The value
of PBH influences the per-row transfer timings of these PIXBLTs.
The sense of the PBV bit determines the order in which rows are transferred
to the destination array.
PBV=O: Rows are transferred in the order of increasing addresses.
PBV=1: Rows are transferred in the order of decreasing addresses.
This value affects the setup timing, but not the transfer timing.
13.4.2.6 Selected Graphics Operations (G)
Graphics operations such as plane masking, transparency, and pixel process-
ing influence PIXBLT transfer timing because the destination pixels must be
read before they are replaced. However, the effects of these operations vary
because they are performed by different portions of the TMS3401 0 hardware.
For instance, plane masking, transparency, and field insertion are all performed
by the TMS34010 memory controller hardware; any combination of these
operations uses 2 machine states for each word written. Pixel processing, on
the other hand, is performed by the TMS3401 0 CPU, and requires 2, 4, 5, or
6 states per word independent, of other operations. The minimum time for any
graphics operation, then, is 2 machine states(one memory cycle) using the
rep/ace operation with plane masking and transparency disabled. These values
are shown in Table 13-10.
Table 13-10. Timing Values per Word for Graphics Operations (G)
Pixel Processing Operation
Other ADDS,SUB
Graphics Operation Replace Booleans MAX or SUBS
or ADO MIN
No plane masking or 2 4 5 6
transparency
Read-modify-write. plane 4 6 7 8
masking. or transparency
13-24
Instruction Timings - PIXBLT Instructions
13.4.2.7 Alignment/Graphics Adjustment
An additional adjustment may be necessary when plane masking or transpar-
ency are enabled and the alignment type is 8, C, or D. As the second line of
Table 13-10 shows, if a particular word in a destination row has already been
read as part of a read-modify-write operation, no additional states are re-
quired to perform plane masking or transparency for that word. Since the
alignment types with misaligned edges (8, C, and D) already assume a RMW
(read-modify-write) on their respective edges, the effect of plane masking or
transparency can be ignored for these edges. That is, after you have computed
the timing using the proper value for the graphics operation, you can subtract
2 states (case 8 and C) or 4 states (case D) per row from the row timings for
the respective alignment cases. Case A requires no adjustment.
13-25
Instruction Timings - PIXBLT Instructions
13.4.3 PIXBLT Timing Examples
To determine PIXBLT timing, add the PIXBLT setup value to the PIXBLT
transfer value and subtract the alignment adjustment:
PIXBLT time = PIXBLT setup time + PIXBLT transfer time
- alignment adjustment
PIXBLT setup timings, transfer timings, and the effects of graphics operations
are in the following tables:
Table Page
13-8 PIXBLT Setup Time ........................................................................... 13-18
13-9 PIXBLT Transfer Timingt .................................................................. 13-20
13-10 Timing Values per Word for Graphics Operations (G) ................. 13-24
The following three examples illustrate timing for a PIXB LT XV, l. The setup
and transfer timings for these examples are the same, except each uses a dif-
ferent graphics operation. Figure 13-12 illustrates the destination array and
window used in these examples, as defined by the implied operands in Figure
13-11. The shaded portion of Figure 13-12 is the destination array.
***************************************************
* Implied operand setup for PIXBLT XY, L examples *
* (assume that the B register and I/O register *
* names are equated with the proper registers) *
***************************************************
MOVI 003AOOE6h, SADDR X=230, Y= 58
MOVI 800h, SPTCH X extent = 512 pixels
(at 4 bits per pixel)
MOVI 000030E8, DADDR linear address
MOVI 800h, DPTCH X extent = 512 pixels
MOVI 00040000, OFFSET
CLR WSTART ignored
CLR WEND ignored
MOVI 000F0036, DYDX DY=15, DX=54
MOVI 4h, AO
MOVE AO, @PSIZE Pixel size 4
MOVI 14h, AO
MOVE AO, CONVSP
MOVE AO, CONVDP ignored
CLR AO
MOVI AO, PMASK Disable plane masking
MOVI 0300h, AO
MOVE AO, @CONTROL PBH=l, PBV=l
Figure 13-11. Implied Operand Setup for PIXBLTTiming Examples
13-26
Instruction Timings - PIXBlT Instructions
DADOR
N= It plXel8s:ar word =13.6:::::14
Adjusted destination
~~~~~~~~~~~~~~~ starting comer
Even word
SADDR
J1~) boundary
.t-------64 -------+
15
1 ......_ _ _ _ _ _ _ _ _ _ _ _ _.... Adjusted source
starting comer
Figure 13-12. PIXBlT XV,l Timing Example
To calculate the number of machine steps consumed by these PIXBLT exam-
ples, follow these steps:
1) Determine the setup time; refer to Table 13-8 (page 13-18). Setup
timing comprehends windowing and corner,.adjust operations.
a) Windowing: Windowing is not enabled for this example (W=O, 9
states).
b) Corner adjust: PBH=1 and PBV=1, so the starting corner must
be adjusted in both the X and Y dimensions (+4 states).
As Table 13-8 shows, the setup time for a PIXBLT XY,L with these op-
erations is 9 + 4 machine states.
2) Determine the transfer time; refer to Table 13-9 (page 13-20).
Transfer time comprehends the direction of the move, array and row
alignments, and line lengths.
• PBH=1.
• Number of rows in the array: The Y dimension is 15, so L =15.
• Number of words in a row: The X dimension is 54 pixels, and the
pixel size is four; 54 divided by 4 produces 13.5, so the number of
words per row, N, = 14.
• Row length and alignment: N is greater than 3, so this example
conforms to the long case.
13-27
Instruction Timings - PIXBlT Instructions
• The four LSBs of DADDR are greater than the four LSBs of
SADDR (D~S).
• Destination array alignment: The trailing edge is word aligned but
the leading edge is not, so the alignment type is C.
As Table 13-9 shows, the transfer time for this PIXBLT instruction is
[5+(2+G)N]L + 4. The only variable in the following three examples
is G, which represents the selected graphics operations.
Example 13-4. Replace, No Transparency, No Plane Masking
The implied operand setup in Figure 13-11 selects the following graphics
options:
• Pixel processing replace operation (PPOP=O),
• No transparency, and
• No plane masking.
According to Table 13-10 on page 13-24, variable G = 2. The total ma-
chine states required for this instruction are:
PIXBLT time = PIXBLT setup time + PIXBLT transfer time
=9+4 + [5+ (2+G)N]L + 4
= 13 + (5+4x14)x15+4
= 932 states
The instruction in this example consumes 932 machine states.
13-28
Instruction Timings - PIXBlT Instructions
Example 13-5. MAX Option, No Transparency, No Plane Masking
Select the pixel processing MAX option (be sure to retain the values of the
W bits and the T bit, which are also in the CONTROL register):
MOVI 50COh, AO
MOVE AO, @CONTROL i MAX, W=3, T=O
These instructions, in combination with the implied operand setup in Figure
13-11, select the following graphics options:
• Pixel processing MAX operation (PPOP=14h),
• No transparency, and
• No plane masking.
According to Table 13-10, variable G = 5. Thus, the timing equation be-
comes:
PIXBLT time = PIXBLT setup time + PIXBLT transfer time
= 9 +4 + [5+(2+G)N]L + 4
= 13 + (5 + 7x14)x15 + 4
= 1562 states
The instruction in this example consumes 1,562 machine states.
13-29
Instruction Timings - PIXBlT Instructions
Example 13-6. XNOR with Transparency and Plane Masking
Select the pixel processing XNOR operation and enable transparency and
plane masking:
MOVI 14EDh, AD
MOVE AD, @CONTROL XNOR, W=3, T=l
MOVI llllh, AD
MOVE AD, @PMASK Use a plane mask
These instructions, in combination with the implied operand setup in Figure
13-11, select the following graphics options:
• Pixel processing XNOR operation (PPOP=05h),
• No transparency, and
• No plane masking.
According to Table 13-10, variable G = 6.
If plane masking or transparency is enabled, you must consider the array
alignment in the timing. Alignment type C incurs a read-modify-write at the
leading edge of each row. The extra read included in the RMW can be used
by the plane masking or transparency hardware, so an alignment/graphics
adjustment is necessary. The adjustment negates the effect of the extra read
cycles in each row that are attributed to the graphics operations. For this
example, the amount subtracted is 2L (the number of machine states for a
read cycle times the number of rows). The timing is now calculated as:
PIXBLT time = PIXBLT setup time+ PIXBLT transfer time - adjustment
= 9 + 4 + [5+(2+G)N]L + 4 - 2L
= 13 + (5 + 8x14)x15 + 4 - (2x15)
= 1772 states
The instruction in this example consumes 1,772 machine states.
13.4.4 The Effect of Interrupts on PIXBlT Instructions
The PIXBLT instruction may be interrupted on a destination word boundary
during the transfer portion of the algorithm. It may also be interrupted at the
end of any row in the array. The context of the PIXBLT is saved in reserved
registers. The PBX bit is set in the copy of the ST register that is pushed to
the stack. The worst case latency caused by an interrupt is 20 machine states
for the interrupt to be recognized. The time for the context switch must be
added to this; see Section 8.5.1, Interrupt Latency (page 8-6) for context
switch timing.
13-30
Instruction Timings - PIXBLT Expand Instructions
13.5 PIXBl..T Expand Instructions
PIXBLT expand instructions include:
• PIXBLT B,L
• PIXBLT B,XY
To determine PIXBLT expand instruction timing, add a setup time to a transfer
time:
PIXBL T time = PIXBL T setup time + PIXBL T transfer time
• The setup f,equence executes an initialization sequence, performing
any necessary setup operations and translations. (This includes XY-
to-linear conversion and window preclipping.) The result of the setup
includes the dimensions of the source array.
• The transfer sequence performs the actual data transfer from the
source array to the destination array.
PIXBLT setup and transfer timings are in the following tables:
Table Page
13-11 PIXB LT Expand Setup Time ............................................................. 13-32
13-12 PIXBLT Expand Transfer Timingt .................................................... 13-32
13.5.1 PIXBLT Setup Time
PIXBLT setup time is the overhead incurred by the PIXBLT instructions from
performing initialization, XY conversions, and window operations.
Window operations are performed before the PIXBLT transfer begins. Win-
dow options that affect PIXBLT setup timing include:
• No window checking (W=O)
• A window clip that requires no change (array fits)
• A window clip that affects the starting pointer (adjust start)
• A window clip that affects the array transfer dimensions (dimension
adjust)
• A window clip that affects both the starting and ending pointers (adjust
both)
• A window miss that requests an interrupt
• A window hit
Table 13-11 shows the effect of these options on the PIXBLT setup time.
Corner adjust operations have no effect on PIXBLT setup timing.
13-31
Instruction Timings - PIXBlT Expand Instructions
Table 13-11. PIXBlT Expand Setup Time
Window Operation Corner Adjust
Array Start Dimens Adjust PBH=1 PBH=O PBH=1
Instruction W=O Fits Adjust Adjust Both Miss Hit PBV=O PBV=1 PBV=1
PIXBLT B, L 4 - - - - - - - - -
PIXBLT B,XV 6 9 17 12 21 - - - - -
For example, a PIXBlT B,XY with the preclipping option requiring an adjust-
ment to the end corner of the array requires 12 states of setup time.
13.5.2 PIXBlT Transfer Timing
Table 13-12 shows transfer timing for PIXBlT expand instructions. Transfer
timing is the time required (in addition to the setup time) to execute the actual
data transfer to memory. Transfer timing is affected by several factors, in-
eluding the number of rows in the adjusted array (L), the number of words
affected per row (N), graphics operations (G), the four possible destination
array alignments (A, B, C, and D), and the arrangement of words in source
rows. These factors are described in the ~ist that follows the table.
Table 13-12. PIXBlT Expand Transfer Timingt
Destination Alignment Transfer Timing
Short case (3+2R+G)L + 3
Medium case
Alignment A or C (3+2R+NG)L + 3
Alignment B or 0 (5+2R+NG)L + 3
Long case
Alignment A [(3+2R+2GP)S + 2V + NG]L+ 3
Alignment 0 [(8+2R+2GP)S + 2V + YG + 8JL + 3
t Subtract any alignment/graphics adjustment from these values
Key:
L Number of rows in the array (below)
N Number of destination words per row (see page 13-33)
R Number of source words involved in set (see page 13-33)
S Number of 32-bit sets in long source rows (DX/32), except for the case
of an even number of sets; in this case, S is the number of 32-bit sets
minus 1 (DX/32 - 1) (see page 13-35)
V Number of source words involved in reading source pixels at end of
row after all the complete 32-bit sets have been transferred P Current
pixel size
G Value dependent on selected graphics operations (see Table 13-13)
Y Number of remaining destination words affected in a given row after
S 32-bit sets are written
13-32
Instruction Timings - PIXBLT Expand Instructions
13.5.2.1 Number of Rows in the Array (L)
The working dimensions (L rows x N words) for the block transfer are deter-
mined by the original destination pointer (DADDR) and dimensions (DYDX)
in conjunction with window preclipping. The symbol L is used to represent
the number of rows in the clipped destination array.
13.5.2.2 Alignment of Leading and Trailing words in Rows
After clipping, the data transfer portion of the PIXBLT treats the array as a se-
ries of L rows of M pixels. These R pixels are spread across N words in each
row of the destination array. Nand L affect the transfer timing. This alignment
does not vary from row to row because DPTCH is constrained to be a multiple
of 16 for binary PIXBLTs.
Figure 13-13 illustrates a single row of a destination array in memory. The
PIXBLT algorithm resolves rows into three portions:
1) The leading edge at the beginning of the row
2) The center N-2 words of the row
3) The trailing edge at the end of the row
Word Boundaries
I I
I I
~
:....- - - - - + - - - - N W o r d s - - - - r - - - - -......
,....----------------------------
~-"':""I- - - - - - - - - - - - - - - - - - - - . - -
I I
Leading
Pixels ~center N-2 Words-+! Trailing
PIXels
I I
: M PIXels :
I I
Figure 13-13. Pixel Block Alignment in X
As Figure 13-13 shows, a row of N words includes one word each for the
leading and trailing parts of the transfer and N-2 words for the center portion.
PIXBLT expand instructions always transfer the center portion of the row as a
series of 16 bit words, and are not affected by the alignment of the leading
word. Thus, the alignment of the trailing words in the row characterize the
alignment type for the row. Figure 13-14 illustrates the four possible align-
ments (A, B, C, and D) of a row in the destination array.
13-33
Instruction Timings - PIXBLT Expand Instructions
1....- - - - - - - - - N Words---------t..:
: : . - -Word Boundartea---':
;.i ----~I ---------------------1----""""'i
~1--Lea-dlng--":""i.---c;t;;N:2-W;;----:t:~-Tr-allln-g-...I!
AIIgnmentB
...--------------------------.....
! - - - - - " : " " I------------------ 1
Leading :t-- Center N-2 Words--+: Trailing
AlIgnment C
,....---------------------------i
--':"'"1- - - - - - - - - - - - - - - - - - -......
Leading :t-- Center N-2 Words---+:
,-----...I!
Trailing
Alignment 0
,....-----------------------
.....-'!'"'I- - - - - - - - - - - - - - - - - - - . . . . , . , - -
Leading :t-- Center N-2 Words ---+: Trailing
~
1
N W o r d s - - - - - - - - - t . . :1
Figure 13-14. Pixel Block Row Alignments
13.5.2.3 Row Length (N Words per Row)
Row length is determined by a combination of the computed array pointer
value in OAODR, the clipped OX dimension, and the pixel size stored in the
PSIZE register. The data transfer algorithm breaks down into one of three
cases, short, medium, or long, according to the number of words N in a row.
These three cases include:
Short case. A row of source array pixels is contained in 16 bits or less
and the expanded data involves only one word of the destination array
per row (N=1). Alignment does not affect the short case.
Medium case. A row of source array pixels is contained in 32 bits or
less but the expanded data involves more than one word of the destina-
tion array per row (N)1). In this case, the array alignment is determined
by the alignments of the last word in the row. Thus, alignments A,C and
8,0 have equal transfer timings.
Long case. A row of source array pixels is contained in more than 32
bits. The expanded data involves multiple words in the destination array
row. In this case, the array alignment is determined by the alignments
of the last word in the row. Thus, alignments A and 8 and alignments
C and 0 have equal transfer timings.
13-34
Instruction Timings - PIXBLT Expand Instructions
Note that the timings for the short and medium row lengths are not affected
by the alignment of the first word on each row of the destination array. That
is, the destination array row transfer can start with either a write or a read-
modify-write. The long case is treated as a series of 32-pixel medium cases
followed by a short case (if necessary) at the end of each row. Each 32-pixel
set is expanded and written to the destination in a serial fashion, without op-
timizing for beginning and ending alignments. Thus, the timing for the long
case becomes a product of the number of 32-pixel sets (S) and the timing for
each set, plus the timing for expanding any remaining segment of the source
array (less than or equal to 32 bits) that is left in the row. Note that the re-
maining segment of the source array may have an alignment type (B or C) that
is different from the preceding 32-bit sets.
13.5.2.4 Arrangement of Source Rows
As discussed in the Row Length section, the number of bits in a row of the
source array affects the time required to perform the PIXBLT transfer algorithm.
The short and medium cases have explicit timings based on the number of
words read from the source row, R. Note that the timings for the short and
medium row lengths are not affected by the alignment of the last word on each
row of the destination array. That is, the destination array row transfer can
either end with a write or a read-modify-write.
The long case is treated as a series of 32-pixel segments. Each 32-pixel set
is expanded and written to the destination in a serial fashion without opti-
mizing for beginning and ending alignments for the source or destination. The
final portion of the transfer may be up to a 32-pixel "partial" segment. Thus,
the timing for the long case becomes a product of the timing for each set and
the number of 32-pixel sets (S), plus the timing for expanding any remaining
segment of the source array (up to 32 bits). Note that the alignment of the
remaining segment of the source array is determined by the original (clipped)
source array alignment.
The PIX B LT does not attempt to optimize read operations from the source ar-
ray; therefore, depending on the alignment of the source array, either two or
three words may need to be read in order to obtain a 32-bit set of source pixels
for expansion. This value, R, is the number of source words involved in a
32-bit set of source pixels and may be either two or three. The timings are
affected by R as wells as the number of such complete 32-bit sets S in a
source row.
The bits remaining after all of the complete 32-bit sets on a row have been
moved are transferred. Depending on the number of remaining bits and the
alignment of the source array, either one, two, or three words may need to be
read in order to obtain the remaining set of source pixels for expansion. This
value, V, is the number of of source words read to obtain the final segment
while Y is is the number of destination words involved for this fragment.
13-35
Instruction Timings - PIXBl T Expand Instructions
13.5.2.5 Transfer Direction in X (PBH Bit)
These PIXBLT instructions proceed a single word of pixels at a time in the di-
rection of increasing X and increasing Y. This corresponds to left-to-right and
top-to-bottom for the default screen orientation. Setting the PBH and PBV
bits has no effect.
13.5.2.6 Selected Graphics Options (G)
Graphics operations such as plane masking, transparency, and pixel process-
ing influence PIXBLT transfer timing because the destination pixels must be
read before they are replaced. However, the effects of these operations are
performed by different parts of the TMS3401 0 hardware. For instance, plane
masking, transparency, and field insertion are all performed by the TMS3401 0
memory controller hardware; any combination of these operations uses 2 ma-
chine states for each word written. Pixel processing, on the other hand, is
performed by the TMS3401 0 CPU, and requires 2, 4, 5, or 6 states per word
independent of other operations. The minimum time for any graphics opera-
tion, then, is 2 machine states (one memory cycle) using the replace oper-
ation with plane masking and transparency disabled. These values are shown
in Table 13-13.
Table 13-13. Timing Values per Word for Graphics Operations (G)
Pixel Processing Operation
Other ADDS,SUB
Graphics Operation Replace Booleans MAX or SUBS
or ADD MIN
No plane masking or 2 4 5 6
transparency
Read-modify-write, plane 4 6 7 8
masking, or transparency
13.5.2.7 Alignment/Graphics Adjustment
An additional adjustment may be necessary when plane masking or transpar-
ency are enabled and the alignment type is B, C, or O. As the second line of
Table 13-13 shows, if a particular word in a destination row has already been
read as part of a read-modify-write operation, no additional states are re-
quired to perform plane masking or transparency for that word. Since the
alignment types with misaligned edges (B, C, and D) already assume a RMW
(read-modify-write) on their respective edges, the effect of plane masking or
transparency can be ignored for these edges. That is, after you have calculated
the timing using the proper value for the graphics operation, you can subtract
2 states (cases B and C) or 4 states (case D) per row from the row timings for
the respective alignment cases. Case A requires no adjustment.
13-36
Instruction Timings - PIXBlT Expand Instructions
13.5.3 PIXBlT Timing Examples
PIXBLT timing is calculated by adding the PIXBLT setup value to the PIXBLT
transfer value:
PIXBLT time = PIXBLT setup time + PIXBLT transfer time
- alignment adjustment
PIXBLT setup timings, transfer timings, and the effects of graphics operations
are listed in the following tables:
Table Page
13-11 PIXBLT Expand Setup Time ............................................................. 13-32
13-12 PIXBLT Expand Transfer Timingt .................................................... 13-32
13-13 Timing Values per Word for Graphics Operations (G) ................. 13-36
The following three examples illustrate timing for a PIXBlT B,XV that ex-
pands a 10-by-1 0 font (L=1 0) into eight bits per pixel with color. The setup
and transfer timings for these examples are the same, except each uses a dif-
ferent graphics operation. Figure 13-16 illustrates the destination array and
window used in these examples, as defined by the implied operands in Figure
13-15. The shaded portion in Figure 13-16 is the destination array.
***************************************************
* Implied operand setup for PIXBLT B, XY examples *
* (assume that B register and I/O regiser names *
* are equated to with proper registers) *
***************************************************
MOVI 0003E2E8h, SADDR linear address
MOVI OOADOh, SPTCH X extent = 2768 pixels
MOVI 00320l0Bh, DADDR X=267, Y= 50
MOVI 800h, DPTCH X extent = 512 pixels
MOVI 00040000h, OFFSET
CLR WSTART ignored
MOVI OlOOOlOOh, WEND ignored
MOVI OOOAOOOAh, DYDX DX=10, DY=10
MOVI 8h, AO
MOVE AO, @PSIZE Pixel size 8 bits
MOVI 14h, AO
MOVE AO, @CONVDP
MOVE AO, @CONVSP ignored
CLR AO
MOVE AO, @PMASK
MOVI 0300h, AO
MOVE AO, @CONTROL ; W=O,T=O,PP=O,PBH=l,PBV=l
Figure 13-15. Implied Operand Setup for PIXBlT-Expand Examples
13-37
Instruction Timings - PIXBLT Expand Instructions
+--2.788 pixels per row~
6AODR
~
i
i--_-_-_
+-10-+
..... ......
:
': :
10
'"I . .: ......
: :: : •••••
: •••••: ' : :
DADDR
N= 12 =e
" PIXelSper word
Figure 13-16. PIX8LT 8,XV Timing Example
Follow these steps to determine the number of machine states consumed in
these PIXBLT examples:
1) Determine the setup time; refer to Table 13-11 (page 13-32). Setup
time comprehends the machine states consumed by windowing and
corner adjust operations;
a) Windowing: Is not enabled for this example.
b) Corner adjust: PBH and PBV are ignored.
As Table 13-11 shows, the setup time for this PIXBLT is 6 machine
states.
2) Determine the transfer time; refer to Table 13-12 (page 13-32).
Transfer time comprehends the number and alignment of rows in the
array, row length, the direction of the move, and the graphics operations.
a) Number of words per row: The source is part of a packed font.
The source array starts in the middle of a word and extends into the
next word, so two words are read for each row of the font (R=2).
b) Number of rows in the array: The Y dimension is 10 (L=10).
c) Neither the leading nor the trailing edges are word aligned, so the
alignment type is D.
d) Array alignment: The X dimension is 10 pixels wide, but with
alignment type 0, an extra word is involved for both the leading
and trailing pixels; the pixel size is eight, so 12 divided by 2 (two
pixels per word) produces N=6. Since the width is less than 32
pixels (10), but more than one word of the destination is affected,
this example is a medium case.
13-38
Instruction Timings - PIXBlT Expand Instructions
As Table 13-12 shows, the transfer timing is (5+2R+2GN)L + 3. The
only variable in the timing for these three examples is the selected
graphics operations.
Example 13-7. Replace, No Transparency, No Plane Masking
The implied operand setup in Figure 13-15 selects the following graphics
options:
• Pixel processing rep/ace operation (PPOP=O),
• No transparency, and
• No plane masking.
According to Table 13-13, variable G :;: 2. The total machine states re-
quired for this instruction are:
PIXBLT time = PIXBLT setup time + PIXBLT transfer time
= 6 + (5+2R+NG)L + 3
= 6 + (5 + 2 x 2 + 6 x 2) x 1 0 + 3
= 219 states
This examples consumes 219 machine states as it reads, expands, and
writes these 100 pixels.
Example 13-8. MAX, No Transparency, No Plane Masking
Select the pixel processing MAX option (be sure to retain the values of the
W bits and the T bit, which are also in the CONTROL register):
MOVI 50COh, AO
MOVE AO, @CONTROL ; MAX, W=3, T=O
These instructions, in combination with the implied operand setup in Figure
13-15, select the following graphics options:
• Pixel processing MAX operation (PPOP=14h),
• No transparency, and
• No plane masking.
According to Table 13-13, variable G:;:5; the timing equation becomes:
PIXBLT time = PIXBLT setup time + PIXBLT transfer time
= 6 + (5+2R+NG)L + 3
=6 + (5+2x2+6x5)x10+3
= 399 states
The instruction in this example consumes 399 machine states.
13-39
Instruction Timings - PIXBl T Expand Instructions
Example 13-9. XNOR with Transparency and Plane Masking
Select the pixel processing XNOR operation and enable transparency and
plane masking:
MOVI 14EDh, AD
MOVE AD, @CONTROL XNOR, W=3, T=l
MOVI llllh, AD
MOVE AD, @PMASK Use a plane mask
These instructions, in combination with the implied operand setup in Figure
13-15, select the following graphics options:
• Pixel processing XNOR operation (PPOP=05h),
• No transparency, and
• No plane masking.
According to Table 13-13, variable G = 6.
If plane masking or transparency is enabled, you must consider the array
alignment in the timing. Alignment type 0 incurs a read-modify-write at the
leading and trailing edges of each row. The extra read included in the RMW
can be used by the plane masking or transparency hardware, so an
alignment/graphics adjustment is necessary. The adjustment negates the
effect of the extra read cycles in each row that are attributed to the graphics
operations. For this example, the amount subtracted is 4L (the number of
machine states for a read cycle times 2 times the number of rows). The
timing is now calculated as:
PIXBLT time = PIXBLT setup time+ PIXBLT transfer time - adjust-
ment
=6 + (5+2R+NG)L + 3 - 4L
= 6 + (5 + 2x2 + 6x6) x10+3 - (4x10)
= 419 states
The instruction in this example consumes 419 machine states.
13.5.4 The Effect of Interrupts
The PIXBLT instruction may be interrupted on a destination word boundary
during the transfer portion of the algorithm. It may also be interrupted at the
end of any row inthe array. The context of the PIXBlT is saved in reserved
registers. The PBX bit is set in the copy of the ST register that is pushed to
the stack. The worst case latency caused by an interrupt is 20 machine states
for the interrupt to be recognized. The time for the context switch must be
added to this; see Section 8.5.1, Interrupt Latency (page 8-6) for context
switch timings.
13-40
Appendix A
TMS34010 Data Sheet
A-1
Appendix A - TMS3401 0 Data Sheet
A-2
TMS34010
GRAPHICS SYSTEM PROCESSOR
JANUARY 1986 - REVISED JUNE 1988
• Instruction Cycle Time:
- 132 ns ... (TMS34010-60)
FN PACKAGE
(TOP VIEW)
- 160 ns ... (TMS34010-50)
- 200 ns ... (TMS34010-40)
• Fully Programmable 32-Bit General-Purpose
Processor with 128-Megabyte Address
9 8 7 6 5 4 3 2 1 6867666564636261
Range
• Window
Pixel Processing. XV Addressing. and
Checking Built into the Instruction
LAD1
Set
• Size
Programmable 1. 2. 4. 8. or 16-Bit Pixel
with 16 Boolean and 6 Arithmetic Pixel
Processing Options (Raster-Ops)
• 30 General-Purpose 32-bit Registers and
32-bit Stack Pointer HD9
HD10
• 256-Byte LRU On-Chip Instruction Cache HD11
HD12
• Direct Interfacing to Both Conventional
DRAM and Multiport Video RAM
HD13
HD14
• and
Dedicated 8/16-Bit Host Processor Interface
HOLD/HLDA Interface
26
27 28 29 3031 32 33 34 35 36 37 38 39 4041 4243
44 HD15
U
u ~ N IU 1 1:><: I<! I..J Ul f-IZ IUl IUl I~ IUJ If-
• VSYNC. BLANK)
Programmable CRT Control (HSVNC. U:><::><:ZZZ~<!Ul~UJ<!<!
> ~ ~ ~ ~ ~ ~ ..J > g 0 ex: U
I>!D~ 0
ozo
I~ I ~
>-
• High-Level Language Support I~
• Full Line of Hardware and Software
Development Tools Including a "c"
Compiler
• 68-Leaded Packaging (PLCC)
• 5-Volt CMOS Technology
description
The TMS34010 Graphics System Processor (GSP) is an advanced high-performance CMOS 32-bit
microprocessor optimized for graphics display systems. With a built-in instruction cache. the ability to
simultaneously access memory and registers. and an instruction set designed specifically for raster graphics
operation. the TMS34010 provides user-programmable control of the CRT interface as well as the memory
interface (both standard DRAM and multiport video RAM). The 1-gigabit address space is completely bit-
addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics addressing
modes support 1. 2. 4. 8. and 16-bit wide pixels. The TMS3401 0 is exceptionally well-supported by graphics
software interface standards such as CGI/VDI. DGIS. and MS-Windows. as well as a full line of hardware
and software support tools. Current support is highlighted in the TMS3401 0 Third Party Reference Guide
(literature number SPVB066A).
architecture
The TMS34010 is a CMOS 32-bit processor with hardware support for graphics operations such as PixBlts
(raster ops) and curve-drawing algorithms. Also included is a complete set of general-purpose instructions
with addressing tuned to support high-level languages. In addition to its ability to address a large external
memory range. the TMS34010 contains 30 general-purpose 32-bit registers. a hardware stack pointer
This document contains information ob products Copyright © 1986, Texas Instruments Incorporated
in more than one 'phase of davalopment. TIle status
of each device is Indicated on the pagels) specifying
its electrical characteristics. TEXAS • A-3
INSTRUMENTS
POST OFFiCe BOX 1443 • HOUSTON, TeXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
and a 256-byte instruction cache. On-chip functions include 28 programmable I/O registers that contain
CRT control, input/output control, and instruction parameters. The TMS3401 0 directly interfaces to dynamic
RAMs and video RAMs and generates video monitor control signals. It also accommodates a conventional
HOLD/HLDA shared access as well as a separate, generalized interface for communicating with any standard
host processor.
pin descriptions
PIN
1/0 DESCRIPTION
NAME NUMBER
Host Interface Bus Pins
HCS 66 I Host chip select
HDO-HD15 44-51.53-60 1/0 Host bidirectional data bus
HFSO. HFS1 67. 68 I Host function select
HINT 42 a Host interrupt request
HLDS 63 I Host lower data select
HUDS 62 I Host upper data select
HRDY 43 a Host ready
HREAD 64 I Host read strobe
HWRITE 65 I Host write strobe
Local Bus Interface Pins
RAS 38 a Local row-address strobe
CAS 39 a Local column-address strobe
DDOUT 36 a Local data direction out
DEN 37 0 Local data enable
LADO-LAD15 10-17.19-26 1/0 Local addressldata bus
LAL 34 0 Local address latched
LCLK 1. LCLK2 28.29 0 Local output clocks
LlNT1. LlNT2 6. 7 I Local interrupt request pins
LRDY 9 I Local ready
TR/OE 41 0 Local shift register transfer or output enable
Vii 40 0 Local write strobe
INCLK 5 I Input clock
Hold and Emulation
HOLD 8 I Hold request
RUNIEMU 2 I RunlNot emulate
HLDA/EMUA 33 0 Hold acknowledge or emulate acknowledge
Video Timing Signals
BLANK 32 0 Blanking
HSYNC 30 1/0 Horizontal sync
VCLK 4 I Video clock
VSYNC 31 I/O Vertical sync
Miscellaneous
RESET 3 I Reset
VCC 27.61 I Nominal 5-volt power supply
VSS 1. 18.35. 52 I Ground
A-4 TEXAS . .
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POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
system block diagram
GRAPHICS MEMORY BUS
1
1
1
I
REFRESH 1
CONTROL CONTROL 1
~~TNITOR
1 }
------------------------ L.-_-_-_-_J______---t.
r----------------------------------------
, 110 REGISTERS
EXTERNAL 'r-----------I
INTERRUPT --LL.,
REQUESTS -rr', INTERRUPT
1
.......- - o . . J INSTRUCTION INSTRUCTION
1 REGISTERS N-,---.' CACHE DECODE
RESET~ I
I'
, 1 I
1
HOSl
INTERFACE
#': HOST
INTERFACE
I !
lI"'-
,r---- 1-----
........'---.....,
BUS
, 1
REGISTERS N-I , ,..-_
, 1 1 , PROGRAM
COUNTER
, 1 ,
9'1
, i--------t
,,;-'1 ,
I STATUS
SYNC AND VIDEO TIMING ~ REGISTER
L__________ J ~
BLANKING REGISTERS
ALU
1 I MICRO CONTROL
T11---_
GPR FILE A
ROM
,,
_- - - 1
LOCAL MEMOR't GPR FILE B
CONTROL , 1--------1
REGISTERS ,L.-____
, ........
STACK POINTER I - t ' - - - t
L _________ _
EXECUTION UNIT
I CLOCK
9 LOCAL MEMORY
CONTROL LOGIC
AND BUFFERS
____________{} _________________________ J
INTERNAL CLOCK
CIRCUITRY
OUTPUTS
CLOCK
INPUTS
LOCAL MEMORY
INTERFACE BUS
FIGURE 1. TMS34010 INTERNAL ARCHITECTURE
TEXAS . . A-5
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
The TMS3401 0 provides single-cycle execution of most common integer arithmetic and Boolean operations
from its instruction cache. Additionally, the TMS3401 0 incorporates a hardware barrel shifter that provides
a single-state bidirectional shift and rotate function for 1 to 32 bits.
A microcoded local memory controller supports pipelined memory write operations of variable-size fields
that can be performed in parallel with subsequent instruction execution.
TMS34010 graphics processing hardware supports pixel and pixel-array processing capabilities for both
monochrome and color systems that have a variety of pixel sizes. The hardware incorporates two-operand
raster operations with Boolean and arithmetic operations, XY addressing, window clipping, window checking
operations, 1 to n bits per pixel transforms, transparency, and plane masking. The architecture further
supports operations on single pixels (PIXT instructions) or on two-dimensional pixel arrays of arbitrary size
(PixBlts).
The TMS3401 O's flexible graphics processing capabilities allow software-based graphics algorithms without
sacrificing performance. These algorithms include: arbitrary window size, custom incremental curve drawing,
and two-operand raster operations.
register files
Boolean, arithmetic, byte, and field move instructions operate on data within the TMS3401 O's general-
purpose register files. The TMS3401 0 contains thirty-one 32-bit registers, including a system stack pointer
(SP). The SP is accessible to both Register File A and B as the sixteenth register. Transfers between registers
and memory are facilitated via a complete set of field MOVE instructions with selectable field sizes. Transfers
between registers are facilitated via the MOVE instruction.
The fifteen general-purpose registers in Register File A are used for high-level language support and assembly
language programming. The fifteen registers in Register File B are dedicated to special functions during
PixBlts and other pixel operations, but can be used as general-purpose registers at other times.
A-6 TEXAS ~
INSTRUMENTS
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TMS34010
GRAPHICS SYSTEM PROCESSOR
31(MSB) O(LSB) 31(MSB) O(LSB)
SOURCE ADDRESS
AO BO SADDR (PIXBLTS)
A1 B1 SPTCH SOURCE PITCH
DESTINATION ADDRESS
A2 B2 DADDR (PIXBL TS AND FILLS)
A3 B3 DPTCH DESTINATION PITCH
A4 B4 OFFSET OFFSET
A5 B5 WSTART WINDOW START
A6 B6 WEND WINDOW END
A7 B7 DYDX DELTA YI DELTA X
COLORO
A8 B8 COLORO (BINARY PIXBLTS)
COLOR1
A9 B9 COLOR1 (BINARY PIXBL TS. FILLS AND DRAV)
A10 B10 TEMPORARY REGISTER
A11 B11 TEMPORARY REGISTER
THESE ARE USED AS TEMPORARY
A12 B12 TEMPORARY REGISTER STORAGE FOR PIXBLT AND
FILL INSTRUCTIONS.
A13 B13 TEMPORARY REGISTER
A14 B14 TEMPORARY REGISTER
SP STACK POINTER SP STACK POINTER
FIGURE 2. REGISTER FILES A AND B
program counter (PCI
The TMS3401 D's 32-bit program counter register points to the next instruction-stream word to be fetched.
Since instruction words are aligned to 16-bit boundaries, the four LSBs of the PC are always zero.
instruction cache
An on-chip instruction cache contains 256 bytes of RAM and provides fast access to instructions. It operates
automatically and is transparent to software. The cache is divided into four 64-byte segments. Associated
with each segment is a 23-bit segment address register to identify the addresses in memory corresponding
to the current contents of the cache segment. Each cache segment is further partitioned into eight
subsegments of four words each. Each subsegment has associated with it a present (PI flag to indicate
whether the subsegment contains valid data.
TEXAS. A-7
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
SEGMENT START ADDRESS FLAGS DATA REGISTERS
1\
,-"--. r-----"-..
SUBSEGMENT 0
11~.~-------------23--------------~•• 1 SUBSEGMENT 1
SUBSEGMENT 2
SUBSEGMENT 3
>SEGMENT 0
4 SUBSEGMENT 4
SUBSEGMENT 5
SUBSEGMENT 6
SUBSEGMENT 7
1.--16 _ _ 1
SUBSEGMENT 0
SUBSEGMENT 1
WORD 0
SUBSEGMENT 2
SUBSEGMENT 3 -"'-"'-...,- WORD 1 SUBSEGMENT 2
'-. WORD 2 OF SEGMENT 1
4 SUBSEGMENT 4
-""-"''-' - I - - - - - - - - - j
'_ WORD 3
SUBSEGMENT 5
1-16_1
SUBSEGMENT 6
SUBSEGMENT 7
SUBSEGMENT 0
SUBSEGMENT 1
SUBSEGMENT 2
SUBSEGMENT 3
>SEGMENT 2
4 SUBSEGMENT 4
SUBSEGMENT 5 MOST
RECENTlY~
SUBSEGMENT 6 USED
SUBSEGMENT 7
LRU
>STACK
SUBSEGMENT 0
LEAST
SUBSEGMENT 1 RECENTlY-
USED
SUBSEGMENT 2
SUBSEGMENT 3
4 SUBSEGMENT 4
>SEGMENT 3
SUBSEGMENT 5
SUBSEGMENT 6
SUBSEGMENT 7
FIGURE 3. INSTRUCTION CACHE
A-a TEXAS -1./1
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
The cache is loaded only when an instruction requested by the TMS3401 0 is not already contained within
the cache. A least-recently-used (LRU) algorithm is used to determine which of the four segments of the
cache is overwritten with the new data. For this purpose, an internal four-by-two LRU stack is used to
keep track of cache usage.
status register
The status register (ST) is a special-purpose 32-bit register dedicated to status codes set by the results
of implicit and explicit compare operations and parameters used to specify the length and behavior of fields
o and 1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
N . Sign bit IE - Interrupt enable bit
C - Carry bit FE1 - Field extension bit 1
Z - Zero bit FS 1 - Field size bit 1
V - Overflow bit FEO - Field extension bit 0
PBX - Pix Bit executing FSO - Field size bit 0
FIGURE 4. STATUS REGISTER
fields, bytes, pixels, and pixel arrays
A 26-bit address output by the TMS3401 0 selects a 16-bit word of physical memory; logically, however,
the TMS3401 0 views memory data as fields addressable at the bit level. Primitive data types supported
by the TMS3401 0 include: bytes, pixels, two 1- to 32-bit fields, and user-defined pixel arrays.
Fields 0 and 1 are specified independently to be from 1 to 32 bits in length. Bytes are special 8-bit cases
of the field data type, while pixels are 1, 2, 4, 8 or 16 bits in length. In general, fields (including bytes)
may start and terminate on arbitrary bit boundaries; pixels must pack evenly into 16-bit words.
pixel operations
Pixel arrays are two-dimensional data types of user-defined width, height, pixel depth (number of bits per
pixel), and pitch (distance between rows). A pixel or pixel array may be accessed by means of either its
memory address or its XY coordinates. Transfers of individual pixels or pixel blocks are influenced by the
pixel processing, transparency, window checking, plane masking, or corner adjust operations selected.
I/O registers
The GSP contains an on-chip block of twenty-eight 16-bit I/O registers mapped into the TMS34010's
memory address space. They can be accessed either by the TMS3401 O's CPU or by the host processor
via the host interface. The I/O registers contain control parameters necessary to configure the operation
of the following interfaces: interface to host processor (5 I/O registers), interface to local memory (6
registers)' video timing and screen refresh functions (15 registers), and externally and internally generated
interrupts (2 registers). The I/O registers also furnish status information on these interfaces.
TEXAS -1.!1 A-9
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
ADDRESS REGISTER
~A
~
OC00001FOh REFCNT DRAM REFRESH COUNT
OC00001 EOh DPYADR DISPLAY ADDRESS
OC00001DOh VCOUNT VERTICAL COUNT
OC00001COh HCOUNT HORIZONTAL COUNT
OC00001BOh
OC00001AOh
r--
., -
DPYTAP DISPLAY TAP POINT
~ESr~
OC0000190h
OC0000180h
r-- -
OC0000170h
OC0000160h PMASK PLANE MASK
OC0000150h PSIZE PIXEL SIZE
OC0000140h CONVDP CONVERSION (DESTINATION PITCH)
OC0000130h CONVSP CONVERSION (SOURCE PITCH)
OC0000120h INTPEND INTERRUPT PENDING
OC0000110h INTENB INTERRUPT ENABLE
OC0000100h HSTCTLH HOST CONTROL (8 MSB'S)
OCOOOOOFOh HSTCTLL HOST CONTROL (8 LSB'S)
OCOOOOOEOh HSTADRH HOST ADDRESS (16 MSB'S)
OCOOOOODOh HSTADRL HOST ADDRESS (16 LSB'S)
OCOOOOOCOh HSTDATA HOST DATA
OCOOOOOBOh CONTROL CONTROL
OCOOOOOAOh DPYINT DISPLAY INTERRUPT
OC0000090h DPYSTRT DISPLAY START
OC0000080h DPYCTL DISPLAY CONTROL
OC0000070h VTOTAL VIDEO TOTAL
OC0000060h VSBLNK VERTICAL START BLANK
OC0000050h VEBLNK VERTICAL END BLANK
OC0000040h VESYNC VERTICAL END SYNC
OC0000030h HTOTAL HORIZONTAL TOTAL
OC0000020h HSBLNK HORIZONTAL START BLANK
OC0000010h HEBLNK HORIZONTAL END BLANK
OCOOOOOOOh HESYNC HORIZONTAL END SYNC
FIGURE 5. I/O REGISTERS
host interface registers
The host interface registers are provided for communications between the TMS34010 and the host
processor. The registers are mapped into five of the I/O register locations accessible to the TMS3401 O.
These same registers are mapped into four locations in the GSP interface to the host.
One of the registers is devoted to host interface control functions such as the passing of interrupt requests
and 3-bit status codes from host to TMS3401 0 and from TMS3401 0 to host. Other control functions
available to the host processor include flushing the instruction cache, halting the TMS34010, and
transmitting a non-maskable interrupt request to the TMS34010.
A-10 TEXAS . .
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TMS34010
GRAPHICS SYSTEM PROCESSOR
The remaining host registers are used for block transfers between the TMS3401 a and host processor.
The host uses these registers to indirectly access blocks within the TMS3401 a's local memory. Two of
the 16-bit registers contain the 32-bit address of the current word location in memory. Another 16-bit
register buffers data transferred to and from the memory by the host processor. The host interface can
be programmed to automatically increment the pointer address following each transfer to provide the host
with rapid access to a block of sequential addresses.
memory interface control registers
Six of the I/O registers are dedicated to various local memory interface functions including:
• Frequency and type of DRAM refresh cycles
• Pixel size
• Masking (write protection) of individual color planes
• Various pixel access control parameters
- Window checking mode
- Boolean or arithmetic pixel processing operation
- Transparency
- PixBlt direction control
video timing and screen refresh
Fourteen I/O registers are dedicated to video timing and screen refresh functions. The TMS3401 a generates
the horizontal sync (HSYNC), vertical sync (VSYNC), and blanking (BLANK) signals used to drive a video
monitor in a graphics system. These signals are controlled by means of a set of programmable video timing
I/O registers and are based on the input video clock, VCLK. VCLK does not have to be synchronous with
respect to INCLK, the TMS34010's CPU input clock.
The TMS3401 a directly supports multiport video RAMs (VRAMs) by generating the memory-to-register
load cycles necessary to refresh the display being shown on the video monitor. The memory locations
from which display information is taken, as well as the number of horizontal scan lines displayed between
memory-to-register load cycles, are programmable. VRAM tap point addresses are also fully programmable
to support horizontal panning.
The TMS34010 supports various screen resolutions and either interlaced or noninterlaced video. The
TMS34010 can optionally be programmed to synchronize to externally generated sync signals so that
graphics images created by the TMS3401 a can be superimposed upon images created externally. The
external sync mode can also be used to synchronize the video signals generated by two or more TMS3401 a
chips in a multiple-TMS34010 graphics system.
interrupt interface registers
Two dedicated I/O registers monitor and mask interrupt requests to the TMS3401 0, including two externally
generated interrupts and three internally generated interrupts. An internal interrupt request can be generated
on one of the following conditions:
• Window violation: an attempt has been made to write a pixel to a location inside or outside a
specified window boundary.
• Host interrupt: the host processor has set the interrupt request bit in the host control register.
• Display interrupt: a specified line number in the frame has been displayed on the screen.
A nonmaskable interrupt occurs when the host processor sets a particular control bit in the host interface
registers. The TMS34010 reset function is controlled by a dedicated pin.
TEXAS ~ A-11
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POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
memory controller/local memory interface
The memory controller manages the TMS3401 O's interface to the local memory and automatically performs
the bit alignment and masking necessary to access data located at arbitrary bit boundaries within memory.
The memory controller operates autonomously with respect to the CPU. It has a "write queue" one field
(1 to 32 bits) deep that permits it to complete the memory cycles necessary to insert the field into memory
without delaying the execution of subsequent instructions. Only when a second memory operation is
required before the memory controller has completed the first operation is the TMS3401 0 forced to defer
instruction execution.
The TMS3401 0 directly interfaces to all standard dynamic RAMs and, in particular to JEDEC standard
64K and 256K video RAMs such as the TMS4161 and TMS4461 Multiport VRAMs. The TMS34010
memory interface consists of a triple-multiplexed address/data bus plus the associated control signals.
Row address, column address, and data are multiplexed over the same address/data lines. DRAM refresh
is supported with a variety of modes including CAS-before-RAS refresh.
TMS34010 memory map
From the programmer's point of view, the TMS340 10 treats data and instructions as residing in the same
memory space.
A-12 TEXAS •
INSTRUMENTS
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TMSJ4010
GRAPHICS SYSTEM PROCESSOR
instruction set
The TMS3401 0 instructions fall into three categories. The graphics instructions manipulate pixel data,
accessed via memory addresses or XV coordinates. They provide support for graphics operations such
as array and raster ops, pixel processing, windowing, plane masking, and transparency. The move
instructions comprehend bit addressing and field operations; they manipulate fields of data using linear
addressing for transfer to and from memory and the register file. The TMS34010 general-purpose
instructions provide a complete set of arithmetic and Boolean operations on the register file as well as
general program control and data processing. Partial timing information is provided in the table below.
The two values given for jump instructions in the Minimum Cycles column indicate the jump and no-jump
conditions, respectively. Full timing information can be obtained in the TMS34010 User's Guide (number
SPVU001A).
The following abbreviations are used below in the opcodes: S (source register), D (destination register),
R (register file select), F (field select), K (constant), M (cross AlB file boundary), Z (draw option), code
(jump select code), X (don't care), N (trap select and stack adjust), RS (source register), RD (destination
register), xxxx (address displacement), IL (32-bit immediate operand), and IW (16-bit immediate operand).
GRAPHICS INSTRUCTIONS
NO. MINIMUM STATUS
SYNTAX DESCRIPTION WORDS CYCLES 16-BIT OPCODE BITS
MSB LSB
ADDXY Rs, Rd Add Registers in XY Mode 1 1110 OOOS SSSR DDDD N C Z V
CMPXV Rs, Rd Compare X and V Halves of Registers 3 1110 010S SSSR DDDD N C Z V
CPW Rs, Rd Compare Point to Window 1 1110 011S SSSR DDDD V
CVXVL Rs, Rd Convert XV Address to Linear Address 3 1110 100S SSSR DDDD
DRAV Rs, Rd Draw and Advance 1111 011S SSSR DDDD V
FILL L Fill Array with Processed Pixels: Linear 0000 1111 1100 0000
FILL XV Fill Array with Processed Pixels: XV 0000 1111 1110 0000 V
LINE Z Line Draw 1101 1111 Z001 1010 V
MOVX Rs, Rd Move X Half of Register 1110 110S S5SR DDDD
MOVV Rs, Rd Move V Half of Register 1110 1115 S55R DDDD
PIXBLT B,L Pixel Block Transfer: Binary to Linear 0000 1111 1000 0000
PIXBLT B,XV Pixel Block Transfer and Expand: Binary to XV 0000 1111 1010 0000 V
PIXBLT L,L Pixel Block Transfer: Linear to Linear 0000 1111 0000 0000
PIXBLT L,XV Pixel Block Transfer: Linear to XV 0000 1111 0010 0000 V
PIXBLT XV, L Pixel Block Transfer: XV to Linear 0000 1111 0100 0000
PIXBLT XV,XV Pixel Block Transfer: XV to XV 0000 1111 0110 0000 V
PIXT Rs,*Rd Pixel Transfer: Register to Indirect 1111 1005 SSSR DDDD
PIXT Rs, *Rd.XV Pixel Transfer: Register to Indirect XV 1111 0005 SSSR DDDD V
PIXT *Rs, Rd Pixel Transfer: Indirect to Register 4 1111 1015 SSSR DDDD
PIXT *Rs, *Rd Pixel Transfer: Indirect to Indirect 1111 1105 SSSR DDDD
PIXT *Rs.XV, Rd Pixel Transfer: Indirect XV to Register 6 1111 001S SSSR DDDD
PIXT *Rs.XV, *Rd.XV Pixel Transfer: Indirect XV to Indirect XV 1111 010S SSSR DDDD V
SUBXV Rs,Rd Subtract Registers in XV Mode 1110 001S SSSR DDDD N C Z V
tNumber of cycles depends on pixel size and/or pixel array size and graphics option selected. See TMS34010 User's Guide (SPVU001A).
TEXAS • A-13
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
MOVE INSTRUCTIONS
NO. MINIMUM STATUS
SYNTAX DESCRIPTION WORDS CYCLES l6-BIT OPCODE BITS
MSB LSB
MOVB RS,*Rd Move Byte: Register to Indirect 1000 110S SSSR DDDD - - - -
MOVB *Rs,Rd Move Byte: Indirect to Register 1000 111S SSSR DDDD N - Z 0
MOVB *Rs, *Rd Move Byte: Indirect to Indirect 1 t 1001 110S SSSR DDDD - - - -
MOVB Rs, * Rd(offset) Move Byte: Register to Indirect with offset. 2 t 1010 110S SSSR DDDD -
MOVB *Rs(offset),Rd Move Byte: Indirect with offset. to Register 2 1010 111S SSSRDDDD N - Z 0
MOVe *Rs(offset), *Rd(offset) Move Byte: Ind. with offset. to Ind.
with offset. 3 1011 110S SSSR DDDD - - - -
MOVB Rs,@Daddress Move Byte: Register to Absolute 3 00000101 111R SSSS - - - -
MOVB @Saddress,Rd Move Byte: Absolute to Register 3 0000 0111 111 R DDDD N - Z 0
MOVe @Saddress,@Oaddress Move Byte: Absolute to Absolute 5 0000 0011 0100 0000 - - - -
MOVE Rs,Rd Move Register to Register 1 0100 11MS SSSR DDDD N - Z 0
MOVE Rs, *Rd,F Move Field: Register to Indirect 1000 OOFS SSSR DDDD - - - -
MOVE Rs, - *Rd,F Move Field: Register to Indirect (pre-dec) 1010 OOFS SSSR DDDD - - - -
MOVE Rs,*Rd+,F Move Field: Register to Indirect (post-inc) 1001 OOFS SSSR DDDD -
MOVE *Rs,Rd,F Move Field: Indirect to Register 1000 01 FS SSSR DDDD N Z 0
MOVE - *Rs,Rd,F Move Field: Indirect (pre-dec) to Register 1010 01FS SSSR DDDD N - Z 0
MOVE *Rs+,Rd,F Move Field: Indirect (post-inc) to Register 1001 01FS SSSR DDDD N - Z 0
MOVE *Rs, *Rd,F Move Field: Indirect to Indirect 1000 10FS SSSR DDDD - - - -
MOVE - *Rs, - *Rd,F Move Field: Ind. (pre-dec) to Ind. (pre-dec) 1010 10FS SSSR DDDD - - - -
MOVE *Rs +, *Rd + ,F Move Field: Ind. (post-inc) to Ind. (post-inc) 1 1001 10FS SSSR DDDD - - - -
MOVE Rs, * Rd(offset).F Move Field: Register to Indirect with offset. 2 1011 OOFS SSSR DDDD - - - -
MOVE *Rs(offset),Rd,F Move Field: Indirect with offset. to Register 2 1011 01FS SSSR DDDD N - Z 0
MOVE * Rs(offset), *Rd + ,F Move Field: Ind. with offset. to Ind.
(post-inc) 2 1101 OOFS SSSR DDDD - - - -
MOVE *Rs(offset), *Rd(offset),F Move Field: Ind. with offset. to Ind.
with offset. 3 1011 10FS SSSR DDDD - - - -
MOVE Rs,@Daddress,F Move Field: Register to Absolute 3 000001F1 100R SSSS - - - -
MOVE @Saddress,Rd,F Move Field: Absolute to Register 3 0000 01F1 101R DDDD N - Z 0
MOVE @Saddress, *Rd + ,F Move Field: Absolute to Indirect (post-inc) 3 1101 01FO OOOR DDDD - - - -
MOVE @Saddress,@Oaddress,F Move Field: Absolute to Absolute 5 0000 01F1 1100 0000 - - - -
tNumber of cycles depends on field size and alignment. See TMS34010 User's Guide (SPVU001A).
A-14
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
GENERAL INSTRUCTIONS
NO. MINIMUM STATUS
SYNTAX DESCRIPTION WORDS CYCLES 16-BIT OPCODE BITS
MSB LSB
ABS Rd Store Absolute Value 0000 0011 100R DODD N - Z 0
ADD RS,Rd Add Registers 0100 0005 SSSR DODD Nez V
ADDC RS,Rd Add Register with Carry 1 1 0100 0015 S5SR DODD Nez V
ADDIIW,Rd Add Immediate (16 Bits) 2 2 0000 1011 ODOR DODD Nez V
ADDIIL,Rd Add Immediate (32 Bits) 3 3 0000 1011 001R DODD Nez V
ADDK K,Rd Add Constant (5 Bits) 0001 OOKK KKKR DODD Nez V
AND RS,Rd AND Registers 1 0101 0005 SSSR DODD Z
ANDIIL,Rd AND Immediate (32 Bits) 3 3 0000 1011 100R DODD Z
ANON RS,Rd AND Register with Complement 1 1 0101 0015 SSSR DODD Z
ANDNIIL,Rd AND Not Immediate (32 Bits) 3 3 0000 1011 100R DODD Z
BTST K,Rd Test Register Bit - Constant 0001 11KK KKKR DODD Z
BTST Rs,Rd Test Register Bit - Register 2 0100 1015 SSSR DODD Z
CLR Rd Clear Register 0101 0110 DOOR DODD
CLRC Clear Carry 0000 0011 0010 0000 o
CMP RS,Rd Compare Registers 1 0100 100S SSSR DODD Nez V
CMPIIW,Rd Compare Immediate (16 Bits) 2 2 0000 1011 010R DODD Nez V
CMPIIL,Rd Compare Immediate (32 Bits) 3 3 0000 1011 011R DODD Nez V
DEC Rd Decrement Register 1 0001 0100 001R DODD
DINT Disable Interrupts 3 0000 0011 0110 0000
DIVS RS,Rd Divide Registers Signed 40 0101 1005 5S5R DODD N - Z V
DIVU RS,Rd Divide Registers Unsigned 37 0101 1015 5SSR DODD Z V
EINT Enable Interrupts 3 0000 1101 0110 0000
EXGF Rd,F Exchange Field Size 1101 01F1 ODOR DODD
LMO RS,Rd Leftmost One 0110 1015 5SSR DODD Z
MMFM Rs,Register List Move Multiple Registers from Memory 2 0000 1001 101R DODD
MMTM Rd,Register List Move Multiple Registers to Memory 2 0000 1001 100R DODD
MODS RS,Rd Modulus Signed 40 0110 1105 S5SR DODD N - Z V
MODU RS,Rd Modulus Unsigned 1 35 0110 1115 SSSR DODD Z V
MOVIIW,Rd Move Immediate (16 Bits) 2 2 0000 1001 110R DODD N - Z 0
MOVIIL,Rd Move Immediate (32 Bits) 3 3 0000 1001 111R DODD N - Z 0
MOVK K,Rd Move Constant (5 Bits) 0001 10KK KKKR DODD
F51
MPYS RS,Rd Multiply Registers (Signed) 5+- 0101 1105 5SSR DODD N - Z
2
F51
MPYU Rs,Rd Multiply Registers (Unsigned) 5+- 0101 1115 SSSR DDDD Z
2
NEG Rd Negate Register 0000 0011 101R DODD Nez V
NEGB Rd Negate Register with Borrow 0000 0011 110R DODD Nez V
NOP No operation 0000 0011 0000 0000
NOT Rd Complement Register 0000 0011 111R DODD Z
OR Rs,Rd OR Registers 1 0101 0105 SSSR DODD Z
ORIIL,Rd OR Immediate (32 bits) 3 3 0000 1011 101R DODD Z
RL K,Rd Rotate Left - Constant 0011 OOKK KKKR DODD C Z
RL RS,Rd Rotate Left - Register 0110 1005 SSSR DODD C Z
SETC Set Carry 1 0000 1101 1110 0000
SETF FS,FE,F Set Field Parameters 1,2 0000 01 F1 01 FS SS5S
SEXT Rd,F Sign Extend to Long 3 0000 01 F1 ODOR DODD N - Z
t Number of cycles depends on number of registers in list and stack alignment. See TM53401 0 User's Guide (SPVUOO 1 A).
TEXAS . . . A-15
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
NO. MINIMUM STATUS
SYNTAX DESCRIPTION WORDS CYCLES 16-BIT OPCODE BITS
MSB LSB
SLA K,Rd Shift Left Arithmetic - Constant 3 0010 OOKK KKKR DODD N C Z V
SLA Rs,Rd Shift Left Arithmetic - Register 3 0110 OOOS SSSR DODD N C Z V
SLL K,Rd Shift Left Logical - Constant 0010 01KK KKKR DODD C Z
SLL RS,Rd Shift Left Logical - Register 0110 001S SSSR DODD C Z
SRA K,Rd Shift Right Arithmetic - Constant 0010 10KK KKKR DODD N C Z
SRA RS,Rd Shift Right Arithmetic - Register 0110 010S SSSR DODD N C Z
SRL K,Rd Shift Right Logical - Constant 0010 l1KK KKKR DODD C Z
SRL RS,Rd Shift Right Logical - Register 0110 011S SSSR DODD C Z
SUB Rs,Rd Subtract Registers 0100 010S SSSR DODD N C Z V
SUBB Rs,Rd Subtract Registers with Borrow 0100 011S SSSR DODD N C Z V
SUBllW,Rd Subtract Immediate (16 Bits) 2 2 0000 lOll 1"R DODD N C Z V
SUBllL,Rd Subtract Immediate (32 Bits) 3 3 0000 1101 OOOR DODD N C Z V
SUBK K,Rd Subtract Immediate (5 Bits) 1 0001 01 KK KKKR DODD N C Z V
XOR RS,Rd Exclusively OR Registers 1 1 0101 011S SSSR DODD Z
XORllL,Rd Exclusively OR Immediate Value (32 Bits) 3 3 0000 lOll 1100 DODD Z
ZEXT Rd,F Zero Extend to Long 0000 01Fl 001R DODD Z
PROGRAM CONTROL AND CONTEXT SWITCHING
NO. MINIMUM STATUS
SYNTAX DESCRIPTION WORDS CYCLESt 16-BIT OPCODE BITS
MSB LSB
CALL Rs Call Subroutine Indirect 6 0000 1001 001R DODD
CALLA Address Call Subroutine Absolute 3 6 0000 1101 0101 1111
CALLR Address Call Subroutine Relative 2 5 0000 1101 0011 1111
DSJ Rd.Address Decrement Register and Skip Jump 2 3,2 0000 1101 100R DODD
DSJEQ Rd.Address Conditionally Decrement Register and Skip Jump 2 3,2 0000 1101 101R DODD
DSJNE Rd.Address Conditionally Decrement Register and Skip Jump 2 3,2 0000 1101 1 lOR DODD
DSJS Rd,Address Decrement Register and Skip Jump - Short 2,3 0011 1Dxx xxxR DODD
EMU Initiate Emulation 6 0000 0001 0000 0000
EXGPC Rd Exchange Program Counter with Register 2 0000 0001 001R DODD
GETPC Rd Get Program Counter into Register 0000 0001 010R DODD
GETST Rd Get Status Register into Register 1 0000 0001 100R DODD
JAcc Address Jump Absolute Conditional 3 3.4 1 100 code 1000 0000
JRcc Address Jump Relative Conditional 2 3,2 1100 code 0000 0000
JRcc Address Jump Relative Conditional - Short 2,1 1 100 code xxxx xxxx
JUMP Rs Jump Indirect 2 0000 0001 011R DODD
PO PST Pop Status Register from Stack 8 0000 0001 1100 0000
PUSHST Push Status Register onto Stack 2 0000 0001 1110 0000
PUTST Rs Copy Register into Status 3 0000 0001 101R DODD N C Z V
RETI Return from Interrupt 11 0000 1001 0100 0000 N C Z V
RETS (N) Return from Subroutine 7 0000 1001 011N NNNN
REV Rd Get Revision Number 1 0000 0000 001R DODD
TRAP N Software Interrupt 16 0000 1001 OOON NNNN 0 0 0 0
tWhere two numbers appear, the first number assumes that the jump is taken, and the second assumes that the jump is not taken.
A-16 TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
development systems and software support
Texas Instruments, together with third party suppliers, offers a full range of hardware and software
development tools for the TMS3401 O. The support environment is aimed at four areas of support with
the key tools based on the IBM PC, DEC VAX, SUN, MAC II, APOLLO and TI Professional computers:
DESIGNER TOOLS
Hardware XDS-22 Real Time Emulator (with PC-based Debugger Interface)
PC Software Development Board (with Debugger Interface)
Software Assembly Language Package, including:
Assembler, Linker, Archiver, ROM Object Format Converter, Software Simulator (PC only)
Graphics/Math Function Library
Bit-Mapped Font Library
CCITT Data Compression/Decompression Function library
8514A Emulation Function Library
Languages C Compiler Package including:
TMS34010 C Compiler
Runtime Support
Systems Window Management Support
Image Processing Support
Graphics Interfaces and Standards
Debugger Adaptation Software
Further support is provided through a network of Regional Technology Centers (RTCs).
TEXAS . . A-17
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
TMS340 FAMILY HARDWARE AND SOFTWARE SUPPORT
SILICON PART NUMBER
Graphics System Processor 68-Pin PLCC TMS34010FNL
Video System Controller 68-Pin PLCC TMS34061 FNL
Color Palette 22-Pin DIP TMS34070NL
64Kx1 Multiport Memory 22-Lead PLCC (120 and 150 ns) TMS4161FML
64Kx1 Multiport Memory 22-Pin DIP (120 and 150 ns) TMS4161NL
64Kx4 Multiport Memory 24-Pin DIP (120 and 150 ns) TMS4461NL
OPERATING
SOFTWARE TOOLS COMPUTER SYSTEM PART NUMBER
TMS34010 Assembler Package:
Assembler, Linker, Archiver, IBM/TI PC MS-DOS 2.11 + TMDS3440808002
Object Format Converter, Simulator
TMS34010 Assembler Package:
Assembler, Linker, Archiver, VAX VMS TMDS3440200059
Object Format Converter VAX ULTRIX TMDS3440200069
VAX System V TMDS3440200089
HP System V TMDS3440500089
Sun System V TMDS3440550086
Mac 11 MPW TMDS3440560021
Apollo System V TMDS3440570088
TMS34010 C Compiler Package IBMITI PC MS-DOS 2.11 + TMDS3440805002
VAX VMS TMDS3440205059
VAX ULTRIX TMDS3440205069
VAX System V TMDS3440205089
HP System V TMDS3440505089
Sun System V TMDS3440555086
Mac II MPW TMDS3440565021
Apollo System V TMDS3440575088
Combination packages:
Assembler, Linker, Archiver, IBM/TI PC MS-DOS 2.11 + TMDS3440804003
Object Format Converter, Simulator,
C Compiler with runtime support
TMS34010 GraphicslMath
Function Library IBM/TI PC - Source TMDS3440802202
VAX - Source TMDS3440802208
TMS34010 Bit-Mapped Font Library IBM/TI PC MS-DOS 2.11 + TMDS3440802302
VAX ALL TMDS3440202308
TMS34010 CCITT Function Library IBM/TI PC MS-DOS 2.11 + TMDS3440802102
VAX All TMDS3440202108
TMS34010 8514/A Emulation Libraili,MOS- IBM/TIPC, MS-DOS 2.11 +
3440
8020
02
TMS34010 PC Debugger Development Package IBM/TI PC MS-DOS 2.11 + TMDS3440806002
(For Internal Use)
TMS34010 PC Debuffer Development Package IBM/TI PC MS-DOS 2.11 + TMDS3440806003
(For Resale)
HARDWARE TOOLS COMPUTER VERSION PART NUMBER
TMS34010 XDS-22 Real-Time Emulator with BT&T U.S. TMDS346991 0000
Europe TMDS3469981 000
Color Graphics Controller Board (TMS34061, TMS34070) IBMITI PC TMDS3471804000
TMS34010 Software Development Board IBM/TI PC TMDS3411804420
DESIGN KITS PART NUMBER
TMS340 Graphics Design Kit, including TMS34061, TMS34070, TMS4161 s TMS340GDK
TMS34010 Graphics Design Kit, including TMS34010, TMS34070, TMS4461s, PC Assembler TMS34010GDK
A-18 TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
reset
Reset puts the TMS34010 into a known initial state. It is entered when the input signal at the RESET
pin is asserted low. RESET must remain active low for a minimum of 40 local clock (LCLK1 and LCLK2)
periods to ensure that the TMS34010 has sufficient time to establish its initial internal state.
While RESET remains asserted, all outputs are in a known state, no DRAM-refresh cycles take place, and
no screen-refresh cycles are performed.
At the low-to-high transition of the RESET signal, the state of the HCS input determines whether the
TMS34010 will be halted or begin executing instructions. The TMS3401 0 may be in one of two modes,
host-present or self-bootstrap mode.
1 . Host-Present Mode
If HCS is high at the end of reset, TMS34010 instruction execution is halted and remains halted
until the host clears the HLT (halt) bit in HSTCTL (host control register). Following reset, the eight
RAS-only refresh cycles required to initialize the dynamic RAMs are performed automatically by the
TMS34010 memory control logic. As soon as the eight RAS-only cycles are completed, the host is
allowed access to TMS3401 0 memory. At this time, the TMS3401 0 begins to automatically perform
DRAM refresh cycles at regular intervals. The TMS3401 0 remains halted until the host clears the
HLT bit. Only then does the GSP fetch the level-O vector address from location OFFFFFFEOh and begin
executing its reset service routine.
2. Self-Bootstrap Mode
If HCS is low at the end of reset, the TMS3401 0 first performs the eight RAS-only refresh cycles
required to initialize the DRAMs. Immediately following the eight RAS-only cycles, the TMS3401 0
fetches the level-O vector address from location OFFFFFFEOh, and begins executing its reset service
routine.
Unlike other interrupts and software traps, reset does not save previous ST or PC values. This is because
the value of the stack pointer just before a reset is generally not valid, and saving its value on the stack
is unnecessary. A TRAP 0 instruction, which uses the same vector address as reset, similarly does not
save the ST or PC values.
asserting reset
A reset is initiated by asserting the RESET input pin at its active-low level. To reset the TMS3401 0 at power
up, RESET must remain active low for a minimum of 40 local clock periods after power levels have become
stable. At times other than power up, the TMS3401 0 is also reset by holding RESET low for a minimum
of 40 clock periods. The 40-clock interval is required to bring TMS3401 0 internal circuitry to a known
initial state. While RESET remains asserted, the output and bidirectional signals are driven to a known state.
The TMS3401 0 drives its RAS signal inactive high as long as RESET remains low. The specifications for
certain DRAM and VRAM devices, including the TMS4161, TMS41 64 and TMS4464 devices, require that
the RAS signal be driven inactive-high for 100 microseconds during system reset. Holding RESET low for 1 50
microseconds will cause the RAS signal to remain high for the 100 microseconds required to bring the
memory devices to their initial states. DRAMs such as the TMS4256 specify an initial RAS high time of
200 microseconds, requiring that RESET be held low for 250 microseconds. In general, holding RESET
low for t microseconds ensures that RAS remains high initially for t - 50 microseconds.
TEXAS ~ A-19
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
suspension of DRAM-refresh cycles during reset
An active-low level at the RESET pin is considered to be a power-up condition, and DRAM refresh is not
performed until RESET goes inactive high. Consequently, the previous contents of the local memory may
not be valid after a reset.
initial state following reset
While the RESET pin is asserted low, the TMS3401 O's output and bidirectional pins are forced to the states
listed below.
INITIAL STATE OF PINS FOLLOWING A RESET
OUTPUTS DRIVEN OUTPUTS DRIVEN BIDIRECTIONAL
TO HIGH LEVEL TO LOW LEVEL PINS DRIVEN TO
HIGH IMPEDANCE
DDOUT BLANK HSYNC
HRDY VSYNC
DEN HDO-HD15
LAL LADO-LAD15
ffi/OE
RAS
CAS
W
HINT
HLDA/EMUA
Immediately following reset, all I/O registers are cleared (set to Oh), with the possible exception of the
HLT bit in the HSTCTL register. The HLT bit is set to 1 if HCS is high just prior to the low-to-high
transition of RESET.
Just prior to execution of the first instruction in the reset routine, the TMS3401 O's internal registers are
in the following state:
• General-purpose register files A and Bare uninitialized.
• The ST is set to 0000001 Oh.
• The PC contains the 32-bit vector fetched from memory address OFFFFFFEOh.
TMS34010 local memory interface
The TMS3401 0 local memory interface consists of a triple-multiplexed address/data bus on which row
addresses, column addresses, and data are transmitted. The associated memory control signals support
direct interfacing to both DRAMs and VRAMs. At the beginning of a typical memory cycle, the address
is output in multiplexed fashion as a row address followed by a column address. The remainder of the
cycle is used to transfer data between the TMS3401 0 and memory.
A-20 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
TMS34010 local memory interface
The TMS3401 0 local memory interface consists of a triple-multiplexed address/data bus on which row
addresses, column addresses, and data are transmitted. The associated memory control signals support
direct interfacing to both DRAMs and VRAMs. At the beginning of a typical memory cycle, the address
is output in multiplexed fashion as a row address followed by a column address. The remainder of the
cycle is used to transfer data between the TMS3401 0 and memory.
ROW COLUMN
TMS34010 DATA
ADDRESS ADDRESS
RF IAQ 15
26 TR 14
25 29
24 28 12
27 11
10
9
8
4
3
BIT 31 BIT 0 BIT 15 BIT 0
(MSB) (LSB) (MSB) (LSB)
RF = DRAM-REFRESH BUS STATUS BIT
IAQ = INSTRUCTION ACQUISITION BUS STATUS BIT
TR = VRAM SHIFT -REGISTER-TRANSFER BUS STATUS BIT
FIGURE 7. TRIPLE MULTIPLEXING OF ADDRESSES AND DATA
The following types of memory cycles are supported: read, write, VRAM memory-to-shift-register, VRAM
shift-register-to-memory, RAS-only DRAM refresh and CAS-before-RAS DRAM refresh. The functional
timing for these cycles is shown in the next six figures. Each memory cycle is a minimum of two machine
states (a state is one local clock period) in duration. The seventh figure indicates the timing signals output
during an internal cycle, i.e., a cycle during which no memory access takes place. An internal cycle is
one state in duration.
During a memory cycle, the row address, column address, and data are transmitted over the same physical
bus lines. The manner in which logical addresses are output at the memory interface makes external
mUltiplexing hardware unnecessary, while supporting a wide variety of memory configurations. For example,
in Figure 7, 16 consecutive address bits (5 through 20) are output on LAD l-LAD8 during the row and
column address times. Output along with the address are bus status signals that indicate when DRAM
refresh cycles, screen refresh (VRAM memory-to-shift-register) cycles, and instruction fetch cycles are
occurring.
TEXAS . . A-21
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
The following remarks apply to memory timing in general. A row address is output on LA DO-LAD 15 at
the start of the cycle, and is valid before and after the fall of RAS. Next a column address is output on
LADO-LAD 1 5. The column address is valid briefly before and after the falling edge of LAL, but is not valid
at the falling edge of CAS. The column address is clocked into an external transparent latch
(e.g., a 74AS373 octal latch) on the falling edge of LAL to provide the hold time on the column
address required for dynamic RAMs and video RAMs. A transparent latch is required in order that the row
address be available at the outputs of the latch during the start of the cycle.
Very large memory configurations may require external buffering of data lines. The DEN signal serves as
the drive-enable signal to external bidirectional buffers, e.g., 74AS245 octal buffers. The DDOUT signal
serves as the direction control for the buffers.
When an 1/0 register is addressed by the TMS3401 0, a special memory read or write cycle is performed.
During this cycle, the external RAS signal falls, but the external CAS remains inactive-high for the duration
of the cycle.
The timing shown in the first six functional timing diagrams assumes that the LRDY input remains high
during the cycle. The LRDY pin is pulled low by slower memories requiring a longer cycle time. The
TMS34010 samples the LRDY input at the end of Q 1, as indicated in the figures. If LRDY is low, the
TMS34010 inserts an additional state, called a "wait" state, into the cycle. Wait states continue to be
inserted until LRDY is sampled at a high level. The cycle then completes in the manner indicated in the
functional timing diagrams. A wait state is one local clock period in duration. Three additional timing diagrams
provide examples of cycles extended by wait states.
The LRDY input is ignored by the TMS34010 during internal cycles.
A holdlhold acknowledge capability is also built into the local memory interface to allow external devices
to request control of the bus. After acknowledging a hold request, the TMS3401 0 releases the bus by
driving its address/data bus and control outputs into high impedance.
A-22 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
write cycle timing
LClK1
LCLK2
LADO-LAD15
TR/QE
DDOUT
lRDY
TEXAS • A-23
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
read cycle timing
,,
,
Q1 I' Q2 " Q3 I Q4 , Q1 I
I
Q2
l'Q3 Q4'
I
Q1 I
I
LCLK1 V I I
I
I
I
"I
I
I
!I II
'I
I
'V'
I
"'-~I!-------{i
I ,
I
\
I
V'
I
II
I
I I I I I I , I I
LCLK2
!-----r.I I V
I !I ~I,,--+-I_l!--_~'v'
I -I'I·
I, f\ I I
I ,,' r~ ;-
I I I, I ' I I' I
I I
I ! ~! Ie
I I I I, I I I I
LADO-LAD15 ~
t - i- -..... ~ow ~
, I I 'I I I
I' 'I I
I I
I
,
RAS'
I
I
I
I
"
II \
'I
'I'
' I
I
I
I
I
I
I
I
'v
I I
I
'I,
I
I
I
I
'v, I
, " I' I I I II, I
I I I I I I I I I I
I I I 1\1 I , I I VI I
LAL ' I
I
I
I
I
I,'
I I
,
,
, 'I
'I, I
I
' I
' I ,, " '
I II ,, '"
' I, I,
' I , I I I , 'I, I
CAS I
' I
I I I
I I'
!\ I
I ,
I IV
" I
I I
' I , I' I , , I
' I I I' I I 'I I
, I (HIGH) I I' I, I, I
W' I I " I , I, I
' I 'I I , I"
' I 'I I I I, I
'I " I l' I, I
TR/QE I ;
' I
i;
, I
I,! \ :
I , '
I V
I I II
: I I I I I I I I'
DEN!
' I
V !I
I I
~!
I ,
VI!
I I I
I
DDOUT
'IJ
i v I
I
i I
I 1\ I
I
I
I
'I'
I I I
lv/
I I I I I I I I 'I I I
, I I I I I I ' 'I' I
LROY~'~
A-24 TEXAS
INSTRUMENTS
-1!1
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
memory-to-register cycle timing
i 01 I 02 i 03 , 04 , 01 02' 03 I 04 I 01 i
, ' I " ' I ' I
LCLK1 ! "I I VI ~
, - - - - t - - -...... I : I1
, \....--+-'--11---1.
VI 'V'
' II
, ,
I
I
\...·--+-1-11---1.
II I
I
,
, ,I
, I I I,
, 1
1
,--!I------i.t\ ' t \ I,
LCLK21
1
V I
t-I- - - ' ! - ,
1,\ I,
"
I ,
V i i,,\I' l/
-+1---rV
1
I ' I I
I, " \....+-1
$. : : UNDE~INE~;
I ,I, I ,I 1
~DO-LAD15 ! ~ ~ow ~
, , ' ," I , I, I
RAS I,t----+I--~l I II I II !I I I
i\
'V,
' I I _,
I ' ' '---+,--+I--+,-----fl--~!------f' I '
I
I
,
,
I
I
,I,
,I, I
I I
,
,
LALP'
V I
I
It\! I '
I !v
I
I I ' I' I I
I I I I 1 I I
I I I I!\' IV
CAS II I
I
', I !\ I ''---+I---+-----f-~
.
I I " ,
I I I I I
t-I---!----+I-(HIGH) -+--+-,-+---+I----+--~~-It---+----+---
W I '
I I
I I
TR/OE
I
!
I '
~
'---+---~~-_+_--~--_f
Vr---+-+!-+---+---I
I
I ' ' I
DEN!
II
V
,,
!!
"
, I
DDOUT I!
I
'I' ,
VI "
, ',I',
"'
,II' I
I
'
'
'I'
'I'
1
I
I
I I I ," I' I
~I-
TEXAS . . A-25
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
register-to-memory cycle timing
, i, ", , ,
,
, 01 02 03 04 , 01 02' 03 04' 01
LCLK1 V ~
I,~-~'Ij~I~~.
, ,
1 'V',...--1-------1.1\.I,I~ "V'
I.
,
,I 'I' , k "' '
'
LCLK2 :-~----fV I,
I,
~,I' II
,,',
I
V "I i\ ~.I-+-II--~V! ; -
,, ,, ,', '' '' ,,'
,,' ,,
+-,
LADO-LAD151~~ ~OW ~: : UNDE+O:: ~
,, ,, ,, "
"
,, "
"
,,
RAS!, !, ~
,
! !
'---for-~,-+---+---+----!,
V!!
"
!,
, , , " , I' ,
LAL ""V""""--+-'---+-,---!+----11.", ! V '
, , ~--~~-~--~-.,~,
"
"
,, ,,
CAS!, !, "'~-+---~i---~--fV '
, ,
w!
"
1\ V
,
~/QE i ~~-~--~i-+--~---+---~~
DEN! ~ !
OOOUT ! ~ ! I i I
lRDY~ ~
I '" ' " I
A-26
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
RAS-only DRAM refresh cycle timing
LCLK1
LCLK2
DEN I
f
I
I f f
i I I
I
I I I
DDOUT i
I
f
V i
I
I
f
I
I
I I
I
I
I
I
I I
I
I
I
I
LRDY~~
TEXAS • A-27
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
CAS-before-RAS refresh cycle timing
I Q1 i Q2 I Q3 I Q4 i Q1 I Q2 i Q3 I Q4 I Q1
I I I I I I I I I
~I
LCLK1
V I
I
I
I
I \.\,..,_--;-.1
I
I
I
I
I
I
I
I I ,...---+I---i.!\
---111--~.
I
I
I
I
I
I \
I
I
I
I
I
I
I
I
I
IV
.
I
I _ - + I - -......I~I I I~I
LCLK2 ;-
<-----rV I r
• I
I II
I
I
I
I
I
VI
. I
I
! '"+-1I _~I---fV!; - -
I I I I I I I I I I I
_----(~ ~--"T'":__.,. .: -~k=
1
LADO-LAD15 I-! : ROW: : _UN_D_EF_INT-;D---r:_ _
I I I I I I I I I I
I I I l I I I I I I
RAS II I
I
I
I
1\ I
I
I
I
I
I ·
VI I
I
I I I I
I I I I
LAL V!
I I
~
I '---~--;-.-;._--~--;._--;._-'-___fl
v,..--+-!---
I
II I I I I
CAS II
I
!\
1\
I
I
I
'---~I--~-~-+--~---+-"---+~I
V I
I
I
I
I I I I
1
Vii 1-1---+---(HlbH) --!---+--i------1!-------;i----i---+- -1-1- - - + - - - -
I
I
I
I
I
I
II
I I I I
I I I I
I I I I
TR/QE I (HIGH) I I
I I I I
I
I
II I
I
I
I
A-28
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
internal cycles back to back
Ii Ql ,r Q2 i, Q3 Q4' 'Qli, Q2 Ii Q3 '
, Q4 ,
, Ql i
,
LCLK 1 IV I, ! \
I
,
,
"\
'
" V " ! \ I II.
' i , ''
',.
" " " ,
VII ' "\ ,
I
I 'I I' I I ", I
LCLK21 V I
1-1 ---Ii '
\\1
,,'
I I I\I!
I ~,+,--+,-----fV
'V,
.
tr , ,
I , ' ,,' , I ,', '
LADO-~D'5 !, ,X:, ,::: UNDE;'NED:
'I , ,
:::
'"
X=
,
, , I " , , I '" ,
, , (HIGH) , " I , '" ,
RAS ,
,,,
I
,,, ,,,
I ",
",
",
,,
,
,,
, '"
'"
'"
,
,,,
' ",
I" ,, ,, '"
I', ,
LAL ,
V
,
,
,
,
,
I
J
,,
,
,
" ,
",
",
",
,
,
,,
,
,
,,
"
"
"
"
,,
,
,
,
,
,
I
I
(HIGH) i i'
" , ,
i i '
, "
I
,
i
CAS'
,, ,,
,
,!i ,
",
",
'I ,
"" , "
,, ,,,
1 I I I I
,,
(HIGH)
,i ,
",
I' "I I
,,,
1
,,I
,
i---..,.I--(HIGH)
! ,
I
' I
1 1
"
"I I I
,I
TR/QE Ii", " , ,
,
I
,
, ",
", "
" ,, ,,
, I I 1 I I 1 I
~---l. V ;
,
I
,
"
I'
I'
I
' I
' I
I '
,
r
r
I
I
,
, , " ' I J ,
OOOUT
i
.
,
V !
.
,
,
,
I" I
"
I"
' I
I I,
'I
'I
II
I
LROY
TEXAS . " A-29
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
write cycle with one wait state
~WAIT STATE~
I 01 02 I 03 I 04 02 I 03 04 Q2 I 03 04 I 02
LCLK1 Y 1\
I "--~---f I\--+-----f I\,---+--f
I I I
I I I I
I I
LCLK2 I I I I
I I I
*=
I I I I I
LADO-LAD15 ---t----tX ~OW ~~:~::----r"DA~A--,--:-r--:
I I I I I I I I I I I
---r---:
I
I I I I I I I I I I I I
-I-----i...---l I I I I I I I I __+--+---
RAS I I I I I I I I I I I
I I I I I I
I I I I
I I I I I I
I I I I I I I
LALI
Y \j. I I
II
I
I
I
I
I
I
V
,,....-t---
.
I
I
I I I I I I
I I I I I I
I I I I I I
~~~~-r~~ i I I ~ I
CAS
II ',~ \ . II II I,!, II
I I I I I I
I I I I I I
~~~_ _~~I~~ I I AI
I
II f\ II II 11 I
II
'i'R/OE _~_!--_~_~_I --+-1-
I
I
I
I
I
I
.. I
!
......-(HIGH)
I
I
I
I
I
I
I
I
I
I
I
I
I
I I I I I I
-r---t--......-t__-i-----i.' I I I I I
DEN ____"1----rV
I
~ I
I I,
!!
I I
!
I
V-
I
I I I I I I
DDOUT!
II PI
V
I
I
I
!! I! : ! : I! !
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I I I I I I I I I I I I I
LRDY~~:Ct!~!~'~~
A-30 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
read cycle with one wait state
r--WA1T STATE~
01 02 03 04 01 03 04 01 02
LCLK1 I
I
I
I
I
I
LCLK2 I I I I I I I I
I I I I
I I I I I I I I I I
~ ;OW ~~
I I I I I I I I I
LADO-LAD7
I
I I I I I I I I I I
I I I I I I I I I I
I I I I I
I I I I I I I I
I I I I
I I I
I I I I
I I I I
LAL ]I' 1
I
I
I
I
\1 I
I
I
I
I
II VI
I
I I I I ....
1 _ _- -
II
I 1
I
~ 1I 1
I
I: I
I I ! I
IN I I (H GH) I
I I I
I I I
I I I
I r-~--
TR/OE
II j\
I
11 I
I I I
DEN ---+-~v I
~
I
~ I
DDOUT
I. V
I
I
I
r
I
I
I
I
I
I
I
~ 1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
I
I
I
!r-
V
I
I
LRDY
_g~~1~~_! ~'~t~rr~_
TEXAS ~ A-31
INSTRUMENTS
POST OFFice BOX 1443 • HOUSTON. TeXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
register-to-memory cycle with one wait state
iWAITSTATEi
I Q2 I I I I I
--Y,
Q1 Q3 Q4 Q2 Q3 Q4 Q2 Q3 Q4 Q2
,,f\ f\,, ,f\
LCLK1
, ,
, ,
LCLK2 , , I
I
I , I
I I
,I I I I I I I
LADO-LAD7
:
I
,,
I
~ ,,, ~ :
I
ROW
I ' I ,
:
I,UNDEFINED
:I I, *=
I
I
I
I I ' I I I I,
I I I
RAS
, , f\
I
,
I
I
I
II
'
'I I
I
I
I
,I V
I
,
I I
I
I
, I
I I '
,
I
I
I ,I I
I I
1 ' I
, , I
LALy, I
I
I
I
I
II
,
I
1I \1,
I ,
I
,I
I
I
,,
I
I
I
I
I
V
,
I
I
I
I
, , , ,
,,
I, I
I
I I I I
, I I
I
~ ,
I
,
CAS ,,
I
I,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
/: I I
I
I
I I I I
I
I
W I
TR/QE I , I
I I ,
I I I
I I I
, I I
DEN Vii
I I I
I I I
DDOUT !
,
V1
I ,
I
I
1
I
I
I
1
I
!
I
1
,
I
I
I
I
I
I
!I
~I l ~ I ~~I~~I~7rlc'~'7""""'-I""~:"'l'M'rl'~~~I~~~~I~'71:'7
LRDYiXJ&S&R&*n;~! ~ ~~
A-32 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ......................................................... 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 20 V
Off-state output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 2 V to 7 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 DC to 70 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 10 DC to 1 50 DC
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions"
section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to the VSS pins of the chip.
recommended operating conditions
MIN NOM MAX UNIT
Vee Supply voltage 4.75 5.0 5.25 V
VSS Supply voltage t 0 0 0 V
10H High-level output current -400 p.A
10L Low-level output current 2.0t mA
2
TA Operating free-air temperature 0
tCare should be taken by card designers to provide a minimum inductance path between the VSS pins and system ground in order to
70 °e
o-
minimize VSS noise.
iOutput current of 2.0 mA is sufficient to drive five low-power Schottky TTL loads or 10 advanced low-power Schottky TTL loads (worst case).
td:
~
DC electrical characteristics a::
PARAMETER TEST CONDITIONS MINt TYpi MAXt UNIT
oLL
High-level input All inputs
2.2 VCC+0.3
2
VIH§ voltage, TTL-level except INCLK
signal
VCC = 5.0 V V
w
INCLK 3.0 VCC+0.3 U
Low-level input All inputs
2
~
-0.3 0.8
VIL voltage, TTL-level except INCLK
V
signal
INCLK -0.3 0.8 C
High-level output voltage, VCC = min,
2.6 V
«
VOH
TTL-level signal 10H = max,
Low-level output voltage, VCC = max,
VOL 0.6 V
TTL-level signal 10L = max,
10
High-impedance leakage current,
Vcc=max I VO=2.8V 20
p.A
bidirectional pins I VO=0.6V -20
All inputs except
Input current ±20 p.A
II
I RUN/EMU§
VI=VSS to VCC
VCC = max, 40 MHz 125
ICC Supply current VCC = max, 50 MHz 150 mA
VCC = max, 60 MHz 175
CI Input capacitance 10 pF
Output capacitance (except
Co 10 pF
address/data lines)
tFor conditions shown as "min" or "max," use the appropriate value specified under "Recommended Operating Conditions."
tAli typical values are at VCC=5 V, TA=25°C.
§RUN/EMU will be no-connected in a typical configuration. The nominal pull-up current will be 250 p.A.
ADVANCE INFORMATION concerns new products in
the sampling or preproduction phase of development.
Characteristic data and other specifications are TEXAS • A-33
subject to change without notice. INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010 ADVANCE
GRAPHICS SYSTEM PROCESSOR INFORMATION
NOTE
Advance information notices apply only to the TMS34010-60.
signal transition levels
--- ____ 2.6V
~
- - - - - - - - - - 2.0 V
_ _ _ _ _ _ _ _ _ _ 0.8V
0.6 V
FIGURE 8. TTL-LEVEL OUTPUTS
TTL-level outputs are driven to a minimum logic-high level of 2.6 volts and to a maximum logic-low level
of 0.6 volts. Output transition times are specified as follows.
For a high-to-Iow transition on a TTL-compatible output signal, the level at which the output is said to
be "no longer high" is 2.0 volts, and the level at which the output is said to be "low" is 0.8 volts. For
a low-to-high transition, the level at which the output is said to be "no longer low" is 0.8 volts, and the
» level at which the output is said to be "high" is 2.0 volts.
~
J>
---r===\.--- 2.2 v
==.I-----~ 0.8 V
z
om FIGURE 9. TTL-LEVEL INPUTS
-
~
."
Transition times for TTL-compatible inputs are specified as follows. For a high-to-Iow transition on an input
signal, the level at which the input is said to be "no longer high" is 2.2 volts, and the level at which the
o::JJ input is said to be "low" is 0.8 volts. For a low-to-high transition on an input signal, the level at which
the input is said to be "no longer low" is 0.8 volts, and the level at which the input is said to be "high"
s: is 2.2 volts.
~
test measurement
o The test load circuit shown in Figure 10 represents the programmable load of the tester pin electronics,
which are used to verify timing parameters of TMS3401 0 output signals.
z
TESTER PIN
ELECTRONICS
OUTPUT
VLOAD >--.~----~-'o UNDER
I TEST
I
I
I
__ ...JI
Where: IOL = 2.0 mA DC level verification (all outputs)
IOH = 400 p.A (all outputs)
VLOAD = 1.5 V DC level verification
0.7 V Timing verification
CT = 65 pF typical load circuit capacitance
FIGURE 10. TEST LOAD CIRCUIT
A-34 TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
AL LAL HS HSYNC or VSYNC
C CAS ICK INCLK
CA Column address LR LRDY
CK LCLK 1 and LCLK2 OE TRfOE, when used as output enable
CK1 LCLK1 R RAS
CK2 LCLK2 RA Row address
CS HCS RS HREAD
D Data RY HRDY
DD DDOUT S HREAD or HWRITE
EN DEN TR TRfOE, when used as shift register enable
F HFSO, HFS1 VCK VCLK
HK HLDA/EMUA W W
HR HOLD WS HWRITE
Lowercase subscripts and their meaning are:
a access time
c cycle time (period)
d delay time
h hold time
su setup time
t transition time
w pulse duration (width)
The following additional letters and symbols and their meaning are:
H High
L Low
V Valid
Z High impedance
i No longer low
t No longer high
TEXAS ~ A-35
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010 ADVANCE
GRAPHICS SYSTEM PROCESSOR INFORMATION
host interface timing parameters
The timing parameters for host interface signals are shown in the next four figures. The purpose of these
figures and the accompanying table is to quantify the timing relationships among the various signals. The
explanation of the logical relationships among signals will be found in the TMS34010 User's Guide (number
SPVU001A).
The write stobe referred to in the following table is the enabling signal during a write to one of the host
interface registers (see comment 2 on the next page). Similarly, the read strobe is the enabling signal during
a read.
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock period,
or twice the input clock period, tc(ICK).
TMS34010-50
TMS34010-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
Setup time of HWRITE/HREAD high or HFSO,
1 tsu(FV-SL) 10 10 ns
HFS 1 valid to read or write strobe!
» 2 td(WSL-DV) Delay from write strobe! to data in valid, write cycle 2tO 2tO ns
~
Delay from read or write strobe low to next
3 td(SL-SL) 7tO+ 10 7tO+ 10 ns
»,
:2
4 tw(SL)
read or write strobe!
Duration of read or write strobe low
Delay from read or write strobe high to next
80 80 ns
5 td(SH-SL) 60 60 ns
(') read or write strobe!
m 6 th(WSH-DV) Hold time of data in valid after write strobe high, write cycle 10 10 ns
Hold time of HWRITE/HREAD high or HFSO,
7 10 10 ns
:2 th(SH-FV)
HFS 1 valid after read or write strobe high
."
o::0 8 th(RSL-DZ)
Hold time of data high impedance after read strobe!.
read cycle
O§ O§ ns
Delay from read strobe low to data out valid,
ns
S 9 td(RSL-DV)
read cycle with no wait
90 90
~
10 th(RSH-DV) Hold time of data out valid after read strobet, read cycle 0 0 ns
Delay from read strobe high to data out high impedance,
11 30§ 30§ ns
o td(RSH-DZ)
read cycle
th(CSL-RYH) Hold time of HRDY high after HCS!, cycle with wait 0 0 ns
:2 12
13 td(CSL-RYL) Delay from HCS low to HRDY low, cycle with wait 40 40 ns
14 Pulse duration of HRDY low, cycle with wait t t ns
tw(RYL)
15 td(RYL-RYH) Delay from HRDY! to HRDY high, cycle with wait 0:1: 0:1: ns
Hold time of write strobe low after HRDYt,
16 40 40 ns
th(RYH-WSL) write cycle with wait
17 td(RYH-DV) Delay from HRDYt to data out valid, read cycle with wait 40 40 ns
Hold time of read strobe low after HRDYt,
18 th(RYH-RSL) 40 40 ns
read cycle with wait
NOTE: Advance information notices apply only to the TMS34010-60.
tparameter 14 is a function of local bus memory contention. This parameter is not tested. Refer to the TMS340 10 User's Guide for details.
:l:parameter 15 is specified as minimum 0 ns to indicate that a low-going pulse on HRDY can be arbitrarily narrow.
§These values are derived from characterization and are not tested.
TEXAS •
A-36
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
general comments on host interface timing
The following general comments apply to host interface timing:
1. The HRDY signal is enabled by an active-low level on the HCS input. When HCS is inactive-high,
HRDY is forced high regardless of the internal state of the device. Low-going transient pulses on
HCS may result in low-going transient pulses on HRDY, but otherwise have no effect unless
accompanied by active levels on other control signals.
2. A host interface write cycle occurs when HCS, HWRITE, and HLDS are low, or when HCS,
HWRITE, and HUDS are low. The combination of these signals defines a write strobe. In either case,
the last of the three signals to make the high-to-Iow transition is the strobe (write strobe) that begins
the cycle. The first of the three signals to make the low-to-high transition ends the cycle. Similarly,
a host interface read cycle occurs when HCS, HREAD, and HLDS are low, or when HCS, HREAD,
and HUDS are low. The combination at these signals define a read strobe. In either case, the last
of the three signals to make the high-to-Iow transition is the strobe (read strobe) that begins the
cycle. The first of the three signals to make the low-to-high transition ends the cycle. All access
times are specified with respect to the strobing edges that begin and end the cycle.
3. During a host interface read or write, HWRITE and HREAD must not be active-low simultaneously.
4. Host interface input signals HCS, HUDS, HLDS, HFSO, HFS1, HREAD, and HWRITE are assumed
to be asynchronous with respect to the output clocks LCLK1 and LCLK2.
host interface timing: write cycle with no wait
HFSO, HFSl m< I
VALID FUNCTION SELECT ~
I
~1~1 ~7~
I' I. '
HREAD =:71.1-1 r-7~''-___-
I I_
_ _ _ _ _ _1 I 3
AI~5~"\
I -I I
HCS, HWRITE,
HLDS, HUDS ! \:~
1\1' _ r- 01 \.\.._ __
I 1.--4 ' I
I-- 2 -.II -----.., j.- 6 -..I
I
HDO-HD15 ~ VALID DATA IN ~
HRDY
TEXAS • A-37
INSTRUMENlS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
host interface timing: read cycle with no wait
HFSO. HFS1 ~ VALID FUNCTION SELECT ~
I
r- ~
1 1
1 14-- 7---...
HWRITE ~ I I1.-7 ~J'.\.""'----
---./ I~1...J 1
I
1 I. 31 .1
------Sl I I 1
HCS. HREAD.
HLDS. HUDS
"k. !
I\. ,. =r
.f r-- ------.t \.""___
5
,J--------
1 ! . - - 4 -----.j t--11"-1
I 49 '--10~
HDO-HD15 --HI-Z
/4 8", VALID DATA OUT
HRDY
host interface timing: write cycle with wait
HFSO.HFS1 ~~_____________V_A_Ll_D_F_U_N_CT_I_ON__S_EL_E_C_T____________~~
~1
r- --r' !-- 7~ 1
-JL I
HREAD I
~1
I I1
~7~
I J\ ""_____
1 14 3--------i1r---~.1
1I I
HlD:~~~~·------~~~;.~----------4-----------~~~~~5 .~
1~14~-------------3-----------r1------~.~:
HCS -------~~.-------------4------------.~ ~
I ~13 '-1------16 - - - - - 4. .1 ~ 5 ~
...
12~1
______.....
I--~
1
'-
JC
------.l
.....--14------.
~I 1
I
HRDY
I1 T\ I I
j!f1 I
I
I t. 15 ~I ~6
~2~ I
HDO-HD15 ~ VALID DATA IN ~
A-38 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
host interface timing: read cycle with wait
HRDY
TEXAS
INSTRUMENTS
"'!1 A-39
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010 ADVANCE
GRAPHICS SYSTEM PROCESSOR INFORMATION
reset timing
The timing parameters for device reset are shown in the next two figures. The purpose of these figures
is to quantify the timing relationships among the RESET, HCS, and LCLK1 signals. RESET and HCS are
asynchronous inputs that are internally synchronized by latches internal to the TMS3401 O. The timing
relationships specified for these signals relative to LCLK 1 need be met only to guarantee recognition of
a transition of one of these signals at a particular clock edge. The explanation of the logical relationships
among signals will be found in the TMS34010 User's Guide.
Quarter clock time tQ which appears in the following table, is one quarter of a local output clock period,
or twice the input clock period, tc(lCK).
TMS34010-50
TMS34010-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
Duration of HCS low to configure GSP to run
19 tw(CSL) 4tQ+55 4tQ+55 ns
in self-bootstrap mode
Setup time of HCS low to RESETt to configure
20 tsu(CSL-REH) 8tQ+55 8tQ+55 ns
the GSP to run in self-bootstrap mode
l> 21
Duration of RESET low to ensure that GSP
160tQ -40 160tQ-40 ns
~
tw(REL)
is properly reset
Delay from HCSi to RESET high, end of reset,
l> 22 td(CSH-REH)
to configure GSP to run in self-bootstrap mode
4tQ - 50 t 4tQ-50 t ns
:2 Setup time of RESET valid to LCLK 1! to
(") 23 tsu(REV-CK 1 L) 40+ 40+ ns
m guarantee recognition at a particular clock edge
Hold time of RESET valid after LCLK 1 low to
24 th(CK1 L-REV) 10+ 10+ ns
:2 guarantee recognition at a particular clock edge
." Setup time of HCS valid to LCLK 1! to
o 25
t su (CSV-CK1 L) guarantee recognition at a particular clock edge
40+ 40+ ns
:c
s: 26 th(CK1 L-CSV)
Hold time of HCS valid after LCLK 1 low to
guarantee recognition at a particular clock edge
10+ 10+ ns
~ NOTE: Advance information notices apply only to the TMS34010-60.
tparameter 22 is the maximum amount by which the RESET low-to-high transition can be delayed after the HCS low-to-high transition
o and still guarantee that the GSP is configured to run in self-bootstrap mode (HL T bit = 0) following the end of reset. HCS may be held
low for some time past the low-to-high RESET transition, and will be ignored by the GSP for 1 7 local clock periods following the clock
:2 edge at which the low-to-high RESET transition is detected. Following completion of the eight RAS-only cycles that automatically follow
reset, however, a low HCS level will be interpreted as a chip select.
+RESET and HCS are asynchronous inputs. The specified setup and hold times of these signals with respect to the high-to-Iow transition
of LCLK1 need be met only to guarantee that a transition of RESET or HCS is detected by the device at a particular clock edge.
reset: asynchronous timing relationships
19 ----I
~ I
VI - - - - 22 - - - - I
I
I
!
~ 'I • 20 -------i j"
RESET ~~--------------------_________.~;C
i• 2 1 - - - - - -..........!
A-40 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
ADVANCE TMS34010
INFORMATION GRAPHICS SYSTEM PROCESSOR
reset: synchronous timing relationships
LCLK1J
i\1I=------Jr
23;------t I
I 1~24
RESETt ------IX V~LlD X,..-----
25-T------i I
I ~26
---JX
HCSt _ _ _ _ X,..----- VALID
t RESET and HCS are asynchronous inputs. The specified setup and hold times of RESET or HCS with respect to the high-to-Iow LCLK 1
transition must be met only to guarantee that a RESET or HCS transition is detected by the device at a particular clock edge.
2:
local bus timing parameters o
The following six figures show the timing parameters for the signals of the local memory interface bus,
often simply referred to as the local bus. The purpose of these figures and the accompanying tables is ~
to quantify the timing relationships among the various signals. The explanation of the logical relationships ~
among signals will be found in the TMS34010 User's Guide (number SPVU001). a:
A number of parameter values are expressed in terms of quarter clock time tQ, which is one quarter of oLL
a local clock period, or twice the input clock period, tc(ICK).
Input clock INCLK is divided internally by 8 to produce output clocks LCLK 1 and LCLK2. Transitions of
the other local interface output signals are also generated as delays from INCLK transitions. The divide-
-2:w
down logic that converts INCLK to the internal clocks used to generate LCLK 1 and LCLK2 introduces U
significant propagation delays from the transitions of INCLK to the corresponding transitions of LCLK 1 2:
~
and LCLK2. While the frequency of INCLK is precisely eight times the frequency of LCLK 1 or LCLK2, no
timing relationship other than the frequency is specified between transitions of input clock INCLK and
transitions of the output clocks LCLK 1 and LCLK2. C
TMS34010·40 TMS34010·50 TMS34010-60
cd:
NO. PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
27 tc(lCK) Period of INCLK 25 62.5 20 62.5 16.5 62.5 ns
2a tw(lCKH) Pulse duration of INCLK high a:l: a:l: 6.5:1: ns
29 tw(lCKL) Pulse duration of INCLK low a:l: a:l: 6.5:1: ns
30 tt(lCK) Transition time (rise and fall) of INCLK 2t at 2t at 2t at ns
NOTE: Advance information notices apply only to the TMS34010-60.
tThese values are based on computer simulation and are not tested.
:l:This pulse width is tested at 1.4 volts.
local bus timing: input clock
I... 27 _,
1-- ---1 ~29--+1 I
28
r- 30~
'i___--Jlyr---
30-t : -
INCLK J 'X Y
TEXAS -I/} A-41
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010 ADVANCE
GRAPHICS SYSTEM PROCESSOR INFORMATION
local bus timing parameters (continued)
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock period,
or 2tc(lCK).
TMS34010-50
TMS34010-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
31 tc(CK) Period of local clocks LCLK 1 and LCLK2 8t c (lCK) t 8t c (lCK) t ns
32 tw(CKH) Pulse duration of local clock high 2tO-10 2tO-10 ns
33 tw(CKL) Pulse duration of local clock low 2tO-10 2tO-10 ns
34 thICK 1 H-CK2L) Hold time of LCLK2 low after LCLK 1 high to-10 to-10 ns
35 thICK 1 L-CK2H) Hold time of LCLK2 high after LCLK 1 low to-10 to-10 ns
36 th(CK2H-CK 1 H) Hold time of LCLK 1 high after LCLK2 high to-10 to-10 ns
37 th(CK2L-CK 1 L) Hold time of LCLK 1 low after LCLK2 low to-lO to-10 ns
38 thICK 1 H-CK2H) Hold time of LCLK2 high after LCLK 1 high 3tO-10 3tO-10 ns
39 thICK 1 L-CK2L) Hold time of LCLK2 low after LCLK 1 low 3tO-10 3tO-10 ns
»
c
40
41
th(CK2H-CK 1L) Hold time of LCLK 1 low after LCLK2 high
th(CK2L-CK 1 H) Hold time of LCLK 1 high after LCLK2 low
3tO-10
3tO-10
3tO-10
3tO-10
ns
ns
42
~
tt Transition time (rise and fall) of LCLK1 or LCLK2 10 10 ns
43 t su (RAV-CK2H) Setup time of row address valid to LCLK2i 4tO-25 4tO-15 ns
:2 44 t su (CAV-CK2H) Setup time of column address valid to LCLK2i 2tO-25 2tO-15 ns
(") 45 t su(LRV-CK2H) Setup time of LRDY valid to LCLK2i 30+ 30+ ns
m
:-2
46 th(CK2H-LRV) Hold time of LRDY valid after LCLK2 high 0+ 0+ ns
47 tsu(RAV-CK 1 L) Setup time of row address valid to LCLK H to-25 to-15 ns
48 tsu(CAV-CK 1 H) Setup time of column address valid to LCLK 1 i to-25 to-15 ns
."
o:l:I 49 tsu(ALH-CK 1 L) Setup time of LAL high to LCLK 1 ! 2tO-20 2tO-10 ns
NOTE: Advance information notices apply only to the TMS34010-60.
3: tThis is a functional minimum and is not tested. This parameter can also be specified as 4tO'
+LRDY is a synchronous input sampled during the low-to-high transition of LCLK2. The specified setup and hold times must be met for
~ the device to operate properly.
o
:2
A-42 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
local bus timing: output clock and LRDY signal
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
I_ 31 -I
L.-- 32 ----,.!
I I 14--33-----.1 I
I 42 ...... 14- 42 -..;14-
I II I II 11r-----
LCLK1 Jf I II
N ¥f
II
N II~-----'!i
j[
I I I I_ I I 41 -I I I
I I I I I I I I
I I \..-35-.! I I I- 38 I -I I
I I I I I I_ I 40 I _I
I 14- 36 ~ I I I I I I
~34--i I
I .
I
I
I
I I
37
i 1I I
I
I- i 39 -I
I 14--33-----,
LCLK2
----..;,
~49----t
Y I
I X iI "
*48~
II
I j.--32---/1
~
II ~,I
II
I
I
r--
47 ....j
I_
I
43 I
III
_ II I I
42 ---t \.-
I I
42 ---t I~
I I I I" 31 _I
I I j 4 t - - 44 -------.I I
I I I I I
LADO-
LAD15 ! [ ROW ~""'--_~llt-!_____---JX'-___..J)
I
' 1--45----1 :-46--j
I I
LRDV
I~
I
)¢ VALID X"" ___________
!
\'--_ _ _--..J/
TEXAS • A-43
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010 ADVANCE
GRAPHICS SYSTEM PROCESSOR INFORMATION
TMS340 10-40 TMS34010-50 TMS3401 0-60
NO. PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
50 td(RL-RL) Delay from ~.!. to ~.!. 8tO t 8tot 8tO t ns
Setup time of row address
51 tsu(RAV-RL) to-20 to-15 to-15 ns
valid to RAS.!.
Hold time of row address valid
52 th(RL-RAV) to-20 to-10 to-5 ns
after RAS low
53 tw(RH) Pulse duration, RAS high 3tO-20 3tO-10 3tO-5 ns
54 twIRL) Pulse duration, RAS low 5tO-20 5tO-10 5tO-10 ns
Setup time of column address
55 tsu(CAV-ALL) valid to LAU 0. 5tO-20 0. 5tO-10 0. 5tO-10 ns
Hold time of column address
56 th(ALL-CAV) 0. 5tO-15 0. 5tO-10 0. 5tO-10 ns
valid after LAL low
Hold time of RAS high
57 th(ALH-RH) 2tO-20 2tO-10 2tO-10 ns
after LAL high
Hold time of LAL low
58 th(RL-ALL) 6tO-20 6tO-10 6tO-1O ns
after~low
:t>
c 59 th(CL-RL)
Hold time of RAS low
afterCM low
3tO-20 3tO-10 3tO -10 ns
~ 60
Hold time of W high after
after RAS high, shift register 2tO-20 2tO-10 2tO-10 ns
:2 th(RH-WH)
n transfer follows read
m Setup time of column address
:-2
61 tsu(CAV-CL) to-20 to-10 to-10 ns
valid to CAS.!.
Hold time of LAL low
62 th(CL-ALL) 4tO-20 4tO-10 4tO-10 ns
"TI after CAS low
o::D 63 th(CH-ALL)
Hold time of LAL low
after CM high, write cycle
0. 5tO-15 0. 5tO-10 0. 5tO-10 ns
s: 64 th(ALL-CH)
Hold time of CAS high
0. 5tO-15 0. 5tO-10 0. 5tO-10 ns
~
after LAL low
Hold time of RAS high
65 2. 5tO-15 2. 5tO-10 2. 5tO-10 ns
o th(CH-RH)
after CM high
Pulse duration, CAS low
:2 66 tw(CL) 3. 5tO-25 3.5tO-10 3. 5tO-10 ns
Hold time of CAS high
67 th(RL-CH) 2tO-20 2tO-10 2tO-10 ns
after RAS low
Delay time from RAS low
68 td(RL-CL) 2tO+20 2tO+10 2tO+ 10 ns
to CAS low
Hold time of W high after
69 th(CH-WH) CAS high, shift register 1. 5tO-15 1. 5tO-10 1. 5tO-10 ns
transfer follows read
Hold time of CAS low
70 th(RL-CL) 5. 5tO-25 5. 5tO-10 5. 5tO-10 ns
after RAS low
71 tw(CH) Pulse duration, CAS high 4. 5tO-15 4. 5tO-10 4. 5tO-10 ns
Hold time of LAL low after
72 th(WH-ALL) 0. 5tO-15 0. 5tO-10 0. 5tO-10 ns
IN high, write cycle
Setup time of W high to CAS.!.,
73 tsu(WH-CL) 4. 5tO-15 4. 5tO-10 4.5tO -10 ns
end of write
NOTE: Advance information notices apply only to the TMS34010-60.
tThis is a functional minimum and is not tested.
A-44 TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
local bus timing: the RAS, CAS, and LAL outputs
- -----f
N
(\') III
----------]" ;::
o
N
o
~ r ~----r--r
- __ t
~ I
r--
T--:~ --T
-- ------ -- 1 f 1-- --- 1- -
(\')
o
~ -- ----- - -[ ~ ~
N
o
o
'<t r--
III
'<t
o
--- -f r-- ~
(\')
o
3:
oa:
__ __ ____ __~___ ___I
oc.- 13:
I~ I~
III
etC
..1«
15
..I
TEXAS • A-45
INSTRUMENTS
POST OFFice BOX 1443 • HOUSTON. TeXAS 77001
TMS34010 ADVANCE
GRAPHICS SYSTEM PROCESSOR INFORMATION
local bus timing parameters (continued)
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock period,
or 2tc(ICK).
TMS34010·50
TMS34010·40
NO. PARAMETER TMS34010·60 UNIT
MIN MAX MIN MAX
Setup time of W low to RAS!. shift register
74 tsu(WL·RL) tQ-20 tQ-10 ns
transfer cycle
Hold time of W low after RAS low. shift
75 th(RL·WL) tQ-20 tQ-10 ns
register transfer cycle
Setup time of TR/QE low to RAS!. shift
76 tsu(TRL·RL) tQ-20 tQ-10 ns
register transfer cycle
Hold time of TR/QE low after RAS low. shift
77 th(RL·TRL) 4tQ-20 4tQ-10 ns
register transfer cycle
» 78 th(CL·TRL)
Hold time of TR/OE low after CAS low. shift
register transfer cycle
2tQ-20 2tQ-10 ns
~ 79
Setup time of TR/OE high to RASi. shift
tQ-1O ns
»:2 tsu(TRH·RH)
register transfer cycle
Setup time of TR/QE high to CASi. shift
tQ-20
80 tsu(TRH·CH) 1.5tQ-25 1.5tQ-10 ns
n register transfer cycle
-m
:2
NOTES: 1. Advance information notices apply only to the TMS34010·60.
2. Parameters 81 and 82 intentionally omitted.
. " I local bus timing parameters: shift register transfer cycle
o
::Jl 01 I Q2 03 04 01 Q2 03 04 01 I Q2
3:
l>.
::! LADO·
LAD15
________-J)(~____ R_O_W
_____ ~~_______________________________J)( ROW
o
:2
1\
I I~--------------------------------~
I I
j \
II
I:
II
II
II
\----------+-----/
II
II
::
1 I. .1 75
~ 1
~1
74 I. ..I 1 1 1 1
1 II 1 1 1
'i1!;.1 1 1
----jlf-I!---yll
I
I1 :
1
1
14--78~ ~80----ll:ol
79 I..
1
_I! 1
1 \-----
TR/OE
_________7~6~-rl..
----~
i
.. 1 1~.~----------77 "I 1
Y--------------------\----------
A-46 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
ADVANCE TMS34010
INFORMATION GRAPHICS SYSTEM PROCESSOR
local bus timing parameters (continued)
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock period,
or 2tc(lCK).
TMS34010-50
TMS34010-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
Access time from RAS low to data
83 ta(RL-DV) 5. 5tO-40 t 5. 5tO-25 t ns
in valid. read cycle
84 tsu(CH-ALH) Setup time of CAS high to LAL t 0. 5tO-15 0. 5tO-10 ns
85 tsu(ENH-ALH) Setup time of DEN high to LAL t 0. 5tO-15 0. 5tO-10 ns
Access time from CAS low to data
86 ta(CL-DV) 3. 5tO-40 t 3. 5tO-25 t ns
in valid. read cycle
Hold time of data in valid after CASt.
87 th(CH-DV) 0 0 ns
read cycle
Hold time of row address high impedance after
88 th(CH-RAZ) 1.5tO -10:1: 1. 5tO-l0* ns
~ high. end of read cycle
2:
89 th(CL-OEL)
Hold time of TR/OE low after CAS low.
read cycle
3. 5tO-25 3. 5tO-10 ns o
90 tsu(CAZ-OEL)
Setup time of column address high impedance
to TR/OE!. read cycle
to -10* to -10* ns ~
Hold time of data in valid after TR/OEt. :!:
91 th(OEH-DV)
read cycle
0 0 ns a:
92 td(CL-OEL)
Delay time from CAS! to TR/OE low.
to+20 to+10 ns
oLL
read cycle
93 ta(OEL-DV)
Access time from TR/OE low to data
in valid. read cycle
2. 5tO -40t 2. 5tO-25 t ns -2:w
94 th(OEH-RAZ)
Hold time of row address high impedance
1.5tO-10:l: 1. 5tO-l0:l: ns U
after TR/OE high. end of read cycle
2:
~
95 tw(OEL) Pulse duration. TR/OE low. read cycle 2.5tO - 25 2. 5tO-l0 ns
Delay time from CAS low
96 td(CL-ENL) to+20 to+l0 ns
to DEN low. read cycle C
97 th(ENH-DV)
Hold time of data in valid after DEN I.
0 0 ns
<C
read cycle
Setup time of column address high impedance
98 tsu(CAZ-ENL) to -10:1: to -10* ns
to DEN I. read cycle
Hold time of next row address high impedance
99 th(ENH-RAZ) 1. 5tO-10:l: 1. 5tO -10:1: ns
after DEN high. end of read cycle
Access time from DEN low to data in valid.
100 ta(ENL-DV) 2. 5tO -40t 2. 5tO-25 t ns
read cycle
Hold time of DDOUT high after DEN high.
101 th(ENH-DDH) 3tO-20 3tO-10 ns
read follows write cycle
Setup time of DDOUT low to DEN I.
102 tsu(DDL-ENL) to-20 to-l0 ns
read cycle
NOTE: Advance information notices apply only to the TMS34010-60.
t 4 t O is added to these values for each wait state inserted.
*These values are derived from characterization and are not tested.
TEXAS • A-47
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
local bus timing: read cycle
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 '11 Q2
LADO-
LAD15
----C('-._ _ROW
___
X ...J
••
COL )
,
t~~-----~I
DATA ~
1
IN
r i , 1
I I r 1
r 1 r 1
1 1 1 I
~1.~----------83, _I I 1
\~
\
l
I
l
,
/
.
[l
I 1
1 1 r I
r 1 I 1
I
I
1
1 jr--1I 1
f---;I---
I
\ 1 I I I
-'---+I---+--~1 , I
I I 87 I. 1 .1 I
rf 1
'ii 86 a:!: 84y: ~! i
,I 1 1
1 ,. 1 89 I .', 1 1 1
1 1 I 1 1 I
I l~!4-1 90 1 I j.-!--88H
I I I 1 I I
-----..! ~ ~1 -.I
14- 92 -+f
I i I r+-- 93 I I !.--l.- 94 H I
Y' l I
I I' I. 951 _II i-II I .
I III 1 , I
--------------------------~'~I"\LI I 1
TR/QE 1 , II} I
I 1 1 _. 1 , I
I 1 1 I I 1
l I t---100~ 85---t ~ l I
96~ J4-99H
98~ K- i4- 97--l
-------..,r------------------------.I 1 I ;,-1_ _ _ _ _ _ __
IJEN -----J1l ,.......----1 01 ------i.~1
N
I
1: ,
I ,.. -! 102 1.-103-.,j
DDOUT----------------------~"\L~l______________________________~~
A-48 TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
ADVANCE TMS34010
INFORMATION GRAPHICS SYSTEM PROCESSOR
local bus timing parameters (continued)
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock period,
or 2tc(ICK).
TMS34010-50
TMS34010-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
Hold time of DDOUT low after DEN high,
103 th(ENH-DDL) 1.5tQ-15 1.5tQ-l0 ns
read cycle
104 tsu(DV-WL) Setup time of data out valid to W I, write cycle tQ-20 tQ-15 ns
Hold time of data out valid after W low,
105 th(WL-DV) 4tQ-20 4tQ-l0 ns
write cycle
106 tsu(WL-RH) Setup time of W low to RAS I, write cycle 2tQ-20 2tQ-l0 ns
Hold time of data out valid after RAS low,
107 th(RL-DV) 7tQ-20 7tQ-l0 ns
write cycle
Hold time of data out valid after CAS high, 2
108 th(CH-DV)
write cycle
1.5tQ -15 1.5tQ-l0 ns
o
~
109 tsu(WL-CH) Setup time of W low to CASI, write cycle 2.5tQ-25 2.5tQ-l0 ns
Hold time of data out valid after CAS low,
110 5tQ-20 5tQ-l0 ns
~
th(CL-DV)
write cycle
Hold time of data out valid after W high, a:
111
112
th(WH-DV)
write cycle
Pulse duration, W low
1.5tQ -15
2.5tQ-25
1.5tQ-l0
2.5tQ-l0
ns
ns
oLL
tw(WL)
113
114
th(CL-WL)
tsu(CAV-WH)
Hold time of W low after CAS low, write cycle
Setup time of column address valid to WI,
write cycle
3.5tQ-25
4.5tQ-30
3.5tQ-l0
4.5tQ-15
ns
ns
-w
2
(.)
115 Hold time of W low after RAS low, write cycle 5.5tQ - 25 5.5tQ-l0 ns
th(RL-WL) 2
~
Setup time of row address valid to WI,
116 tsu(RAV-WH) 6.5tQ-35 6.5tQ-15 ns
write cycle
117 tsu(ENL-WH) Setup time of DEN low to W!. write cycle tQ-20 tQ-lO ns C
118 th(WH-ENL) Hold time of DEN low after W high, write cycle 1.5tQ -15 1.5tQ -10 ns «
Setup time of DDOUT high to DENI,
119 tsu(DDH-ENL) 3tQ-20 3tQ-l0 ns
write follows read
NOTE: Advance information notices apply only to the TMS3401 0-60.
TEXAS ~ A-49
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
local bus timing: write cycle·
Q1
I Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
I
LADO-
LAD15 )[
I
ROW >G0[
I
DATA
l<
I
I I i j- 105 ..I
I I I I
I I I 1.--106-----.1 I
I I \ I I
II 104~\
RAS
I
I
\ I
I-
\
\
\
\
1\
\ I
\ \
Y I
I
I
I
I I \ \ 107 -\
I \ \
I
I I I 1--------109 _\ 14- 108 ---1I
I II \ \ I I
CAS I
I
I I
I
\ I
\ \
\ \
1\
J!" I
I
I I- I I 110 _I
I I \ I
I I 1\ t---111 ---t
I I 112 -------.I I
It-
I
II
IN
I
I
I
I
I
I
r I N J I I
I
I I
r
\
\ !-
I
r 113 ------f
~I
I
I
I r r- I
I
114
\ I
I I- 115
I
----t I
I- 116
14117../
\
----fl14- 118 ---.I
\ I
DEN
IX J!
I ..
I
119 -,r
DDOUT
!
A-50 TEXAS . .
INSTRUMENTS
POST OFFice BOX 1443 • HOUSTON. TeXAS 77001
ADVANCE TMS34010
INFORMATION GRAPHICS SYSTEM PROCESSOR
local bus timing parameters (continued)
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock period,
or 2tc(ICK).
TMS34010-50
TMS34010-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
120 t su (HRV-CK2H) Setup time of HOLD valid to LCLK2t 50 t 40t ns
121 th(CK2H-HRV) Hold time of HOLD valid after LCLK2 high ot ot ns
Setup time of HLDA/EMUA output valid
122 t su (HKV-CK2L) before LCLK21 to-20 to-10 ns
123 th(CK2L-HKL) Hold time of HLDA/EMUA low, after LCLK2 low to-15 to-15 ns
Delay from LCLK2 high to LAD pins high
124 td(CK2H-DZ) 30 t 30 t ns
impedance, bus release
125 tsu(RH-CK 1 H) Setup time of RAS high to LCLK 1 t to-20 to-10 ns
126 thICK 1H-RH)
Hold time of RAS driven high after LCLK 1
to-lOt to-lOt ns z
high, bus release
Delay from LCLK2 high to RAS high impedance,
o
~
127 td(CK2H-RZ) 30 t 30 t ns
bus release
128 t su (ALH-CK2H) Setup time of LAL high to LCLK2t to-20 to-10 ns
Hold time of LAL driven high after LCLK 1 I, :?i
129 thICK 1L-ALH)
bus release
-5 t -5 t ns a:
130 td(CK 1L-ALZ)
Delay from LCLK1 low to LAL high impedance,
30 t 30 t ns
oLL
bus release
131 tsu(CH-CK 1 H)
Setup time of CAS, W, and TR/OE high
to LCLK1t
0. 5tO-15 0.5tO -10 ns -w
Z
132 thICK 1 H-CH)
Hold time of CAS, W, and TR/OE
to-lOt to -lOt ns U
high after LCLK 1 high, bus release Z
c~
Delay from LCLK2 high to CAS, W, and TR/OE
133 td(CK2H-CZ) 30 t 30 t ns
high impedance, bus release
134 ns
135
tsu(ENH-CK2H) Setup time of DEN or DDOUT high to LCLK11
th(CK2H-ENH)
Hold time of DEN and DDOUT high after
to-20
to-lOt
to-lO
to-10 t ns
«
LCLK 1 I, bus release
Delay from LCLK 1 low to DEN and DDOUT
136 td(CK 1L-ENZ) 30 t 30 t ns
high impedance, bus release
Hold time of LAD bus high impedance
137 th(CK2H-DZ) -5 t -5 t ns
after LCLK2 t
Hold time of RAS, CAS, W, LAL, and TR/OE
138 th(CK2H-RZ) -5 t -5 t ns
high impedance after LCLK 11
Delay from LCLK1 high to RAS, CAS, W, LAL,
139 td(CK 1 H-RH) 30 30 ns
and TR/OE driven high, resume bus control
Hold time of RAS high after LCLK2 high,
140 th(CK2H-RH) to-15 to-lO ns
resumes bus control
Hold time of CAS, W, and TR/OE high
141 th(CK2H-CH) -5 t -5 t ns
after LCLK2 high, resume bus control
NOTE: Advance information notices apply only to the TMS3401 0-60.
tHOLD is a synchronous input sampled during the low-to-high transition of LCLK2. The specified setup and hold times must be met for
the device to operation properly.
tThese values are derived from characterization and are not tested.
TEXAS • A-51
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
GSP releases control of local bus
04 01 04
I 01 02 03 04 02 03
LCLK1
_----J
/
\------"IIA I I
I I
~--
I I
LCLK2 \
'------.......:II!:I I
{ ~II
I\: I J
If,
I ~121 II II II
\1.
14-120-.1 I
y I I
j j \!!I I II
!! /
II
14-122~ I I I I I I I
I 123....J.......f I I I I I I
I I I I ! I I I
HLDA/EMUA '\. YI I II
124!
II
~ -;
III
I i\ '-----
I I I I , I
I , I I 'I
LADO-LAD15
I!I'
!-_---t....1 r---1~6~1
125 ....
i H~1271!!I I HI-Z--
I I I I aJ I ,
RAS
_ _ _ _ _ _ _ _ _ _ _ _ _ _.....J/Jt- II II II II '"1,L...L...-..-i-129
I HI-Z--
128 II... .../ I j-j-I
I 'I I
I f-.iH-
I
I 1I 130
-----------------~I \ - 1 3 2 H
!If
I I'
133-+--,
I
I I ~HI-Z-
III
131~ I I, I t--*136
, II I I
CAS. W
TR/OE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--',
7 I
'1d I
~13J---.j
I HI-Z--
I
, II
134~ II
, 'I
DEN. DDOUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~7 "L- HI-Z -
A-52 TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
GSP resumes control of local bus
Q4 I Q1 I Q2 I Q1 I Q2 I Q3 I Q4 I
LCLK1 ~
\.--.- - - - - '
I \---
LCLK2 /
\'----
HLDA/EMUA \ _____...... I_____-J/ ~!
I' II -II, I' '-137
LADO-LAD15 - - - - - - - H , - z - - - - - - - - - i - l - + - ! - - t l - + I - { \ , - - - - - - -
138--.1 114-', I ~-----
~140
, ,I ,
I"
139--t,'--' , .
'
RAS - - - - - - - H I - Z - - - - - - - - - + ! ---T'1l¥ 'I '\
I, , 1:42 -.:
-+I
I""'" '-----
114-143
" II,
DEN, DDOUT -
-------HI-Z---------+-! -+I_--"I.J~------
I ,
138--1 Ire- I ,
TR/QE
139--"l--J
',';;
CAS. Vii - - - - - - - H I - Z - - - - - - - - - + . . , . . . . . . . , . , , ! 1 '
138 --! ,~
\ '-_____
14-141
139-1,,-
LAL - - - - - - - H I - Z ---------~~~-----------
"r
TEXAS
INSTRUMENTS
'1!1 A-53
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010 ADVANCE
GRAPHICS SYSTEM PROCESSOR INFORMATION
local bus timing parameters (continued)
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock cycle,
or 2tc(ICK).
TMS34010-50
TMS34010-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
Hold time of DEN, DDOUT high impedance
142 th(CK2H-ENZ) -5 t -5 t ns
after LCLK2 high, resume bus control
Delay from LCLK2 high to DEN, and DDOUT
143 td(CK2H-ENH) 30 30 ns
driven high, resume bus control
Setup time of row address valid to RAS I,
144 tsu(RAV-RL) 2tQ-25 2tQ-15 ns
CAS-before-RAS refresh
Hold time of row address valid after RAS low,
145 th(RL-RAV) tQ-20 tQ-10 ns
CAS-before-RAS refresh
Pulse duration, RAS high, start of
» 146 tw(RH)
CAS-before-RAS refresh
4tQ-20 4tQ-10 ns
~ 147 twIRL)
Pulse duration, RAS low, CAS-before-RAS
4tQ-20 4tQ-10 ns
»
z 148 tsu(RAV-ALL)
refresh
Setup time of row address valid to LALI,
CAS-before-RAS refresh
tQ-20 tQ-15 ns
(') Hold time of row address valid after LAL low,
m 149 th(ALL-RAV)
CAS-before-RAS refresh
2tQ-20 2tQ-10 ns
Hold time of RAS high after LAL low,
Z 150 th(ALL-RH)
CAS-before-RAS refresh
tQ-20 tQ-10 ns
"TI
o 151 tsu(RH-ALH)
Setup time of RAS high to LALf,
tQ-20 tQ-10 ns
JJ CAS-before-RAS refresh
S 152 tsu(ALH-CL)
Setup time of LAL high to CASI,
CAS-before-RAS refresh
tQ-20 tQ-10 ns
~ 153 tsu(CL-ALL)
Setup time of CAS low to LALI,
tQ-20 tQ-1O ns
o CAS-before-RAS refresh
z 154 tsu(RH-CL)
Setup time of RAS high to CASI,
CAS-before-RAS refresh
2tQ-20 2tQ-10 ns
Setup time of CAS low to RASI,
155 tsu(CL-RL) 2tQ-20 2tQ-10 ns
CAS-before-RAS refresh
Hold time of CAS low after RAS low,
156 th(RL-CL) 4.5tQ-25 4.5tQ-10 ns
CAS-before-RAS refresh
Pulse duration, CAS low,
157 tw(CL) 6.5tQ-25 6.5tQ-1P ns
CAS-before-RAS refresh
Setup time of CAS high to RASI,
158 tsu(CH-RL) 3.5tQ -15 3.5tQ -10 ns
CAS-before-RAS refresh
NOTE: Advance information notices apply only to the TMS34010-60.
tThese values are derived from characterization and are not tested.
A-54 TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
GRAPHICS SYSTEM PROCESSOR
TMS34010
CAS-before-RAS DRAM refresh cycle timing
04 01 I 02 03 04 I 01 02 03 04 01 I
l~~~~- _ _ _ _ _ _ -J)[ ROW 1<'--_____ x=
U_N_D_E_FIN_E_D_ _ _ _ _......
~144---./ ~145
RAS"
Ji
I
I
I
I
I
I
N I I-
~
-.j1
1 4 7 - - - - - - i..
I
JtTI
i ! r------
I I ~
___~I--------~-
,_ 146 .. I 1 I I
I 148~ II I I
I
I
15o~1
'---149----l
I
151 I
~I
!II
I
I
II
7.
/ I
tI~I;.'I __I I
I!-I 1....._ _ _ _ _ _ _ _ _ _ _ _ _----""1-
I I -'-----! II
153 I
II I
152~1
1---155~ I
II 63~
I
'--154-----.1 I I (0011-.....-----156 - - - - -.......
-.jll
I I_ I ~1 I
CAS -~--""""'i ---"'lIi\1 I
157 - - - - - - - - - - i..
yr-------
(001(0011-----158 - - - - - - i....1
TEXAS • A-55
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010 ADVANCE
GRAPHICS SYSTEM PROCESSOR INFORMATION
local bus timing parameters (continued)
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock cycle,
or 2tc(lCK).
TMS34010-50
TMS34010-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
Hold time of RAS high after LCLK2 high, all
159 th(CK2H-RH) cycles except internal and to-15 to-lO ns
CAS-before-RAS refresh
Setup time of RAS low to LCLK2~, all cycles
160 t su(RL-CK2L) to-20 to-10 ns
except internal and CAS-before-RAS refresh
Hold time of RAS high after LCLK 1 low,
161 th(CK1L-RH) to-15 to-10 ns
CAS-before-RAS refresh
Setup time of RAS low to LCLK 1 i,
162 tsu(RL-CK 1 H) to-20 to-10 ns
CAS-before-RAS refresh
Hold time of RAS low after LCLK 1 low,
163 thICK 1L-RL) to-15 to-10 ns
all cycles except internal
Setup time of RAS high to LCLK 1 i,
164 tsu(RH-CK 1 H) to-20 to-10 ns
all cycles except internal
Hold time of LAL high after LCLK2 low,
165 th(CK2L-ALH) 0. 5tO-15 0.5tO -10 ns
all cycles except internal
Setup time of LAL low to LCLK 1 i,
166 tsu(ALL-CK 1H) 0. 5tO-15 0. 5tO-10 ns
all cycles except internal
-:2
."
167 th(CK2L-ALL)
Hold time of LAL low after LCLK2 low,
all cycles except internal
Setup time of LAL high after LCLK2i,
to-15 to-lO ns
o 168 tsu(ALH-CK2H)
all cycles except internal
to-20 to-lO ns
:l:J 169
Hold time of CAS high after LCLK 1 high,
to-15 to-lO ns
S thICK 1H-CH)
CAS-before-RAS refresh
~
Setup time of CAS low to LCLK!,
170 t su (CL-CK1L) to-20 to-lO ns
CAS-before-RAS refresh
o Hold time of CAS high after LCLK2 low,
ns
:2 171 th(CK2L-CH) cycles except internal, to-15 to-lO
DRAM refresh and CAS-before-RAS refresh
Setup time of CAS low to LCLK2i,
172 t su(CL-CK2H) all cycles except internal, DRAM refresh, to-20 to-10 ns
and CAS-before-RAS refresh
Hold time of CAS low after LCLK2 low, all
173 th(CK2L-CL) 0. 5tO-15 0. 5tO-10 ns
cycles except internal and DRAM refresh
Setup time of CAS high to LCLK 1 i, all
174 tsu(CH-CK 1 H) 0. 5tO-15 0.5tO -10 ns
cycles except internal and DRAM refresh
Hold time of W high after LCLK1 high,
175 thICK 1H-WH)TR to-15 to-10 ns
shift register transfer
Setup time of W low to LCLK1!,
176 tsu(WL-CK 1 LlTR to-20 to-10 ns
shift register transfer
NOTE: Advance inforrpation notices apply only to the TMS34010-60.
A-56 TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
ADVANCE GRAPHICS SYSTEM PROCESSOR
INFORMATION TMS34010
local bus timing parameters (concluded)
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock cycle,
or 2tc(lCK).
TMS34010-50
TMS340 10-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
Hold time of W low after LCLK 1 low,
177 thICK 1 L-WL) to-15 to-1O ns
shift register transfer
Setup time of W high to LCLK 1 t,
178 tsu(WH-CK 1 H) to-20 to-10 ns
shift register transfer
179 th(CK1 H-WH) Hold time of W high after LCLK1 high, write to-15 to-1O ns
180 tsu(WL-CK 1 L) Setup time of W low to LCLKU, write to-20 to-1O ns
11:l1 th(CK2L-WL) Hold time of W low after LCLK2 low, write 0. 5tO-15 0. 5tO-10 ns
182 tsu(WH-CK 1H) Setup time of W high to LCLK 1 t, write 0. 5tO-15 0.5tO -10 ns
Hold time of TR/OE high after LCLK1 high,
183 th(CK1L-TRH) to-15 to-1O ns
shift register transfer
2
184 tsu(TRL-CK 1 H)
Setup time of TR/OE low to LCLK1~,
shift register transfer
to-20 to-1O ns o
185 th(CK2H-TRL)
Hold time of TR/OE low after LCLK2 high,
shift register transfer
to-15 to-1O ns
t:c
Setup time of TR/OE high to LCLK2~, ~
186 t su (TRH-CK2L)
shift register transfer
to-20 to-10 ns
a::
187 th(CK1 H-OEH) Hold time of TR/OE high after LCLK 1 high, read to-15 to-1O ns oLL
188 t su (OEL-CK1 L) Setup time of TR/OE low to LCLKH, read to-20 to-1O ns
189 Hold time of TR/OE low after LCLK2 low, read 0.5tO-15 0. 5tO-10 ns
2
th(CK2L-OEL)
190 tsu(OEH-CK 1 H) Setup time of TR/OE high to LCLK 1t, read 0. 5tO-15 0. 5tO-10 ns w
191 th(CK2L-ENH) Hold time of DEN high after LCLK2 low, write to-15 to-1O ns ()
192 tsulENL-CK2H) Setup time of DEN low to LCLK2t, read to-20 to-1O ns 2
193
194
th(CK1 H-ENL)
tsu(ENH-CK1 L)
Hold time of DEN low after LCLK 1 high, write
Setup time of DEN high to LCLKH, write
to-15
to-20
to-10
to-10
ns
ns
C
~
195
196
th(CK1 H-ENH)
tsu(ENL-CK 1 L)
Hold time of DEN high after LCLK1 high, read
Setup time of DEN low to LCLKH, read
to-15
to-20
to-1O
to-1O
ns
ns
«
197 th(CK2L-ENL) Hold time of DEN low after LCLK2 low, read 0. 5tO-15 0. 5tO-10 ns
198 tsu(ENH-CK1 HI Setup time of DEN high to LCLK1t, read 0. 5tO-15 0. 5tO-10 ns
199 th(CK2L-DDH) Hold time of DDOUT high after LCLK2 low, read to-15 to-1O ns
200 t su (DDL-CK2H) Setup time of DDOUT low to LCLK2t, read to-20 to-1O ns
201 thICK 1 H-DDL) Hold time of DDOUT low after LCLK1 high, read to-15 to-1O ns
202 tsu(DDH-CK 1 L) Setup time of DDOUT high to LCLK 1 ~, read to-20 to-10 ns
Hold time of LAL high after LCLK2 high,
203 th(CK2H-ALH) to-15 to-1O ns
CAS-before-RAS refresh
Setup time of LAL low to LCLK2~,
204 tsu(ALL-CK2L) to-20 to-10 ns
CAS-before-RAS refresh
NOTE: Advance information notices apply only to the TMS3401 0-60.
TEXAS ~ A-57
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34D1D
GRAPHICS SYSTEM PROCESSOR
local bus timing: relationship of control signals to clocks
03 I 04 01 I 02
lClK1 J tL
I
I
I
I
lClK2 ---;r------'I:
159 ,
I.
\t
!~183 '
¥ ,
I
I
~ :VII
I 11t----i-188 !_I....:.J /-+190
'
II 1---i-184 I 187 ~, 186...... r-!"'" " I
I , I , L:".185~ I !-r189
II
I I
~---'--+,"""",--!-I-----I--
~----'-----'-I--r--=----~=---""I~
I I r--r
I
192 I
'L....-i-193
I
I
t-+-
I, I
I i-----t-194
p', !
198--1
I, R'- .~'I
I 195 I 197
!-----+-196
1-4-:I
-1 V Ir
191~
,r--t-200
L
r 202 ~
I
OOOUT -------------1'1 199 -+----i r
201
r
~t----
I
A-58 TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
ADVANCE TMS34010
INFORMATION GRAPHICS SYSTEM PROCESSOR
video interface timing parameters
The timing parameters for TMS3401 0 video interface signals are shown in the next three tables and diagrams.
The video interface includes the following TMS3401 0 pins: VCLK (video input clock), BLANK
(blanking), HSYNC (horizontal sync, bidirectional), and VSYNC (vertical sync, bidirectional). HSYNC and
VSYNC are inputs if external sync mode is enabled; otherwise they are outputs.
video input clock timing parameters
TMS34010-50
TMS34010-40
NO. PARAMETER TMS34010-60 UNIT
MIN MAX MIN MAX
205 tc(VCK) Period of video input clock VCLK 100 80 ns
206 tw(VCKH) Pulse duration of VCLK high 40 30 ns
207 tw(VCKL) Pulse duration of VCLK low 40 30 ns
208 tt(VCK) Transition time (rise and fall) of VCLK 5t 5t ns
NOTE: Advance information notices apply only to the TMS3401 0-60.
tThis value is determined through computer simulation and is not tested.
2:
video input clock timing o
I~
1-- --1206
205 -,
208-1 ~ 208 - - ; ~
fi
:!:
Y
J4--207----.1 1
VCLK J \l 'i~I________~Jr~!------ a:
oLL
video interface timing parameters: outputs 2:
NO. PARAMETER
TMS34010-40
TMS34010-50 w
TMS34010-60 UNIT (.)
MIN MAX MIN MAX
2:
~
209 td(VCKL-HSL) Delay from VCLK low to HSYNC, VSYNC, or BLANK low 30 30 ns
210 td(VCKL-HSH) Delay from VCLK low to HSYNC, VSYNC, or BLANK high 30 30 ns
211 th(VCKL-HSH) Hold time of HSYNC, VSYNC, or BLANK high after VCLK~ C
«
0 0 ns
212 th(VCKL-HSL) Hold time of HSYNC, VSYNC, or BLANK low after VCLK~ 0 0 ns
NOTE: Advance information notices apply only to the TMS34010-60.
video output timing
VCLK ~ / j\ / \---
I ~209--1 I ~210
-211~ I 212~1I . 1
HSYNC,
VSYNC
II
I I
! I
'i I I yl
I I I
....- - - - - - - - - - -
(OUTPUTS) I I !'-----------II*I-
I ~209...J I ~210
14-211--11 212 ~ I
\~I 11"~-------------
BLANK \ ¥
TEXAS • A-59
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS34010 ADVANCE
GRAPHICS SYSTEM PROCESSOR INFORMATION
video interface timing: external sync inputs
TMS34010-50
NO. PARAMETER TMS34010-40 TMS34010-60 UNIT
MIN MAX MIN MAX
213 tsu(HSV-VCKH) Setup time of HSYNC, VSYNC valid to VCLKi 20t 20t ns
214 th(VCKH-HSV) Hold time of HSYNC, VSYNC valid after VCLK high 20t 20t ns
215 tsu(HSH-VCKH) Setup time of HSYNC, VSYNC high to VCLK: 20~ 20~ ns
NOTE: Advance information notices apply only to the TMS3401 0-60.
tSpecified setup and hold times on asynchronous inputs are required only to guarantee recognition at indicated clock edge.
~This value is determined through computer simulation.
VCLK
,
I
1
,
,
,
j4--214-----t 1 , !4-215~
» HSYNC,
VSYNC -------------~~~ill
, '--213~
___________________________________ r
;.---214------.1
},T
¥
.1 _ _ _ _ __
~ (INPUTS) \.
»
2
(NOTE 1) (NOTE 2)
n NOTES: 1. If the falling edge of the sync signal occures more than th(SV-VCH) past VCLK edge A, and at least tsu(SV-VCH) before edge
B, the transition will be detected at edge B instead of edge A.
m
-2
'"T1
2. If the rising edge of the sync signal occurs more than th(SV-VCH) past VCLK edge C, and at least tsu(SV-VCH) before edge
D, the transition will be detected at edge D instead of edge C.
o
::xJ
S
~
o
2
A-60 TEXAS.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS34010
GRAPHICS SYSTEM PROCESSOR
MECHANICAL DATA
~0,25 (0.010) R MAX
"'" IN 3 PLACES
1,27 (0.050) T.P.
(SEE NOTE B)
23,62 (0.930) 25,27 (0.995)
23,11 (0.910) 25,02 (0.985)
(AT SEATING PLANE)
~ 24'33~0'95.)ISEE
I 0,94 (0.037) R
I 0,69 (0.027)
NOTE A)
1,22 (0.048) x 45c
1,07 (0.042)
I 24,13 (0.950)
I 25,27 (0.995)
SEATING PLANE
25,02 (0.985)
lr
0,81 (0.032)
0,66 (0.026)
~"1't 10.0.0) MIN
0,51 (0.020)
0,36 (0.014) JL'
I
~0,64 (0.025) MIN
LEAD DETAIL
NOTES: A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by this dimension.
B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
TEXAS. A-61
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
Printed in U.S.A.
SPVS002B
Appendix B
System Design Considerations
Please read these emulation guidelines before starting a system design that
requires use of an XDS emulator. In-circuit emulators place added constraints
on the system hardware and software design; the XDS TMS34010 emulator
minimizes these constraints as much as possible. Many of the emulator signals
come directly from the device itself keeping the delays to a minimum. The
information provided in this appendix will allow your design to be compatible
with the TMS3401 0 XDS emulator.
Topics in this section include:
Section Page
B.1 Pin Loading ................................................................................................ 8-2
B.2 Signal Timing and Delay .......................................................................... B-4
B.3 Transmission Line Phenomena ................................................................ 8-5
B.4 Host Port Operation .................................................................................. 8-5
B.5 Reset Buffering .......................................................................................... 8-5
B.6 Local Ready Timing .................................................................................. B-6
B.7 Memory Substitution ................................................................................ 8-6
B.8 Write Protecting Memory ......................................................................... 8-6
B.9 Tracing and Cache .................................................................................... 8-7
8-1
Appendix B - System Design Considerations
B.1 Pin Loading
The loading provided by the emulator differs from the device loading; in some
cases, this additional loading can cause a system to fail or pass. For instance,
within the emulator the VCLK and INCLK clocks are buffered by an AS157
device. If the target clocks are driven by an AS driver over a long distance, the
system may operate satisfactorily with the emulator's loading. When the de-
vice is used, the clocks can ring, causing the system to fail.
To minimize ringing caused by the emulator, all the outputs and I/Os are ter-
minated with 22-ohm series resistors. Most of the signals are connected di-
rectly to the target connector to minimize the added delays. Table 8-1 shows
the device loads that are placed on the emulator pins.
In Table 8-1, pin refers to the emulator target pin. An arrow (-+) indicates
that the specified device drives the device(s) it the arrow points to. Devices
in parallel are separated by commas; devices in series are in brackets. As an
example, consider LADO; the pin connects to a 22-ohm series resistor, and the
other side of the resistor is connected to an ALS245, AS573, and the
TMS34010.
Table 8-1. Loading
Pin Signal I/O Loading
1 Vss
2 RUN/EMU pin, 4.7KPU, ALS08
3 "FfrnET I pin, 4.7KPU, TIBPAL-12, TMS9901, ALS574, AS257
-+ [ALS08 + AS04 + ALS08 + AS874 + AS04] -+
TMS34010
4 VCLK I pin, 330PU, 510PD, A5157 -+ TMS3401 0
5 INCLK I pin -+ [AS157] -+ TMS34010
6 ""CTNT1 I pin, 4.7KPU -+ [AS257] -+ TMS34010
7 LlNT2 I pin, 4.7KPU -+ [AS257] -+ TMS34010
8 HOLD I pin, 4.7KPU, AS874, TMS34010
9 LRDY 0 pin, 4.7KPU, [TIBPAL-12] -+ TMS34010
10 LADO I/O pin -+ [22S] -+ ALS245, AS573, TMS34010
11 LAD1 I/O pin -+ [22S] -+ ALS245, AS573, TMS34010
12 LAD2 I/O pin -+ [22S] -+ ALS245, AS573, TMS3401 0
13 LAD3 I/O pin -+ [22S] -+ ALS245, AS573, TMS34010
14 LAD4 I/O pin -+ [22S] -+ ALS245, AS573, TMS34010
15 LAD5 I/O pin -+ [22S] -+ ALS245, AS573, TMS34010
16 LAD6 I/O pin -+ [22S] -+ ALS245, AS573, TMS3401 0
17 LAD7 I/O pin -+ [22S] -+ ALS245, AS573, TMS3401 0
18 V"SS
19 LAD8 I/O pin -+ [22S] -+ ALS245, AS573, TMS3401 0
PD - Pull down
PU - Pull up
S - Series resistor
[] - Devices in series
pin - Emulator target cable pin
B-2
Appendix B - System Design Considerations
Table B-1. Loading (Continued)
Pin Signal I/O Loading
20 LAD9 I/O pin -+ [225] -+ AL5245, A5573, TM53401 0
21 LAD10 I/O pin -+ [225] -+ AL5245, A5573, TM53401 0
22 LAD11 I/O pin -+ [225] -+ AL5245, A5573, TM53401 0
23 LAD12 I/O pin -+ [225] -+ AL5245, A5573, TM53401 0
24 LAD13 I/O pin -+ [225] -+ AL5245, A5573, TM53401 0
25 LAD14 I/O pin -+ [225] -+ AL5245, A5573, TM53401 0
26 LAD15 I/O pin -+ [225] -+ AL5245, A5573, TM534010
27 Vee
28 LCLK1 0 TM534010, A5244, A504 -+ [225] -+ pin
29 LCLK2 0 TM534010, A5244 -+ [225] -+ pin
30 H5YNC I/O TM534010, AL5573 -+ [225] -+ pin
31 V5YNC I/O TM534010, AL5573 -+ [225] -+ pin
32 BLANK 0 TM534010, AL5573 -+ [225] -+ pin
33 HLDA/EMU 0 TM534010 -+ [A508 + 105] -+ pin
34 LAL 0 TM534010, 100KPU, A511, A504 -+ [225] -+ pin
35 VSS
36 DDOUT 0 TM534010 -+ [TIBPAL-12 + 225] -+ pin
37 DEN 0 TM534010 -+ [TIBPAL-12 + 225] -+ pin
38 ~ 0 TM534010 A5157, 100KPU -+ [225] -+ pin
39 ~ 0 TM534010 -+ [TIBPAL-12 + 225] -+ pin
40 WRITE 0 TM534010 -+ [TI B PAL-1 2 + 225] -+ pin
41 TR/QE 0 TM534010 -+ [TIBPAL-12 + 225] -+ AL244, pin
42 HINT 0 TM534010 AL5244 -+ [225] -+ pin
43 HRDY 0 TM534010 -+ [A508 + 105] -+ pin
44 HAD15 I/O TM534010 -+ [225] -+ pin
45 HAD14 I/O TM534010 -+ [225] -+ pin
46 HAD13 I/O TM534010 -+ [225] -+ pin
47 HAD12 I/O TM534010 -+ [225J -+ pin
48 HAD11 I/O TM534010 -+ [225] -+ pin
49 HAD10 I/O TM534010 -+ [225] -+ pin
50 HAD9 I/O TM534010 -+ [225J -+ pin
51 HAD8 I/O TM534010 -+ [225J -+ pin
52 VSS
PO - Pull down
PU - Pull up
5 - 5eries resistor
[] - Devices in series
pin - Emulator target cable pin
B-3
Appendix B - System Design Considerations
Table 8-1. Loading (Concluded)
Pin Signal I{O Loading
53 HAD7 I{O TMS34010 -+ [22S] -+ pin
54 HAD6 I{O TMS34010 -+ [22S] -+ pin
55 HAD5 I{O TMS34010 -+ [22S] -+ pin
56 HAD4 I{O TMS34010 -+ [22S] -+ pin
57 HAD3 I{O TMS34010 -+ [22S] -+ pin
58 HAD2 I{O TMS34010 -+ [22S] -+ pin
59 HAD1 I{O TMS34010 -+ [22S] -+ pin
60 HADO I{O TMS34010 -+ [22S] -+ pin
61 Vee
62 'RU15S I pin, 100KPU, TMS34010
63 ~ I pin, 100KPU, TMS3401 0
64 tm'EAI5 I pin, 100KPU, ALS573, TMS3401 0
65 HWmTE I pin, 100KPU, AS573, TMS3401 0
66 ~ I pin, 4.7KPU -+ [AS232 + AS08 + TMS34010] -+
ALSOO,ALS74,TIBPAL-1~ LS02
67 HFSO I pin, 100KPU, ALS573, TMS3401 0
68 HFS1 I pin, 1OOKPU, ALS573, TMS3401 0
PO - Pull down
PU - Pull up
S - Series resistor
[] - Devices in series
pin - Emulator target cable pin
8.2 Signal Timing and Delay
The target cable delays all signal timings by approximately four nanoseconds;
the following signals impose an additional delay:
Signal Delay Signal Delay
VCLK 6ns CAS 12ns
INCLK 6ns WRITE 12ns
LlNT1 6ns TR/QE 12ns
LlNT2 6ns LRDY 12ns
DDOUT 12ns HRDY 6ns
DEN 12n8 HCS 12ns
Remember these additional delays when you are calculating system timings.
The cable delays should cancel out when comparing the signal to the clock;
for instance, the clock is delayed by four nanoseconds and so is the address.
The problem comes from setup times required by the TMS34010. For in-
stance, CAS out is delayed by 16 nanoseconds and data-in is delayed by four
nanoseconds. This 20 nanoseconds must be added to the memory access
time. For this reason, it is important not to use CAS to control LRDY. Both
B-4
Appendix B - System Design Considerations
LRDY and CAS are delayed by 12 nanoseconds; combined, this adds 24 na-
noseconds to the LRDY setup, which violates the device requirements.
B.3 Transmission Line Phenomena
Since the XDS target cable is approximately 20 inches long, use of advanced
CMOS or fast/advanced Schottky-TIL may cause line reflections (ringing
above input thresholds) on input lines to the XDS. Series termination resistors
(22 to 68 ohms) can help to eliminate this problem. In some cases where
significant additional signal length is added to XDS outputs, the series resis-
tors on the XDS may not be sufficient to control reflections. In this case, ad-
ditional corrective actions may be necessary.
B.4 Host Port Operation
The emulator host port supports two modes of operation:
• The first mode blocks the host port while the emulator is in control mode
(that is, not running) and when the XDS emulator requires its internal
TMS34010 as a resource. Systems that access the host port when in
control mode have H R DY inactive when they start an access and remain
inactive until the emulator is put into run mode. This is a problem for
pes because they use DMA cycles to perform DRAM refresh and are
prevented from performing any further memory cycles.
• The second mode of operation allows host accesses while the emulator
is in control mode. When the emulator is halted, a snapshot is taken of
the I/O registers before transferring control to the user. While halted, the
host has access to the TMS34010's I/O registers and memory space.
Data read from the I/O and memory space may not represent the actual
data as the host can be changing the data through the host port. Data
written through the XDS user interface to any I/O registers or memory
locations used by the host port can cause unpredictable results. This
mode is the typical dual-allocation problem that is prevalent in multiport
memory systems.
B.5 Reset Buffering
The RESET input from the target system is buffered so that reset cannot abort
a memory cycle that is in progress. This is necessary to prevent corruption of
the substitution memory. Reset is AN Ded with RAS and CAS and clocked on
the rising edge of LCLK1. If reset is active and RAS and CAS are inactive, then
reset is applied to the processor. While the RESET input is active, internal
emulator logic provides CAS-before-RAS refreshes for emulator memory, but
not for your system memory; target memory is not refreshed during reset.
Therefore, you shouldn't perform a target reset following a download of object
code into target memory, because this may destroy the contents of target me-
mory.
8-5
Appendix B - System Design Considerations
If the target system also generates a reset during the emulator-TMS3401 0 re-
set, and HCS is high (which, under normal circumstances, would halt the
TMS34010), the emulator reset takes precedence and does not halt the
TMS34010.
B.6 Local Ready Timing
The ready logic requires special attention; the target system should not depend
on having CAS to clear ready. This can cause a deadlock situation if the me-
mory is write protected. In this case, the emulator blocks the CAS output to
the target and the target system is locked waiting for CAS to release LRDY.
Thus, if you are working with the emulator and write-protecting memory, your
ready logic should use a combination of RAS and clock delays instead of CAS.
B.7 Memory Substitution
The 256K bytes of substitution memory is implemented with two banks of
64Kx4 DRAMs. This memory can be mapped on 2K word boundaries. The
memory can be selected as write-only using the memory protect feature de-
scribed below. When a memory access is made that is mapped into substi-
tution memory the signals are modified as follows:
• DEN, CAS, WR, and TR/OE are blocked from going active.
• Ready is accepted from the target to allow adding wait states to the
substitution memory.
Ready should not be controlled by DEN, CAS, WR or TR/OE because these sig-
nals are blocked and a deadlock condition would take place.
All the other signals operate as though a standard memory cycle were taking
place. Be aware that when you're using substitution memory, it can only be
accessed by the processor and host port and cannot be accessed when the
TMS34010 is put into hold. The target system should not drive the LAD bus
unless CAS and DEN are active.
B.8 Write Protecting Memory
The emulator allows memory to be write-protected in blocks of 2048 words.
The memory can be external memory as well as the substitution memory. The
memory write operations are inhibited by blocking the CAS output. As with
the substitution memory, ready should not be controlled by CAS because a
deadlock condition will take place. External system memory is only write
protected from CPU and host accesses and not DMA accesses initiated with
a HOLD/HOLDA sequence.
8-6
Appendix B - System Design Considerations
B.9 Tracing and Cache
Please note that the breakpoint trace and timing capabilities are used to mon-
itor bus activity. The TMS3401 O's pipelined-cache-based architecture fetches
the current instruction and the three associated instructions in the cache sub-
segment when a cache miss occurs. This is indicated as four fetches even
though only one instruction may be executed. Also, when the cache is ena-
bled, code already located in cache does not generate any instruction-fetch
activity on the memory bus when it is executed. If you want to create a com-
plete trace history, run the TMS34010 with cache disabled. By disabling
cache, all instructions executed are moved over the external memory bus every
time they are executed, allowing them to be captured in the trace buffer.
B-7
Appendix B - System Design Considerations
B-8
Appendix C
Software Compatibility with Future GSPs
This appendix provides guidelines for writing TMS34010 programs that will
be compatible with future versions of TMS340xO devices. In some cases,
following these guidelines may not produce the fastest TMS34010 code;
however, your code should run without modification on future GSPs.
These guidelines cover several areas:
Section Page
C.1 General Guidelines .................................................................................... C-2
C.2 Graphics Compatibility ............................................................................. C-2
C.3 Memory Map Compatibility ..................................................................... C-3
C.4 I/O Register and Video Timing Compatibility ....................................... C-4
C.5 Interrupts Compatibility ............................................................................ C-4
C.6 Host Interface Compatibility .................................................................... C-5
C-1
Appendix C - Software Compatibility with Future GSPs
C.1 General Guidelines
• Future GSPs may have different instruction execution times than the
TMS34010 has; therefore, timing loops based on TMS3401 0 instruction
execution time may not be compatible with future GSPs. Even if future
devices are generally faster than the TMS3401 0, specific cases may run
slower. To avoid this, timing could be based on DPYINT (the display
interrupt) or on an external time source (via L1NT1 or L1NT2). Note that
if you use DPYINT, you must consider different display resolutions and
refresh rates.
• For optimum performance on future GSPs, align data on 32-bit bound-
aries (instead of 16-bit boundaries). This could reduce the number of
memory cycles for future GSPs, and in most cases will have little impact
on the TMS3401 O. In particular, keeping the stack pointer (SP) aligned
to 32-bit boundaries will speed up subroutine calls and interrupts.
• Future GSPs may use the reserved bits in the status register and in the
I/O registers. During context switches, the values of reserved bits should
be saved and restored as if they were valid; do not assume that these bits
have known values. If you don't follow this guideline, your code may
inadvertently enable/disable new options or features.
Unless otherwise noted in this user's guide, when reserved bits have a
value of 0, they will cause future GSPs to behave like the TMS3401 O.
However, you should not set these bits to 0, because this may incorrectly
reset a bit.
• Use the REV instruction to determine which version of the GSP you are
using. You can use this instruction to decide whether to enable or dis-
able version -dependent code.
• Instruction cache statistics characteristics (including cache size, loading
order, number of bytes loaded per cache miss, and time per cache fetch)
may differ between versions of GSPs. Code should not depend on the
state of any of these characteristics.
C.2 Graphics Compatibility
• Extend the values in the COLORO and COLOR1 registers to 32 bits. The
TMS34010 uses only the 16 LSBs of these registers; future GSPs may
use all 32 bits.
• Treat the PMASK register as a 32-bit register. The TMS3401 0 uses only
the 16 bits at address OC0000160h; however, future GSPs may also use
the 16 bits at address OC0000170h. \AJhenever you save/restore the
value at OC0000160h, you should also save/restore the value at
OC0000170h.
• When you save/restore the graphics context (this includes all graphics
operations control registers), you should also save/restore the I/O reg-
C-2
Appendix C - Software Compatibility with Future GSPs
isters that are reserved in the TMS34010 I/O register map (addresses
OC00001 30h-oC00001 AOh) .
• At initialization, load register B13 with all 1 s. Future GSPs may use B13
as a pattern register; if you don't set B13 to the suggested value, future
devices may draw a patterned line where the TMS3401 0 would draw a
solid line.
• If an instruction uses the CONVSP register, then SPTCH (B1) must
agree with CONVSP (the 5 LSBs of CONVSP must equal the 1s com-
plement of 1092 SPTCH, which is given by the LMO of SPTCH). Future
GSPs may have instructions that use SPTCH to determine the pitch val-
ues instead of using CONVSP; that is, the instruction may perform the
1092 conversion automatically.
Set the 11 MSBs of CONVSP to 0; the TMS3401 0 ignores the values
of these bits, but future GSPs may use these bits.
• If an instruction uses the CONVDP register, then DPTCH (B3) must
agree with CONVDP (the 5 LSBs of CONVDP must equal the 1 s com-
plement of 1092 DPTCH, which is given by the LMO of DPTCH). Future
GSPs may have instructions that use DPTCH to determine the pitch va-
lues instead of using CONVDP; that is, the instruction may perform the
1092 conversion automatically.
Set the 11 MSBs of CONVDP to 0; the TMS3401 0 ignores the values
of these bits, but future GSPs may use these bits.
C.3 Memory Map Compatibility
• The 32 16-bit words following the TMS34010 I/O registers (addresses
OC0000200h-oC00003FOh) are currently reserved. Future GSPs may
use these addresses for additional I/O registers, so do not write code that
uses these addresses.
• Do not use any reserved addresses in the TMS3401 0 memory map; fu-
ture GSPs may use these locations. Specifically, address OFFFFEOOOh,
which is currently reserved, may be used for system configuration infor-
mation.
C-3
Appendix C - Software Compatibility with Future GSPs
C.4 I/O Register and Video Timing Compatibility
• Future GSPs may use different I/O registers to control video timing and
VRAM shift register control. The vertical and horizontal counters may
still be accessible at their current locations. DPYADR, DPYCTL,
DPYSTRT, and DPYTAP may have new functions and/or addresses.
HESYNC, HEBLNK, HSBLNK, HTOTAL, VESYNC, VEBLNK, VSBLNK,
and VTOTAL may have similar functions but different addresses. These
video control functions may be redefined so that future GSPs can take
advantage of new advances in video RAM technology.
• Code that accesses video timing registers should be separated from other
code so that you can easily replace it.
• Future GSPs may use different DRAM refresh methods; the TMS3401 0
provides control every 32 or 64 CPU cycles, and it may be necessary to
have more control.
C.S Interrupts Compatibility
• Interrupt service routines should not make assumptions about the state
of the stack (except for the location of the ST and the PC). Future GSPs
may push additional parameters or status information on the stack before
pushing the PC and ST.
Note:
You must use RETI to return from an interrupt service routine. This en-
sures that any additional parameters that future GSPs may push on the
stack will also be popped from the stack, and also ensures that the correct
internal registers will be restored.
• PIXBLT interruption may behave differently on future GSPs. An inter-
rupted PIXBLT may store status information on the stack instead of in
registers, and different information may be stored.
Note:
Do not modify values stored in the register file by an interrupted PIXBLT.
Future GSPs may not use this information or these locations.
• Opcodes that the TMS34010 flags as illegal may be valid opcodes for
future GSPs. Therefore, if you want to use a software trap, use the TRAP
instruction instead of an illegal opcode.
• Traps 3-7 and 12-15 are reserved for future interrupts.
C-4
Appendix C - Software Compatibility with Future GSPs
C.6 Host Interface Compatibility
• Certain features of the TMS3401 0 host interface may need to be imple-
mented in external hardware for future GSPs. However, the host inter-
face registers and their functions will remain the same so that TMS3401 0
code that uses these registers will be compatible with future GSPs.
• Code written for a host processor that accesses the GSP host interface
may have to be modified to comprehend a modified host interface.
C-5
Appendix C - Software Compatibility with Future GSPs
C-6
Appendix 0
Glossary
aliasing: A stairstep effect on a raster display of a line or arc segment.
antialiasing: A method for reducing the severity of aliasing effects seen in
lines and edges drawn on a bit-mapped display device. This method adjusts
the intensity of a pixel used to represent a portion of a line or edge according
to the pixel's distance from the line or edge. Antialiasing requires that the
display device be capable of producing one or more intermediate intensity
levels between bright and off.
asynchronous communications: A method of transmitting data in which
the timing of character placement of connecting transmitting lines is not crit-
ical. The transmitted characters are preceded by a start and followed by a stop
bit, thus permitting the interval between characters to vary.
aspect ratio: The ratio of width to height. For the rectangular picture
transmitted by a television station, the aspect ratio is 4:3.
back porch: The portion of a horizontal blanking pulse that follows the
trailing edge of the horizontal synchronizing pulse.
background illumination: The average brightness of a screen.
bandwidth: The number of bits per second that can be transferred by a
device.
binary array: Alternate name for a two-dimensional bit map in which each
pixel is represented as single bit.
BitBlt: Bit aligned block transfer. Transfer of a rectangular array of pixel
information from one location in a bitmap to another with potential of applying
1 of 16 boolean operators during the transfer.
bit map: 1. The digital representation of an image in which bits are mapped
to pixels. 2. A block of memory used to hold raster images in a device-specific
format.
bit plane: Hardware used as a storage medium for a bit map.
black level: The amplitude of the composite signal at which the beam of the
picture tube is extinguished (becomes black) to blank retrace of the beam.
This level is established at 75% of the signal amplitude.
blanking signal: Pulses used to extinguish the scanning beam during hor-
izontal and vertical retrace periods.
0-1
Appendix 0 - Glossary
breakpoint: A place in a routine specified by an instruction, instruction di-
git, or other condition, where the routine may be interrupted by external in-
tervention or by a monitor routine.
clipping: Removing parts of display elements that lie outside a given boun-
dary, usually a window or a viewport.
composite video: The color-picture signal plus all blanking and synchro-
nizing signals. The signal includes luminance and chrominance signals, verti-
cal- and horizontal-sync pulses, vertical- and horizontal-sync pulses,
vertical-and horizontal-blanking pulses, and the color-burst signal.
DAC: Digital-to-analog converter. A device that converts a digital input
code to an analog output voltage or current. The analog output level repres-
ents the value of the digital input code.
direct access: Pertaining to the process of obtaining data from, or placing
data into, storage where the time required for such access is independent of
the location of the data most recently obtained or placed in storage.
display area: The rectangular part of the physical display screen in which
information coded in conformance with a video encoding standard is visibly
displayed. The display area does not include the border area.
display element: A basic graphic element that can be used to construct a
display image.
display memory: The area of memory which is used to hold the graphics
image output to the video monitor.
display pitch: The difference in memory addresses between two pixels that
appear in vertically adjacent positions (one directly above the other) on the
screen.
display unit: A device which provides a visual representation of data.
dot clock: The dot clock cycles the rate at which video data is output to a
CRT monitor.
DRAM refresh: The operation of maintaining data stored in dynamic
RAMs. Data are stored in dynamic RAms as electrical charges across a grid
of capacitive cells. The charge stored in a cell will leak off over time.
execution unit: The portion of a central processing unit that actually exe-
cutes the data operations specified by program instructions.
field: 1. A group of contiguous bits in a register or memory dedicated to a
particular function or representing a single entity. 2. A software-configurable
data type in the TMS3401 0 whose length can be programmed to be any value
in the range 1 to 32 bits.
fill: Solid coloring or shading of a display surface, often achieved as a pat-
tern of horizontal segments.
frame: 1. The time required to refresh an entire screen. 2. The screen image
output during a single vertical sweep.
0-2
Appendix D - Glossary
frame buffer: A portion of memory used to buffer rasterized data to be
output to a CRT display monitor. The contents of the frame buffer are often
referred to as the bit map of the display and contain the logical pixels corre-
sponding to the points on the monitor screen.
front porch: The portion of a horizontal blanking pulse that precedes the
leading edge of the horizontal sync pulse.
GKS: Graphical Kernel System. An application programmer's standard in-
terface to a graphics display.
glue logic: The small- and medium-scale-integrated devices necessary to
complete the interface between two or more large or very-large-scale inte-
grated devices.
gray scale: A scale of light intensities from black to white.
GSP: Graphics System Processor. A single-chip device embodying all the
processing power and control capabilities necessary to manage a high-
performance bit-mapped graphics system. The TMS34010 is the first such
device.
high-impedance: The third state of a three-state output driver, in which the
output is driven neither high or low but behaves as an open connection.
hold signal: A signal from a device capable of controlling a processor bus
(for example, a processor or a DMA controller) which the device sends to a
bus arbiter to request control of the bus. Typically, the arbiter signals the
granting of the request by sending a hold-acknowledgement signal to the re-
questing device.
hold time: The minimum amount of time that valid data must be present at
an input after the device is clocked to ensure proper data acceptance.
horizontal blanking interval: The time during which the display is
blanked to cover the horizontal retracing of the electron beam.
horizontal sync: The synchronization signal that enables horizontal retrace
of the electron beam of a CRT display.
icon: A graphic symbol representing a menu item.
interlaced scanning: A system of TV-picture scanning. Odd-numbered
scanning lines, which make up an odd field, are interlaced with the even-
numbered lines of an even field. The two interlaced fields constitute one
frame. In effect, the number of transmitted pictures is doubled, thus reducing
flicker.
lookup table: A table used during scan conversion of the digital image that
converts color-map addresses into the actual color values displayed.
LRU: Least-recently-used cache-replacement algorithm. When a cache miss
occurs, a cache-replacement algorithm selects which cache segment will be
overwritten, based on the likelihood that the data in the discarded segment
will not be needed again for some time. The LRU algorithm selects the seg-
ment which was used least recently.
0-3
Appendix 0 - Glossary
mask: A pattern of characters that is used to control the retention or elimi-
nation of portions of another pattern of characters.
memory map: A map of memory space partitioned into functional blocks.
monotonicity: The quality of proceeding in a uniform manner. For exam-
ple, the analog level output from a DAC should increase with each increase in
the value of the digital input code.
multiplexing: Refers to a process of transmitting more than one set of sig-
nals at a time over a single wire or communications link.
NABTS: North American Broadcast Teletext Specification
NAPLPS: Abbreviation for the North American Presentation Level Protocol
Syntax, which is a proposed standard for Videotex services.
nonmaskable interrupt: An interrupt request that cannot be disabled.
NMI: Nonmaskable interrupt. The NMI is an interrupt that is permanently
enabled; it cannot be disabled.
NTSC: Abbreviation for the National Television System Committee, a group
representing a wide range of interests in the television broadcast and video
industry. The NTSC is instrumental in developing standards.
operand: That which is operated upon. An operand is usually identified by
an address part of an instruction.
origin: The zero intersection of X and Y axes from which all points are cal-
culated.
overlay: The plane of a graphics display that can be superimposed on an-
other plane.
pack: To compress data in a storage medium by eliminating redundant in-
formation in such a way that the original data can later be recovered.
palette: A digital lookup table used in a computer graphics display for
translating data from the bit map into the pixel values to be shown on the
display.
pan: Apparent horizontal or vertical movement of a computer graphics screen
(or window) over an image contained in a frame buffer that is too large to be
completely displayed in a single static picture.
phase: The time interval for each clock period in a system is divided into two
phases. One phase corresponds to the time the clock signal is high, and the
other phase corresponds to the time the clock signal is low.
PHIGS: The programmer's Hierarchical Interactive Graphics Standard
pipelining: A design technique for reducing the effective propagation delay
per operation by partitioning the operation into a series of stages, each of
which performs a portion of the operation. A series of data is typically clocked
through the pipeline in sequential fashion, advancing one stage per clock pe-
riod.
0-4
Appendix 0 - Glossary
pitch: The difference in starting addresses of two adjacent rows of pixels in
a two-dimensional pixel array.
pixel: Picture element. 1. The smallest controllable point of light on a CRT
display screen. 2. In a bit-mapped display, the logical data structure that
contains the attributes to be shown at the corresponding physical pixel posi-
tion on the CRT display screen.
pixel processing operation: A specified Boolean or arithemetic operation
used to combine two pixel values (source and destination).
PixBlt: (Abbreviation of Pixel Block transfer) Operations on arrays of pixels
in which each pixel is represented by one or more bits. PixBlt operations are
a superset of BitBlt operations, and include not only the commonly-used
boolean functions, but also integer arithmetic and other multi-bit operations.
plane: (Also bit plane or color plane.) A plane is a bit-map layer in a display
device with multiple bits per pixel. If the pixel size is n bits, and the bits in
each pixel are numbered 0 to n-1 , plane 0 is made up of bits numbered 0 from
all the pixels, and the plane n-1 is made up of bits numbered n-1 from all the
pixels. A layered graphics display allows planes or groups of planes to be
manipulated independently of the other planes.
primary colors: A set of three colors from which all other colors may be
regarded as derived; hence, any of a set of visual stimuli from which all colors
may be produced by mixture. Each primary color must be different from the
others, and a combination of two primaries must be capable of producing a
third. In color television, the three primary colors are red, green and blue.
propagation delay: The time required for a change in logic level at an input
to a circuit to be translated into a resulting change at an output.
protocol: A set of rules, formats, and procedures governing the exchange
of information between peer processes at the same level.
pulse width: Pulse width, Tw. The time interval between specified refer-
ence points on the leading and trailing edges of the pulse waveform.
Random Access Memory (RAM): A memory from which all information
can be obtained at the output with approximately the same time delay by
choosing an address randomly and without first searching through a vast
amount of irrelevant data.
raster: A rectangular grid of picture elements whose intensity levels are
manipulated to represent images. In a bit-mapped display, the bits within a
portion of the memory referred to as the frame buffer are mapped to the raster
pattern of a CRT monitor.
raster display: A CRT display generated by an electron beam that illumi-
nates the CRT by sweeping the beam horizontally across the phosphor surface
in a predetermined pattern, providing substantially uniform coverage of the
display area.
raster graphics: Computer graphics in which a display image is composed
of an array of pixels arranged in rows and columns.
0-5
Appendix 0 - Glossary
Raster-Op: The arithmetic or logical combination operation that takes place
during the transfer of pixel arrays from one location to another.
raster scan: The grid pattern traced by the electron beam on the face of the
CRT in a television or similar raster-scan display device.
ready signal: A signal from a memory or a memory-mapped peripheral that
informs the processor when it is ready to complete a memory cycle. Slower
memories or memory-mapped peripherals must extend the length of the me-
mory cycle by negating the ready signal (in other words, by sending the pro-
cessor a "not ready" signal until such time as the cycle can be completed.
resolution: The number of visible distinguishable units in the device coor-
dinate space.
refresh: Method which restores charge on capacitance which deteriorates
because of leakage.
reset: To restore to normal action.
resolution: The number of visible distinguishable units in the device coor-
dinate space.
retrace: The line traced by the scanning beam or beams of a picture tube
as it travels from the end of one horizontal line or field to the beginning of the
next line or field.
RGB monitor: Red-Green-Blue Monitor. An RGB monitor is a CRT moni-
tor capable of displaying colors and having separate inputs for the three sig-
nals used to drive the red, green and blue guns of the CRT.
relative coordinates: Location of a point relative to another data point.
rotate: To transform a display or display item by revolving it around a spe-
cified axis or center point.
scale: A size change made by multiplying or dividing the coordinate dimen-
sions by a constant value.
scale factor: The value by which you divide or multiply the display dimen-
sions in a scaling operation.
scaling: Enlarging or reducing all or part of a display image by multiplying
the coordinates of display elements by a constant value.
scan line: A horizontal line traced across a CRT by the electron beam in a
television or similar raster-scan device.
screen refresh: The operation of dumping the contents of the frame buffer
to a CRT monitor in synchronization with the movement of the electron beam.
sCiolling: ~v1oving text stiings Oi giaphics vertically Oi hOiizontally.
segment: A collection of display elements that can be manipulated as a unit.
sequencing: Control method used to cause a set of steps to occur in a
particular order.
0-6
Appendix D - Glossary
setup time: The minimum amount of time that valid data must be present
at an input before the device is clocked to ensure proper data acceptance.
shift register transfer: A transfer between the RAM storage and internal
shift register in a video RAM.
sprite: A graphic object of a specified pattern appearing on its plane in a
position determined by a single coordinate pair, specifying the sprite's location
on the screen in the horizontal and vertical axis.
stairstepping: A visual effect seen in bit-mapped display devices which
produce images by brightening or dimming individual picture elements (or
pixels) contained in a two-dimensional grid of such elements. Stairstepping
(also called aliasing) is the rough or jagged appearance of lines and edges
which are not perfectly horizontal or vertical, resulting from transitions of the
line or edge from one row or column of elements to another.
superimposed: Refers to the process that moves data from one location to
another, superimposing bits or characters on the contents of specified lo-
cations.
tap point: The column address provided to a VRAM during a memory-to-
shift-register cycle. The column address specifies the point at which the shift
register is to be "tapped;" in other words, which cell of the shift register is to
be connected to the serial output of the VRAM.
trace: A line of the graphics display.
transformation: Geometric alteration of a graphics display, such as scaling,
translation, or rotation.
transparency: When a pixel with the attribute of transparency is written IO
the screen, it is effectively invisible, and does not alter that portion of the
screen it is written to. For example, in a pixel array containing the pattern for
the letter A, all pixels surrounding the A pattern could be given a special value
indicating that they are transparent. When the array is written to the screen,
the A pattern, but not the pixels in the rectangle containing it, would be in-
visible.
VDI: Virtual Device Interface. The standard interface between the device-
independent and the device-dependent levels of a graphics system.
VDM: Virtual Device Metafile. A standard mechanism for retaining and and
transporting graphics data and control information at the level of the Virtual
Device Interface.
vertical blanking interval: The time during which the display is blanked
to cover the vertical retracing of the electron beam.
vertical blanking pulse: A positive or negative pulse developed during
vertical retrace and appearing at the end of each field. It is used to blank out
scanning lines during the vertical retrace interval.
vertical sync: The synchronization signal that enables vertical retrace of the
electron beam of a CRT display.
video display processor: A microprocessor device dedicated to the tasks
of display memory management (storage, retrieval, and refresh) and gener-
0-7
Appendix 0 - Glossary
ation of all required video, control, and synchronization signals required by a
TV display or CRT monitor.
video overlay: The mixing of one video signal with another such that parts
of the image carried by the first signal replace the corresponding parts of the
image carried by the second signal.
video RAM, VRAM: Video Random-Access Memory. A dual-ported me-
mory device for computer graphics applications, containing two interfaces;
one interface to allow a processor to read or write data from an internal mem-
ory array; a second interface to provide a serial stream of screen refresh data
to a CRT display device.
viewport: The specified window on the display surface that marks the limits
of a display.
virtual coordinate system: A coordinate system created by mapping a
portion of the world coordinate system to the space available on your device.
virtual space: Space referenced with the coordinates defined by the appli-
cation.
wait state: A clock period inserted into a memory cycle in order to permit
accesses of slower memories and slower memory-mapped peripherals.
window: A specified rectangular area of a virtual space shown on the dis-
play.
window clipping: Allowing text and graphics drawing to occur only within
a specified rectangular window on the screen.
wire frame: A three-dimensional image displayed as a series of line seg-
ments outlining its surface.
zoom: To scale a display or display item so it is magnified or reduced on the
screen.
0-8
Index
B1 (SPTCH) 5-7
A B10 (COUNT) 5-17
B11 (INC1) 5-17
ABS instruction 12-35 B12 (INC2) 5-17
absolute branch 5-19 B13 (PATIRN) 5-17
absolute operands 12-5 B13 (TEMP) 5-17
ADD instruction 12-36 B2 (DADDR) 5-8
add with saturation 7-16 B3 (DPTCH) 5-10
ADDC instruction 12-37 B4 (OFFSET) 5-11
ADDI instruction 12-38, 12-39 B5 (WSTART) 5-12
ADDK instruction 12-40 B6 (WEND) 5-13
addressing 3-2-3-3 B7 (DYDX) 5-14
addressing modes 12-4 B8 (COLORO) 5-15
ADDXY instruction 12-41 B9 (COLOR1) 5-16
A-file registers 5-2
airbrush effect 7-23
ALU 1-6
AN 0 instruction 12-42 c
ANDI instruction 12-43
ANON instruction 12-44 C bit 5-18
ANDNI instruction 12-45 C compiler 1-12
antialiasing 7 -23 cache disable 6-14
applications 1 -8 cache hit 5-22
arithmetic instructions 12-19 cache miss 5-22
array pitch 4-16 cache replacement algorithm 5-21
CALL instruction 12-48
CALLA instruction 12-49
CALLR instruction 12-50
B Cartesian coordinates 4-16
CAS 2 -7, 11 -2
background color register 5-15 CD bit 5-24,6-11,6-14
bank selection 11-25 CF bit 5-23, 5-24, 6-32, 6-33
barrel shifter 1 -6 chip select pin 2-5
B-file registers 5-3, 5-5-5-17 clearing ...
Bt:A'N'R 2-9, 9-3 a register 12-51
blanking 2-9, 6-27, 6-29, 6-49, 6-51 the carry bit 12-52
block diagram 1-5 clock timing logic 1 -7
Boolean operations 7 -1 7 CLR instruction 12-51
Boolean pixel processing 6-13 CLRC instruction 12-52
Bresenham line algorithm 7-2,7-10 CMP instruction 12-53
BTST instruction 12-46, 12-47 CMPI instruction 12-54, 12-55
bulk initialization of VRAMs 9-18, 9-26 CMPXY instruction 12-56
bus request priorities 11 -4 Cohen-Sutherland algorithm 7-30
bus request signal 2-10 color planes 7 -12
byte addressing 10-20 color-expand operation 7-5
bytes 4-1 COLORO register 5-15
BO (SADDR) 5-6 COLOR1 register 5-16
Index-1
column address strobe 2-7 refresh cycles 6 -11
compare instructions 12-19 refresh interval 6-46
compare point to window 7-3 refresh rate 6 -11
context switching instructions 12-29 DRAM refresh 11-11,11-12,11-25
CONTROL 6-11 DRAV instruction 12-67
CONTROL register 6-11 draw and advance 7 -10
CONVDP 7-4 DSJ instruction 12-70
CONVDP register 4-12,6-15 DSJ EQ instruction 12-71
conversion factor 6-15, 6-16 DSJNE instruction 12-73
CONVSP 7-4 DSJS instruction 12-75
CONVSP register 4-12, 6-16 DUDATE bits 6-19, 6-20
COUNT register 5-17 DXV bit 6-19,6-22
CPW instruction 12-57 DYDX register 5-14
CVXYL instruction 12-59
E
D
EINT instruction 12-76
DADDR register 5-8 EMU instruction 12-77
data enable pin 2-7 emulation 2-10
data paths 1 -6, 5-25 enabling interrupts 12-76
data select pins 2-5 ENV bit 6-19
data structures EXG F instruction 12-78
bytes 4-1 EXG PC instruction 12-79
fields 4-1,4-2-4-5 external interlaced video 9-17
pixel arrays 4-1 external interrupts 8-3
pixels 4-1,4-6-4-10 external synchronization 9-15
DDOUT 2-7, 11-2 external video 6-19
DEC instruction 12-61
DEN 2-7, 11-2
destination address register 5-8
destination conversion factor 6-15 F
destination pitch register 5-10
development tools list 1 -3 FE bit 4-2
DIE bit 6-40 FEO bit 5-18
DINT instruction 12-62 FE1 bit 5-18
DIP bit 6-41 field size 5-18, 5-19
direct operands 12-6 fields 4-1, 4-2-4-5
display interrupt 8-5,9-13 addressing 4-2
display memory 9-18 alignment 4-3
display pitch 4-10,5-7,5-10,6-15, extraction 4-2
6-16,9-18 insertion 4-2, 4-5
DIVS instruction 12-63 size 4-2
DIVU instruction 12-65 fill 7-5
dot rate 9-14 FILL instruction 12-80, 12-84
DPTCH register 5-10, 6-15 font library 1 -1 2
DPYADR register 6-17 foreground color register 5-16
DPYCTL register 6-19 FSO 4-2
DPYINT register 6-23 FSO bits 5-18
DPYSTRT register 6-24 FS1 4-2
DPYTAP register 6-25 FS1 bits 5-18
DRAM 6-11,11-5 function select pins 2-5
Index-2
HSTADRH 10-3
G HSTADRH register 6-30
HSTADRL 6-31, 10-3
general-purpose register files 1-5, 5-2- HSTCTL 10-3
5-17 HSTCTLH 6-32, 10-3
GETPC instruction 12-89 HSTCTLL 6-36, 10-3
GETST instruction 12-90 HSTDATA 6-38,10-3
graphics instructions 12-26 selection 10-2
graphics standards 1 -2 signals 10-2
timing examples 10-5
host interface bus pins 2-3, 2-5
HCS 2-5
H HDO-HD15 2-6
HFSO,HFS1 2-5
HINT 2-6
halt latency 1 0-1 9 HLDS 2-5
halt program execution 6-35
HRDY 2-6
HCOUNT register 6-26 HREAD 2-5
HCS 2-5, 10-2 H015S 2-5
HDO-HD15 2-6,10-2
HWRITE 2-5
HEBLNK register 6-27 host interrupt 8-5
HESYNC register 6-28
host read/write strobes 2-5
HFSO, HFS1 2-5, 10-2
host-present mode 8-10, 8-13
hidden states 13-2 HRDY 2-6,10-2, 10-8
HIE bit 6-40 HREAD 2-5,10-2
HINT 2-6, 10-2 HSBLNK register 6-29
HIP bit 6-41
HSD bit 6-19
HLDA/EMUA 2-10 HSTADRH register 6-30
HLDS 2-5, 10-2 HSTADRL register 6-31
HLT bit 5-23,6-3,6-32,6-35
HSTCTLH register 6-32
HOLD 2-10
HSTCTLL register 6-36
hold and emulation signals 2-4, 2-10 HSTDATA register 6-38
'R"[1)A/EMUA 2-10
HSYNC 2-9,6-22,6-26,9-3
HOLD 2-10 HTOTAL register 6-39
RUN/EMU 2-10 ~ 2-5, 10-2
hold interface 11 -18 HWRITE 2-5, 10-2
hold request 11 -4
horizontal back porch 9-5
horizontal front porch 9-5
horizontal sync 2-9
horizontal timing 9-12
horizontal timing registers
HCOUNT 6-26, 9-4 I/O registers 1 -6, 6-1 -6-52
HEBLNK 6-27, 9-4 addressing 6-2
HESYNC 6-28, 9-4 at reset 6-3
HSBLNK 6-29, 9-4 host interface registers 6-7
HTOTAL 6-39, 9-4 interrupt interface registers 6-8
horizontal video timing 9-6, 9-7 latency of writes 6-4
host interface 10-1, 10-24 local memory interface registers 6-8
bandwidth 10-22 memory map 6-2
data transfer 10-8 summary 6-5
indirect accesses of local video timing and screen refresh regis-
memory 10-11 ters 6-9
reads and writes 10-4 IE bit 5-18
ready signal to host 10-8 illegal opcode interrupts 8-9
reg isters 6 -7 illegal operand 8-5
Index-3
immediate operands 12-4 registers 6-8
implied graphics operands 5-5 I NTEN B 6-40, 8-3
INC instruction 12-91 I NTPEN 0 6-41, 8-3
INCLK 2-7, 11-2 interruptible instructions 7-8
INCR bit 6-32, 6-34, 10-11 interrupts 2-6, 8-1-8-8
incremental algorithms 7 -10 display interrupt 6-23, 8-5, 9-13
INCW bit 6-32, 6-35, 10-11 enable bit 5-18
INC1 register 5-17 external interrupts 8-3
INC2 register 5-17 host interrupt 8-5
indirect accesses of local memory 10-11 host interrupt request signal 2-6
indirect branch 5-19 IE bit 5-18
indirect operands 12-7,12-8,12-9, illegal opcode interrupts 8-9
12-10,12-11 illegal operand 8-5
in XV mode 12-11 INTENB 6-40
with offset 12-8 internal interrupts 8-5
with postincrement 12-9 interrupt request pins 8-3
with predecrement 12-10 interrupt requests 6-37
input clock 2-7 INTIN bit 6-37
instruction cache 1-6, 5-20-5-25 INTOUT bit 6-37
cache disable 6-14 INTPEND 6-41
cache flush 6-33 local interrupt request signals 2-8
cache hit 5-22 nonmaskable interrupt 6-32, 6-33,
cache miss 5-22 8-5
cache replacement algorithm 5-21 priorities 8-2, 8-5
disabling 5-24 processing 8-6
downloading new code 5-23 reg isters 8 -3
flushing 5-23 RESET 2-11
LRU stack 5-21 stack operations 3-8
operation 5-22 vector addresses 8-2
P flag 5-22 window interrupt 8-5
segment miss 5-22 intersecting rectangles 7-3
segments 5-21 INTIN bit 6-36, 6-37
SSA register 5-21 INTOUT bit 6-36, 6-37
subsegment miss 5-22 INTPEND register 6-12, 6-41
instruction set 12-1
addressing modes 12-4
arithmetic instructions 1 2 -1 9
compare instructions 12-19 J
condition codes 12-31
graphics instructions 12-26 JAcc instruction 12-92
jump instructions 12-30 J Rcc instruction 12-94, 12-96
logical instructions 12-19 JUMP instruction 12-98
move instructions 12-20 jump instructions 12-30
operand formats 12-4
program control instructions 12-29
shift instructions 12-32
instruction words 5-20 K
INTENB register 6-40
interlaced display 9-25
interlaced video 9-1 i, 9-17 key features of the TMS3401 0 1 -3
internal interrupts 8-5
interrupt interface
Index-4
LRDY 2-8, 11-2
L
LADO-LAD15 2-8, 11 -2
LAL 2-7,11-2 M
LBL bit 6-32, 6-34
LCLK1,LCLK2 2-8, 11 -2 MAX operation 7 -16
LCSTRT bits 6-24 memory bus request priorities 11 -4
line clipping 7 -29 memory map 3-4
LINE instruction 12-99 message buffers 6-36, 6-37
linear addressing 4-10 microcontrol ROM 1 -7
LlNT1,LlNT2 2-8,8-3, 11-2 midpoint subdivision 7 -30
LMO instruction 12-108 MIN operation 7-16
LNCNT bits 6-17,6-24 MMFM instruction 12-109
local address/data bus 2-8 MMTM instruction 12-111
local memory interface 11 -1, 11 -30 MODS instruction 12-113
addressing mechanisms 11-23 MODU instruction 12-114
hold interface timing 11 -18 MOVB instruction 12-115,12-116,12-
I/O register access cycles 11-13 117,12-118,12-119,12-120,12-121,
internal cycles 11 -13 1 2 -1 23, 1 2 -1 24
memory bus request priorities 11 -4 MOVE instruction 12-126, 12-127, 12-
read cycle 11 -8 128, 12-130, 12-132, 12-134, 12-135,
read-modify-write operations 11-15 12-137,12-139,12-141,12-143,12-
registers 6-8 145, 12-147, 12-149, 12-151, 12-153,
CONTROL 6-11, 11-3 12-155,12-157,12-159,12-160
CONVDP 6-15, 11-3 move instructions 12-20
CONVSP 6-16, 11-3 MOVK instruction 12-161
PMASK 6-43, 11-3 MOVX instruction 12-162
PSIZE 6-45, 11-3 MOVY instruction 12-163
REFCNT 6-46, 11-3 MPYS instruction 12-164
register-transfer cycles 11 -9 MPYU instruction 12-166
signals 11 -2 MSGIN bits 6-36
timing 11 -5-11 -22 MSGOUT bits 6-36, 6-37
wait states 11 -1 6 multiple-GSP systems 9-15
write cycle 11 -7
local memory interface pins 2-4, 2-7 -2-8
CAS 2-7
DDOUT 2-7 N
DEN 2-7
INCLK 2-7
LADO-LAD15 2-8 Nbit 5-18
LAL 2-7 NEG instruction 12-168
LCLK1,LCLK2 2-8 NEG B instruction 12-169
LlNT1,LlNT2 2-8 NIL bit 6-19, 6-22
LRDY 2-8 NMI bit 6-32
RAS 2-7 non-branch 5-19
TR/OE 2-7 noninterlaced video 9-9
W 2-7 nonmaskable interrupt 6-8, 6-32, 8-5
local read/write strobes 2-7 nonmaskable interrupt mode 6-33
logical instructions 12-19 NOP instruction 12-170
logical pixels 4-6 NOT instruction 12-171
Index-5
o program counter 1 -5, 5-19
PSIZE register 4-12, 6-45
PUSHST instruction 12-228
OFFSET register 4-12, 5-11 PUTST instruction 12-229
on-screen memory 9-18
OR instruction 12-172
ORG bit 6-19, 6-20
ORI instruction 12-173 R
outcode 7-30
output clocks 2-8 RAS 2-7,11-2
REFCNT register 6-46
references 1 -11
p register file A 5-2
register file B 5-3, 5-5-5-17
register-direct operands 12-6
P flag 5-22 related documentation 1 -1 2
panning 9-25 relative branch 5-1 9
PATTRN register 5-17 replace operation 7 -18
PBHbit 6-11,6-12 RESET 2-11,8-10-8-13
PBV bit 6-11, 6-13 effect on cache 5-21
PBX bit 5-18 effect on instruction cache 8-11
PC 5-19 effect on TMS3401 0 registers 8-12
pick window 7 -26 effects on I/O registers 6-3
picture elements 4-6 HLT bit 6-35
pin descriptions 2-2 RETI instruction 12-230
pinout 2-2 RETS instruction 12-232
pitch 7-4 REV instruction 12-233
pitch conversion factors 4-1 2 RINTVL bits 6-46
PlxBlt direction 6-13 RL instruction 12-234, 12-235
PIXBLT instruction 12-174, 12-179, row address strobe 2-7
12-187,12-193,12-200,12-206 row and column addressing 11 -6
PixBlts 4-15, 7-4 ROWAOR bits 6-46
pixel array 4-1 5 RR bit 6-11
pixel block transfers 4-15, 7-4 RUN/EMU 2-10
pixel processing 6-1 3, 7 -1 5
pixels 4-1,4-6-4-10
addressing 4-6
on the screen 4- 7 s
pixel size 6-45
PSIZE register 6-45 SAOOR register 5-6
representation in a register 4-6 scan line counter 6-17
size 4-6 screen origin 4-8, 6-19, 6-20
storage in memory 4-7 screen refresh 6-21,6-24, 9-1-9-27
XV addressing 4-8 screen refresh enable 6-19
PIXT instructions 12-213, 12-215, 12- screen size limits 9-2
218,12-220,12-222,12-224 screen-refresh address 6-17
plane mask 7 -1 2 screen-refresh cycles 9-18
plane masking 6-43 SOB 1-12
DII." J\CI{ r"" ... i.,+""r ~_A'2
I IYlr-1o",," I\,I,=,I~L"" V '"TV
segment miss 5-22
POPST instruction 12-227 self-bootstrap mode 8-10, 8-13
postclipping 7 -29 self-modifying code 5-23
PP bit 6-11 SETC instruction 12-236
PPOP bits 6-13 SETF instruction 12-237
preclipping 7-29 SEXT instruction 12-238
program control instructions 12-29 shift instructions 12-32
Index-6
shift register transfer enable pin 2-7
shift register transfers 6-19 v
sign (N) bit 5-18
SLA instruction 12-239, 12-240 V bit 5-18
SLL instruction 12-241, 12-242 and window checking 7-25
software development board 1 -1 2 VCLK 2-9, 9-3
software traps 8-9 VCOUNT register 6-23, 6-48
source address register 5-6 VEBLNK register 6-49
source conversion factor 6-16 vector addresses 8-2
source pitch register 5-7 vertical back porch 9-5
SP 1-6,3-6,5-2,5-4 vertical front porch 9-5
SPTCH register 5-7,6-16 vertical sync 2-9
SRA instruction 12-243, 12-244 vertical timing registers
SRE bit 6-19, 6-21 VCOUNT 6-48, 9-4
SRFADR bits 6-17, 6-24 VEBLNK 6-49, 9-4
SRL instruction 12-245, 12-246 VESYNC 6-50, 9-4
SRSTRT bits 6-24 VSBLNK 6-51, 9-4
SRT bit 6-19, 6-21 VTOTAL 6-52, 9-4
SSA register 5-21 vertical video timing 9-8-9-12
ST 5-18 VESYNC register 6-50
stack 3-6-3-11 video clock 2-9
multiple-register operations 3-8 video enable 6-19
operation during a subroutine 3-9 video timing 9-1 -9-27
operation during interrupts 3-9 video timing and screen refresh
structure 3-7 display address 6-17, 6-19
32-bit register operations 3-8 display interrupt 6-23
stack pointer 5-2, 5-4 reg isters 6 -9
starting address of array 4-15, 7-7 DPYADR 6-17
starting corner selection 7 -7 DPYCTL 6-19
status register 1 -5, 5-18-5-19 DPYINT 6-23
strobes 10-4 D PYSTRT 6-24
SUB instruction 12-247 DPYTAP 6-25
SUBB instruction 12-248 HCOUNT 6-26, 9-4
SUBI instruction 12-249, 12-250 HEBLNK 6-27, 9-4
SUBK instruction 12-251 H ESYNC 6-28, 9-4
subroutine calls 12-48, 12-49, 12-50 HSBLNK 6-29, 9-4
subsegment miss 5-22 HTOT AL 6-39, 9-4
subtract with saturation 7 -16 VCOUNT 6-48, 9-4
SUBXY instruction 12-252 VEBLNK 6-49, 9-4
VESYNC 6-50, 9-4
VSBLNK 6-51, 9-4
VTOTAL 6-52, 9-4
T video timing signals 9-3
video timing signals 2-4, 2-9
T bit 6-11 BLANK 2-9
tap point register 6-25 HSYNC 2-9
TEMP register 5-17 VCLK 2-9
TR/QE 2-7, 11-2 VSYNC 2-9
transparency 7 -11 VRAM 11-5
enabling (T bit) 6-12 VRAMs 6-9, 9-18
TRAP 8-9 bulk initialization 9-26
TRAP instruction 12-253 tap point address 6-25
traps 8-9 VSBLNK register 6-51
two-dimensional arrays 4-15, 7-4
Index-7
VSYNC 2-9, 6-22, 9-3
VTOTAL register 6-52 x
XOR instruction 12-255
w XORI instruction 12-256
XY addressing 4-8, 4-10, 4-11, 4-14,
5-14
W 2-7,11-2 benefits 4-11
Wbit 6-11,6-12 DYDX register 5-14
WEND register 5-13 format 4-11
window checking 4-16,6-12,7-25 OFFSET register 5-11
window clipping 7 -27 XY -to-linear conversion 4-12, 6-15,
window end address register 5-13 6-16
window hit detection 7 -26 X1 E bit 6-40
window interrupt 8-5 X1 P bit 6-41
window miss detection 7-27 X2E bit 6-40
window start address register 5-12 X2P bit 6-41
windows 5-12, 5-13 X3E bit 6-40
WEND register 5-13 X3P bit 6-41
WSTART register 5-12
WSTART register 5-12
WVE bit 6-40
WVP bit 6-41 z
Z bit 5-18
ZEXT instruction 12-257
Index-8
August 1988 Reader Response Card
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How do you use this book - did you (or will you) read it from front to back, or do you use
it mainly as a reference?
Are the descriptions of graphics operations (transparency, pixel processing, XV addressing,
etc.) clear and complete?
Is the Instruction Set (Section 12) clear? Is it easy to use as a reference?
What kinds of examples would you like to be included in this manual?
What information would you add to or delete from the Reference Card?
What would you add or change that would make this manual more accurate or easy to read?
Additional comments:
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