SDD c69d2c295f reference: level-1 host-port test — can it be skipped? (analysis, no skip) ...

Answers the five sub-questions from the service guide, the linear dis34 dump,
the existing reports, and one empirical capture:

* level 1 runs unconditionally at power-up; the boot calls the level-1 runner
  at bit 0x3F204400 (calla L3FDF72D0). The only conditional at the call site is
  the DUART1 IP3 hardware input bit (firmware @0x64000D0 bit 3), not a stored
  value.
* the host-port test has no 'not installed' sense; only SIMMs (@0x5000000) and
  the Image Option (@0x62000D0 bit 5) have presence checks.
* no persistent test-selection record: the power-up test set is a hard-coded
  ROM immediate (0x10FEFD80) written into a RAM descriptor; the interactive
  menu and NCP P3 only modify a run. NVRAM is read only by the user-settings
  code, never on the level-1 path.
* a level-1 failure wedges the boot in the board-LED code loop (0x3F208060,
  jruc itself); transcript = LEVEL1/2 TESTING, HOST PORT - 15, TYPE 'GO' TO
  CONTINUE, then the LED loop.
* the one in-ROM bypass (0x3F2043B0 -> OS cold-start 0x3F5788C0) is a
  board-input gate (IP3 high + no 0x55 signature); it skips all of level 1,
  not just the host port, and is not a firmware setting.

Verdict: no persistent/configurable skip; harness must pass level 1 or assert
DUART1 IP3 (0x0640000D bit 3) to take the OS branch.

Evidence + scratch: reference/l1probe/.

2026-10-16 12:42:35 +03:00

..

console-transcript.txt

reference: level-1 host-port test — can it be skipped? (analysis, no skip)

2026-10-16 12:42:35 +03:00

gate.lua

reference: level-1 host-port test — can it be skipped? (analysis, no skip)

2026-10-16 12:42:35 +03:00