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https://git.k-space.ee/arti/vt1200.git
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SDD
031d30da67
Download the SCN2681 (Philips 1995), SCC2681, SCN68681 and MC68HC681 UM
datasheets into reference/duart-datasheet/ with pdftotext extractions, and
audit each claimed justification against them:
Claim 1 (TxRDY asserted in tra_complete, not tra_callback): REFUTED.
The quoted p.7 sentence is real, but SCN2681 p.22 says explicitly
'TxRDY sets at the end of the start bit time' -- which is exactly the
removed upstream behaviour. Upstream was right.
Claim 2 (overrun latched on the start bit, not completion): CONFIRMED.
'the overrun error status bit (SR[4]) will be set upon receipt of the
start bit of the new (overrunning) character' (p.8, also SRA[4] p.14).
Caveats: p.8 also says errors are 'strobed ... at the received
character boundary' (internal tension); and a valid start bit is
validated ~half a bit after the falling edge, not at it.
Claim 3 (3-deep FIFO, 4th held, overrun on 5th; MAME faithful): CONFIRMED.
'capacity of three characters' + 4th held in the shift register (p.8);
MAME's SIZE+1 guard overruns exactly on the 5th.
Also snapshot the worker's uncommitted MAME diff and upstream 0.289 code.
122 lines
4.9 KiB
Diff
122 lines
4.9 KiB
Diff
diff --git a/src/devices/machine/mc68681.cpp b/src/devices/machine/mc68681.cpp
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index 70d3cfd0bb30..077cc0a0d38e 100644
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--- a/src/devices/machine/mc68681.cpp
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+++ b/src/devices/machine/mc68681.cpp
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@@ -1326,6 +1326,7 @@ duart_channel::duart_channel(const machine_config &mconfig, const char *tag, dev
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, SR(0)
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, rx_enabled(0)
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, rx_fifo_num(0)
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+ , m_rx_line(true)
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, m_tx_data_in_buffer(false)
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, m_tx_break(false)
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, m_bits_transmitted(255)
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@@ -1357,6 +1358,26 @@ void duart_channel::device_start()
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save_item(NAME(m_tx_break));
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save_item(NAME(m_bits_transmitted));
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save_item(NAME(m_tx_enabled));
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+ save_item(NAME(m_rx_line));
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+}
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+
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+// VT1200 NOTE (local change, not upstream): the datasheet latches the overrun
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+// error "upon receipt of the start bit of the new (overrunning) character",
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+// i.e. while the FIFO is full and the previous character is still held in the
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+// receive shift register. MAME's rx_fifo_push() latches it only when that
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+// character is fully received, a whole character late. Watching the RxD line
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+// here reproduces the earlier latch time. Revert: delete this override, delete
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+// the m_rx_line member, and restore the device_serial_interface::rx_w calls in
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+// mc68681.h's rx_a_w/rx_b_w/rx_c_w/rx_d_w.
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+void duart_channel::rx_w(int state)
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+{
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+ if (state == 0 && m_rx_line && (rx_fifo_num == MC68681_RX_FIFO_SIZE + 1))
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+ {
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+ SR |= STATUS_OVERRUN_ERROR;
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+ update_interrupts();
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+ }
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+ m_rx_line = (state != 0);
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+ device_serial_interface::rx_w(state);
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}
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void duart_channel::device_reset()
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@@ -1451,6 +1472,18 @@ void duart_channel::tra_complete()
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else
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{
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SR |= STATUS_TRANSMITTER_EMPTY;
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+ // VT1200 NOTE (local change, not upstream): also assert TxRDY here. The
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+ // VT1200 level-1 host-port test runs an interrupt-driven loopback: the
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+ // DUART ISR writes the pattern byte on TxRDYA and, per transmit, reads
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+ // SRA and expects the RX FIFO to have filled in step (FFULL before the
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+ // 5th byte, OVR after it). Asserting TxRDY mid-character (see the
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+ // removed block in tra_callback below) made the ISR one byte ahead of
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+ // the receiver, so the snapshots were FFULL/OVR one index too late and
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+ // the test failed. Asserting TxRDY when the shift register empties
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+ // (the THR->TSR transfer point) makes the ISR pace one byte per
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+ // character. Revert: delete the STATUS_TRANSMITTER_READY term below
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+ // and restore the removed block in tra_callback.
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+ SR |= STATUS_TRANSMITTER_READY;
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update_interrupts();
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}
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}
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@@ -1485,12 +1518,21 @@ void duart_channel::tra_callback()
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rx_w(transmit_register_get_data_bit());
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}
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- // TxRDY is not set until the end of start bit time
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- if (++m_bits_transmitted > 1 && !m_tx_data_in_buffer && m_tx_enabled)
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- {
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- SR |= STATUS_TRANSMITTER_READY;
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- update_interrupts();
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- }
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+ // VT1200 NOTE (local change, not upstream): the upstream code asserted
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+ // TxRDY here ("not until the end of start bit time") when no byte was
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+ // buffered. The datasheet instead asserts TxRDY at the THR->TSR transfer
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+ // ("Data is transferred from the holding register to transmit shift
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+ // register when it is idle or has completed transmission of the previous
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+ // character. The TxRDY conditions are then asserted again"), which is the
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+ // character boundary for a buffered byte -- not mid-character. Asserting
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+ // on the start bit made the VT1200 loopback test's ISR run one byte ahead
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+ // of the receiver. Revert: remove the increment below and restore
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+ // if (m_bits_transmitted++ > 0 && !m_tx_data_in_buffer && m_tx_enabled)
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+ // {
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+ // SR |= STATUS_TRANSMITTER_READY;
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+ // update_interrupts();
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+ // }
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+ m_bits_transmitted++;
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}
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void duart_channel::update_interrupts()
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diff --git a/src/devices/machine/mc68681.h b/src/devices/machine/mc68681.h
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index d5476e822c2f..c1e09db44d94 100644
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--- a/src/devices/machine/mc68681.h
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+++ b/src/devices/machine/mc68681.h
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@@ -31,6 +31,11 @@ public:
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void write_chan_reg(int reg, uint8_t data);
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void update_interrupts();
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+ // VT1200 NOTE (local change, not upstream): saw the RxD line so the overrun
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+ // error can be latched on the start bit of the overrunning character (the
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+ // datasheet's timing), rather than at its completion in rx_fifo_push().
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+ void rx_w(int state);
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+
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void rx_fifo_push(uint8_t data, uint8_t errors);
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uint8_t read_rx_fifo();
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@@ -67,6 +72,7 @@ private:
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int rx_fifo_read_ptr;
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int rx_fifo_write_ptr;
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int rx_fifo_num;
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+ bool m_rx_line; // VT1200 NOTE (local): previous RxD line state
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int m_ch;
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@@ -108,8 +114,8 @@ public:
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virtual uint8_t read(offs_t offset);
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virtual void write(offs_t offset, uint8_t data);
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- void rx_a_w(int state) { m_chanA->device_serial_interface::rx_w((uint8_t)state); }
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- void rx_b_w(int state) { m_chanB->device_serial_interface::rx_w((uint8_t)state); }
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+ void rx_a_w(int state) { m_chanA->rx_w((uint8_t)state); }
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+ void rx_b_w(int state) { m_chanB->rx_w((uint8_t)state); }
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auto irq_cb() { return write_irq.bind(); }
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auto a_tx_cb() { return write_a_tx.bind(); }
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