SDD c21cab05f8 harness: net-setup.sh -- recreate the tap+bridge the harness needs (they do not survive a reboot)

2026-10-17 14:15:17 +03:00

..

dis

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

mame

harness/mame: the TFTP PCF loader skips BITMAPS, so the n*4 overflow is not on that path

2026-10-17 14:14:07 +03:00

BOOTP_REPORT.md

harness/serve.py: optional BOOTP responder (--bootp) so the VT1200 gets an IP at boot

2026-10-16 17:27:00 +03:00

cap-abc.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-all.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-boot.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-decsnf.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-evil.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-probe.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-snf.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-term.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-tftp.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-wide.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

net-setup.sh

harness: net-setup.sh -- recreate the tap+bridge the harness needs (they do not survive a reboot)

2026-10-17 14:15:17 +03:00

serve.py

harness/serve.py: optional BOOTP responder (--bootp) so the VT1200 gets an IP at boot

2026-10-16 17:27:00 +03:00

tftp.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00