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Spec 8.3's hoist, and the 60 fps work showed it was the per-tile cost that mattered, not the per-frame one. Every tile_blit() call used to save 8 B registers, load B1/B3/B4/B7/B8/B9 and write 11 I/O registers (PSIZE, CONVSP, CONVDP, PMASK, the CONTROL read-modify- write and its read-back) -- all constants. The user's guide marks only SADDR and DADDR changed by PIXBLT, and the TMS34010 agent's reading of it confirms B1/B3 survive, so those two are the only ones a per-tile call has to reload. vram_tile.asm now exports tile_init_() (the constants, once per frame, called from paint_tiles/paint_delta) and a tile_blit_() that is setf, two pushes, two register loads, pixblt, two pops, rets. Measured on the real 140-tile deltas at a 60 fps send, same window, terminal's own status frames: before the hoist 162 accepted after the hoist 231 accepted (+43%) and the one-tile stream (where tile cost is nil) already runs at 60 fps with DINT: 600 frames sent at 59.8 fps, 579 accepted (96.5%), drops=0. Pixel verdicts unchanged: modes tiles, delta and replay all RESULT PASS with tile_check; 155 unit tests pass. What the remaining gap is, for the next reader: MAME's PIXBLT moves about 3.4 us per destination word (0.22 ms per 32x32 tile, measured from the accepted rate) against the unit's measured 0.40 us/word for FILL. A 140-tile delta is 8,960 words, i.e. ~30 ms of MAME CPU against a 16.7 ms frame -- so 60 fps for this content is bounded by the emulator's pixel engine, not by the design. Whether the unit can do it turns on the one number nobody has measured there: PIXBLT B,XY's per-word rate (spec 10, risk table).
131 lines
5.8 KiB
NASM
131 lines
5.8 KiB
NASM
; vram_tile.asm -- PIXBLT B,XY: one 32x32 1-bpp dictionary tile to the screen.
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;
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; Task 4's tile primitive. A dictionary entry is 32 rows of FOUR bytes (32 px
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; is two 16-bit words) = 128 bytes = 1024 bits, row-major, LSB first within each
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; byte (bit 0 is the leftmost pixel -- the scanout order) -- tilecost.py's
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; layout. PIXBLT's B source form reads packed 1-bit
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; pixels from a linear bit address and writes an XY destination, so one tile is
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;
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; SADDR = dict_base + index * 1024 (128 bytes a tile: index << 10)
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; SPTCH = 32 (4 bytes a source row)
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; DADDR = (ty*32 << 16) | (tx*32) (XY destination)
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; DYDX = (32 << 16) | 32 (32 rows, 32 pixels)
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;
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; DESCRIPTION-register assignments for PIXBLT B,XY (TMS34010 User's Guide,
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; instruction reference; vram.asm already uses the same values for L,XY and
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; vram_b.asm for B,XY):
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; SADDR = B0 source bit address (1 bpp, packed)
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; SPTCH = B1 source pitch in bits (4 bytes = 32 bits a row)
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; DADDR = B2 destination XY: (y << 16) | x
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; DPTCH = B3 destination pitch in bits (0x800 = 256-byte screen row)
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; OFFSET = B4 VRAM base bit address
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; DYDX = B7 dimensions in XY form: (rows << 16) | columns
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;
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; COLOR0 = B8 pixel value for a clear source bit (0 = black)
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; COLOR1 = B9 pixel value for a set source bit (0xFFFF = white)
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;
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; B8/B9 are NOT I/O registers: they are implied operands of every graphics
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; instruction, and a PIXBLT B expands a packed 1-bpp source into pixel values.
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; They are set explicitly because the resident OS leaves them arbitrary --
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; measured in the strip work: the first draw run painted every row black
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; because nothing had set B9. vram_b.asm's comment records the same finding.
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;
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; PSIZE (0C0000150h) 1 one bit per destination pixel
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; CONVSP (0C0000130h) 14h 0x800-bit pitch code (1 << (~0x14 & 0x1F) = 2048)
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; CONVDP (0C0000140h) 14h same, for the XY destination
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; PMASK (0C0000160h) 0 every plane writable
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; CONTROL (0C00000B0h) raster op 0 (replace), CD/RM/RR preserved
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;
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; Entry point / calling form (ruling R13). The TMS34010 C compiler's argument
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; frame is not decoded by any hand-written assembly in this repository; the
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; published-word form of vram.asm and vram_b.asm is used instead. This symbol
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; takes NO arguments: the two values a caller can change live in .bss words
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;
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; tile_src the source tile's bit address
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; tile_daddr the destination XY word
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;
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; and the C wrapper tile_blit(src, tx, ty) is the only entry point. B7 (DYDX)
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; is the constant 32x32 this primitive exists for.
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;
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; Two entry points, split by what changes: tile_init_() programs the constants
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; (pitch, offset, dimensions, colours, PSIZE/CONVSP/CONVDP/PMASK/CONTROL) once
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; per frame, and tile_blit_() then only reloads SADDR and DADDR -- the two
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; registers PIXBLT destroys -- before executing it.
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;
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; Revert note: this file is new in Task 4 and nothing else calls it. To
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; revert, delete it, the VRAMTILE entries in build-stream.sh and the
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; tile_blit/paint_tiles code in vidstream.c; the strip path (vram_b.asm) does
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; not reference any symbol defined here and is unaffected. The disassembly
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; this copies is vram_b.asm's, and its value table is quoted above from
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; vram_b.asm rather than re-derived.
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;
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; This file does NOT define _vid_dint_/_vid_eint_: they live in vram_b.asm and
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; both objects are linked, so a second definition would be a duplicate symbol.
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.ref _tile_src
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.ref _tile_daddr
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.text
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; _tile_init_ -- program everything that does not vary between tiles.
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;
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; Spec 8.3's hoist, and it is worth real time in MAME: measured per-tile cost
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; was ~0.36 ms against the unit's ~40 us, and the call did 11 I/O-register
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; accesses plus 8 push/pop pairs for constants that never change. The registers
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; this sets -- PSIZE, CONVSP, CONVDP, PMASK, CONTROL and B1 (SPTCH), B3 (DPTCH),
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; B4 (OFFSET), B7 (DYDX), B8 (COLOR0), B9 (COLOR1) -- survive PIXBLT (the
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; user's guide marks only SADDR/DADDR and B10-B14 as changed), so once per
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; frame is enough.
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;
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; B8/B9 are NOT I/O registers: they are implied operands of every graphics
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; instruction, and the resident OS leaves them arbitrary -- measured in the
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; strip work: the first draw run painted every row black because nothing had
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; set B9.
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.globl _tile_init_
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_tile_init_:
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setf 32, 0, 1
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movi 020h, b1 ; SPTCH = 32 bits = four bytes a tile row
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movi 800h, b3 ; DPTCH = 2048 bits = 256-byte screen row
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movi 04000000h, b4 ; OFFSET = VRAM base
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movi 0200020h, b7 ; DYDX = (32 rows << 16) | 32 pixels
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clr b8 ; COLOR0 = 0 (black)
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movi 0FFFFh, b9 ; COLOR1 = all planes set (white)
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movi 1, a1
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move a1, @0C0000150h, 0 ; PSIZE = 1
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movi 14h, a1
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move a1, @0C0000130h, 0 ; CONVSP = pitch code for 0x800 bits
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move a1, @0C0000140h, 0 ; CONVDP
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clr a1
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move a1, @0C0000160h, 0 ; PMASK = 0 (all planes writable)
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move a1, @0C0000170h, 0 ; upper half, for forward compatibility
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; raster op 0 (replace), CD/RM/RR preserved
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move @0C00000B0h, a1, 0 ; CONTROL
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andi 0801Fh, a1
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move a1, @0C00000B0h, 0
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move @0C00000B0h, a1, 0 ; read back: I/O writes are pipelined
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rets
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; _tile_blit_ -- one 32x32 tile, everything already programmed.
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;
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; Only B0 (SADDR) and B2 (DADDR) vary, and PIXBLT destroys both, so those two
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; are the only registers this saves and reloads. tile_init_() must have run.
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;
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; Revert note: this file is new in Task 4 and nothing else calls it. To
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; revert, delete it, the VRAMTILE entries in build-stream.sh and the
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; tile_blit/paint_tiles code in vidstream.c; the strip path (vram_b.asm) does
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; not reference any symbol defined here and is unaffected.
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.globl _tile_blit_
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_tile_blit_:
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setf 32, 0, 1
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move b0, -*sp, 1
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move b2, -*sp, 1
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move @_tile_src, b0, 1 ; SADDR: dictionary entry, index << 10 bits
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move @_tile_daddr, b2, 1 ; DADDR (XY): (ty*32 << 16) | tx*32
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pixblt b, xy
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move *sp+, b2, 1
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move *sp+, b0, 1
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rets
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.end
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