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SDD
88d006730a
Direct writer evidence (VT1200_STRUCTLOG): test +0x3c0 = ISR struct[idx4].0x3b0 and +0x3d0 = the ISR index5 SRA snapshot (TxRDYA path, 3FA79690/3FA7A390); test struct[i].0x60 = the ISR's received-status field (RxRDYA path 3FA79690). So both sub-tests' failures are the ISR's SRA snapshots and nothing else. L3FA71BC0 (18 flag sites probed, exactly one fires): c6, cmp 3FA73970 btst5 on struct[i].0x60, set when bit5 = SRA PARITY ERROR is set. Observed 0x0001 (clean) in most combinations and 0x0021 (RxRDY|parity error) in 3 -> its remaining failure is a parity error in the received status, not a timing one. c5 (framing error) does not fire. L3FA753D0's failure is the index4/index5 snapshots lacking FFULL/OVR (receive-count lag). One mechanism can produce both (a receive-side sub-bit mis-sampling/offset) but the parity error should be checked directly before attributing. Owner's L3FA753D0 reading verified with two corrections: their PCs are the loads (the compares are 3FA76050/E0, 3FA761E0, 3FA76390); and the flag encoding is bit N = flag +cN (proof: the +c6 store logs as val=0040 at the word a13(0xc0)), with the caveat that the 32-bit return also spans a13+0xd0.