SDD 47dac6b283 docs: DUART2 modelled; Terminal Manager reached; the bare run's old level-1 pass was a latch artefact (honest failure now)

2026-10-16 14:00:23 +03:00

..

dis

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

mame

docs: DUART2 modelled; Terminal Manager reached; the bare run's old level-1 pass was a latch artefact (honest failure now)

2026-10-16 14:00:23 +03:00

cap-abc.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00

cap-all.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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cap-boot.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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cap-decsnf.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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cap-evil.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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cap-probe.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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cap-snf.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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cap-term.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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cap-tftp.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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cap-wide.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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cap.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

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serve.py

checkpoint: VT1200 reverse-engineering workspace before board-model work

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tftp.log

checkpoint: VT1200 reverse-engineering workspace before board-model work

2026-10-16 01:37:50 +03:00