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SDD
c19c603d77
Add an opt-in knob (VT1200_DUART_IP3=1) that asserts DUART1 input-port bit 3. The POST gate at bit 0x3F2042D0 tests IP3 (@0x64000D0 bit 3) and, when it is high and the 0x6200000 status handshake did not return 0x55, branches to the OS cold-start 0x3F5788C0 (jauc), skipping the whole level-1 batch: the sole caller of the level-1 runner 0x3FDF72D0 is 0x3F204400, inside the skipped region. Verified from the raw opcodes against MAME's tms34010 opcode table (BTST_K sets Z=NOT bit; jane=JNE absolute-long) and empirically. Default behaviour is unchanged (no env -> the gate is not taken). The real terminal reads IP3 low, so this is a modelled board input, not a faithful POST path; results from a level-1-skipped harness are not evidence about the real hardware's POST, but are evidence about the OS/graphics route. osprobe.lua: gate/OS/Park probe (breakpoints on 0x3F2043B0 / 0x3F204400 / 0x3F5788C0, per-frame PC histogram, optional instruction trace and RAM-global dump).