From 5cd708460ad858662a3d680cc79dfb6ff1d2ec19 Mon Sep 17 00:00:00 2001 From: "opencode.energia.arti.ee" Date: Sat, 31 Oct 2026 00:01:57 +0000 Subject: [PATCH] plan: align the remaining CRC text with R14 (header-only) --- ...10-30-vt1200-stream-transport-and-row-strips.md | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/docs/superpowers/plans/2026-10-30-vt1200-stream-transport-and-row-strips.md b/docs/superpowers/plans/2026-10-30-vt1200-stream-transport-and-row-strips.md index aab6a4f..954a784 100644 --- a/docs/superpowers/plans/2026-10-30-vt1200-stream-transport-and-row-strips.md +++ b/docs/superpowers/plans/2026-10-30-vt1200-stream-transport-and-row-strips.md @@ -84,7 +84,7 @@ Expected: FAIL — `ModuleNotFoundError: harness.udpstream.frame` - [ ] **Step 3: Implement `frame.py`** -Layout (little-endian): `'V','S'`, version `0x01`, `kind`, `frame_no` u16, `payload_len` u16, `rows` u8, `stretch` u8, 2 reserved, `crc16` u16 over header bytes 0..11 plus the payload. CRC is CCITT-FALSE: poly `0x1021`, init `0xFFFF`, no reflection. +Layout (little-endian): `'V','S'`, version `0x01`, `kind`, `frame_no` u16, `payload_len` u16, `rows` u8, `stretch` u8, 2 reserved, `crc16` u16 over the 12 header bytes only (R14). CRC is CCITT-FALSE: poly `0x1021`, init `0xFFFF`, no reflection. - [ ] **Step 4: Run test to verify it passes** @@ -149,7 +149,8 @@ Expected: FAIL — no module `vidsrc` - [ ] **Step 3: Implement `Rows.pack_row` and `StripSource`** -`pack_row` sets bit `i` of the byte stream for pixel `i` (MSB first within each byte). `StripSource.encode` prepends `pack_header(KIND_STRIP, frame_no, len(rows), rows, stretch, payload=rows)` — **the payload must be passed so the CRC covers it**, or the terminal rejects every frame — and chunks the result at 1450 bytes. +`pack_row` sets bit `i` of the byte stream for pixel `i` (MSB first within each byte). `StripSource.encode` prepends `pack_header(KIND_STRIP, frame_no, len(rows), rows, stretch, payload=rows)` (the payload is +advisory under R14 — the CRC covers the header only) and chunks the result at 1450 bytes. - [ ] **Step 4: Run test to verify it passes** @@ -237,9 +238,10 @@ into a slot and asserts the payload's counters. The real DMA path is proven in T `tests/test_frame_parse.c`: build a 16-byte header + payload with the same layout `frame.py` writes (magic 'V','S', version 1, kind 1, frame_no, payload_len, rows, stretch, CRC16 at offset -12 over bytes 0..11 + payload). Assert `fp_parse` accepts it; flip one payload byte and assert it -is rejected; truncate it below `16 + payload_len` and assert rejection; corrupt the magic and the -version and assert rejection. +12 over the 12 header bytes). Assert `fp_parse` accepts it; flip one payload byte and assert it is +**still accepted** (the body is protected by the Ethernet FCS, R14); truncate it below +`16 + payload_len` and assert rejection; corrupt the magic, version and a header byte and assert +rejection. - [ ] **Step 2: Run it to verify it fails** @@ -250,7 +252,7 @@ Expected: link error, `fp_parse` undefined. K&R-compatible C89 that also compiles with the 1987 compiler: no `//`, no declarations after statements, CRC16 CCITT-FALSE as in `frame.py`. `fp_parse` checks length first, then magic and -version, then CRC over `buf[0..11] + payload`. +version, then CRC over the 12 header bytes only (R14). - [ ] **Step 4: Run the host test to verify it passes**