diff --git a/harness/mame/DUART_REPORT.md b/harness/mame/DUART_REPORT.md index 75a8d24..6231109 100644 --- a/harness/mame/DUART_REPORT.md +++ b/harness/mame/DUART_REPORT.md @@ -356,3 +356,193 @@ obvious common cause: **an ISR-driven transmit whose interrupt is never delivere enables, because the level-0 restart enters at `3F208060` with `DINT`. If the CPU really runs with interrupts disabled during the tests, an IRQ-driven transmit cannot work either — establish whether the test enables interrupts before relying on this. + +--- + +# FINAL FINDINGS — root cause found, acceptance NOT met (2026-10-16) + +## 0. Status in one paragraph + +**Root cause found and fixed:** the level-1 HOST PORT test drives its loopback with an +ISR, and **the DUART interrupt was never wired to the CPU**, so the transmit register +(`THRA`, reg 3) was never written. Wiring `duart1->irq_cb()` to the TMS34010's external +interrupt 1 makes `THRA` get written (0 -> 20 writes per run) and immediately fixes two +of the test's five checks: `SRA & 0xF0 == 0x10` (overrun) and the three `RHRA` pattern +reads now **pass**. **The acceptance line `LEVEL1/2 ERROR -> HOST PORT - 15` still +appears.** The remaining failure is a *timing* condition (below), not a wiring or a +modelling-of-the-device error. + +Address conventions: **Ghidra = `0x07E40000 + file`; bit = `0x3F200000 + file*8`; +a handler at base receives `(bitaddr-base) >> 4`.** All numbers below are stated in the +convention named. + +## 1. The root cause (verified) + +* The firmware's fixed CPU vector table points INT1 (vector `0xffffffc0`) and INT2 + (`0xffffffa0`) at **RAM trampolines**: `RLONG(0xffffffc0) = 0x00000F60`, and bit `0x0F60` + holds `JA 0x3FA92F40` (a 3-word stub the firmware installs at boot). INT2 -> bit `0x0F30` + -> `JA 0x3FA93070`. This resolves the earlier "vector reads 0xF60, which is bogus" + confusion: the vectors are fine, they point at RAM stubs. +* Those stubs call the DUART ISR `L3FA78D90` with `(mask, struct, window)` = + `(2, 0x270860, 0x6400000)` for INT1. So **DUART1's interrupt is expected on INT1**. +* The ISR is the only code anywhere that writes `THRA`: the TxRDYA path at + `3FA79ED0` does `window[reg3] = struct[i].0x360`, and `struct[i].0x360` (ISR base) is + the test's pattern array `struct[i].0x330`. +* `INTENB` **is** enabled at the test: `VT1200_*` run shows `INTENB` going `0x0400` + (display) at f154 and `0x0006` (**INT1|INT2**) at f474, i.e. the orchestrator's caveat + is cleared — interrupts are on when the host-port test runs. + +## 2. What I changed (kept) + +* `harness/mame/vt1200.cpp`: `m_duart1->irq_cb()` / `m_duart2->irq_cb()` -> new + `duart1_irq_w` / `duart2_irq_w`, which call `m_maincpu->set_input_line(0/1, ...)`. + Gated on `VT1200_DUART` (no-env baseline untouched). This is **the** fix for the + missing transmit. +* `/home/arti/code/k-space/mame0289/src/devices/machine/mc68681.cpp`: **one datasheet- + backed timing correction**, with a revert note inline. MAME asserted `TxRDY` + mid-character ("not until the end of start bit time"); the datasheet says TxRDY is + re-asserted at the **THR->TSR transfer** ("Data is transferred from the holding + register to transmit shift register when it is idle or has completed transmission of + the previous character. The TxRDY conditions are then asserted again"). Corrected to + assert at `tra_complete()`. This took the failure from **two** failing checks to + **one**. (Caveat: for the *idle* case the datasheet's transfer is immediate, so this is + exact only for the buffered case, which is the test's steady state.) + +## 3. Evidence that the wiring is the fix + +`VT1200_DUARTLOG` (non-deduplicated), 900 frames, before vs after: + +``` +before: writes to reg 3 (THRA): 0 +after : writes to reg 3 (THRA): 20 (0xAA,0xFF,0xAA,0x55,0x00 ..., one per TxRDYA) +``` + +The test's own comparisons, breakpointed: + +``` +before SRA&0xF0 = 0x00 (needs 0x10) RHRA = 0x00 (needs 0x0A,0x1F,0x0A) +after SRA&0xF0 = 0x10 PASS RHRA = 0x0A,0x1F,0x0A PASS +``` + +So the "external responder" conclusion in §0/§4 is **dead**: the source of the pattern is +the firmware's own DUART ISR, reached only when the DUART IRQ is wired. + +## 4. The remaining failure — measured, with numbers + +The host-port test's `L3FA753D0` pass additionally snapshots `SRA` at *every* TxRDY +interrupt and stores it into the descriptor as `struct[index].0x3b0` (ISR base), where +`index` = number of `THRA` writes so far. The test then requires: + +* `struct[4].0x3b0` (read as the test's `struct+0x3c0`) to have **bit 1 = FFULL**, and +* `struct[5].0x3b0` (test `struct+0x3d0`) to have **bit 4 = OVERRUN**. + +i.e. the loopback receiver must be **in lockstep** with the transmitter: after k bytes are +transmitted, k bytes must have been received. + +Measured (cycles of the TMS34010, `total_cycles()`), final pass: + +``` +TxRDY IRQ T_k = 44592754, 44611168, 44629580, 44647992, 44666403, 44684815 (spacing 18414) +THRA write W_k = T_k + 185 +RX start-bit sync = W_k + 2605 (= 1 bit time; bit = 2604) +RX rcv_complete = sync + 16926 (= 6.5 bit times, the bit-centre samples) + = W_k + 19531 +``` + +So the received character is delivered **19531 cycles after its THRA write**, while the +test's next snapshot is **18414 cycles** later. The receiver is **1117 cycles (~0.43 bit) +behind per character**, so at `index5` the FIFO holds 3, not the required 4, and OVERRUN +is not yet set. Concretely: `flags` = `0x00000001` (only the `struct[5]` OVR check fails), +`SRA` snapshots = `0x0C,0x0C,0x0D,0x0D,0x0F,0x0F`. + +To pass, the delivery must be `< 18229` cycles after the write. + +## 5. MAME-vs-datasheet audit of the remaining margin + +I checked each candidate against the SCC68681 datasheet. **Do not tune these — one is a +genuine bug, the others are faithful.** + +1. **FIFO depth / overrun threshold — MAME is FAITHFUL.** The owner's candidate + (`rx_fifo_push` overruns at `SIZE+1 == 4`) is correct: the datasheet says the FIFO is + **three** characters, a 4th character is **held in the receive shift register**, and + overrun occurs only on the 5th ("If the FIFO is full when a new character is received, + that character is held in the receive shift register ... If an additional character is + received while this state exists ... the overrun error status bit (SR[4]) will be + set"). MAME's `SIZE+1` guard models exactly that. **Not the bug.** +2. **TxRDY timing — MAME was WRONG (fixed, §2).** Removed one failing check. +3. **Overrun *timing* — MAME is WRONG, and this is the remaining margin.** The datasheet + says SR[4] is set **"upon receipt of the start bit of the new (overrunning) + character"** — i.e. at the start of the 5th character (~`W+1.5` bits), not at its + completion. MAME sets it in `rx_fifo_push()`, i.e. at the 5th character's + **completion** (`W+7.5` bits) — about a whole character late. Setting it at the + overrunning character's start bit would move `SRA`'s OVR bit into `struct[5]`'s + snapshot with ~15k cycles of margin and **should make the test pass**. This is the + concrete next step; it was *not* implemented here because it needs a "new character + started" hook in the receive path (generic `diserial.cpp`, or a DUART override), which + I could not land and validate within budget without risking a green-on-a-guess. +4. **Loopback receive clock — MAME deviates, but is not the immediate blocker.** The + datasheet's local-loopback mode says "**the transmit clock is used for the receiver**"; + MAME clocks the loopback receiver from the independent receive clock + (`set_rcv_rate` + the generic RX sampling, with a deliberate half-cycle start guard). + This is the source of the 0.5-bit phase; I tried removing the guard and the received + bytes became **wrong** (`0x14,0x1E,0x14` instead of `0x0A,0x1F,0x0A`), confirming the + guard is what puts the samples on the bit centres. Do not remove it. + +## 6. Acceptance / regression + +* **Acceptance: NOT MET.** With `VT1200_VRAM=1 VT1200_BOARD_MODEL=handshake + VT1200_BOARD_BUSY_TICKS=2 VT1200_BOARD_SWITCH="0640000D:70:70" VT1200_DUART=1 + VT1200_DUART_SEL=1`, `cap.lua` still prints `'LEVEL1/2 ERROR -> HOST PORT - 15 '`. + No next gate is reached. +* **Regression: HELD.** With no `VT1200_*` env vars, `progress.lua` at 200 frames: + `PC=3FDCE400 samples=199`. + +## 7. Artifacts + +* `harness/mame/vt1200.cpp` — IRQ wiring + `VT1200_STRUCTLOG` / `VT1200_IRQLOG` + (transparent logging proxies) and a cycle stamp on `VT1200_DUARTLOG`. +* `harness/mame/hp_trace.lua`, `hp_probe.lua`, `hp_probe2.lua`, `hp_snap.lua`, + `hp_int.lua`, `hp_ret.lua`, `hp_dump.lua`, `hp_dump2.lua` — the measurement scripts. +* `harness/mame/hp_*.log`, `hp_*.out` — the raw evidence quoted above. +* MAME tree: `mc68681.cpp` (TxRDY timing, revert note inline). `diserial.cpp` left + **unmodified**. + +## 8. UPDATE — overrun-latch timing fixed; acceptance still not met + +Item 3 of §5 was implemented and is the second datasheet-backed MAME correction: + +* `mc68681.h` / `mc68681.cpp`: added `duart_channel::rx_w()` (and routed + `rx_a_w`/`rx_b_w` through it). When the RxD line falls (a start bit) while + `rx_fifo_num == MC68681_RX_FIFO_SIZE + 1` (FIFO full and the previous character + still held), it latches `STATUS_OVERRUN_ERROR`. This is the datasheet's timing + ("the overrun error status bit (SR[4]) will be set **upon receipt of the start + bit** of the new (overrunning) character") instead of `rx_fifo_push()`'s + latch-at-completion. Revert note inline. + +Effect on the test's own comparisons (the `struct[4]`/`struct[5]` SRA snapshots): + +``` +before RX-3c0 = 0x70005 (FFULL clear) RX-3d0 = 0x0007 (OVR clear) flags = 0x00000001 +after RX-3c0 = 0x1F000F (FFULL set) RX-3d0 = 0x001F (OVR set) flags = 0x00000000 +``` + +i.e. **every check in `L3FA753D0` (RXCHECK) now passes, and it proceeds to test the +next parameter combination** — which it never did before. This confirms §5.3 was a +real MAME inaccuracy, not a guess. + +**The acceptance is still not met**, and I did not resolve the next failure. The +host-port test's first sub-test `L3FA71BC0` now returns 6, and the caller +(`3FA84FE0`) turns any non-zero return into the reported error. `L3FA71BC0`'s own +check sites (`3FA73500`/`3FA73580`/`3FA73610`, which set its flag bits) were +breakpointed and **never fired** in 700 frames, so its return value does not come +from the path I read statically; that is the loose end. `L3FA71BC0` is the DUART +*baud/timer* sub-test that runs before RXCHECK, so it is a separate condition from +the loopback data path. + +Final state of the acceptance instrument (900 frames): + +``` +'LEVEL1/2 TESTING ** ' +'LEVEL1/2 ERROR -> HOST PORT - 15 ' <-- unchanged +regression (no VT1200_* env): PC=3FDCE400 samples=199 HOLD +``` diff --git a/harness/mame/hp_bc0.lua b/harness/mame/hp_bc0.lua new file mode 100644 index 0000000..f853054 --- /dev/null +++ b/harness/mame/hp_bc0.lua @@ -0,0 +1,21 @@ +-- hp_bc0.lua -- L3FA71BC0's own checks (the first host-port sub-test). +local machine = manager.machine +local cpu = machine.devices[':maincpu'] +local dbg = machine.debugger +if not dbg then print("ERROR: no debugger"); machine:exit(); return end +local function bp(addr, body) + dbg:command('bpset ' .. addr .. ',,{ ' .. body .. ' ; g }') +end +bp("3fa73500", 'printf "BC0-C1 a7=%08X s320=%04X\\n", a7, d@270BB0') +bp("3fa73580", 'printf "BC0-C2 a7=%08X s0=%04X\\n", a7, d@270890') +bp("3fa73610", 'printf "BC0-C3 a7=%08X s320=%04X\\n", a7, d@270BB0') +bp("3fa73630", 'printf "BC0-C4 a7=%08X s0=%04X\\n", a7, d@270890') +bp("3fa735a0", 'printf "BC0-C5 a7=%08X\\n", a7') +bp("3fa73830", 'printf "BC0-C6 a7=%08X s9=%08X\\n", a7, a9') +local n = 0 +emu.register_frame_done(function() + n = n + 1 + if n >= tonumber(os.getenv("HP_FRAMES") or "700") then print("done "..n); machine:exit() end +end, "vt1200-hp-bc0") +dbg.visible_cpu = cpu +dbg.execution_state = 'run' diff --git a/harness/mame/hp_board.log b/harness/mame/hp_board.log new file mode 100644 index 0000000..c527799 --- /dev/null +++ b/harness/mame/hp_board.log @@ -0,0 +1,126 @@ +# kind addr pc value (bit addresses; distinct (addr,pc) only) +W 0640000D pc=3F2000B0 val=0000 +R 0640000F pc=3F200100 val=00FF +R 0640000E pc=3F200150 val=00FF +W 0620000D pc=3F200190 val=0000 +W 0620000F pc=3F2001E0 val=0004 +R 0640000F pc=3F200250 val=00FF +R 0640000D pc=3F200380 val=00F0 +R 0640000D pc=3F200A20 val=00F0 +R 0640000D pc=3F202650 val=00F0 +W 05900000 pc=3FDDCAE0 val=0000 +W 05800000 pc=3FDDCB20 val=0004 +R 0640000D pc=3F2045A0 val=00F0 +W 0620000D pc=3F2052C0 val=0000 +W 0620000E pc=3F205310 val=00FF +W 0620000F pc=3F205370 val=0004 +R 0640000E pc=3F2042D0 val=00FF +R 0640000D pc=3F204300 val=00F0 +W 0640000D pc=3FDF1150 val=0000 +W 0640000F pc=3FDF1190 val=0001 +R 06200001 pc=3FDF3900 val=0000 +R 06200001 pc=3FDF3A20 val=0000 +W 06200003 pc=3FDF3AD0 val=0011 +W 06200003 pc=3FDF3BE0 val=008C +R 0640000D pc=3FDF7DE0 val=00F0 +W 06200002 pc=3FA91260 val=00CA +W 06200002 pc=3FA91300 val=002A +W 06200002 pc=3FA913B0 val=003A +W 06200002 pc=3FA91460 val=004A +W 06200002 pc=3FA91500 val=005A +W 06200002 pc=3FA915A0 val=001A +W 0620000A pc=3FA91650 val=00CA +W 0620000A pc=3FA916F0 val=002A +W 0620000A pc=3FA917A0 val=003A +W 0620000A pc=3FA91850 val=004A +W 0620000A pc=3FA91900 val=005A +W 0620000A pc=3FA919A0 val=001A +W 06200000 pc=3FA91A30 val=0013 +W 06200000 pc=3FA91AC0 val=0007 +W 06200001 pc=3FA91B70 val=0099 +W 06200002 pc=3FA91C70 val=0005 +W 06200008 pc=3FA91D10 val=0007 +W 06200008 pc=3FA91DB0 val=0007 +W 06200009 pc=3FA91E60 val=0099 +W 0620000A pc=3FA91F40 val=0005 +W 06200005 pc=3FA91FE0 val=0000 +R 06200001 pc=3FDCE670 val=0099 +R 06200003 pc=3FDCE700 val=008C +R 06200001 pc=3FDCE820 val=0099 +W 06200003 pc=3FDCE8D0 val=00E1 +R 06200001 pc=3FDCE910 val=0099 +R 06200003 pc=3FDCE970 val=00E1 +R 06200001 pc=3FDCEA90 val=0099 +W 0620000D pc=3FDF1B40 val=0000 +W 0620000E pc=3FDF1B80 val=000C +W 06400002 pc=3FA90A00 val=00CA +W 06400002 pc=3FA90AB0 val=002A +W 06400002 pc=3FA90B60 val=003A +W 06400002 pc=3FA90C10 val=004A +W 06400002 pc=3FA90CC0 val=005A +W 06400002 pc=3FA90D60 val=001A +W 0640000A pc=3FA90E10 val=00CA +W 0640000A pc=3FA90EC0 val=002A +W 0640000A pc=3FA90F70 val=003A +W 0640000A pc=3FA91020 val=004A +W 0640000A pc=3FA910D0 val=005A +W 0640000A pc=3FA91170 val=001A +W 06200002 pc=3FA90A00 val=00CA +W 06200002 pc=3FA90AB0 val=002A +W 06200002 pc=3FA90B60 val=003A +W 06200002 pc=3FA90C10 val=004A +W 06200002 pc=3FA90CC0 val=005A +W 06200002 pc=3FA90D60 val=001A +W 0620000A pc=3FA90E10 val=00CA +W 0620000A pc=3FA90EC0 val=002A +W 0620000A pc=3FA90F70 val=003A +W 0620000A pc=3FA91020 val=004A +W 0620000A pc=3FA910D0 val=005A +W 0620000A pc=3FA91170 val=001A +W 0640000F pc=3FA7C330 val=0080 +W 06400002 pc=3FA778D0 val=00FA +W 06400002 pc=3FA77990 val=00CA +W 06400002 pc=3FA77A30 val=002A +W 06400002 pc=3FA77AD0 val=003A +W 06400002 pc=3FA77B70 val=004A +W 06400002 pc=3FA77C10 val=005A +W 06400002 pc=3FA77CA0 val=001A +W 0640000A pc=3FA77990 val=00CA +W 0640000A pc=3FA77A30 val=002A +W 0640000A pc=3FA77AD0 val=003A +W 0640000A pc=3FA77B70 val=004A +W 0640000A pc=3FA77C10 val=005A +W 0640000A pc=3FA77CA0 val=001A +W 06400005 pc=3FA78B40 val=0007 +W 0640000D pc=3FA704E0 val=0000 +W 06400004 pc=3FA71CB0 val=0060 +W 06400002 pc=3FA71F20 val=003A +W 06400002 pc=3FA71FD0 val=002A +W 06400002 pc=3FA72080 val=004A +W 06400002 pc=3FA72120 val=001A +W 06400001 pc=3FA72220 val=0088 +W 06400000 pc=3FA73090 val=0012 +W 06400000 pc=3FA731B0 val=0080 +W 06400002 pc=3FA73260 val=0005 +W 06400002 pc=3FA73420 val=000A +W 06400002 pc=3FA74BE0 val=002A +W 06400002 pc=3FA74C80 val=002B +W 06400002 pc=3FA74D10 val=004A +W 06400002 pc=3FA74DA0 val=0065 +W 06400002 pc=3FA74E60 val=007A +W 06400002 pc=3FA74F10 val=0050 +W 06400005 pc=3FA78D10 val=0000 +W 06400002 pc=3FA75570 val=003A +W 06400002 pc=3FA75620 val=002A +W 06400002 pc=3FA756D0 val=004A +W 06400002 pc=3FA75770 val=001A +W 06400001 pc=3FA75870 val=0088 +W 06400000 pc=3FA75BC0 val=0010 +W 06400000 pc=3FA75CE0 val=0080 +W 06400002 pc=3FA75D90 val=0005 +W 06400002 pc=3FA76010 val=000A +R 06400001 pc=3FA761B0 val=0000 +R 06400003 pc=3FA76360 val=0000 +W 0640000F pc=3FA850F0 val=0080 +W 0640000D pc=3F208830 val=0000 +W 0640000F pc=3F208880 val=00FF diff --git a/harness/mame/hp_duart7.log b/harness/mame/hp_duart7.log new file mode 100644 index 0000000..24e7a82 --- /dev/null +++ b/harness/mame/hp_duart7.log @@ -0,0 +1,443 @@ +# win kind reg val pc -- every DUART access (not de-duplicated) +1 W reg=D val=0000 pc=3F2000B0 cyc=7 +1 R reg=F val=00FF pc=3F200100 cyc=12 +1 W reg=F val=00FF pc=3F200100 cyc=12 +1 R reg=E val=00FF pc=3F200150 cyc=15 +1 W reg=E val=000F pc=3F200150 cyc=15 +1 R reg=F val=00FF pc=3F200250 cyc=29 +1 W reg=F val=0001 pc=3F200250 cyc=29 +1 R reg=D val=00F0 pc=3F200380 cyc=46 +1 R reg=D val=00F0 pc=3F200A20 cyc=2123 +1 R reg=D val=00F0 pc=3F202650 cyc=2715 +1 R reg=D val=00F0 pc=3F2045A0 cyc=465049 +1 R reg=E val=00FF pc=3F2042D0 cyc=576004 +1 W reg=E val=0001 pc=3F2042D0 cyc=576004 +1 R reg=D val=00F0 pc=3F204300 cyc=576005 +1 W reg=D val=0000 pc=3FDF1150 cyc=576167 +1 W reg=F val=0001 pc=3FDF1190 cyc=576171 +1 R reg=D val=00F0 pc=3FDF7DE0 cyc=1297177 +1 R reg=D val=00F0 pc=3F2045A0 cyc=1897379 +1 W reg=2 val=00CA pc=3FA90A00 cyc=3737622 +1 W reg=2 val=002A pc=3FA90AB0 cyc=3737945 +1 W reg=2 val=003A pc=3FA90B60 cyc=3738268 +1 W reg=2 val=004A pc=3FA90C10 cyc=3738591 +1 W reg=2 val=005A pc=3FA90CC0 cyc=3738914 +1 W reg=2 val=001A pc=3FA90D60 cyc=3739236 +1 W reg=A val=00CA pc=3FA90E10 cyc=3739559 +1 W reg=A val=002A pc=3FA90EC0 cyc=3739882 +1 W reg=A val=003A pc=3FA90F70 cyc=3740205 +1 W reg=A val=004A pc=3FA91020 cyc=3740528 +1 W reg=A val=005A pc=3FA910D0 cyc=3740851 +1 W reg=A val=001A pc=3FA91170 cyc=3741173 +1 W reg=F val=0080 pc=3FA7C330 cyc=3744820 +1 R reg=D val=00F0 pc=3F2045A0 cyc=10040220 +1 R reg=D val=00F0 pc=3F2045A0 cyc=15792800 +1 R reg=D val=00F0 pc=3F2045A0 cyc=15926711 +1 R reg=D val=00F0 pc=3F2045A0 cyc=34826663 +1 W reg=2 val=00FA pc=3FA778D0 cyc=43724635 +1 W reg=2 val=00CA pc=3FA77990 cyc=43724961 +1 W reg=2 val=002A pc=3FA77A30 cyc=43725282 +1 W reg=2 val=003A pc=3FA77AD0 cyc=43725603 +1 W reg=2 val=004A pc=3FA77B70 cyc=43725924 +1 W reg=2 val=005A pc=3FA77C10 cyc=43726245 +1 W reg=2 val=001A pc=3FA77CA0 cyc=43726565 +1 W reg=A val=00CA pc=3FA77990 cyc=43726956 +1 W reg=A val=002A pc=3FA77A30 cyc=43727277 +1 W reg=A val=003A pc=3FA77AD0 cyc=43727598 +1 W reg=A val=004A pc=3FA77B70 cyc=43727919 +1 W reg=A val=005A pc=3FA77C10 cyc=43728240 +1 W reg=A val=001A pc=3FA77CA0 cyc=43728560 +1 W reg=2 val=00FA pc=3FA778D0 cyc=43735282 +1 W reg=2 val=00CA pc=3FA77990 cyc=43735608 +1 W reg=2 val=002A pc=3FA77A30 cyc=43735929 +1 W reg=2 val=003A pc=3FA77AD0 cyc=43736250 +1 W reg=2 val=004A pc=3FA77B70 cyc=43736571 +1 W reg=2 val=005A pc=3FA77C10 cyc=43736892 +1 W reg=2 val=001A pc=3FA77CA0 cyc=43737212 +1 W reg=A val=00CA pc=3FA77990 cyc=43737603 +1 W reg=A val=002A pc=3FA77A30 cyc=43737924 +1 W reg=A val=003A pc=3FA77AD0 cyc=43738245 +1 W reg=A val=004A pc=3FA77B70 cyc=43738566 +1 W reg=A val=005A pc=3FA77C10 cyc=43738887 +1 W reg=A val=001A pc=3FA77CA0 cyc=43739207 +1 W reg=5 val=0007 pc=3FA78B40 cyc=43739320 +1 W reg=D val=0000 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pc=3FA75D90 cyc=44592754 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44592836 +1 R reg=1 val=000C pc=3FA79E50 cyc=44592917 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44592939 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44592961 +1 W reg=E val=0000 pc=3FA7A060 cyc=44592983 +1 W reg=F val=0000 pc=3FA7A110 cyc=44593005 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44593027 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44593061 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44611247 +1 R reg=1 val=000C pc=3FA79E50 cyc=44611328 +1 W reg=3 val=00FF pc=3FA79F00 cyc=44611350 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44611372 +1 W reg=E val=0000 pc=3FA7A060 cyc=44611394 +1 W reg=F val=0000 pc=3FA7A110 cyc=44611416 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44611438 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44611472 +1 R reg=5 val=000B pc=3FA78E30 cyc=44629659 +1 R reg=1 val=000D pc=3FA79E50 cyc=44629740 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44629762 +1 R reg=1 val=0001 pc=3FA79FB0 cyc=44629784 +1 W reg=E val=0000 pc=3FA7A060 cyc=44629806 +1 W reg=F val=0000 pc=3FA7A110 cyc=44629828 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44629850 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44629884 +1 R reg=5 val=000B pc=3FA78E30 cyc=44648071 +1 R reg=1 val=000D pc=3FA79E50 cyc=44648152 +1 W reg=3 val=0055 pc=3FA79F00 cyc=44648174 +1 R reg=1 val=0001 pc=3FA79FB0 cyc=44648196 +1 W reg=E val=0000 pc=3FA7A060 cyc=44648218 +1 W reg=F val=0000 pc=3FA7A110 cyc=44648240 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44648262 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44648296 +1 R reg=5 val=000B pc=3FA78E30 cyc=44666482 +1 R reg=1 val=000F pc=3FA79E50 cyc=44666563 +1 W reg=3 val=0000 pc=3FA79F00 cyc=44666585 +1 R reg=1 val=0003 pc=3FA79FB0 cyc=44666607 +1 W reg=E val=0000 pc=3FA7A060 cyc=44666629 +1 W reg=F val=0000 pc=3FA7A110 cyc=44666651 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44666673 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44666707 +1 R reg=5 val=000B pc=3FA78E30 cyc=44684894 +1 R reg=1 val=000F pc=3FA7A3C0 cyc=44684964 +1 W reg=2 val=0008 pc=3FA7A3F0 cyc=44684970 +1 R reg=1 val=0003 pc=3FA7A440 cyc=44684978 +1 W reg=2 val=000A pc=3FA76010 cyc=44775477 +1 R reg=1 val=0012 pc=3FA761B0 cyc=44775514 +1 R reg=3 val=000A pc=3FA76360 cyc=44775554 +1 R reg=1 val=0012 pc=3FA761B0 cyc=44775579 +1 R reg=3 val=001F pc=3FA76360 cyc=44775619 +1 R reg=1 val=0010 pc=3FA761B0 cyc=44775644 +1 R reg=3 val=000A pc=3FA76360 cyc=44775684 +1 W reg=5 val=0000 pc=3FA78D10 cyc=44775853 +1 W reg=5 val=0007 pc=3FA78B40 cyc=44775978 +1 W reg=5 val=0000 pc=3FA78D10 cyc=44776206 +1 W reg=2 val=00FA pc=3FA778D0 cyc=44776311 +1 W reg=2 val=00CA pc=3FA77990 cyc=44776637 +1 W reg=2 val=002A pc=3FA77A30 cyc=44776958 +1 W reg=2 val=003A pc=3FA77AD0 cyc=44777279 +1 W reg=2 val=004A pc=3FA77B70 cyc=44777600 +1 W reg=2 val=005A pc=3FA77C10 cyc=44777921 +1 W reg=2 val=001A pc=3FA77CA0 cyc=44778241 +1 W reg=A val=00CA pc=3FA77990 cyc=44778632 +1 W reg=A val=002A pc=3FA77A30 cyc=44778953 +1 W reg=A val=003A pc=3FA77AD0 cyc=44779274 +1 W reg=A val=004A pc=3FA77B70 cyc=44779595 +1 W reg=A val=005A pc=3FA77C10 cyc=44779916 +1 W reg=A val=001A pc=3FA77CA0 cyc=44780236 +1 W reg=F val=0080 pc=3FA850F0 cyc=44780471 +1 R reg=D val=00F0 pc=3F2045A0 cyc=44780939 +1 W reg=D val=0000 pc=3F208830 cyc=45055851 +1 W reg=F val=00FF pc=3F208880 cyc=45055856 diff --git a/harness/mame/hp_duart8.log b/harness/mame/hp_duart8.log new file mode 100644 index 0000000..e655c06 --- /dev/null +++ b/harness/mame/hp_duart8.log @@ -0,0 +1,234 @@ +# win kind reg val pc -- every DUART access (not de-duplicated) +1 W reg=D val=0000 pc=3F2000B0 cyc=7 +1 R reg=F val=00FF pc=3F200100 cyc=12 +1 W reg=F val=00FF pc=3F200100 cyc=12 +1 R reg=E val=00FF pc=3F200150 cyc=15 +1 W reg=E val=000F pc=3F200150 cyc=15 +1 R reg=F val=00FF pc=3F200250 cyc=29 +1 W reg=F val=0001 pc=3F200250 cyc=29 +1 R reg=D val=00F0 pc=3F200380 cyc=46 +1 R reg=D val=00F0 pc=3F200A20 cyc=2123 +1 R reg=D val=00F0 pc=3F202650 cyc=2715 +1 R reg=D val=00F0 pc=3F2045A0 cyc=465049 +1 R reg=E val=00FF pc=3F2042D0 cyc=576004 +1 W reg=E val=0001 pc=3F2042D0 cyc=576004 +1 R reg=D val=00F0 pc=3F204300 cyc=576005 +1 W reg=D val=0000 pc=3FDF1150 cyc=576167 +1 W reg=F val=0001 pc=3FDF1190 cyc=576171 +1 R reg=D val=00F0 pc=3FDF7DE0 cyc=1297177 +1 R reg=D val=00F0 pc=3F2045A0 cyc=1897379 +1 W reg=2 val=00CA pc=3FA90A00 cyc=3737622 +1 W reg=2 val=002A pc=3FA90AB0 cyc=3737945 +1 W reg=2 val=003A pc=3FA90B60 cyc=3738268 +1 W reg=2 val=004A pc=3FA90C10 cyc=3738591 +1 W reg=2 val=005A pc=3FA90CC0 cyc=3738914 +1 W reg=2 val=001A pc=3FA90D60 cyc=3739236 +1 W reg=A val=00CA pc=3FA90E10 cyc=3739559 +1 W reg=A val=002A pc=3FA90EC0 cyc=3739882 +1 W reg=A val=003A pc=3FA90F70 cyc=3740205 +1 W reg=A val=004A pc=3FA91020 cyc=3740528 +1 W reg=A val=005A pc=3FA910D0 cyc=3740851 +1 W reg=A val=001A pc=3FA91170 cyc=3741173 +1 W reg=F val=0080 pc=3FA7C330 cyc=3744820 +1 R reg=D val=00F0 pc=3F2045A0 cyc=10040220 +1 R reg=D val=00F0 pc=3F2045A0 cyc=15792800 +1 R reg=D val=00F0 pc=3F2045A0 cyc=15926711 +1 R reg=D val=00F0 pc=3F2045A0 cyc=34826663 +1 W reg=2 val=00FA pc=3FA778D0 cyc=43724635 +1 W reg=2 val=00CA pc=3FA77990 cyc=43724961 +1 W reg=2 val=002A pc=3FA77A30 cyc=43725282 +1 W reg=2 val=003A pc=3FA77AD0 cyc=43725603 +1 W reg=2 val=004A pc=3FA77B70 cyc=43725924 +1 W reg=2 val=005A pc=3FA77C10 cyc=43726245 +1 W reg=2 val=001A pc=3FA77CA0 cyc=43726565 +1 W reg=A val=00CA pc=3FA77990 cyc=43726956 +1 W reg=A val=002A pc=3FA77A30 cyc=43727277 +1 W reg=A val=003A pc=3FA77AD0 cyc=43727598 +1 W reg=A val=004A pc=3FA77B70 cyc=43727919 +1 W reg=A val=005A pc=3FA77C10 cyc=43728240 +1 W reg=A val=001A pc=3FA77CA0 cyc=43728560 +1 W reg=2 val=00FA pc=3FA778D0 cyc=43735282 +1 W reg=2 val=00CA pc=3FA77990 cyc=43735608 +1 W reg=2 val=002A pc=3FA77A30 cyc=43735929 +1 W reg=2 val=003A pc=3FA77AD0 cyc=43736250 +1 W reg=2 val=004A pc=3FA77B70 cyc=43736571 +1 W reg=2 val=005A pc=3FA77C10 cyc=43736892 +1 W reg=2 val=001A pc=3FA77CA0 cyc=43737212 +1 W reg=A val=00CA pc=3FA77990 cyc=43737603 +1 W reg=A val=002A pc=3FA77A30 cyc=43737924 +1 W reg=A val=003A pc=3FA77AD0 cyc=43738245 +1 W reg=A val=004A pc=3FA77B70 cyc=43738566 +1 W reg=A val=005A pc=3FA77C10 cyc=43738887 +1 W reg=A val=001A pc=3FA77CA0 cyc=43739207 +1 W reg=5 val=0007 pc=3FA78B40 cyc=43739320 +1 W reg=D val=0000 pc=3FA704E0 cyc=43739379 +1 W reg=4 val=0060 pc=3FA71CB0 cyc=43739476 +1 W reg=2 val=003A pc=3FA71F20 cyc=43739539 +1 W reg=2 val=002A pc=3FA71FD0 cyc=43739862 +1 W reg=2 val=004A pc=3FA72080 cyc=43740185 +1 W reg=2 val=001A pc=3FA72120 cyc=43740507 +1 W reg=1 val=0088 pc=3FA72220 cyc=43740837 +1 W reg=0 val=0012 pc=3FA73090 cyc=43745391 +1 W reg=0 val=0080 pc=3FA731B0 cyc=43745728 +1 W reg=2 val=0005 pc=3FA73260 cyc=43805849 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43805931 +1 R reg=1 val=000C pc=3FA79E50 cyc=43806012 +1 W reg=3 val=00AA pc=3FA79F00 cyc=43806034 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43806056 +1 W reg=E val=0000 pc=3FA7A060 cyc=43806078 +1 W reg=F val=0000 pc=3FA7A110 cyc=43806100 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43806122 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43806156 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43817832 +1 R reg=1 val=000C pc=3FA79E50 cyc=43817913 +1 W reg=3 val=00FF pc=3FA79F00 cyc=43817935 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43817957 +1 W reg=E val=0000 pc=3FA7A060 cyc=43817979 +1 W reg=F val=0000 pc=3FA7A110 cyc=43818001 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43818023 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43818057 +1 R reg=5 val=000A pc=3FA78E30 cyc=43829551 +1 R reg=1 val=0001 pc=3FA796D0 cyc=43829633 +1 R reg=3 val=006F pc=3FA79780 cyc=43829655 +1 R reg=1 val=0000 pc=3FA79830 cyc=43829677 +1 R reg=D val=00F0 pc=3FA798E0 cyc=43829699 +1 R reg=D val=00F0 pc=3FA79A20 cyc=43829733 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43831034 +1 R reg=1 val=000C pc=3FA79E50 cyc=43831115 +1 W reg=3 val=00AA pc=3FA79F00 cyc=43831137 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43831159 +1 W reg=E val=0000 pc=3FA7A060 cyc=43831181 +1 W reg=F val=0000 pc=3FA7A110 cyc=43831203 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43831225 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43831259 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43844237 +1 R reg=1 val=000C pc=3FA79E50 cyc=43844318 +1 W reg=3 val=0055 pc=3FA79F00 cyc=43844340 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43844362 +1 W reg=E val=0000 pc=3FA7A060 cyc=43844384 +1 W reg=F val=0000 pc=3FA7A110 cyc=43844406 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43844428 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43844462 +1 R reg=5 val=000A pc=3FA78E30 cyc=43855956 +1 R reg=1 val=0041 pc=3FA796D0 cyc=43856038 +1 R reg=3 val=000F pc=3FA79780 cyc=43856060 +1 R reg=1 val=0000 pc=3FA79830 cyc=43856082 +1 R reg=D val=00F0 pc=3FA798E0 cyc=43856104 +1 R reg=D val=00F0 pc=3FA79A20 cyc=43856138 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43857439 +1 R reg=1 val=000C pc=3FA79E50 cyc=43857520 +1 W reg=3 val=0000 pc=3FA79F00 cyc=43857542 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43857564 +1 W reg=E val=0000 pc=3FA7A060 cyc=43857586 +1 W reg=F val=0000 pc=3FA7A110 cyc=43857608 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43857630 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43857664 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43870641 +1 R reg=1 val=000C pc=3FA7A3C0 cyc=43870711 +1 W reg=2 val=0008 pc=3FA7A3F0 cyc=43870717 +1 R reg=1 val=0000 pc=3FA7A440 cyc=43870725 +1 R reg=5 val=000A pc=3FA78E30 cyc=43882361 +1 R reg=1 val=0001 pc=3FA796D0 cyc=43882443 +1 R reg=3 val=0078 pc=3FA79780 cyc=43882465 +1 R reg=1 val=0000 pc=3FA79830 cyc=43882487 +1 R reg=D val=00F0 pc=3FA798E0 cyc=43882509 +1 R reg=D val=00F0 pc=3FA79A20 cyc=43882543 +1 W reg=2 val=000A pc=3FA73420 cyc=44113386 +1 W reg=2 val=002A pc=3FA74BE0 cyc=44114724 +1 W reg=2 val=002B pc=3FA74C80 cyc=44115046 +1 W reg=2 val=004A pc=3FA74D10 cyc=44115367 +1 W reg=2 val=0065 pc=3FA74DA0 cyc=44115688 +1 R reg=5 val=000F pc=3FA78E30 cyc=44115770 +1 R reg=1 val=008D pc=3FA78FD0 cyc=44115811 +1 W reg=2 val=0055 pc=3FA79010 cyc=44115818 +1 W reg=2 val=0075 pc=3FA790C0 cyc=44116141 +1 R reg=1 val=008D pc=3FA796D0 cyc=44116222 +1 R reg=3 val=0000 pc=3FA79780 cyc=44116244 +1 R reg=1 val=000C pc=3FA79830 cyc=44116266 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44116288 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44116322 +1 R reg=5 val=000D pc=3FA78E30 cyc=44116549 +1 W reg=2 val=005A pc=3FA79110 cyc=44116588 +1 W reg=2 val=007A pc=3FA74E60 cyc=44176869 +1 W reg=2 val=0050 pc=3FA74F10 cyc=44177192 +1 W reg=5 val=0000 pc=3FA78D10 cyc=44177360 +1 W reg=5 val=0001 pc=3FA78B40 cyc=44177492 +1 W reg=2 val=003A pc=3FA75570 cyc=44177617 +1 W reg=2 val=002A pc=3FA75620 cyc=44177940 +1 W reg=2 val=004A pc=3FA756D0 cyc=44178263 +1 W reg=2 val=001A pc=3FA75770 cyc=44178585 +1 W reg=1 val=0088 pc=3FA75870 cyc=44178915 +1 W reg=0 val=0010 pc=3FA75BC0 cyc=44182007 +1 W reg=0 val=0080 pc=3FA75CE0 cyc=44182344 +1 W reg=2 val=0005 pc=3FA75D90 cyc=44242465 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44242547 +1 R reg=1 val=000C pc=3FA79E50 cyc=44242628 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44242650 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44242672 +1 W reg=E val=0000 pc=3FA7A060 cyc=44242694 +1 W reg=F val=0000 pc=3FA7A110 cyc=44242716 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44242738 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44242772 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44253146 +1 R reg=1 val=000C pc=3FA79E50 cyc=44253227 +1 W reg=3 val=00FF pc=3FA79F00 cyc=44253249 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44253271 +1 W reg=E val=0000 pc=3FA7A060 cyc=44253293 +1 W reg=F val=0000 pc=3FA7A110 cyc=44253315 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44253337 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44253371 +1 R reg=5 val=000B pc=3FA78E30 cyc=44263744 +1 R reg=1 val=000D pc=3FA79E50 cyc=44263825 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44263847 +1 R reg=1 val=0001 pc=3FA79FB0 cyc=44263869 +1 W reg=E val=0000 pc=3FA7A060 cyc=44263891 +1 W reg=F val=0000 pc=3FA7A110 cyc=44263913 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44263935 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44263969 +1 R reg=5 val=000B pc=3FA78E30 cyc=44274342 +1 R reg=1 val=000D pc=3FA79E50 cyc=44274423 +1 W reg=3 val=0055 pc=3FA79F00 cyc=44274445 +1 R reg=1 val=0001 pc=3FA79FB0 cyc=44274467 +1 W reg=E val=0000 pc=3FA7A060 cyc=44274489 +1 W reg=F val=0000 pc=3FA7A110 cyc=44274511 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44274533 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44274567 +1 R reg=5 val=000B pc=3FA78E30 cyc=44284940 +1 R reg=1 val=000D pc=3FA79E50 cyc=44285021 +1 W reg=3 val=0000 pc=3FA79F00 cyc=44285043 +1 R reg=1 val=0001 pc=3FA79FB0 cyc=44285065 +1 W reg=E val=0000 pc=3FA7A060 cyc=44285087 +1 W reg=F val=0000 pc=3FA7A110 cyc=44285109 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44285131 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44285165 +1 R reg=5 val=000B pc=3FA78E30 cyc=44295538 +1 R reg=1 val=000D pc=3FA7A3C0 cyc=44295608 +1 W reg=2 val=0008 pc=3FA7A3F0 cyc=44295614 +1 R reg=1 val=0001 pc=3FA7A440 cyc=44295622 +1 W reg=2 val=000A pc=3FA76010 cyc=44365049 +1 R reg=1 val=0002 pc=3FA761B0 cyc=44365090 +1 R reg=3 val=0017 pc=3FA76360 cyc=44365134 +1 R reg=1 val=0040 pc=3FA761B0 cyc=44365163 +1 R reg=3 val=0007 pc=3FA76360 cyc=44365207 +1 R reg=1 val=0000 pc=3FA761B0 cyc=44365236 +1 R reg=3 val=001C pc=3FA76360 cyc=44365280 +1 W reg=5 val=0000 pc=3FA78D10 cyc=44365453 +1 W reg=5 val=0007 pc=3FA78B40 cyc=44365578 +1 W reg=5 val=0000 pc=3FA78D10 cyc=44365806 +1 W reg=2 val=00FA pc=3FA778D0 cyc=44365911 +1 W reg=2 val=00CA pc=3FA77990 cyc=44366237 +1 W reg=2 val=002A pc=3FA77A30 cyc=44366558 +1 W reg=2 val=003A pc=3FA77AD0 cyc=44366879 +1 W reg=2 val=004A pc=3FA77B70 cyc=44367200 +1 W reg=2 val=005A pc=3FA77C10 cyc=44367521 +1 W reg=2 val=001A pc=3FA77CA0 cyc=44367841 +1 W reg=A val=00CA pc=3FA77990 cyc=44368232 +1 W reg=A val=002A pc=3FA77A30 cyc=44368553 +1 W reg=A val=003A pc=3FA77AD0 cyc=44368874 +1 W reg=A val=004A pc=3FA77B70 cyc=44369195 +1 W reg=A val=005A pc=3FA77C10 cyc=44369516 +1 W reg=A val=001A pc=3FA77CA0 cyc=44369836 +1 W reg=F val=0080 pc=3FA850F0 cyc=44370071 +1 R reg=D val=00F0 pc=3F2045A0 cyc=44370539 +1 W reg=D val=0000 pc=3F208830 cyc=44645458 +1 W reg=F val=00FF pc=3F208880 cyc=44645463 diff --git a/harness/mame/hp_dump.lua b/harness/mame/hp_dump.lua new file mode 100644 index 0000000..300ba43 --- /dev/null +++ b/harness/mame/hp_dump.lua @@ -0,0 +1,32 @@ +local machine = manager.machine +local cpu = machine.devices[':maincpu'] +local dbg = machine.debugger +local prog = cpu.spaces['program'] +if not dbg then machine:exit(); return end +local function w(a) return prog:read_u16(a) end +local function l(a) return prog:read_u32(a) end +local function dump(label, base, n) + local t = {} + for i=0,n-1 do t[#t+1] = string.format("%04X", w(base + i*16)) end + print(label .. " @ " .. string.format("%08X", base) .. ": " .. table.concat(t, " ")) +end +print(string.format("VEC INT1=%08X INT2=%08X HI=%08X DI=%08X RESET=%08X", + l(0xffffffc0), l(0xffffffa0), l(0xfffffec0), l(0xfffffea0), l(0xffffffe0))) +local n=0 +emu.register_frame_done(function() + n=n+1 + if n==476 or n==482 then + print("---- frame "..n) + dump("RAM0f60", 0x0f60, 12) + dump("RAM0d80", 0x0d80, 12) + dump("TBL1d0", 0x2701d0, 8) + dump("TBL270", 0x270270, 8) + dump("TBL2f0", 0x2702f0, 8) + dump("TBL350", 0x270350, 8) + dump("TBL3b0", 0x2703b0, 8) + dump("TBL3f0", 0x2703f0, 8) + dump("STRUCT+0x0", 0x270890, 0x40) + end + if n>=485 then machine:exit() end +end, "vt1200-hp-dump") +dbg.execution_state='run' diff --git a/harness/mame/hp_dump2.lua b/harness/mame/hp_dump2.lua new file mode 100644 index 0000000..578092e --- /dev/null +++ b/harness/mame/hp_dump2.lua @@ -0,0 +1,19 @@ +local machine = manager.machine +local cpu = machine.devices[':maincpu'] +local dbg = machine.debugger +local prog = cpu.spaces['program'] +local function w(a) return prog:read_u16(a) end +local function dump(label, base, n) + local t = {} + for i=0,n-1 do t[#t+1] = string.format("%04X", w(base + i*16)) end + print(label .. " @ " .. string.format("%08X", base) .. ": " .. table.concat(t, " ")) +end +local n=0 +emu.register_frame_done(function() + n=n+1 + if n==476 then + dump("stubs", 0x0d80, 40) + end + if n>=480 then machine:exit() end +end, "vt1200-hp-dump2") +dbg.execution_state='run' diff --git a/harness/mame/hp_final.log b/harness/mame/hp_final.log new file mode 100644 index 0000000..24e7a82 --- /dev/null +++ b/harness/mame/hp_final.log @@ -0,0 +1,443 @@ +# win kind reg val pc -- every DUART access (not de-duplicated) +1 W reg=D val=0000 pc=3F2000B0 cyc=7 +1 R reg=F val=00FF pc=3F200100 cyc=12 +1 W reg=F val=00FF pc=3F200100 cyc=12 +1 R reg=E val=00FF pc=3F200150 cyc=15 +1 W reg=E val=000F pc=3F200150 cyc=15 +1 R reg=F val=00FF pc=3F200250 cyc=29 +1 W reg=F val=0001 pc=3F200250 cyc=29 +1 R reg=D val=00F0 pc=3F200380 cyc=46 +1 R reg=D val=00F0 pc=3F200A20 cyc=2123 +1 R reg=D val=00F0 pc=3F202650 cyc=2715 +1 R reg=D val=00F0 pc=3F2045A0 cyc=465049 +1 R reg=E val=00FF pc=3F2042D0 cyc=576004 +1 W reg=E val=0001 pc=3F2042D0 cyc=576004 +1 R reg=D val=00F0 pc=3F204300 cyc=576005 +1 W reg=D val=0000 pc=3FDF1150 cyc=576167 +1 W reg=F val=0001 pc=3FDF1190 cyc=576171 +1 R reg=D val=00F0 pc=3FDF7DE0 cyc=1297177 +1 R reg=D val=00F0 pc=3F2045A0 cyc=1897379 +1 W reg=2 val=00CA pc=3FA90A00 cyc=3737622 +1 W reg=2 val=002A pc=3FA90AB0 cyc=3737945 +1 W reg=2 val=003A pc=3FA90B60 cyc=3738268 +1 W reg=2 val=004A pc=3FA90C10 cyc=3738591 +1 W reg=2 val=005A pc=3FA90CC0 cyc=3738914 +1 W reg=2 val=001A pc=3FA90D60 cyc=3739236 +1 W reg=A val=00CA pc=3FA90E10 cyc=3739559 +1 W reg=A val=002A pc=3FA90EC0 cyc=3739882 +1 W reg=A val=003A pc=3FA90F70 cyc=3740205 +1 W reg=A val=004A pc=3FA91020 cyc=3740528 +1 W reg=A val=005A pc=3FA910D0 cyc=3740851 +1 W reg=A val=001A pc=3FA91170 cyc=3741173 +1 W reg=F val=0080 pc=3FA7C330 cyc=3744820 +1 R reg=D val=00F0 pc=3F2045A0 cyc=10040220 +1 R reg=D val=00F0 pc=3F2045A0 cyc=15792800 +1 R reg=D val=00F0 pc=3F2045A0 cyc=15926711 +1 R reg=D val=00F0 pc=3F2045A0 cyc=34826663 +1 W reg=2 val=00FA pc=3FA778D0 cyc=43724635 +1 W reg=2 val=00CA pc=3FA77990 cyc=43724961 +1 W reg=2 val=002A pc=3FA77A30 cyc=43725282 +1 W reg=2 val=003A pc=3FA77AD0 cyc=43725603 +1 W reg=2 val=004A pc=3FA77B70 cyc=43725924 +1 W reg=2 val=005A pc=3FA77C10 cyc=43726245 +1 W reg=2 val=001A pc=3FA77CA0 cyc=43726565 +1 W reg=A val=00CA pc=3FA77990 cyc=43726956 +1 W reg=A val=002A pc=3FA77A30 cyc=43727277 +1 W reg=A val=003A pc=3FA77AD0 cyc=43727598 +1 W reg=A val=004A pc=3FA77B70 cyc=43727919 +1 W reg=A val=005A pc=3FA77C10 cyc=43728240 +1 W reg=A val=001A pc=3FA77CA0 cyc=43728560 +1 W reg=2 val=00FA pc=3FA778D0 cyc=43735282 +1 W reg=2 val=00CA pc=3FA77990 cyc=43735608 +1 W reg=2 val=002A pc=3FA77A30 cyc=43735929 +1 W reg=2 val=003A pc=3FA77AD0 cyc=43736250 +1 W reg=2 val=004A pc=3FA77B70 cyc=43736571 +1 W reg=2 val=005A pc=3FA77C10 cyc=43736892 +1 W reg=2 val=001A pc=3FA77CA0 cyc=43737212 +1 W reg=A val=00CA pc=3FA77990 cyc=43737603 +1 W reg=A val=002A pc=3FA77A30 cyc=43737924 +1 W reg=A val=003A pc=3FA77AD0 cyc=43738245 +1 W reg=A val=004A pc=3FA77B70 cyc=43738566 +1 W reg=A val=005A pc=3FA77C10 cyc=43738887 +1 W reg=A val=001A pc=3FA77CA0 cyc=43739207 +1 W reg=5 val=0007 pc=3FA78B40 cyc=43739320 +1 W reg=D val=0000 pc=3FA704E0 cyc=43739379 +1 W reg=4 val=0060 pc=3FA71CB0 cyc=43739476 +1 W reg=2 val=003A pc=3FA71F20 cyc=43739539 +1 W reg=2 val=002A pc=3FA71FD0 cyc=43739862 +1 W reg=2 val=004A pc=3FA72080 cyc=43740185 +1 W reg=2 val=001A pc=3FA72120 cyc=43740507 +1 W reg=1 val=0088 pc=3FA72220 cyc=43740837 +1 W reg=0 val=0012 pc=3FA73090 cyc=43745391 +1 W reg=0 val=0080 pc=3FA731B0 cyc=43745728 +1 W reg=2 val=0005 pc=3FA73260 cyc=43805849 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43805931 +1 R reg=1 val=000C pc=3FA79E50 cyc=43806012 +1 W reg=3 val=00AA pc=3FA79F00 cyc=43806034 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43806056 +1 W reg=E val=0000 pc=3FA7A060 cyc=43806078 +1 W reg=F val=0000 pc=3FA7A110 cyc=43806100 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43806122 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43806156 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43828249 +1 R reg=1 val=000C pc=3FA79E50 cyc=43828330 +1 W reg=3 val=00FF pc=3FA79F00 cyc=43828352 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43828374 +1 W reg=E val=0000 pc=3FA7A060 cyc=43828396 +1 W reg=F val=0000 pc=3FA7A110 cyc=43828418 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43828440 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43828474 +1 R reg=5 val=000A pc=3FA78E30 cyc=43829551 +1 R reg=1 val=0001 pc=3FA796D0 cyc=43829633 +1 R reg=3 val=002A pc=3FA79780 cyc=43829655 +1 R reg=1 val=0000 pc=3FA79830 cyc=43829677 +1 R reg=D val=00F0 pc=3FA798E0 cyc=43829699 +1 R reg=D val=00F0 pc=3FA79A20 cyc=43829733 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43851868 +1 R reg=1 val=000C pc=3FA79E50 cyc=43851949 +1 W reg=3 val=00AA pc=3FA79F00 cyc=43851971 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43851993 +1 W reg=E val=0000 pc=3FA7A060 cyc=43852015 +1 W reg=F val=0000 pc=3FA7A110 cyc=43852037 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43852059 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43852093 +1 R reg=5 val=000A pc=3FA78E30 cyc=43853170 +1 R reg=1 val=0001 pc=3FA796D0 cyc=43853252 +1 R reg=3 val=007F pc=3FA79780 cyc=43853274 +1 R reg=1 val=0000 pc=3FA79830 cyc=43853296 +1 R reg=D val=00F0 pc=3FA798E0 cyc=43853318 +1 R reg=D val=00F0 pc=3FA79A20 cyc=43853352 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43875487 +1 R reg=1 val=000C pc=3FA79E50 cyc=43875568 +1 W reg=3 val=0055 pc=3FA79F00 cyc=43875590 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43875612 +1 W reg=E val=0000 pc=3FA7A060 cyc=43875634 +1 W reg=F val=0000 pc=3FA7A110 cyc=43875656 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43875678 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43875712 +1 R reg=5 val=000A pc=3FA78E30 cyc=43876789 +1 R reg=1 val=0001 pc=3FA796D0 cyc=43876871 +1 R reg=3 val=002A pc=3FA79780 cyc=43876893 +1 R reg=1 val=0000 pc=3FA79830 cyc=43876915 +1 R reg=D val=00F0 pc=3FA798E0 cyc=43876937 +1 R reg=D val=00F0 pc=3FA79A20 cyc=43876971 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43899106 +1 R reg=1 val=000C pc=3FA79E50 cyc=43899187 +1 W reg=3 val=0000 pc=3FA79F00 cyc=43899209 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=43899231 +1 W reg=E val=0000 pc=3FA7A060 cyc=43899253 +1 W reg=F val=0000 pc=3FA7A110 cyc=43899275 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43899297 +1 R reg=D val=00F0 pc=3FA7A320 cyc=43899331 +1 R reg=5 val=000A pc=3FA78E30 cyc=43900409 +1 R reg=1 val=0001 pc=3FA796D0 cyc=43900491 +1 R reg=3 val=0055 pc=3FA79780 cyc=43900513 +1 R reg=1 val=0000 pc=3FA79830 cyc=43900535 +1 R reg=D val=00F0 pc=3FA798E0 cyc=43900557 +1 R reg=D val=00F0 pc=3FA79A20 cyc=43900591 +1 R reg=5 val=0009 pc=3FA78E30 cyc=43922726 +1 R reg=1 val=000C pc=3FA7A3C0 cyc=43922796 +1 W reg=2 val=0008 pc=3FA7A3F0 cyc=43922802 +1 R reg=1 val=0000 pc=3FA7A440 cyc=43922810 +1 R reg=5 val=000A pc=3FA78E30 cyc=43924027 +1 R reg=1 val=0001 pc=3FA796D0 cyc=43924109 +1 R reg=3 val=0000 pc=3FA79780 cyc=43924131 +1 R reg=1 val=0000 pc=3FA79830 cyc=43924153 +1 R reg=D val=00F0 pc=3FA798E0 cyc=43924175 +1 R reg=D val=00F0 pc=3FA79A20 cyc=43924209 +1 W reg=2 val=000A pc=3FA73420 cyc=43931657 +1 W reg=2 val=002A pc=3FA74BE0 cyc=43933007 +1 W reg=2 val=002B pc=3FA74C80 cyc=43933329 +1 W reg=2 val=004A pc=3FA74D10 cyc=43933650 +1 W reg=2 val=0065 pc=3FA74DA0 cyc=43933971 +1 R reg=5 val=000F pc=3FA78E30 cyc=43934053 +1 R reg=1 val=008D pc=3FA78FD0 cyc=43934094 +1 W reg=2 val=0055 pc=3FA79010 cyc=43934101 +1 W reg=2 val=0075 pc=3FA790C0 cyc=43934424 +1 R reg=1 val=008D pc=3FA79AE0 cyc=43934494 +1 R reg=3 val=0000 pc=3FA79B00 cyc=43934499 +1 W reg=2 val=0002 pc=3FA79B60 cyc=43934508 +1 R reg=1 val=000C pc=3FA79BB0 cyc=43934516 +1 R reg=5 val=000D pc=3FA78E30 cyc=43934741 +1 W reg=2 val=005A pc=3FA79110 cyc=43934780 +1 W reg=2 val=007A pc=3FA74E60 cyc=43995061 +1 W reg=2 val=0050 pc=3FA74F10 cyc=43995384 +1 W reg=2 val=003A pc=3FA71F20 cyc=43995432 +1 W reg=2 val=002A pc=3FA71FD0 cyc=43995755 +1 W reg=2 val=004A pc=3FA72080 cyc=43996078 +1 W reg=2 val=001A pc=3FA72120 cyc=43996400 +1 W reg=1 val=0088 pc=3FA72220 cyc=43996730 +1 W reg=0 val=0013 pc=3FA73090 cyc=44001284 +1 W reg=0 val=0080 pc=3FA731B0 cyc=44001621 +1 W reg=2 val=0005 pc=3FA73260 cyc=44061742 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44061824 +1 R reg=1 val=000C pc=3FA79E50 cyc=44061905 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44061927 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44061949 +1 W reg=E val=0000 pc=3FA7A060 cyc=44061971 +1 W reg=F val=0000 pc=3FA7A110 cyc=44061993 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44062015 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44062049 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44088048 +1 R reg=1 val=000C pc=3FA79E50 cyc=44088129 +1 W reg=3 val=00FF pc=3FA79F00 cyc=44088151 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44088173 +1 W reg=E val=0000 pc=3FA7A060 cyc=44088195 +1 W reg=F val=0000 pc=3FA7A110 cyc=44088217 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44088239 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44088273 +1 R reg=5 val=000A pc=3FA78E30 cyc=44089350 +1 R reg=1 val=0001 pc=3FA796D0 cyc=44089432 +1 R reg=3 val=00AA pc=3FA79780 cyc=44089454 +1 R reg=1 val=0000 pc=3FA79830 cyc=44089476 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44089498 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44089532 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44114272 +1 R reg=1 val=000C pc=3FA79E50 cyc=44114353 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44114375 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44114397 +1 W reg=E val=0000 pc=3FA7A060 cyc=44114419 +1 W reg=F val=0000 pc=3FA7A110 cyc=44114441 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44114463 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44114497 +1 R reg=5 val=000A pc=3FA78E30 cyc=44115574 +1 R reg=1 val=0001 pc=3FA796D0 cyc=44115656 +1 R reg=3 val=00FF pc=3FA79780 cyc=44115678 +1 R reg=1 val=0000 pc=3FA79830 cyc=44115700 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44115722 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44115756 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44140495 +1 R reg=1 val=000C pc=3FA79E50 cyc=44140576 +1 W reg=3 val=0055 pc=3FA79F00 cyc=44140598 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44140620 +1 W reg=E val=0000 pc=3FA7A060 cyc=44140642 +1 W reg=F val=0000 pc=3FA7A110 cyc=44140664 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44140686 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44140720 +1 R reg=5 val=000A pc=3FA78E30 cyc=44141797 +1 R reg=1 val=0001 pc=3FA796D0 cyc=44141879 +1 R reg=3 val=00AA pc=3FA79780 cyc=44141901 +1 R reg=1 val=0000 pc=3FA79830 cyc=44141923 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44141945 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44141979 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44166719 +1 R reg=1 val=000C pc=3FA79E50 cyc=44166800 +1 W reg=3 val=0000 pc=3FA79F00 cyc=44166822 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44166844 +1 W reg=E val=0000 pc=3FA7A060 cyc=44166866 +1 W reg=F val=0000 pc=3FA7A110 cyc=44166888 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44166910 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44166944 +1 R reg=5 val=000A pc=3FA78E30 cyc=44168021 +1 R reg=1 val=0001 pc=3FA796D0 cyc=44168103 +1 R reg=3 val=0055 pc=3FA79780 cyc=44168125 +1 R reg=1 val=0000 pc=3FA79830 cyc=44168147 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44168169 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44168203 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44192942 +1 R reg=1 val=000C pc=3FA7A3C0 cyc=44193012 +1 W reg=2 val=0008 pc=3FA7A3F0 cyc=44193018 +1 R reg=1 val=0000 pc=3FA7A440 cyc=44193026 +1 R reg=5 val=000A pc=3FA78E30 cyc=44194245 +1 R reg=1 val=0001 pc=3FA796D0 cyc=44194327 +1 R reg=3 val=0000 pc=3FA79780 cyc=44194349 +1 R reg=1 val=0000 pc=3FA79830 cyc=44194371 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44194393 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44194427 +1 W reg=2 val=000A pc=3FA73420 cyc=44197687 +1 W reg=2 val=002A pc=3FA74BE0 cyc=44199037 +1 W reg=2 val=002B pc=3FA74C80 cyc=44199359 +1 W reg=2 val=004A pc=3FA74D10 cyc=44199680 +1 W reg=2 val=0065 pc=3FA74DA0 cyc=44200001 +1 R reg=5 val=000F pc=3FA78E30 cyc=44200083 +1 R reg=1 val=008D pc=3FA78FD0 cyc=44200124 +1 W reg=2 val=0055 pc=3FA79010 cyc=44200131 +1 W reg=2 val=0075 pc=3FA790C0 cyc=44200454 +1 R reg=1 val=008D pc=3FA79AE0 cyc=44200524 +1 R reg=3 val=0000 pc=3FA79B00 cyc=44200529 +1 W reg=2 val=0002 pc=3FA79B60 cyc=44200538 +1 R reg=1 val=000C pc=3FA79BB0 cyc=44200546 +1 R reg=5 val=000D pc=3FA78E30 cyc=44200771 +1 W reg=2 val=005A pc=3FA79110 cyc=44200810 +1 W reg=2 val=007A pc=3FA74E60 cyc=44261091 +1 W reg=2 val=0050 pc=3FA74F10 cyc=44261414 +1 W reg=2 val=003A pc=3FA71F20 cyc=44261487 +1 W reg=2 val=002A pc=3FA71FD0 cyc=44261810 +1 W reg=2 val=004A pc=3FA72080 cyc=44262133 +1 W reg=2 val=001A pc=3FA72120 cyc=44262455 +1 W reg=1 val=0088 pc=3FA72220 cyc=44262785 +1 W reg=0 val=0002 pc=3FA73090 cyc=44267339 +1 W reg=0 val=0080 pc=3FA731B0 cyc=44267676 +1 W reg=2 val=0005 pc=3FA73260 cyc=44327797 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44327879 +1 R reg=1 val=000C pc=3FA79E50 cyc=44327960 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44327982 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44328004 +1 W reg=E val=0000 pc=3FA7A060 cyc=44328026 +1 W reg=F val=0000 pc=3FA7A110 cyc=44328048 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44328070 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44328104 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44354103 +1 R reg=1 val=000C pc=3FA79E50 cyc=44354184 +1 W reg=3 val=00FF pc=3FA79F00 cyc=44354206 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44354228 +1 W reg=E val=0000 pc=3FA7A060 cyc=44354250 +1 W reg=F val=0000 pc=3FA7A110 cyc=44354272 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44354294 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44354328 +1 R reg=5 val=000A pc=3FA78E30 cyc=44355405 +1 R reg=1 val=0021 pc=3FA796D0 cyc=44355487 +1 R reg=3 val=002A pc=3FA79780 cyc=44355509 +1 R reg=1 val=0000 pc=3FA79830 cyc=44355531 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44355553 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44355587 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44380327 +1 R reg=1 val=000C pc=3FA79E50 cyc=44380408 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44380430 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44380452 +1 W reg=E val=0000 pc=3FA7A060 cyc=44380474 +1 W reg=F val=0000 pc=3FA7A110 cyc=44380496 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44380518 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44380552 +1 R reg=5 val=000A pc=3FA78E30 cyc=44381629 +1 R reg=1 val=0021 pc=3FA796D0 cyc=44381711 +1 R reg=3 val=007F pc=3FA79780 cyc=44381733 +1 R reg=1 val=0000 pc=3FA79830 cyc=44381755 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44381777 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44381811 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44406550 +1 R reg=1 val=000C pc=3FA79E50 cyc=44406631 +1 W reg=3 val=0055 pc=3FA79F00 cyc=44406653 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44406675 +1 W reg=E val=0000 pc=3FA7A060 cyc=44406697 +1 W reg=F val=0000 pc=3FA7A110 cyc=44406719 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44406741 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44406775 +1 R reg=5 val=000A pc=3FA78E30 cyc=44407852 +1 R reg=1 val=0021 pc=3FA796D0 cyc=44407934 +1 R reg=3 val=002A pc=3FA79780 cyc=44407956 +1 R reg=1 val=0000 pc=3FA79830 cyc=44407978 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44408000 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44408034 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44432774 +1 R reg=1 val=000C pc=3FA79E50 cyc=44432855 +1 W reg=3 val=0000 pc=3FA79F00 cyc=44432877 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44432899 +1 W reg=E val=0000 pc=3FA7A060 cyc=44432921 +1 W reg=F val=0000 pc=3FA7A110 cyc=44432943 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44432965 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44432999 +1 R reg=5 val=000A pc=3FA78E30 cyc=44434076 +1 R reg=1 val=0001 pc=3FA796D0 cyc=44434158 +1 R reg=3 val=0055 pc=3FA79780 cyc=44434180 +1 R reg=1 val=0000 pc=3FA79830 cyc=44434202 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44434224 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44434258 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44458997 +1 R reg=1 val=000C pc=3FA7A3C0 cyc=44459067 +1 W reg=2 val=0008 pc=3FA7A3F0 cyc=44459073 +1 R reg=1 val=0000 pc=3FA7A440 cyc=44459081 +1 R reg=5 val=000A pc=3FA78E30 cyc=44460300 +1 R reg=1 val=0001 pc=3FA796D0 cyc=44460382 +1 R reg=3 val=0000 pc=3FA79780 cyc=44460404 +1 R reg=1 val=0000 pc=3FA79830 cyc=44460426 +1 R reg=D val=00F0 pc=3FA798E0 cyc=44460448 +1 R reg=D val=00F0 pc=3FA79A20 cyc=44460482 +1 W reg=2 val=000A pc=3FA73420 cyc=44463742 +1 W reg=2 val=002A pc=3FA74BE0 cyc=44465104 +1 W reg=2 val=002B pc=3FA74C80 cyc=44465426 +1 W reg=2 val=004A pc=3FA74D10 cyc=44465747 +1 W reg=2 val=0065 pc=3FA74DA0 cyc=44466068 +1 R reg=5 val=000F pc=3FA78E30 cyc=44466150 +1 R reg=1 val=008D pc=3FA78FD0 cyc=44466191 +1 W reg=2 val=0055 pc=3FA79010 cyc=44466198 +1 W reg=2 val=0075 pc=3FA790C0 cyc=44466521 +1 R reg=1 val=008D pc=3FA79AE0 cyc=44466591 +1 R reg=3 val=0000 pc=3FA79B00 cyc=44466596 +1 W reg=2 val=0002 pc=3FA79B60 cyc=44466605 +1 R reg=1 val=000C pc=3FA79BB0 cyc=44466613 +1 R reg=5 val=000D pc=3FA78E30 cyc=44466838 +1 W reg=2 val=005A pc=3FA79110 cyc=44466877 +1 W reg=2 val=007A pc=3FA74E60 cyc=44527158 +1 W reg=2 val=0050 pc=3FA74F10 cyc=44527481 +1 W reg=5 val=0000 pc=3FA78D10 cyc=44527649 +1 W reg=5 val=0001 pc=3FA78B40 cyc=44527781 +1 W reg=2 val=003A pc=3FA75570 cyc=44527906 +1 W reg=2 val=002A pc=3FA75620 cyc=44528229 +1 W reg=2 val=004A pc=3FA756D0 cyc=44528552 +1 W reg=2 val=001A pc=3FA75770 cyc=44528874 +1 W reg=1 val=0088 pc=3FA75870 cyc=44529204 +1 W reg=0 val=0010 pc=3FA75BC0 cyc=44532296 +1 W reg=0 val=0080 pc=3FA75CE0 cyc=44532633 +1 W reg=2 val=0005 pc=3FA75D90 cyc=44592754 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44592836 +1 R reg=1 val=000C pc=3FA79E50 cyc=44592917 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44592939 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44592961 +1 W reg=E val=0000 pc=3FA7A060 cyc=44592983 +1 W reg=F val=0000 pc=3FA7A110 cyc=44593005 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44593027 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44593061 +1 R reg=5 val=0009 pc=3FA78E30 cyc=44611247 +1 R reg=1 val=000C pc=3FA79E50 cyc=44611328 +1 W reg=3 val=00FF pc=3FA79F00 cyc=44611350 +1 R reg=1 val=0000 pc=3FA79FB0 cyc=44611372 +1 W reg=E val=0000 pc=3FA7A060 cyc=44611394 +1 W reg=F val=0000 pc=3FA7A110 cyc=44611416 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44611438 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44611472 +1 R reg=5 val=000B pc=3FA78E30 cyc=44629659 +1 R reg=1 val=000D pc=3FA79E50 cyc=44629740 +1 W reg=3 val=00AA pc=3FA79F00 cyc=44629762 +1 R reg=1 val=0001 pc=3FA79FB0 cyc=44629784 +1 W reg=E val=0000 pc=3FA7A060 cyc=44629806 +1 W reg=F val=0000 pc=3FA7A110 cyc=44629828 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44629850 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44629884 +1 R reg=5 val=000B pc=3FA78E30 cyc=44648071 +1 R reg=1 val=000D pc=3FA79E50 cyc=44648152 +1 W reg=3 val=0055 pc=3FA79F00 cyc=44648174 +1 R reg=1 val=0001 pc=3FA79FB0 cyc=44648196 +1 W reg=E val=0000 pc=3FA7A060 cyc=44648218 +1 W reg=F val=0000 pc=3FA7A110 cyc=44648240 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44648262 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44648296 +1 R reg=5 val=000B pc=3FA78E30 cyc=44666482 +1 R reg=1 val=000F pc=3FA79E50 cyc=44666563 +1 W reg=3 val=0000 pc=3FA79F00 cyc=44666585 +1 R reg=1 val=0003 pc=3FA79FB0 cyc=44666607 +1 W reg=E val=0000 pc=3FA7A060 cyc=44666629 +1 W reg=F val=0000 pc=3FA7A110 cyc=44666651 +1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44666673 +1 R reg=D val=00F0 pc=3FA7A320 cyc=44666707 +1 R reg=5 val=000B pc=3FA78E30 cyc=44684894 +1 R reg=1 val=000F pc=3FA7A3C0 cyc=44684964 +1 W reg=2 val=0008 pc=3FA7A3F0 cyc=44684970 +1 R reg=1 val=0003 pc=3FA7A440 cyc=44684978 +1 W reg=2 val=000A pc=3FA76010 cyc=44775477 +1 R reg=1 val=0012 pc=3FA761B0 cyc=44775514 +1 R reg=3 val=000A pc=3FA76360 cyc=44775554 +1 R reg=1 val=0012 pc=3FA761B0 cyc=44775579 +1 R reg=3 val=001F pc=3FA76360 cyc=44775619 +1 R reg=1 val=0010 pc=3FA761B0 cyc=44775644 +1 R reg=3 val=000A pc=3FA76360 cyc=44775684 +1 W reg=5 val=0000 pc=3FA78D10 cyc=44775853 +1 W reg=5 val=0007 pc=3FA78B40 cyc=44775978 +1 W reg=5 val=0000 pc=3FA78D10 cyc=44776206 +1 W reg=2 val=00FA pc=3FA778D0 cyc=44776311 +1 W reg=2 val=00CA pc=3FA77990 cyc=44776637 +1 W reg=2 val=002A pc=3FA77A30 cyc=44776958 +1 W reg=2 val=003A pc=3FA77AD0 cyc=44777279 +1 W reg=2 val=004A pc=3FA77B70 cyc=44777600 +1 W reg=2 val=005A pc=3FA77C10 cyc=44777921 +1 W reg=2 val=001A pc=3FA77CA0 cyc=44778241 +1 W reg=A val=00CA pc=3FA77990 cyc=44778632 +1 W reg=A val=002A pc=3FA77A30 cyc=44778953 +1 W reg=A val=003A pc=3FA77AD0 cyc=44779274 +1 W reg=A val=004A pc=3FA77B70 cyc=44779595 +1 W reg=A val=005A pc=3FA77C10 cyc=44779916 +1 W reg=A val=001A pc=3FA77CA0 cyc=44780236 +1 W reg=F val=0080 pc=3FA850F0 cyc=44780471 +1 R reg=D val=00F0 pc=3F2045A0 cyc=44780939 +1 W reg=D val=0000 pc=3F208830 cyc=45055851 +1 W reg=F val=00FF pc=3F208880 cyc=45055856 diff --git a/harness/mame/hp_int.lua b/harness/mame/hp_int.lua new file mode 100644 index 0000000..f96454e --- /dev/null +++ b/harness/mame/hp_int.lua @@ -0,0 +1,30 @@ +-- hp_int.lua -- is the DUART IRQ reaching the CPU? +local machine = manager.machine +local cpu = machine.devices[':maincpu'] +local dbg = machine.debugger +local prog = cpu.spaces['program'] +if not dbg then print("ERROR: no debugger"); machine:exit(); return end +local function bp(addr, msg) + dbg:command(string.format('bpset %s,,{ printf "%s pc=%%08X a7=%%08X a9=%%08X a11=%%08X\\n", pc, a7, a9, a11 ; g }', addr, msg)) +end +bp("0f60", "INT1-TRAMPOLINE") +bp("0f30", "INT2-TRAMPOLINE") +bp("3fa92f40", "INT1-HANDLER") +bp("3fa78d90", "DUART-ISR") +bp("3fa79c00", "ISR-THRA") +bp("3fa7b6e0", "DUART-ISR2") + +local rd = function(a) return prog:read_u16(a) end +local last = {} +local keys = { INTPEND=0xc0000120, INTENB=0xc0000110, D1ISR=0x06400050 } +local n = 0 +emu.register_frame_done(function() + n = n + 1 + for k,a in pairs(keys) do + local v = rd(a) + if last[k] ~= v then print(string.format("f%4d %s -> %04X", n, k, v)); last[k]=v end + end + if n >= tonumber(os.getenv("HP_FRAMES") or "700") then print("done "..n); machine:exit() end +end, "vt1200-hp-int") +dbg.visible_cpu = cpu +dbg.execution_state = 'run' diff --git a/harness/mame/hp_irq.log b/harness/mame/hp_irq.log new file mode 100644 index 0000000..d9aa536 --- /dev/null +++ b/harness/mame/hp_irq.log @@ -0,0 +1,43 @@ +# DUART1 IRQ assert: ISR/SRA at the moment of the interrupt +irq=1 isr=09 sra=0C cyc=43805849 +irq=1 isr=09 sra=0C cyc=43828170 +irq=1 isr=0A sra=01 cyc=43829472 +irq=1 isr=09 sra=0C cyc=43851789 +irq=1 isr=0A sra=01 cyc=43853091 +irq=1 isr=09 sra=0C cyc=43875408 +irq=1 isr=0A sra=01 cyc=43876710 +irq=1 isr=09 sra=0C cyc=43899027 +irq=1 isr=0A sra=01 cyc=43900330 +irq=1 isr=09 sra=0C cyc=43922647 +irq=1 isr=0A sra=01 cyc=43923948 +irq=1 isr=0C sra=00 cyc=43933971 +irq=1 isr=09 sra=0C cyc=44061742 +irq=1 isr=09 sra=0C cyc=44087969 +irq=1 isr=0A sra=01 cyc=44089271 +irq=1 isr=09 sra=0C cyc=44114193 +irq=1 isr=0A sra=01 cyc=44115495 +irq=1 isr=09 sra=0C cyc=44140416 +irq=1 isr=0A sra=01 cyc=44141718 +irq=1 isr=09 sra=0C cyc=44166640 +irq=1 isr=0A sra=01 cyc=44167942 +irq=1 isr=09 sra=0C cyc=44192863 +irq=1 isr=0A sra=01 cyc=44194166 +irq=1 isr=0C sra=00 cyc=44200001 +irq=1 isr=09 sra=0C cyc=44327797 +irq=1 isr=09 sra=0C cyc=44354024 +irq=1 isr=0A sra=21 cyc=44355326 +irq=1 isr=09 sra=0C cyc=44380248 +irq=1 isr=0A sra=21 cyc=44381550 +irq=1 isr=09 sra=0C cyc=44406471 +irq=1 isr=0A sra=21 cyc=44407773 +irq=1 isr=09 sra=0C cyc=44432695 +irq=1 isr=0A sra=01 cyc=44433997 +irq=1 isr=09 sra=0C cyc=44458918 +irq=1 isr=0A sra=01 cyc=44460221 +irq=1 isr=0C sra=00 cyc=44466068 +irq=1 isr=09 sra=0C cyc=44592754 +irq=1 isr=09 sra=0C cyc=44611168 +irq=1 isr=0B sra=0D cyc=44629580 +irq=1 isr=0B sra=0D cyc=44647992 +irq=1 isr=0B sra=0F cyc=44666403 +irq=1 isr=0B sra=0F cyc=44684815 diff --git a/harness/mame/hp_probe.lua b/harness/mame/hp_probe.lua new file mode 100644 index 0000000..5c06f45 --- /dev/null +++ b/harness/mame/hp_probe.lua @@ -0,0 +1,40 @@ +-- hp_probe.lua -- breakpoints on the level-1 host-port test's decision points. +-- +-- HP_FRAMES=700 vt1200 ... -autoboot_script harness/mame/hp_probe.lua +-- Output goes to debug.log (debugger console), not stdout. + +local machine = manager.machine +local cpu = machine.devices[':maincpu'] +local dbg = machine.debugger + +if not dbg then print("ERROR: no debugger"); machine:exit(); return end + +local function bp(addr, msg) + dbg:command(string.format('bpset %s,,{ printf "%s pc=%%08X a7=%%08X a9=%%08X a11=%%08X a13=%%08X\\n", pc, a7, a9, a11, a13 ; g }', addr, msg)) +end + +bp("3fa6e4b0", "ENTER-L3FA6E4B0") +bp("3fa753d0", "ENTER-RXCHECK") +bp("3fa767e0", "ENTER-XMITPASS") +bp("3fa76890", "XMIT-SKIPCHK") +bp("3fa761e0", "SRA-CHECK") +bp("3fa76390", "RHRA-CMP") +bp("3fa76300", "PATTERN") +bp("3fa76320", "MASK") +bp("3fa75bb0", "MR1-WRITE") +bp("3fa75cd0", "MR2-WRITE") +bp("3fa75dd0", "RXCHECK-COUNT") +bp("3fa75d70", "RXCHECK-CRA5") +bp("3fa76a40", "XMIT-SET-AA") +bp("3fa772d0", "XMIT-SET-COUNT4") + +print("probe armed") +local n = 0 +local maxframes = tonumber(os.getenv("HP_FRAMES") or "700") +emu.register_frame_done(function() + n = n + 1 + if n >= maxframes then print("done " .. n); machine:exit() end +end, "vt1200-hp-probe") + +dbg.visible_cpu = cpu +dbg.execution_state = 'run' diff --git a/harness/mame/hp_probe2.lua b/harness/mame/hp_probe2.lua new file mode 100644 index 0000000..dd0e7f9 --- /dev/null +++ b/harness/mame/hp_probe2.lua @@ -0,0 +1,24 @@ +-- hp_probe2.lua -- status flags and struct fields during the host-port test. +local machine = manager.machine +local cpu = machine.devices[':maincpu'] +local dbg = machine.debugger +if not dbg then print("ERROR: no debugger"); machine:exit(); return end +local function bp(addr, body) + local cmd = 'bpset ' .. addr .. ',,{ ' .. body .. ' ; g }' + print("CMD " .. cmd) + dbg:command(cmd) +end +bp("3fa76030", 'printf "RX-3d0 a7=%08X s3d0=%04X\\n", a7, d@270C60') +bp("3fa760b0", 'printf "RX-3c0 a7=%08X s3c0=%04X\\n", a7, d@270C50') +bp("3fa76440", 'printf "RX-FLAGS a13=%08X flags=%08X cnt320=%04X\\n", a13, d@1D70, d@270BB0') +bp("3fa76390", 'printf "RHRA-CMP exp=%08X got=%08X\\n", a7, a9') +bp("3fa73440", 'printf "BC0-CHK s0=%04X s320=%04X\\n", d@270890, d@270BB0') +bp("3fa74be0", 'printf "BC0-LATE s0=%04X s320=%04X s730=%04X\\n", d@270890, d@270BB0, d@270C00') +bp("3fa79ed0", 'printf "ISR-TX-THRA val=%08X\\n", d@270890') +local n = 0 +emu.register_frame_done(function() + n = n + 1 + if n >= tonumber(os.getenv("HP_FRAMES") or "700") then print("done "..n); machine:exit() end +end, "vt1200-hp-probe2") +dbg.visible_cpu = cpu +dbg.execution_state = 'run' diff --git a/harness/mame/hp_ret.lua b/harness/mame/hp_ret.lua new file mode 100644 index 0000000..3da23af --- /dev/null +++ b/harness/mame/hp_ret.lua @@ -0,0 +1,20 @@ +-- hp_ret.lua -- return values of the host-port sub-tests. +local machine = manager.machine +local cpu = machine.devices[':maincpu'] +local dbg = machine.debugger +if not dbg then print("ERROR: no debugger"); machine:exit(); return end +local function bp(addr, msg) + dbg:command(string.format('bpset %s,,{ printf "%s a8=%%08X a7=%%08X a9=%%08X a13=%%08X\\n", a8, a7, a9, a13 ; g }', addr, msg)) +end +bp("3fa71bb0", "RET-BC0") -- L3FA71BC0 rets +bp("3fa753c0", "RET-RXCHECK") -- L3FA753D0 rets +bp("3fa767d0", "RET-XMITPASS") -- L3FA767E0 rets +bp("3fa84fe0", "RET-HOSTPORT") -- after calla L3FA6E4B0 +bp("3fa6e4b0", "ENTER-GENERIC") +local n = 0 +emu.register_frame_done(function() + n = n + 1 + if n >= tonumber(os.getenv("HP_FRAMES") or "700") then print("done "..n); machine:exit() end +end, "vt1200-hp-ret") +dbg.visible_cpu = cpu +dbg.execution_state = 'run' diff --git a/harness/mame/hp_snap.lua b/harness/mame/hp_snap.lua new file mode 100644 index 0000000..42c9162 --- /dev/null +++ b/harness/mame/hp_snap.lua @@ -0,0 +1,21 @@ +-- hp_snap.lua -- ISR SRA snapshots (struct[index].0x3b0) and the transmit sequence. +local machine = manager.machine +local cpu = machine.devices[':maincpu'] +local dbg = machine.debugger +if not dbg then print("ERROR: no debugger"); machine:exit(); return end +local function bp(addr, body) + local cmd = 'bpset ' .. addr .. ',,{ ' .. body .. ' ; g }' + print("CMD " .. cmd) + dbg:command(cmd) +end +-- ISR TxRDYA path: snapshot store, and transmit store. +bp("3fa79e20", 'printf "SNAP a7=%08X idx=%d SRA=%04X s320=%04X\\n", a7, (a7-270860)/16, d@6400010, d@270BB0') +bp("3fa79ed0", 'printf "TX a7=%08X idx=%d SRA=%04X\\n", a7, (a7-270860)/16, d@6400010') +bp("3fa7a390", 'printf "SNAP5 idx5 SRA=%04X\\n", d@6400010') +local n = 0 +emu.register_frame_done(function() + n = n + 1 + if n >= tonumber(os.getenv("HP_FRAMES") or "700") then print("done "..n); machine:exit() end +end, "vt1200-hp-snap") +dbg.visible_cpu = cpu +dbg.execution_state = 'run' diff --git a/harness/mame/hp_struct.log b/harness/mame/hp_struct.log new file mode 100644 index 0000000..9a67158 --- /dev/null +++ b/harness/mame/hp_struct.log @@ -0,0 +1,663 @@ +# kind bitaddr pc value -- DUART descriptor area (bit 0x270000-0x270fff) +W 270100 pc=3FB43E40 val=0000 +W 2701D0 pc=3FB43E40 val=00AA +W 2701E0 pc=3FB43E40 val=00FF +W 2701F0 pc=3FB43E40 val=00AA +W 270200 pc=3FB43E40 val=0055 +W 270210 pc=3FB43E40 val=0000 +W 270270 pc=3FB43E40 val=0088 +W 270280 pc=3FB43E40 val=0099 +W 270290 pc=3FB43E40 val=00BB +W 2702A0 pc=3FB43E40 val=00CC +W 2702F0 pc=3FB43E40 val=0000 +W 270300 pc=3FB43E40 val=0007 +W 270310 pc=3FB43E40 val=000F +W 270350 pc=3FB43E40 val=0004 +W 270360 pc=3FB43E40 val=0000 +W 270370 pc=3FB43E40 val=0001 +W 2703B0 pc=3FB43E40 val=0000 +W 2703C0 pc=3FB43E40 val=0001 +W 2703D0 pc=3FB43E40 val=0002 +W 2703E0 pc=3FB43E40 val=0003 +W 2703F0 pc=3FB43E40 val=001F +W 270400 pc=3FB43E40 val=003F +W 270410 pc=3FB43E40 val=007F +W 270420 pc=3FB43E40 val=00FF +W 2704B0 pc=3FB43E40 val=0101 +W 2704C0 pc=3FB43E40 val=0101 +W 2704D0 pc=3FB43E40 val=0001 +W 2704E0 pc=3FB43E40 val=0101 +W 2704F0 pc=3FB43E40 val=0101 +W 270500 pc=3FB43E40 val=0001 +W 270510 pc=3FB43E40 val=0101 +W 270520 pc=3FB43E40 val=0101 +W 270530 pc=3FB43E40 val=0001 +W 270540 pc=3FB43E40 val=0101 +W 270550 pc=3FB43E40 val=0101 +W 270560 pc=3FB43E40 val=0001 +W 270570 pc=3FB43E40 val=0000 +W 270580 pc=3FB43E40 val=0000 +W 270590 pc=3FB43E40 val=0000 +W 2705A0 pc=3FB43E40 val=0000 +W 2705B0 pc=3FB43E40 val=0000 +W 2705C0 pc=3FB43E40 val=0000 +W 2705D0 pc=3FB43E40 val=0000 +W 2705E0 pc=3FB43E40 val=0000 +W 2705F0 pc=3FB43E40 val=0000 +W 270600 pc=3FB43E40 val=0000 +W 270610 pc=3FB43E40 val=0000 +W 270620 pc=3FB43E40 val=0000 +W 270630 pc=3FB43E40 val=040C +W 270640 pc=3FB43E40 val=0404 +W 270650 pc=3FB43E40 val=0404 +W 270660 pc=3FB43E40 val=040C +W 270670 pc=3FB43E40 val=0404 +W 270680 pc=3FB43E40 val=0404 +W 270690 pc=3FB43E40 val=040C +W 2706A0 pc=3FB43E40 val=0404 +W 2706B0 pc=3FB43E40 val=0404 +W 2706C0 pc=3FB43E40 val=040C +W 2706D0 pc=3FB43E40 val=0404 +W 2706E0 pc=3FB43E40 val=0404 +W 2706F0 pc=3FB43E40 val=0000 +W 270700 pc=3FB43E40 val=0000 +W 270710 pc=3FB43E40 val=0000 +W 270720 pc=3FB43E40 val=0000 +W 270730 pc=3FB43E40 val=0000 +W 270740 pc=3FB43E40 val=0000 +W 270750 pc=3FB43E40 val=0000 +W 270760 pc=3FB43E40 val=0000 +W 270770 pc=3FB43E40 val=0000 +W 270780 pc=3FB43E40 val=0000 +W 270790 pc=3FB43E40 val=0000 +W 2707A0 pc=3FB43E40 val=0000 +W 2707B0 pc=3FB43E40 val=0202 +W 2707C0 pc=3FB43E40 val=0202 +W 2707D0 pc=3FB43E40 val=0102 +W 2707E0 pc=3FB43E40 val=0101 +W 2707F0 pc=3FB43E40 val=0101 +W 270800 pc=3FB43E40 val=0000 +W 270810 pc=3FB43E40 val=0000 +W 270860 pc=3FA78950 val=0000 +W 270870 pc=3FA78950 val=0000 +W 270880 pc=3FA78950 val=0000 +W 270890 pc=3FA78950 val=0000 +W 2708A0 pc=3FA78950 val=0000 +W 2708B0 pc=3FA78950 val=0000 +W 2708C0 pc=3FA78950 val=0000 +W 2708D0 pc=3FA78950 val=0000 +W 2708E0 pc=3FA78950 val=0000 +W 2708F0 pc=3FA78950 val=0000 +W 270900 pc=3FA78950 val=0000 +W 270910 pc=3FA78950 val=0000 +W 270920 pc=3FA78950 val=0000 +W 270930 pc=3FA78950 val=0000 +W 270940 pc=3FA78950 val=0000 +W 270950 pc=3FA78950 val=0000 +W 270960 pc=3FA78950 val=0000 +W 270970 pc=3FA78950 val=0000 +W 270980 pc=3FA78950 val=0000 +W 270990 pc=3FA78950 val=0000 +W 2709A0 pc=3FA78950 val=0000 +W 2709B0 pc=3FA78950 val=0000 +W 2709C0 pc=3FA78950 val=0000 +W 2709D0 pc=3FA78950 val=0000 +W 2709E0 pc=3FA78950 val=0000 +W 2709F0 pc=3FA78950 val=0000 +W 270A00 pc=3FA78950 val=0000 +W 270A10 pc=3FA78950 val=0000 +W 270A20 pc=3FA78950 val=0000 +W 270A30 pc=3FA78950 val=0000 +W 270A40 pc=3FA78950 val=0000 +W 270A50 pc=3FA78950 val=0000 +W 270A60 pc=3FA78950 val=0000 +W 270A70 pc=3FA78950 val=0000 +W 270A80 pc=3FA78950 val=0000 +W 270A90 pc=3FA78950 val=0000 +W 270AA0 pc=3FA78950 val=0000 +W 270AB0 pc=3FA78950 val=0000 +W 270AC0 pc=3FA78950 val=0000 +W 270AD0 pc=3FA78950 val=0000 +W 270AE0 pc=3FA78950 val=0000 +W 270AF0 pc=3FA78950 val=0000 +W 270B00 pc=3FA78950 val=0000 +W 270B10 pc=3FA78950 val=0000 +W 270B20 pc=3FA78950 val=0000 +W 270B30 pc=3FA78950 val=0000 +W 270B40 pc=3FA78950 val=0000 +W 270B50 pc=3FA78950 val=0000 +W 270B60 pc=3FA78950 val=0000 +W 270B70 pc=3FA78950 val=0000 +W 270B80 pc=3FA78950 val=0000 +W 270B90 pc=3FA78950 val=0000 +W 270BA0 pc=3FA78950 val=0000 +W 270BB0 pc=3FA78950 val=0000 +W 270BC0 pc=3FA78950 val=0000 +W 270BD0 pc=3FA78950 val=0000 +W 270BE0 pc=3FA78950 val=0000 +W 270BF0 pc=3FA78950 val=0000 +W 270C00 pc=3FA78950 val=0000 +W 270C10 pc=3FA78950 val=0000 +W 270C20 pc=3FA78950 val=0000 +W 270C30 pc=3FA78950 val=0000 +W 270C40 pc=3FA78950 val=0000 +W 270C50 pc=3FA78950 val=0000 +W 270C60 pc=3FA78950 val=0000 +W 270C70 pc=3FA78950 val=0000 +W 270C80 pc=3FA78950 val=0000 +W 270C90 pc=3FA78950 val=0000 +W 270CA0 pc=3FA78950 val=0000 +W 270CB0 pc=3FA78950 val=0000 +W 270CC0 pc=3FA78950 val=0000 +W 270CD0 pc=3FA78950 val=0000 +W 270CE0 pc=3FA78950 val=0000 +W 270CF0 pc=3FA78950 val=0000 +W 270D00 pc=3FA78950 val=0000 +W 270D10 pc=3FA78950 val=0000 +W 270D20 pc=3FA78950 val=0000 +W 270D30 pc=3FA78950 val=0000 +W 270D40 pc=3FA78950 val=0000 +W 270D50 pc=3FA78950 val=0000 +W 270D60 pc=3FA78950 val=0000 +W 270D70 pc=3FA78950 val=0000 +W 270D80 pc=3FA78950 val=0000 +W 270D90 pc=3FA78950 val=0000 +W 270DA0 pc=3FA78950 val=0000 +W 270DB0 pc=3FA78950 val=0000 +W 270DC0 pc=3FA78950 val=0000 +W 270DD0 pc=3FA78950 val=0000 +W 270DE0 pc=3FA78950 val=0000 +W 270DF0 pc=3FA78950 val=0000 +W 270E00 pc=3FA78950 val=0000 +W 270E10 pc=3FA78950 val=0000 +W 270E20 pc=3FA78950 val=0000 +W 270E30 pc=3FA78950 val=0000 +W 270E40 pc=3FA78950 val=0000 +W 270E50 pc=3FA78950 val=0000 +W 270E60 pc=3FA78950 val=0000 +W 270E70 pc=3FA78950 val=0000 +W 270E80 pc=3FA78950 val=0000 +W 270E90 pc=3FA78950 val=0000 +W 270EA0 pc=3FA78950 val=0000 +W 270EB0 pc=3FA78950 val=0000 +W 270EC0 pc=3FA78950 val=0000 +W 270ED0 pc=3FA78950 val=0000 +W 270EE0 pc=3FA78950 val=0000 +W 270EF0 pc=3FA78950 val=0000 +W 270F00 pc=3FA78950 val=0000 +W 270F10 pc=3FA78950 val=0000 +W 270F20 pc=3FA78950 val=0000 +W 270F30 pc=3FA78950 val=0000 +W 270F40 pc=3FA78950 val=0000 +W 270F50 pc=3FA78950 val=0000 +W 270F60 pc=3FA78950 val=0000 +W 270F70 pc=3FA78950 val=0000 +W 270F80 pc=3FA78950 val=0000 +W 270F90 pc=3FA78950 val=0000 +W 270FA0 pc=3FA78950 val=0000 +W 270FB0 pc=3FA78950 val=0000 +W 270FC0 pc=3FA78950 val=0000 +W 270FD0 pc=3FA78950 val=0000 +W 270FE0 pc=3FA78950 val=0000 +W 270FF0 pc=3FA78950 val=0000 +R 2701D0 pc=3FA6EF60 val=00AA +W 270220 pc=3FA6EF60 val=00AA +R 2701E0 pc=3FA6EF60 val=00FF +W 270230 pc=3FA6EF60 val=00FF +R 2701F0 pc=3FA6EF60 val=00AA +W 270240 pc=3FA6EF60 val=00AA +R 270200 pc=3FA6EF60 val=0055 +W 270250 pc=3FA6EF60 val=0055 +R 270210 pc=3FA6EF60 val=0000 +W 270260 pc=3FA6EF60 val=0000 +R 270270 pc=3FA6F0D0 val=0088 +W 2702B0 pc=3FA6F0D0 val=0088 +R 270280 pc=3FA6F0D0 val=0099 +W 2702C0 pc=3FA6F0D0 val=0099 +R 270290 pc=3FA6F0D0 val=00BB +W 2702D0 pc=3FA6F0D0 val=00BB +R 2702A0 pc=3FA6F0D0 val=00CC +W 2702E0 pc=3FA6F0D0 val=00CC +R 2702F0 pc=3FA6F240 val=0000 +W 270320 pc=3FA6F240 val=0000 +R 270300 pc=3FA6F240 val=0007 +W 270330 pc=3FA6F240 val=0007 +R 270310 pc=3FA6F240 val=000F +W 270340 pc=3FA6F240 val=000F +R 270350 pc=3FA6F3B0 val=0004 +W 270380 pc=3FA6F3B0 val=0004 +R 270360 pc=3FA6F3B0 val=0000 +W 270390 pc=3FA6F3B0 val=0000 +R 270370 pc=3FA6F3B0 val=0001 +W 2703A0 pc=3FA6F3B0 val=0001 +R 2703B0 pc=3FA6F520 val=0000 +W 270430 pc=3FA6F520 val=0000 +R 2703C0 pc=3FA6F520 val=0001 +W 270440 pc=3FA6F520 val=0001 +R 2703D0 pc=3FA6F520 val=0002 +W 270450 pc=3FA6F520 val=0002 +R 2703E0 pc=3FA6F520 val=0003 +W 270460 pc=3FA6F520 val=0003 +R 2703F0 pc=3FA6F690 val=001F +W 270470 pc=3FA6F690 val=001F +R 270400 pc=3FA6F690 val=003F +W 270480 pc=3FA6F690 val=003F +R 270410 pc=3FA6F690 val=007F +W 270490 pc=3FA6F690 val=007F +R 270420 pc=3FA6F690 val=00FF +W 2704A0 pc=3FA6F690 val=00FF +R 270860 pc=3FA78AF0 val=0000 +W 270860 pc=3FA78B10 val=0007 +R 2702B0 pc=3FA72220 val=0088 +R 270220 pc=3FA723C0 val=00AA +W 270BC0 pc=3FA723C0 val=00AA +R 270230 pc=3FA723C0 val=00FF +W 270BD0 pc=3FA723C0 val=00FF +R 270240 pc=3FA723C0 val=00AA +W 270BE0 pc=3FA723C0 val=00AA +R 270250 pc=3FA723C0 val=0055 +W 270BF0 pc=3FA723C0 val=0055 +R 270260 pc=3FA723C0 val=0000 +W 270C00 pc=3FA723C0 val=0000 +R 2704B0 pc=3FA72670 val=0101 +W 2709B0 pc=3FA726A0 val=0001 +R 270630 pc=3FA728B0 val=040C +W 270CD0 pc=3FA728E0 val=000C +W 2709C0 pc=3FA726A0 val=0001 +W 270CE0 pc=3FA728E0 val=0004 +R 2704C0 pc=3FA72670 val=0101 +W 2709D0 pc=3FA726A0 val=0001 +R 270640 pc=3FA728B0 val=0404 +W 270CF0 pc=3FA728E0 val=0004 +W 2709E0 pc=3FA726A0 val=0001 +W 270D00 pc=3FA728E0 val=0004 +R 2704D0 pc=3FA72670 val=0001 +W 2709F0 pc=3FA726A0 val=0001 +R 270650 pc=3FA728B0 val=0404 +W 270D10 pc=3FA728E0 val=0004 +W 270A00 pc=3FA726A0 val=0000 +W 270D20 pc=3FA728E0 val=0004 +R 270570 pc=3FA72670 val=0000 +W 270A10 pc=3FA726A0 val=0000 +R 2706F0 pc=3FA728B0 val=0000 +W 270D30 pc=3FA728E0 val=0000 +W 270A20 pc=3FA726A0 val=0000 +W 270D40 pc=3FA728E0 val=0000 +R 270580 pc=3FA72670 val=0000 +W 270A30 pc=3FA726A0 val=0000 +R 270700 pc=3FA728B0 val=0000 +W 270D50 pc=3FA728E0 val=0000 +W 270A40 pc=3FA726A0 val=0000 +W 270D60 pc=3FA728E0 val=0000 +R 270590 pc=3FA72670 val=0000 +W 270A50 pc=3FA726A0 val=0000 +R 270710 pc=3FA728B0 val=0000 +W 270D70 pc=3FA728E0 val=0000 +W 270A60 pc=3FA726A0 val=0000 +W 270D80 pc=3FA728E0 val=0000 +W 270F90 pc=3FA729F0 val=0000 +R 270450 pc=3FA72FC0 val=0002 +R 270380 pc=3FA73040 val=0004 +R 270320 pc=3FA73190 val=0000 +R 270860 pc=3FA78E40 val=0007 +W 270820 pc=3FA78E80 val=0001 +R 270820 pc=3FA78EB0 val=0001 +R 270820 pc=3FA791B0 val=0001 +R 270820 pc=3FA794B0 val=0001 +W 270820 pc=3FA79CB0 val=0000 +R 270BB0 pc=3FA79CF0 val=0000 +R 270F90 pc=3FA79D30 val=0000 +R 270BB0 pc=3FA79DE0 val=0000 +W 270C10 pc=3FA79E50 val=000C +R 270BB0 pc=3FA79E90 val=0000 +R 270BC0 pc=3FA79F00 val=00AA +R 270BB0 pc=3FA79F40 val=0000 +W 270C70 pc=3FA79FB0 val=0000 +R 270BB0 pc=3FA79FF0 val=0000 +R 270ED0 pc=3FA7A060 val=0000 +R 270BB0 pc=3FA7A0A0 val=0000 +R 270F20 pc=3FA7A110 val=0000 +R 270BB0 pc=3FA7A150 val=0000 +W 270D90 pc=3FA7A1C0 val=00F0 +R 270F90 pc=3FA7A200 val=0000 +R 270BB0 pc=3FA7A2B0 val=0000 +W 270DE0 pc=3FA7A320 val=00F0 +R 270BB0 pc=3FA7A480 val=0000 +W 270BB0 pc=3FA7A4B0 val=0001 +R 270880 pc=3FA7B650 val=0000 +W 270880 pc=3FA7B690 val=0002 +R 270890 pc=3FA73290 val=0000 +R 270BB0 pc=3FA79CF0 val=0001 +R 270BB0 pc=3FA79DE0 val=0001 +W 270C20 pc=3FA79E50 val=0004 +R 270BB0 pc=3FA79E90 val=0001 +R 270BD0 pc=3FA79F00 val=00FF +R 270BB0 pc=3FA79F40 val=0001 +W 270C80 pc=3FA79FB0 val=0000 +R 270BB0 pc=3FA79FF0 val=0001 +R 270EE0 pc=3FA7A060 val=0000 +R 270BB0 pc=3FA7A0A0 val=0001 +R 270F30 pc=3FA7A110 val=0000 +R 270BB0 pc=3FA7A150 val=0001 +W 270DA0 pc=3FA7A1C0 val=00F0 +R 270BB0 pc=3FA7A2B0 val=0001 +W 270DF0 pc=3FA7A320 val=00F0 +R 270BB0 pc=3FA7A480 val=0001 +W 270BB0 pc=3FA7A4B0 val=0002 +R 270880 pc=3FA7B650 val=0002 +R 270890 pc=3FA73390 val=0000 +R 270BB0 pc=3FA79CF0 val=0002 +R 270BB0 pc=3FA79DE0 val=0002 +W 270C30 pc=3FA79E50 val=0004 +R 270BB0 pc=3FA79E90 val=0002 +R 270BE0 pc=3FA79F00 val=00AA +R 270BB0 pc=3FA79F40 val=0002 +W 270C90 pc=3FA79FB0 val=0000 +R 270BB0 pc=3FA79FF0 val=0002 +R 270EF0 pc=3FA7A060 val=0000 +R 270BB0 pc=3FA7A0A0 val=0002 +R 270F40 pc=3FA7A110 val=0000 +R 270BB0 pc=3FA7A150 val=0002 +W 270DB0 pc=3FA7A1C0 val=00F0 +R 270BB0 pc=3FA7A2B0 val=0002 +W 270E00 pc=3FA7A320 val=00F0 +R 270BB0 pc=3FA7A480 val=0002 +W 270BB0 pc=3FA7A4B0 val=0003 +W 270820 pc=3FA78E80 val=0002 +R 270820 pc=3FA78EB0 val=0002 +R 270820 pc=3FA791B0 val=0002 +R 270820 pc=3FA794B0 val=0002 +W 270820 pc=3FA79530 val=0000 +R 270890 pc=3FA79570 val=0000 +R 270F90 pc=3FA795D0 val=0000 +R 270890 pc=3FA79660 val=0000 +W 2708F0 pc=3FA796D0 val=0001 +R 270890 pc=3FA79710 val=0000 +W 2708A0 pc=3FA79780 val=002A +R 270890 pc=3FA797C0 val=0000 +W 270950 pc=3FA79830 val=0000 +R 270890 pc=3FA79870 val=0000 +W 270A70 pc=3FA798E0 val=00F0 +R 270F90 pc=3FA79920 val=0000 +R 270890 pc=3FA799B0 val=0000 +W 270AC0 pc=3FA79A20 val=00F0 +R 270890 pc=3FA79BF0 val=0000 +W 270890 pc=3FA79C20 val=0001 +R 270890 pc=3FA73390 val=0001 +R 270BB0 pc=3FA79CF0 val=0003 +R 270BB0 pc=3FA79DE0 val=0003 +W 270C40 pc=3FA79E50 val=0004 +R 270BB0 pc=3FA79E90 val=0003 +R 270BF0 pc=3FA79F00 val=0055 +R 270BB0 pc=3FA79F40 val=0003 +W 270CA0 pc=3FA79FB0 val=0000 +R 270BB0 pc=3FA79FF0 val=0003 +R 270F00 pc=3FA7A060 val=0000 +R 270BB0 pc=3FA7A0A0 val=0003 +R 270F50 pc=3FA7A110 val=0000 +R 270BB0 pc=3FA7A150 val=0003 +W 270DC0 pc=3FA7A1C0 val=00F0 +R 270BB0 pc=3FA7A2B0 val=0003 +W 270E10 pc=3FA7A320 val=00F0 +R 270BB0 pc=3FA7A480 val=0003 +W 270BB0 pc=3FA7A4B0 val=0004 +R 270890 pc=3FA79570 val=0001 +R 270890 pc=3FA79660 val=0001 +W 270900 pc=3FA796D0 val=0001 +R 270890 pc=3FA79710 val=0001 +W 2708B0 pc=3FA79780 val=007F +R 270890 pc=3FA797C0 val=0001 +W 270960 pc=3FA79830 val=0000 +R 270890 pc=3FA79870 val=0001 +W 270A80 pc=3FA798E0 val=00F0 +R 270890 pc=3FA799B0 val=0001 +W 270AD0 pc=3FA79A20 val=00F0 +R 270890 pc=3FA79BF0 val=0001 +W 270890 pc=3FA79C20 val=0002 +R 270890 pc=3FA73390 val=0002 +R 270BB0 pc=3FA79CF0 val=0004 +R 270BB0 pc=3FA79DE0 val=0004 +W 270C50 pc=3FA79E50 val=0004 +R 270BB0 pc=3FA79E90 val=0004 +R 270C00 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pc=3FA75CC0 val=0000 +R 270860 pc=3FA78E40 val=0001 +R 270BB0 pc=3FA75DF0 val=0001 +W 270C40 pc=3FA79E50 val=0005 +W 270CA0 pc=3FA79FB0 val=0001 +W 270C50 pc=3FA79E50 val=0005 +W 270CB0 pc=3FA79FB0 val=0001 +R 270BB0 pc=3FA75F00 val=0005 +W 270C60 pc=3FA7A3C0 val=0007 +W 270CC0 pc=3FA7A440 val=0003 +R 270C60 pc=3FA76050 val=0007 +R 270C50 pc=3FA760E0 val=0005 +R 270BC0 pc=3FA76320 val=00AA +R 270470 pc=3FA76330 val=001F +R 270BD0 pc=3FA76320 val=00FF +R 270BE0 pc=3FA76320 val=00AA +R 270860 pc=3FA78CC0 val=0001 +R 270880 pc=3FA852B0 val=0002 diff --git a/harness/mame/hp_trace.lua b/harness/mame/hp_trace.lua new file mode 100644 index 0000000..a1999a9 --- /dev/null +++ b/harness/mame/hp_trace.lua @@ -0,0 +1,50 @@ +-- hp_trace.lua -- dynamic trace of the level-1 HOST PORT test. +-- +-- Polls (per frame, via the address map so device side effects apply): +-- INTENB/INTPEND (CPU I/O regs) +-- DUART1 ISR (window 0x06400000 + reg 5 -> program space 0x06400050) +-- DUART1 SRA (reg 1 -> 0x06400010) +-- DUART1 CRA read? no (write-only-ish); MR1A read ok (reg 0 -> 0x06400000) +-- DO NOT read reg 3 (RHRA) -- it pops the FIFO. +-- +-- Also breaks at key PCs and logs registers. +-- +-- HP_FRAMES=900 vt1200 ... -autoboot_script harness/mame/hp_trace.lua + +local machine = manager.machine +local cpu = machine.devices[':maincpu'] +local dbg = machine.debugger +local prog = cpu.spaces['program'] + +if not dbg then print("ERROR: no debugger"); machine:exit(); return end + +local rd = function(a) return prog:read_u16(a) end +local maxframes = tonumber(os.getenv("HP_FRAMES") or "900") +local n = 0 + +-- Frame polling: report changes and every 25 frames a compact snapshot. +local last = {} +local keys = { + INTENB = 0xc0000110, + INTPEND = 0xc0000120, + D1_ISR = 0x06400050, -- reg 5 + D1_SRA = 0x06400010, -- reg 1 + D1_MR1 = 0x06400000, -- reg 0 +} +emu.register_frame_done(function() + n = n + 1 + for name, addr in pairs(keys) do + local v = rd(addr) + if last[name] ~= v then + print(string.format("f%4d %s CHANGED -> %04X", n, name, v)) + last[name] = v + end + end + if n >= maxframes then + print("done (" .. n .. " frames)") + machine:exit() + end +end, "vt1200-hp") + +dbg.visible_cpu = cpu +dbg.execution_state = 'run' diff --git a/harness/mame/vt1200.cpp b/harness/mame/vt1200.cpp index 59f7ddf..523d591 100644 --- a/harness/mame/vt1200.cpp +++ b/harness/mame/vt1200.cpp @@ -54,6 +54,12 @@ VT1200_DUART_LB1/LB2=1 external TX->RX loopback on DUART1 / DUART2. VT1200_DUARTLOG= every DUART access (not de-duplicated). + VT1200_DUART also wires each DUART's IRQ output to the TMS34010's external + interrupt inputs (DUART1 -> INT1, DUART2 -> INT2). This is required: the + level-1 host-port test's transmit is entirely ISR-driven (the ISR writes + THRA), and without the wiring THRA is never written at all. See + DUART_REPORT.md section FINAL FINDINGS. + The remaining board knobs refine VT1200_BOARD_MODEL=handshake. They are modifiers, not on-switches: one of the knobs above must also be set, or the windows stay unmapped and they do nothing. @@ -141,6 +147,15 @@ public: u16 duart1_r(offs_t off); void duart1_w(offs_t off, u16 data); u16 duart2_r(offs_t off); void duart2_w(offs_t off, u16 data); + // DUART interrupt outputs -> the TMS34010's two external interrupt lines. + // The firmware installs RAM trampolines in the CPU's fixed vector table + // (INT1 at vector 0xffffffc0 -> stub at bit 0x0f60 = JA 0x3FA92F40, the + // DUART1 ISR; INT2 at 0xffffffa0 -> stub at bit 0x0f30 = JA 0x3FA93070, + // also a DUART1 entry). Without this wiring the level-1 host-port test's + // interrupt-driven transmit never runs (see DUART_REPORT.md). + void duart1_irq_w(int state); + void duart2_irq_w(int state); + private: void program_map(address_map &map) ATTR_COLD; @@ -246,6 +261,17 @@ private: void lowlog_w(offs_t off, u16 data); void log_low(char kind, u32 addr, u16 value); + // VT1200_STRUCTLOG= + // Transparent logging proxy over the DUART self-test descriptor area + // (bit 0x270000-0x270fff), to find who writes the status/count fields the + // level-1 port tests check. Forwards to the real mainram share. + FILE *m_irqlog = nullptr; + FILE *m_structlog = nullptr; + std::map, u32> m_structlog_seen; // (addr,pc,val,kind) -> count + u16 structlog_r(offs_t off); + void structlog_w(offs_t off, u16 data); + void log_struct(char kind, u32 addr, u16 value); + // VT1200_DUARTLOG= // EVERY DUART access (not de-duplicated), so a write that happens once per // iteration cannot hide. Used to prove whether the transmit register is @@ -364,6 +390,20 @@ void vt1200_state::machine_start() fprintf(m_lowlog, "# kind bitaddr pc value -- transparent low-RAM access log\n"); } + if (const char *p = getenv("VT1200_IRQLOG")) + { + m_irqlog = fopen(p, "w"); + if (m_irqlog) + fprintf(m_irqlog, "# DUART1 IRQ assert: ISR/SRA at the moment of the interrupt\n"); + } + + if (const char *p = getenv("VT1200_STRUCTLOG")) + { + m_structlog = fopen(p, "w"); + if (m_structlog) + fprintf(m_structlog, "# kind bitaddr pc value -- DUART descriptor area (bit 0x270000-0x270fff)\n"); + } + if (const char *p = getenv("VT1200_DUARTLOG")) { m_duartlog = fopen(p, "w"); @@ -476,6 +516,8 @@ void vt1200_state::machine_reset() fflush(m_unmapped_log); if (m_lowlog) fflush(m_lowlog); + if (m_structlog) + fflush(m_structlog); } void vt1200_state::log_unmapped(const char *kind, u32 addr, const char *pc) @@ -527,6 +569,37 @@ void vt1200_state::log_low(char kind, u32 addr, u16 value) } } +void vt1200_state::log_struct(char kind, u32 addrof, u16 value) +{ + if (!m_structlog) + return; + const u32 pc = (u32)m_maincpu->state_int(TMS34010_PC); + auto key = std::make_tuple(addrof, pc, (u32)value, (u32)(u8)kind); + if (m_structlog_seen.find(key) == m_structlog_seen.end()) + { + m_structlog_seen.emplace(key, 1); + fprintf(m_structlog, "%c %06X pc=%08X val=%04X\n", kind, addrof, pc, value); + fflush(m_structlog); + } +} + +// The entry base is bit 0x270000, so the delegate offset is +// (bitaddr - 0x270000) >> 4 and the mainram word index is bitaddr >> 4. +u16 vt1200_state::structlog_r(offs_t off) +{ + const u32 bitaddr = 0x270000 + ((u32)off << 4); + const u16 v = m_mainram[bitaddr >> 4]; + log_struct('R', bitaddr, v); + return v; +} + +void vt1200_state::structlog_w(offs_t off, u16 data) +{ + const u32 bitaddr = 0x270000 + ((u32)off << 4); + m_mainram[bitaddr >> 4] = data; + log_struct('W', bitaddr, data); +} + u16 vt1200_state::lowlog_r(offs_t off) { const u16 v = m_mainram[(u32)off & 0x3ff]; @@ -654,6 +727,10 @@ void vt1200_state::program_map(address_map &map) // of RAM. It forwards to the real mainram share and only records. if (getenv("VT1200_LOWLOG")) map(0x00000000, 0x00003fff).rw(FUNC(vt1200_state::lowlog_r), FUNC(vt1200_state::lowlog_w)); + + // Transparent logging proxy over the DUART self-test descriptor area. + if (getenv("VT1200_STRUCTLOG")) + map(0x270000, 0x270fff).rw(FUNC(vt1200_state::structlog_r), FUNC(vt1200_state::structlog_w)); } // MAME may hand us either an entry-relative offset (0..0xffff) or the absolute // address; BOARD_BASE is 0x10000-aligned, so ORing the low 16 bits is correct @@ -774,12 +851,37 @@ void vt1200_state::duart2_w(offs_t off, u16 data) board_write(2, off, data); } +// The DUART's IRQ output is a single open-drain line per chip. Wire it to the +// CPU's external interrupt input the firmware's vector trampoline expects: +// line 0 -> TMS34010_INT1 (INTPEND 0x0002), line 1 -> TMS34010_INT2 (0x0004). +// MAME's tms34010 latches the pending bit from the line state, so deasserting +// the line (which the DUART does once ISR & IMR == 0) clears it again. +void vt1200_state::duart1_irq_w(int state) +{ + if (m_irqlog && state) + { + // ISR (reg 5) and SRA (reg 1) are side-effect-free reads. + const u32 isr = m_duart1->read(5) & 0xff; + const u32 sra = m_duart1->read(1) & 0xff; + fprintf(m_irqlog, "irq=1 isr=%02X sra=%02X cyc=%llu\n", isr, sra, + (unsigned long long)m_maincpu->total_cycles()); + fflush(m_irqlog); + } + m_maincpu->set_input_line(0, state ? ASSERT_LINE : CLEAR_LINE); +} + +void vt1200_state::duart2_irq_w(int state) +{ + m_maincpu->set_input_line(1, state ? ASSERT_LINE : CLEAR_LINE); +} + void vt1200_state::log_duart(int win, char kind, u32 reg, u16 value) { if (!m_duartlog) return; - fprintf(m_duartlog, "%d %c reg=%X val=%04X pc=%08X\n", - win, kind, reg, value, (unsigned)m_maincpu->state_int(TMS34010_PC)); + fprintf(m_duartlog, "%d %c reg=%X val=%04X pc=%08X cyc=%llu\n", + win, kind, reg, value, (unsigned)m_maincpu->state_int(TMS34010_PC), + (unsigned long long)m_maincpu->total_cycles()); fflush(m_duartlog); } @@ -980,6 +1082,17 @@ void vt1200_state::vt1200(machine_config &config) m_duart2->a_tx_cb().set(m_duart2, FUNC(scn2681_device::rx_a_w)); m_duart2->b_tx_cb().set(m_duart2, FUNC(scn2681_device::rx_b_w)); } + + // Connect the DUART interrupt outputs to the CPU. The level-1 host-port + // test enables the DUART's TxRDYA/RxRDYA interrupts (IMR = 7) and the + // firmware's ISR is what feeds THRA -- but only if the IRQ reaches the CPU. + // Gated on VT1200_DUART so the no-env baseline is untouched. DUART1's + // firmware trampoline sits on INT1; DUART2's on INT2. + if (getenv("VT1200_DUART")) + { + m_duart1->irq_cb().set(FUNC(vt1200_state::duart1_irq_w)); + m_duart2->irq_cb().set(FUNC(vt1200_state::duart2_irq_w)); + } } INPUT_PORTS_START(vt1200)