; hello.asm -- minimal TMS34010 payload for the VT1200 harness.
;
; Built with GSPA 2.00 / GSPLNK 2.00 (1987 TI SDK, DOSBox) and linked at
; bit address 01800000h (byte 00300000h in main RAM).
;
; It leaves two independent pieces of evidence:
;   1. RAM:  two magic words and a loop counter at bit 01810000h.
;   2. VRAM: a solid 256x64 block at framebuffer row 100, column 64.
;
; The screen renderer (harness/mame/vt1200.cpp, render_active_line) reads
; VRAM at bit 04000000h with a row pitch of 1024 bits and bit 0 = leftmost
; pixel, LSB-first inside each 16-bit word.
;
; Addresses in operands are BIT addresses, like every TMS34010 pointer.
; A 16-bit pixel row is 64 words; we write 16 words (256 pixels) and then
; advance the destination by 1024 - 256 = 768 bits (0300h).

	.text
_start:
	dint				; stay deterministic: no firmware ISR
	setf	16, 0, 0		; field 0 = 16 bits, zero-extended
	setf	32, 0, 1		; field 1 = 32 bits, zero-extended

	; ---- channel 1: RAM markers -----------------------------------
	movi	0DEADh, a0, L
	move	a0, @01810000h, 0	; MAGIC1 (bytes AD DE in a dump)
	movi	0BEEFh, a0, L
	move	a0, @01810010h, 0	; MAGIC2 (bytes EF BE)

	; ---- channel 2: solid block in video RAM ----------------------
	movi	04019040h, a2, L	; 04000000h + 100*1024 + 64
	movi	64, a3, L		; 64 rows
	movi	16, a4, L		; 16 words = 256 pixels per row
	sub	a1, a1			; counter = 0
	movi	0FFFFh, a0, L
row_loop:
	move	a4, a5
word_loop:
	move	a0, *a2+, 0		; store word, postincrement by 16 bits
	addi	1, a1			; count this store
	dsjs	a5, word_loop
	addi	0300h, a2		; skip 768 bits to the next row
	dsjs	a3, row_loop

	; The counter is 0400h only if all 64*16 stores executed.
	move	a1, @01810020h, 0	; COUNT

spin:
	nop
	jruc	spin

	.end