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vt1200/reference/lance-datasheet/Am7990-TechnicalManual-1986.txt
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SDD 7612fcbda9 reference: LANCE loopback-FCS datasheet evidence (MAME condition is right) 
Add the Am7990 Technical Manual and Am79C90 datasheet to
reference/lance-datasheet/ and a report, reference/lance-loopback-fcs.md,
that answers whether MAME's am79c90 receive() FCS condition
(!(MODE_LOOP) || MODE_DTCR) is inverted.

Verdict: MAME is right. The CRC generator and checker share one circuit,
so with LOOP=1 the receiver can only check the FCS when DTCR=1 -- exactly
what MAME does. The proposed inversion would be wrong in both loopback
cases. No MAME change made.
2026-10-16 16:46:47 +03:00

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Am7990 Advanced
Local Area Network Controller (LANCE) Micro
Technicai Manuai Devices
I
HOST
PROCESOOR
Am7990
lANCE
TAP
TRANSCEIVER
ffifERNEf CABLE
Advanced Micro Devices
Local Area
Network Controller
Am7990 (LANCE)
© 1986 Advanced Micro Devices, Inc.
The material in this document is subject to change without notice.
Advanced Micro Devices cannot accept responsibility for use of any circuitry
described other than circuitry embodied in an Advanced Micro Devices' product.
The applications software contained in this publication are for illustration
purposes only and Advanced Micro Devices makes no representation or
warranty that such programs will be suitable for the use specified
without further testing or modification.
Printed in U.S.A.
by Rasoul M. Oskouy, Senior Applications Engineer
Erland Kyllonen, Technical Writer
Harry Lau, Copyeditor
AMO Headquarters Applications
TABLE OF CONTENTS
Page
1. OVERVIEW ............................................................................ . 1-3
1.1 Ear!y Design Stage Testing .................. , , , , .............................. . 1-3
1.2 Reset ........................................................................ . 1-3
1 .3 Bus Slave Operation .......................................................... . 1-3
1 .4 Initialization Procedure ......................................................... . 1-4
1.4. 1 CSR Programming .......................................................... . 1-4
1.4.2 Initialization Block ........................................................... . 1-6
1.4.3 Diagnostics ................................................................. . 1-6
1 .4.4 Normal Operation ........................................................... . 1-6
1.5 Bus Master Operation ......................................................... . 1-6
1 .6 General Description ........................................................... . 1-7
1.7 Pin Description ............................................................... . 1-9
1.8 Functional Description ......................................................... . 1-11
1.8.1 Addressing ................................................................. . i-i;
1.8.2 Collision Detection and Implementation ........................................ . 1-11
Collision Jam ............................................................. . 1-11
Collision During Reception ................................................. . 1-11
Collision During Transmission .............................................. . 1-11
Collision-Microcode Interaction ............................................ . 1-11
Time Domain Reflectometry ................................................ . 1-11
Collision Pair Test (Heartbeat, SOE) ......................................... . 1-12
1.8.3 Error Reporting and Diagnostics .............................................. . 1-12
Cyclic Redundancy Check (CRC) ........................................... . 1-12
Loopback ................................................................ . 1-12
1.8.4 Buffer Management ......................................................... . 1-12
Ring Access by the LANCE ................................................ . 1-i5
Transmit Ring Buffer Management .......................................... . 1-15
Receive Ring Buffer Management ........................................... . 1-15
1.8.5 Lance Interface ............................................................. . 1-16
Read Sequence .......................................................... . 1-16
\Alri+o C:o.n1 10.nl".o.
ww1111.v '-'"'"1""""'''"'"" • • • • • · · · • • • · • • • · · · • • · · · • • • • · · · · · · · · · · · · · 1-16
1.8.6 LANCE OMA Transfer (Bus Master Mode) ..................................... . 1-16
Burst Mode ............................................................... . 1-16
Single Word OMA Transfers ................................................ . 1-16
1.8.7 Silo Operation .............................................................. . 1-16
Transmit ................................................................. . 1-16
Receive .................................................................. . 1-16
Memory Byte Alignment ................................................... . 1-16
1.8.8 Ethernet/IEEE 802.3 Interface ................................................ . 1-17
Serial Transmission ....................................................... . 1-17
Serial Reception .......................................................... . i-17
The LANCE Recovery and Re-initialization ................................... . 1-19
Ethernet/IEEE 802.3 Differences ............................................ . 1-19
1.9 LANCE Registers and Buffers .................................................. . 1-19
1.9.1 Address and Data Ports ..................................................... . 1-19
Register Address Port (RAP) ............................................... . 1-20
Register Data Port (ADP) .................................................. . 1-20
1.9.2 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Control and Status Register O (CSRo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Control and Status Register 1 (CSR 1 ) .......................................'. 1-22
Control and Status Register 2 (CSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Control and Status Register 3 (CSR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.9.3 Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Physical Address Register (PADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Logical Address Filter (LADRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Receive Descriptor Ring Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Transmit Descriptor Ring Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
1.9.4 Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Receive Message Descriptor O (RMDo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Receive Message Descriptor 1 (RMD 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Receive Message Descriptor 2 (RMD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . 1-26
Receive Message Descriptor 3 (RMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Transmit Message Descriptor O (TMDo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Transmit Message Descriptor 1 (TMD 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Transmit Message Descriptor 2 (TMD 2) .................-. . . . . . . . . . . . . . . . . . . . . . 1-27
Transmit Message Descriptor 3 (TMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
2. BUS INTERFACE CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Bus Bandwidth Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Bus Latency Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 LANCE OMA Cycle (Bus Master Mode)........................................... 2-2
2.4 LANCE and One CPU on the Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4.1 Bus Latency With One Other Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.5 LANCE With Multiple Master Devices on the Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.5.1 Bus Latency for Multimaster Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
No Data-chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
With Data-chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.6 LANCE in a Daisy-Chain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2. 7 LANCE With 8-bit Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.7.1 8-bit Microprocessors with 8-bit Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.7.2 8-bit Microprocessors with 16-bit Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
3. LANCE-CPU INTERFACE CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 General LANCE Interface Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1 LANCE Interface to Popular Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 68000 to LANCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2.1 68000 to LANCE Interface PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.3 Z8001 to LANCE Interface . .. .. .. .. . . . .. .. .. . .. . . . .. .. . . . .. . . . . . . . .. . . . .. . . . .. . . 3-3
3.3.1 Z8001 to LANCE Interface PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4 80186 to LANCE Interface . . . . . . . . . . .. .. . . . . . . . . . . . . .. . .. . . . . .. . . . .. .. . . . . .. . . . . 3-4
3.4.1 LANCE in a Bus Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.2 LANCE in Bus Master Mode ........................... , . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.3 186 to LANCE Interface PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.5 8086 to LANCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.5.1 8086 RQ/ GT Conversion to LANCE HOLD/HLDA PAL........................... 3-7
3.5.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
4. SOFlWARE CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Software Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.3 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.3.1 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.3.2 External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3.3 CRC Generator/Checker Logic Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3.4 Collision Detection/Retry Logic Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4 Main Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.5 Descriptor and Buffer Pitfalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.5.1 Transmit Message Descriptors, TMD 1 and TMD3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.5.2 Transmit Descriptor Ring Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.5.3 Data Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.5.4 Transmit Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5.5 Receive Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4. 7 Transmit Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.8 Receive Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.9 Status Monitoring and Error Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.9.1 MISS Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.9.2 Receiver and/or Transmitter Turnoff Due to Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.1 O Programmer Organization of the LANCE Register Information . . . . . . . . . . . . . . . . . . . . . . . 4-15
APPENDIXES
A. GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
B. 8086 PROGRAM FOR MULTI-CAST ADDRESSING AND HASH FILTER...................... B-1
C. EXTERNAL LOOPBACK TEST PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
iii
TABLES
Page
1-1 Processor Interface Requirements .............................................. . 1-6
1-2 Silo-Memory Byte Alignment .................................................. . 1-17
FIGURES
Page
1-1 LANCE Block Diagram ........................................................ . 1-1
1-2 Data Flow .................................................................... . 1-2
1-3 Control and Status Registers in LANCE ......................................... . 1-4
1-4 Initialization Block and Descriptor Rings ......................................... . 1-5
1-5 LANCE/CPU Interfacing ....................................................... . 1-8
1-6 LANCE/Processor Memory Interface ............................................ . 1-13
1-7 LANCE Memory Management .................................................. . 1-14
1-8 Typical EtherneVIEEE 802.3 Node .............................................. . 1-18
1-9 Ethernet Frame Format ........................................................ . 1-18
1-10 IEEE 802.3 MAC Frame Format ................................................ . 1-18
2-1 Bus Bandwidth Requirement ................................................... . 2-1
2-2 Block Diagram of Pre-emption in the LANCE ..................................... . 2-3
3-1 68000 to LANCE Interface ..................................................... . 3-2
3-2 Z8001 to LANCE Interface ..................................................... . 3-3
3-3 80186 to LANCE Interface ..................................................... . 3-5
3-4 8086 RG/RT, Am7990 HOLD/HLDA Conversion PAL .............................. . 3-6
3-5 AmPAL 16R4, 8086 (max. mode)/LANCE Interface Timing Diagram ................. . 3-6
4-1 Initialization/Diagnostic Flowchart ............................................... . 4-2
4-2 Main Program for the LANCE in Normal Operation ................................ . 4-5
4-3 Interrupt Service Routine ....................................................... . 4-7
4-4 Transmit Block Buffer Packing .................................................. . 4-8
4-5 Transmit Routine (TXDRIVE) to Setup Packets for Transmission .................... . 4-10
4-6 Transmit Packet Status Processing (TX-STATUS) ................................. . 4-12
4-7 Receive Packet Status Processing .............................................. . 4-14
4-8 CSR0 Status Processing ....................................................... . 4-16
4-9 CSR 0 Error Bit Processor, ERR-CSRO ........................................... . 4-17
4-10 Initialization Block Organization in 68000 Assembly Code .......................... . 4-18
4-11 Receive Descriptor Ring Entry Organization in 68000 Assembly Code ............... . 4-18
4-12 Transmit Descriptor Ring Entry Organization in 68000 Assembly Code .............. . 4-18
4-13 Initialization Block Organization in 8086 Assembly Code ........................... . 4-19
4-14 Receive Descriptor Ring Entry Organization in 8086 Assembly Code ................ . 4-19
4-15 Transmit Descriptor Ring Entry Organization in 8086 Assembly Code ............... . 4-19
4-16 Control Data Transfers Between the LANCE and CPU ............................. . 4-20
4-17 Serial Data Storage in Memory ................................................. . 4-20
iv
CHAPTER 1
OVERVIEW
The LANCE (Local Area Network Controller for Ethernet) is a As a communication controller, the LANCE manages descrip-
48-pin VLSI device designed to greatly simplify interfacing a tor rings and data buffers in memory for both transmitting and
microcomputer or minicomputer to an IEEE 802.3/ receiving data. It shares OMA access to this memory with other
Ethemet/Cheapernet Local Area Network. In addition to master bus devices such as CPUs.
transferring data packets to and from the Ethernet transceiver, In the transmitting mode, the LANCE transfers data from the
the LANCE has the ability to manage the data buffers in current buffer to a 48-byte (FIFO) register in the LANCE called
memory. Figure 1-1 is a block diagram of the LANCE. a Silo. The output of the Silo is serialized and then goes to a
This technical manual discusses the hardware and software Serial Interface Adapter (SIA), the Am7992B. Design consider-
considerations that may be useful for the user designing sys- ations for the SIA are not discussed in this manual. The output
tems around the Am7990 LANCE. It examines the LANCE of the SIA is connected to the Ethernet lines through a
interfaces with typical microprocessors to show the flexibility transceiver. A pin-for-pin compatible IEEE 802.3/
under different environments. Bus bandwidth, bus latency, and Ethemet/Cheapemet transceiver, Am7995, is available from
system performance are discus....c:ed for different architectures. AMD.
The flowcharts of software drivers, along with some guidelines, In the receiving mode, the SIA receives data from the Ethernet
are introduced for a better understanding of how the part may cable. It transfers the data to the Silo in the LANCE. The
be programmed and used in typical applications. No attempt is LANCE transfers the data from the Silo to the current buffer in
made to explore software issues relating to the upper layer local memory. Figure 1-2 is a simplified diagram of the data
protocols of the ISO model. flow.
To initialize the LANCE, it must be in the Bus Slave mode.
When CS is active, the LANCE is in the Bus Slave mode.
DAL1s:o
OMA/ MICROPROGRAM
DATA PATH
STORE
CONTROL
w
<.>
if
a:
w
I-
~
::::>
0.
u
..J
C(
LANCE/
g CPU
..J
CONTROL
BUS RX
INTERFACE
RCLK
STATION TX
RETRY SERIAL 110 Am7992A
ADDRESS TCLK
LOGIC INTERFACE SIA
DETECTION CLSN
TENA
RENA
80002061
Figure 1-1 LANCE Block Diagram
1-1
, - - - MEMORY _ _ _ _ l
I DESCRIPTOR RINGS
DATA
I
I BUFFER I CPU
I I
I I
I I
INITIALIZATION CURRENT I
I BLOCK
12 WORDS
DATA
BUFFER
L _J
I --,
I
POINTER TO
CURRENT
BUFFER SILO
I Am7992
(DESCRIPTOR 48 BYTES SIA
RING ENTRY)
I I
I POINTER TO
I
LOOK AHEAD TRANSCEIVER
I BUFFER
(DESCRIPTOR I
RING ENTRY)
I I
L LANCE _____ J ETHERNET
CABLE
06363A-1
Figure 1-2 Data Flow
1-2
The LANCE is initialized by entering configuration parameters 1.2 RESET
into the four Control and Status Registers (CSR) and into an
There are two ways to reset the LANCE: Hard Reset (RESET
Initialization Block of 12 words. CSRo contains interrupt and
input to the LANCE), and Soft Reset (by setting the stop bit in
error status flags and control bits. CSR1 and CSR2 contain the
CSRo). Reset causes the LANCE to cease operation and clear
address of the Initialization Block. CSR3 contains control bits
its internal logic.
to configure Byte Swap (BSWP), ALE Control (ACON), and
Byte Control (BCON). The Initialization Block contains pointers Control Status Registers (CSRo CSR3) contents are affected
to the descriptor rings and their length. as follows:
Buffer management is accomplished through message - CSRo is cieared. (Stop bit gets set.)
descriptors organized in ring structures in memory. Each - CSR3 is cleared.
message descriptor entry is four words long. There are sepa- - CSR1, CSR2 undefined by reset.
rate descriptor rings for transmitting and receiving. Packets to The LANCE operation may be resumed by setting the STAT bit
be transmitted are loaded into buffers by the CPU and the in CSRo after it is stopped. However, the above condition
addresses and lengths of the buffers are stored in consecutive implies that when the LANCE is stopped (Soft Reset), CSR3
entries in the Transmit Descriptor ring. Then, the ownership bit must be reprogrammed if the LANCE interface had been con-
is set in each entry indicating that the LANCE owns the buffers. figured for non-default values. If CSR3 has a non-zero value, it
The LANCE polls the first descriptor entry and when it finds must be reloaded each time that the stop bit is set.
that it owns it, it proceeds to transmit the packet.
The LANCE maintains a copy of the descriptor entry that points 1.3 BUS SLAVE OPERATION
to the current buffer. If the current buffer entry is not the final The LANCE enters the Bus Slave mode whenever CS
buffer for the packet being sent, the LANCE maintains a copy becomes active. This mode is used for accessing the four
of the descriptor ring entry for the next buffer to be transmitted Control Status Registers (CSRo, CSR1, CSR2, CSR3), and the
in the look-a-head buffer. Register Address Pointer (RAP). It takes the CPU normally two
When a Receive Descriptor Ring entry is empty, the ownership separate cycles to access CSR 0-CSR3. The first cycle selects
bit for it is set meaning that the buffer it points to is available to the CSR by writing to RAP, and the second cycle accesses the
the LANCE to store an incoming packet. After the LANCE has CSR pointed to by RAP. RAP is a latch and is not changed until
stored a packet in the buffer or filled the buffer, it resets the it is rewritten; therefore, accessing the same CSR does not
ownership bit thus giving control of the buffer to the host. It then require the register select cycle.
polls the next descriptor entry to see if the next buffer is avail- During Bus Master Mode operation, the LANCE uses the pa-
able to; additional incoming packets. rameters contained in CSR 1-CSR3. Therefore, LANCE opera-
The LANCE also enters status information into the descriptor tion must be stopped by setting the Stop bit in CSRo whenever
entries. CSR 1 -CSR3 accesses are required. The LANCE and CPU
interface can be tested by writing and then reading the Control
It is recommended that the reader refer to the LANCE Data
Status Registers (CSR0-CSR3).
Sheet for further detail such as timing.
The CPU communicates with the LANCE in a handshake se-
1.1 EARLY DESIGN STAGE TESTING quence by asserting the DAS signal as a request for Data
Transfer, and receiving the READY output from the LANCE in
As with any other peripherals, a hierarchical approach should
return as an acknowledge, (refer to the LANCE Data Sheet for
be taken to integrate the LANCE into a system for proper oper-
Bus Slave Timing and Read/Write operation). Note that there
ation. The fellowing outline shc,1i1s the order in 'llhich the vari-
are two different types of delays involved in accessing the
ous LANCE functions should be developed and tested.
CSRs. The shorter delays refer to accesses to CSRo, CSR3,
- RESET and RAP. The longer delays refer to accesses to CSR 1 and
- BUS SLAVE OPERATION CSR2. Proper operation of the LANCE in Bus Slave Mode is a
- INITIALIZATION prerequisite for the LANCE to operate in Bus Master Mode.
- BUS MASTER OPERATION
- DIAGNOSTICS
- NORMAL OPERATION
The initialization, Bus Master operation, and the diagnostic
steps are closely tied together, such that each step requires the
proper operation or arrangement of the other steps. A brief
discussion of significant points for each step follows. A detailed
description appears later in this chapter.
1-3
When BCON = 0, pins 15, 16, and 17 are defined as BMo.
1.4 INITIALIZATION PROCEDURE
BM 1, and HOLD. Pins 15 and 16 specify byte selection on the
The LANCE is initialized (configured) for a desired operation by DAL lines as whole word, upper byte, lower byte, or none. Pin
programming the CSR registers (CSR1-CSR3) and providing 17, HOLD, is asserted by LANCE whenever it requires access
the parameters required by the LANCE in the Initialization to memory.
Block. Proper initialization is a prerequisite for the LANCE op-
When BCON = 1, these pins are defined as BYTE, BUS AKO,
eration in Bus Master mode. Refer to Figure 1-3 and Figure
and BUSRQ. The BYTE line (pin 15) is used in conjunction
1-4.
with the least significant bit of the DMA address to specify byte
selection as whole word, lower output. If the LANCE is not
1.4.1 CSR PROGRAMMING
requesting the bus and it receives HDLA BU SAKO is driven
Depending upon which processor is to be interfaced to the low. If the LANCE is requesting the bus when it receives HDLA
LANCE, ACON, BCON, and BSWP in the Control Status Reg- BUSAKO will remain high. BUSRQ pin 17, will only be as-
ister 3 (CSR 3) must be programmed when initializing the serted if pin 17 is high prior to assertion when in the daisy chain
LANCE. configuration.
ACON (ALE control) defines the polarity of ALE signal when
The BSWP bit in CSR3 determines if the LANCE treats the
the LANCE is in Bus Master Mode. Multiplexed buses use this
high byte as the most significant or least significant byte when
signal (ALE) to latch the least significant part of the Address
writing into the Silo (Bus Master Mode, read operation) or when
Bus (A1s:Ao).
reading it from the Silo (Bus Master Mode, write operation).
BCON (byte control) redefines the byte mask 1/0 pins (pins 15 This function facilitates operation with different 16-bit micropro-
and 16) for different ways to handle odd address boundaries cessors. When BSWP = 1, the LANCE will swap the high and
and redefines HOLD 1/0 pin 17 to configure the LANCE as a low bytes on DMA transfers between the Silo and and bus
daisy-chain system. memory.
15 14 13 12 11 10 8 7 3 0
ERR IBABL I CERR I MISS I
MERR I RINT I TINT ! 100N I iNTR I iNEA IAXON ITXON ITDMD ISTOP I STRT I INIT CSR0
15 2 1-0
IADR 00 I CSR1
15 8 7
RES IADR I CSR2
15 3 2 1 0
RES IBSWP IACON I BCON ICSR3
06363A-2
Figure 1-3 Control and Status Registers in LANCE
1-4
31-29 28-24 23 Transmit Descriptor Ring Pointer 3 2-0
I TLEN I RES I TORA 000
31-29 28-24 23 Receive Descriptor Ring Pointer 3 2-0
I ALEN I RES I RORA 000
63 Logical Address Filter 0
LADRF
I
47 Physical Address 0
PADR
I 0 I
Mode Register
15 14 7 6 5 4 3 2 1 0
IPROMj RES I INTL I DATY I COLL I DTCR I LOOP I DTX I DRX I
Initialization Block
15 0
LADA
I TM Do
15 14 13 12 11 10 9 0
I OWN I ERR I RES IMORE I ONE I DEF I STP ENP I HADA
I
15 12 11 0
I 1111 BCNT
I
15 14 13 12 11 10 9 0
I BUFF I UFLO I RES I
LCOL I LCAR I RTRY I TOR
Transmit Message Descriptor Ring Components
15 0
I LADA
I RM Do
15 14 13 12 11 10 8 0
I OWN I ERR IFRAM I OFLO I CRC I BUFF I STP ENP I HADR
I
15-12 11 0
1111 BCNT
I
15-12 11
RES I MCNT RMD3
Receive Message Descriptor Ring Components
06363A-3
Figure 1-4 lnltiallzation Block and Descriptor Rings
1-5
Table 1-1. Processor Interface Requirements
Z8000 8086 68000 LSl-11
Dedicated Z-bus Multibus Versa bus Q-bus
buses (multiplexed) (multiplexed) (demultiplexed) (multiplexed)
Address
latch enable AS ALE* ALE ALE
polarity
Byte Byte/Word Upper Upper and Byte/Word
addressing signal Byte Strobe lower signal
of memory strobes
Even address Even address Even address Even address
Memory accesses upper accesses lower accesses upper accesses lower
organization byte; odd address byte; odd address byte; odd address byte; odd address
accesses lower accesses upper accesses lower accesses upper
byte byte byte byte
* The Am7990 Tri-states ALE; the 8086 does not.
Table 1-1 shows how to program CSR3 when interfaced to of the LANCE. The user must make sure to process all the
different processors. CSR1 and CSR2 are programmed to con- transmitted or received packets and rearrange the packets
tain a pointer to the Initialization Block. queued for transmission in the Transmit Ring before re-
initializing the LANCE. This is necessary since, upon re-
initialization, the LANCE sets its pointers to the beginning of
1.4.2 INITIALIZATION BLOCK the Transmit and Receive Rings.
This block contains the operating parameters necessary for
device operation. The Initialization Block is 12 words long in 1.5 BUS MASTER OPERATION
contiguous memory starting on a word boundary (See Figure
The LANCE must be in Bus Master mode to access the exter-
1-3). The Initialization Block contains:
nal memory. Local memory external to the LANCE is used for
• Mode of operation (Mode Register) the Initialization Block, transmit/receive rings, and
• Physical Address transmit/receive buffers. HOLD and HLDA of the LANCE both
• Logical Address Mask active indicate that the LANCE is a Bus Master. The HLDA
• Location of Transmit and Receive Descriptor Rings input to the LANCE may be directly connected to the HOLD
• Number of entries in Transmit and Receive Descriptor output from the LANCE. This is desirable in some applications.
Rings.
To guarantee that the LANCE is not switched into Slave Mode
inadvertently, CS must not be asserted when the LANCE in
1.4.3 DIAGNOSTICS Bus Master Mode (HLDA active). This is usually guaranteed by
The Mode Register in the Initialization Block is used to set up design when the LANCE and CPU share the same bus.
the LANCE for diagnostic or normal operation. There are four However, in a dual port RAM design in which the LANCE is not
user-programmable diagnostic modes. Each mode requires on the same bus with the CPU, some external logic is required
the user to change bits in the Mode Register and reinitialize the to monitor and control HOLD and HLDA before a CS is as-
LANCE. The four modes are listed as follows: serted.
1. Internal Loopback Each OMA cycle initiated by the LANCE consists of 6 T-states
2. CRC Logic Check (600 ns) plus any additional wait states (Tw) which is required
3. Collision Detection and Retry Logic for slower memories. Wait states may be added between T4
4. External Loopback. and T5 of the LANCE OMA cycle. The READY input to the
The detailed description of the diagnostic functions and flow- LANCE inserts wait states in 100 ns increments. To guarantee
charts appear in a later section of this technical manual. that no Wait State is added to the bus cycle, the READY signal
input to the LANCE must be asserted within 80 ns (max), fol-
1.4.4 NORMAL OPERATION lowing the falling edge of the ALE signal. Memory chips with
600 ns (max) cycles time and an access time of 280 ns from
Once the LANCE interface with the system is checked out both
ALE falling edge, or 355 ns from Address Valid, can be used
in Bus Master and Bus Slave Mode, and the internal logic of
without adding any Wait States to the LANCE OMA cycles.
the LANCE has been tested in diagnostic mode for both inter-
nal and external loopback test, the LANCE can be configured It is possible for one or more wait states to be added to the
for normal operation via the Initialization Block. The user nor- LANCE OMA cycle even with fast memory chips if the timing
mally initializes the LANCE once for normal operation. Any specification of the LANCE is not met. It is recommended that
change in the LANCE configuration requires the re-initialization the memory cycle sequencer be synchronized with the falling
1-6
edge of DAS and that READY be asserted within 80 ns follow- In general, the programming sequence of the chip may be
ing the falling edge of ALE in order to assure that no wait states summarized as:
are added. 1. Programming the chip's CSRs by a host device to locate an
In the Bus Master Mode, the LANCE has two types of OMA Initialization Block in memory. The byte control, byte
transfers: burst or single OMA cycle. Each burst transfer uses addressing, and address latch enable modes are defined
eight OMA cycles and transfers eight 16-bit words unless fewer here also.
than eight words remain to be transferred. Separate single 2. The chip loads itself with the information contained within
word OMA cycles are used to access the transmit/receive rings the Initialization Block.
and the Initialization Block.
3. The chip accesses the descriptor rings for packet handling.
The LANCE is equipped with some additional features, includ-
ing two transceiver control signals, DALI (DAL In) and DALO The parallel interface of the Local Area Network Controller for
(DAL Out). When in Bus Master Mode, the LANCE asserts Ethernet (LANCE) has been designed to be "friendly" or easy
DALI and DALO to enable the data transceivers for Read and to interface to a variety of popular 16-bit microprocessors.
Write operations. DALI is asserted only during the data portion These microprocessors include the following: Z8000, 8086,
of a read transfer. DALO is asserted during the write operation 68000 and LSl-11. The LANCE has a 24-bit wide linear ad-
to enable the transceiver for both address and data dress space when it is in the Bus Master Mode allowing it to
(multiplexed Address/Data), and also during the read operation OMA directly into the entire address space of the above micro-
processors.
to transfer the address (refer to the LANCE Data Sheet). It is
important to note that, during the read operation, there is a A programmable mode of operation allows byte addressing in
delay from deassertion of DALO to assertion of DALI or vice one of two ways: A Byte/Word control signal compatible with
versa. This is to prevent bus contention which would cause the 8086 and Z8000, or an Upper Data Strobe and Lower Data
electromagnetic interference (EMI). Strobe signal compatible with microprocessors such as the
68000. A programmable polarity on the Address Strobe signal
1.6 GENERAL DESCRIPTION eliminates the need for external logic. The LANCE interfaces
The Am7990 (LANCE) is designed to operate in an environ- with both multiplexed and demultiplexed data buses and
ment that includes close coupling with a local memory and a features control signals for address/data bus transceivers. See
Figure 1-5.
microprocessor (HOST). The Am7990 LANCE is programmed
by a combination of registers and data structures resident During initialization, the CPU loads the starting address of the
within the chip and in memory. There are four Control and Initialization Block into two internal control registers. The
Status Registers (CSRs) within the chip which are LANCE has four internal control and status registers (CSRo. 1 ,
programmed by the HOST device. Once enabled, the chip has 2, 3) which are used for various functions such as the loading
the ability to access memory locations to acquire additional of the Initialization Block address, different programming
operating parameters. modes and status conditions. The host processor commun-
icates with the LANCE during the initialization phase-for
The Am7990 has the ability to do independent buffer manage-
ment as well as transfer data packets to and from the Ethernet. demand transmission and periodically to read the status bits
There are three memory structures accessed by the Chip: following interrupts. All other transfers to and from the memory
are handled as OMA under microword control.
1. Initialization Block-12 words in contiguous memory start-
ing on a word boundary. It also contains the operating pa- Interrupts to the microprocessor are generated by the LANCE
rameters necessary for device operation. The Initialization upon: 1) completion of its initialization routine, 2) the reception
Block is comprised of: of a packet, 3) the transmission of a packet, 4) transmitter
timeout error, 5) a missed packet and 6) memory error.
• Mode of Operation
• Physical Address The cause of the interrupt is ascertained by reading CSR 0 . Bit
• Logical Address Mask (06) of CSRo. (INEA) enables or disables interrupts to the
• Location of Receive and Transmit Descriptor Rings microprocessor. In systems where polling is used in place of
• Number of Entries in Receive and Transmit Descriptor interrupts, bit (07) of CSRo (INTR) indicates an interrupt condi-
Rings tion.
2. Receive and Transmit Descriptor Rings-Two ring The basic operation of the LANCE consists of two, distinct
structures, one each for incoming and outgoing packets. modes: transmit and receive. In the transmit mode, the LANCE
Each entry in the rings is 4 words long and each entry must chip directly accesses data (in a transmit buffer) in memory. It
start on a quadword boundary. The Descriptor Rings are prefaces the data with a preamble, sync pattern, and calc-
comprised of: ulates and appends a 32-bit CRC. This packet is then ready for
transmission to the Am7992A SIA. On transmission, the first
• The address of a data buffer. byte of data loads into the 48-byte FIFO. The LANCE then
• The length of that data buffer. begins to transmit preamble while simultaneously loading the
• Status information associated with the buffer. rest of the packet into FIFO for transmission.
3. Data Buffers-Contiguous portions of memory reserved for
packet buffering. Data buffers may begin on arbitrary byte
boundaries.
J
1-7
a. Multiplexed Bus
DATA AND ADDRESS
ADDRESS BITS
BITS 0-15 16-23 CONTROL
LANCE
DAL.o·DAL 15
1--------------t ALE
..._---~-+IADR
ALE DECODER
DF000390
b. Demultiplexed Bus
DATA BITS ADDRESS BITS
0-15 0-23
DATA/ ADDRESS
BITS 0-15
LANCE
LATCH
~---.
•-"-----9 ALE
,,.__ ___. ADDRESS
'- .-----1 BITS 16-23
DF000140
Figure 1-5 LANCE/CPU Interfacing
1-8
In the receive mode, packets are sent via the SIA to the BYTE, BUSAKO
LANCE. The packets are loaded into the 48-byte FIFO for
If CSR3 (00) BCON = 1,
preparation of automatic downloading into buffer memory. A
1/0 Pin 15 = BYTE (Output 3-state)
CRC is calculated and compared with the CRC appended to
1/0 Pin 16 = BUSAKO(Output)
the data packet. If the calculated CRC checksum doesn't agree
with the packet CRC, an error bit is set. Byte selection may also be done using the
BYTE line and DALoo line, latched during the
address portion of the bus cycle. The LANCE
1.7 PIN DESCRIPTION drives BYTE only as a Bus Master and ignores it
DALoo- Data/Address Lines (Input/Output 3-State) when a Bus Slave selection is done (similar to
DAL15 The time multiplexed Address/Data bus. During BMo, BM1.
the address portion of a memory transfer,
Byte selection is done as outlined in the follow-
DALoo-DAL 15 contains the lower 16 bits of the
ing table.
memory address. The upper 8 bits of address
are coniained in A15-A23. BYTE DALoo
During the data portion of a memory transfer, LOW LOW Whole Word
DALoo-DAL15 contains the read or write data, LOW HIGH Illegal Condition
depending on the type of transfer. HIGH LOW Lower Byte
The LANCE drives these lines as a Bus Master HIGH HIGH Upper Byte
and as a Bus Slave. BU SAKO is a bus request daisy chain output. If
High Order Address Bus (Output 3=State} the chip is not requesting the bus and it received
Additional address bits that access a 24-bit ad- HLDA, BUSAKO will be driven low. If the
dress space. These lines are driven as a Bus LANCE is requesting the bus when it received
Master only. HLDA, BUSAKO will remain high.
READ (Input/Output 3-State)
Indicated the type of operation to be performed Byte Swapping
in the current bus cycle. This signal is an output In an effort to be compatible with the variety of 16-bit micropro-
when the LANCE is a Bus Master. cessors available to the designer, the LANCE may be
High - Data is taken off the DAL by the programmed to swap the position of the upper and lower order
LANCE. bytes on data involved in transfers with the internal FIFO.
Low - Data is placed on the DAL by the Byte swapping is done when BSWP = 1. The most significant
LANCE. byte of the word in this case will appear on DAL lines 7-0 and
The signal is an input when the LANCE is a Bus the least significant byte on DAL lines 15-8.
Slave. When BYTE = H (indicating a byte transfer) the table indicates
High - Data is placed on the DAL by the on which part of the 16-bit data bus the actual data will appear.
LANCE.
Whenever the byte swap is activated, the only data that is
Low - Data is taken off the DAL by the swapped is data traveling to and from the Silo.
LANCE.
BMo/ 1/0 pins 15 and 16 are programmable through
BYTE bit (00) of CSR3 mOue coi•S
BSWP = 0 BSWP = 1
Signal Line and BCON = 1 and BCON = 1
BMo, BM1
BYTE= Land Word Word
If CSR3 (00) BCON = 0, DALoo = L
1/0 Pin 15 = BMo (Output 3-state)
1/0 Pin 16 = BM1 (Output 3-state) BYTE= Land Illegal Illegal
DALoo = H
BM 0 , BM 1 (Byte Mask). This indicates the
byte(s) on the DAL are to be read or written BYTE= Hand Upper Byte Lower Byte
during this bus transaction. The LANCE/ drives DAloo = H
these lines only as a Bus Master. It ignores the BYTE= Hand Lower Byte Upper Byte
Byte Mask lines when it is a Bus Slave and DAloo = L
assumes word transfers.
Byte selection using Byte Mask is done as Chip Select {Input)
described by the following table. Indicates, when asserted, that the LANCE is the
slave device of the data transfer. CS must be
BM1 BMo valid throughout the data portion of the bus
LOW LOW Whole Word cycle. CS must not be asserted when HLDA is
LOW HIGH Upper Byte LOW.
HIGH LOW Lower Byte
HIGH HIGH None
1-9
ADR Register Address Port Select (Input) HLDA Bus Hold Acknowledge (Input)
When LANCE is slave, ADA indicates which of A response to HOLD. When HLDA is low in
the two register ports is selected. ADA LOW response to the chip's assertion of HOLD, the
selects register data port; ADA HIGH selects chip is the Bus Master. HLDA deasserts upon
register address port, ADA must be valid the deassertion of HOLD.
throughout the data portion of the bus cycle and INTR Interrupt (Output Open Drain)
is only used by the LANCE when CS is low. An attention signal that indicates, when active,
ALE/AS Address Latch Enable (Output 3-State) that one or more of the following CSRo status
Used to demultiplex the DAL lines and define flags is set: BABL, MERA, MISS, RINT, TINT or
the address portion of the bus cycle. This 1/0 pin IDON. INTR is enables by bit 06 of CSRo (INEA
is programmable through bit (01) of CSR3. = 1). INTR remains asserted until the source of
As ALE (CSR3 (01 ), ACON = 0), the signal Interrupt is removed.
transitions from a HIGH to a LOW during the RX Receive (Input)
address portion of the transfer and remains low Receive Input Bit Stream.
during the data portion. ALE can be used by a TX Transmit Enable (Output)
slave device to control a latch on the bus ad- Transmit Output Bit Stream.
dress lines. When ALE is high the latch is open
and when ALE goes low the latch is closed. TENA Transmit (Output)
Transmit Output Bit Stream enable. When as-
As AS (CSR3 (01), ACON = 1), the signal serted, it enables the external transmit output.
pulses LOW during the address portion of the
bus transaction. The low to high transition of AS RCLK Receive Clock (Input)
can be used by a slave device to strobe the A 10MHz square wave synchronized to the
address into a register. Receive data and only active while receiving an
Input Bit Stream.
The LANCE drives the ALE/AS line only as a
Bus Master. CLSN Collision (Input)
A logical input that indicates that a collision is
DAS Data Strobe (Input/Output 3-State) occurring on the channel.
Defines the data portion of the bus transaction.
DAS is high during the address portion of a bus RENA Receive Enable (Input)
transaction and low during the data portion. The A logical input that indicates the presence of
low to high transition can be used by a slave carrier on the channel.
device to strobe bus data into a register. DAS is TCLK Transmit Clock (Input)
driven only as a Bus Master. 1OM Hz clock.
DALO Data/Address Line Out (Output 3-State) READY (Input/Output Open Drain)
An external bus transceiver control line. DALO When the LANCE is a Bus Master, READY is an
is asserted when the LANCE drives the DAL asynchronous acknowledgement from the bus
lines. DALO is low only during the address por- memory that it will accept data in a WRITE cycle
tion if the transfer is a READ. It is low for the or that it has put data on the DAL lines in a
entire transfer if the transfer is a WRITE. DALO READ cycle.
is driven only when LANCE is a Bus Master. As a Bus Slave, the LANCE asserts READY
DALI Data/Address Line In (Output 3-State) when it has put data on the DAL lines during a
An external bus transceiver control line. DALI is READ cycle or is about to take data off the DAL
asserted when the LANCE reads from the DAL lines during a write cycle. READY is a response
lines. It is low during the data portion of a READ to DAS and will return HIGH after DAS has gone
transfer, and remain high for the entire transfer if HIGH. READY is an input when the LANCE is a
it is a WRITE. DALI is driven only when LANCE Bus Master and an output when the LANCE is a
is a Bus Master. Bus Slave.
HOLD Bus Hold Request (Output Open Drain) RESET (Input)
BUSRQ Asserted by the LANCE when it requires access Bus Reset Signal. Causes the LANCE to cease
to memory. HOLD is held LOW for the entire operation, clears its internal logic, and enter an
ensuing bus transaction. The function of this pin idle state. The stop bit in CSRo is also set.
is programmed through bit (00) of CSR 3 Bit (OO) A 3.3K pull-up resistor should be used at the
of CSR3 is cleared when RESET is asserted. RESET pin of the LANCE.
When CSR3 (00) BCON = 0
Vee Power supply pin +5 volts ±5%.
1/0 pin 17 = HOLD(Output Open Drain) A 0.1 µf and a 1Oµf decoupling capacitors
When CSR3 (OO) BCON = 1 should be used for Vee to Vss-
1/0 pin 17 = BUSRQ(Output Open Drain) Vss Ground Pins 1 and 24 should be connected
together externally, as close to the chip as
BUSRQ will be asserted only if 1/0 pin 17 is high
prior to assertion. possible.
1-10
1.8 FUNCTIONAL DESCRIPTION rejected and the Silo pointer is reset if the collision occurs
within six byte times (4.8us) because of an address mismatch.
1.8.1 ADDRESSING
The packet is rejected as a runt packet if the collision occurs
Packets can be received using 3 different destination within 64 byte times (51.2us). If a collision occurs after 64 byte
addressing schemes: physical, logical, and promiscuous. times (late collision), a truncated packet is written to the
The first type is a full comparison of the 48-bit destination memory buffer with the CRC error bit usually set in the Status
address in the packet with the node address programmed into Word of the receive ring. Late collision error is not recognized
the LANCE during an initialization cycle. in receive mode.
There are two types of logical address. One is group type mask
where the 48-bit address in the packet is put through a hash COLLISION DURING TRANSMISSION
filter in order to map the 48-bit physical addresses into 1 of 64 When a transmission is terminated due to the assertion of
logical groups. If any of these 64 groups have been CLSN (a collision within the first 64 byte times of the packet),
preselected as the logical address, then the 48-bit address is the LANCE retries it 15 times. The LANCE does not re-read the
stored in main memory. At this time, a look up is performed descriptor entries from the TX ring upon each collision. The
comparing the 48-bit incoming address with the prestored 48- descriptor entries for the current buffer are internally saved.
bit logical address. The mode can be useful if sending packets The scheduling of the retransmissions is determined by a con-
to all of a particular type of device simultaneously (i.e., send a trolled randomized process called "truncated binary exponen-
packet to all file servers or all printer servers). Additional details tial backoff". Upon the completion of the COLLISION JAM
on logical addressing can be found in the INITIALIZATION interval, the LANCE calculates a delay before retransmitting.
section under "Logical Address Filter". The second logical ad- The delay is an integral multiple of the slot time. The slot time is
dress is a broadcast address where ali nodes on the network 64 by1e times (512 bit times). The numbei of slot times to delay
receive the packet. before the nth retransmission is chosen as a uniformly dis-
tributed random integer in the range of:
The last receive mode of operation is the so-called
"promiscuous mode" in which a node will accept all packets on O .-;;: r < 2k
the coax regardless of their destination address. where: k = minimum (n, 10)
For example, if this is the third retry,
1.8.2 COLLISION DETECTION AND
n=3
IMPLEMENTATION
k = min(3,10) = 3.
The Ethernet CSMA/CD network access algorithm is imple- 23 = 8
mented completely within the LANCE. in addition to iistening
for a clear coax before transmitting, Ethernet handles collisions Therefore, r is a random number from zero to eight.
in a predetermined way. Should two transmitters attempt to If all 16 attempts fail, the LANCE sets the RTRY bit in the
seize the coax at the same time, they will collide and the data current Transmit Message Descriptor 3 (TMD3) in memory,
on the coax wili be garbled. The transmitting nodes listen while gives up ownership (sets the own bit to zero) for this packet,
they transmit, detect the collision, then continue to transmit for and processes the next packet in transmit ring for transmis-
a predetermined length of time to "jam" the network and sion. If a late collision occurs, the LANCE does not transmit the
ensure that all nodes have recognized the collision. The same packet again. It terminates the transmission, notes the
transmitting nodes then delay a random amount of time LCOL error in TMD3, and transmits the next packet in the ring.
according to the Ethernet "truncated binary backoff" algorithm
in order that the coWding nodes don't try to iepeatedly access COLLISION - MICROCODE iNTERACTiON
the network at the same time. Up to 16 attempts to access the The microprogram uses the time provided by Collision Jam,
network are made by the LANCE before reporting back an lnterpacket Delay, and the backoff interval to restore the ad-
error due to excessive collisions. dress and byte counts internally and to start loading the Silo in
anticipation of retransmission. To utilize the channel properly, it
COLLISION JAM is important that the LANCE be ready to transmit when the
Collisions are detected by monitoring the CLSN 1/0 pin. If backoff interval elapses.
CLSN becomes asserted during a frame transmission, TENA
will remain asserted for at least 32 additional bit times TIME DOMAIN REFLECTOMETRV
(including C:SM synchronization). This additional transmission
after collision is called COLLISION JAM. If collision occurs The LANCE contains a time domain ref!ectometry counter
during the transmission of the preamble, the LANCE continues (TOR). The TOR counter is ten bits wide. It counts at a 10MHz
to send the preamble followed by a JAM pattern. If collision rate. It is cleared by the microprogram and counts upon the
occurs after the preamble, the LANCE sends the JAM pattern assertion of RENA during transmission. Counting stops if
following the transmission of the current byte. The JAM pattern CLSN becomes true or if RENA goes inactive. The counter
is any pattern except the CRC bytes. does not wrap around. When the counter reaches a value of all
ones, that value is held until it is cleared. The value in the TOR
COLLISION DURING RECEPTION is written into memory following the transmission of the packet.
If CLSN becomes asserted during the reception of a packet, TOR is used to determine the location of suspected cable
this reception is immediately terminated. The action taken faults.
depends on the timing of collision detection. The packet is
1-11
COLLISION PAIR TEST (HEARTBEAT, SQE) byte boundaries and, when the incoming bit stream stops,
An open in the cable causes a reflection which the coaxial the last sample determines the state of the CRC error.
cable transceiver detects as a collision. A short in the cable Framing error (FRAM) is not reported if there is no CRC
causes RENA not to become active or to drop out after becom- error.
ing active. During the lnterpacket Delay following the negation 3. LOOPBACK - Mode bit 2 (LOOP) = 1, Mode bit 3
of TENA, the CLSN input is asserted (as a result of collision (DTRC) = 0. The LANCE generates and appends the CRC
becoming active) by some transceivers as a self-test called value to the outgoing bit stream as in transmission but does
Heartbeat or SOE (Signal Quality Error) test. If the CLSN input not perform the CRC check of the incoming bit stream.
is not asserted within 2.0us following the completion of
4. LOOPBACK - Mode bit 2 (LOOP) = 1, Mode bit 3
transmission (after TENA goes low), then the LANCE will set
(DTRC) = 1. The LANCE performs the CRC check on the
the CERA bit in CSRo. CERA error does not cause an interrupt
incoming bit stream as in reception but does not generate or
to occur (INTR = 0).
append the CRC value to the outgoing bit stream during
transmission.
1.8.3 ERROR REPORTING AND
DIAGNOSTICS LOOPBACK
Extensive error reporting is provided by the LANCE. Error con- The LANCE normally operates as a half-duplex device.
ditions reported relate to either the network as a whole or to However, to provide an on-line operational test of the LANCE,
data packets. Network-related errors are recorded as flags in a pseudo-full duplex mode is provided. In this mode, simulta-
the CSRs and are examined by the CPU following interrupt. neous transmission and reception of a loopback packet are
Packet-related errors are written into descriptor entries corres- enabled with the following constraints:
ponding to the packet.
1. The packet length must be from eight to 32 bytes long,
System-related errors include: exclusive of the CRC bits.
1. Babbling Transmitter - Transmitter attempting to transmit
2. Serial transmission does not begin until the Silo contains
more than 1518 data bytes in one packet.
the entire output packet.
2. Collision - Collision detection circuitry non-functional.
3. Moving the input packet from the Silo to the memory does
3. Missed Packet - Insufficient buffer space. not begin until the serial input bit stream terminates.
4. Memory Timeout - Memory response failure 4. CRC may be either generated and appended to the output
Packet-related errors include: serial bit stream or may be checked on the input serial bit
1. CRC - Invalid data stream but not both in the same transaction.
2. Framing - Packet did not end on byte boundary 5. In internal loopback, the packets should be addressed to
the node itself. If not, the chip must be re-initialized with
3. Overflow/Underflow - Abnormal latency in servicing a
non-matching source and destination addresses after each
OMA request
test.
4. Buffer - Insufficient buffer space available
6. In external loopback, multicast addressing can be used only
The LANCE performs several diagnostic routines that enhance when DTCR = 1 is in the mode register. In this case, the
the reliability and integrity of the system. These include a CRC user needs to append the CRC bytes.
logic check and two loopback modes (internal/external). Errors
7. In external loopback, the Silo pointers sometimes get
may be introduced into the system to check error detection
misaligned with heavy traffic on the network. It is recom-
logic. A Time Domain Reflectometer is incorporated into the
mended that the user repeats the test several times after
LANCE to aid system designers to locate faults in the Ethernet
the first time it fails. This can help isolate the failure to Silo
cable. Shorts and opens manifest themselves in reflections
pointer misalignment or other causes. For detail External
that are sensed by the TOR.
Loopback Test Procedure, please refer to Appendix C.
CYCLIC REDUNDANCY CHECK (CRC) Loopback is controlled by the INTL, DTCR, and LOOP (bits 2,
The LANCE utilizes the 32 bit CRC function used in the 3,and 6) of the MODE register.
Autodin-11 network. Refer to the Ethernet specification (Section
6.2.4 Frame Check Sequence Field and Appendix C, CRC 1.8.4 BUFFER MANAGEMENT
Implementation) for more detail. The LANCE requirements for A key feature of the LANCE and its on-board OMA channel is
the CRC logic are: the flexibility and speed of communication between the LANCE
1. TRANSMISSION - Mode bit 2 (LOOP) = 0, Mode bit 3 and the host microprocessor through common memory loca-
(DTCR) = 0. The LANCE calculates the CRC from the first tions. The basic organization of the buffer management is a
bit following the Start bit to the last bit of the data field. The circular queue of tasks in memory called descriptor rings. Refer
CRC value inverted is appended to the transmission in one to Figure 1-6 and Figure 1-7.
unbroken bit stream. The transmit and receive operations are described by separate
2. RECEPTION - Mode bit 2 (LOOP) = 0. The LANCE per- descriptor rings. Up to 128 tasks may be queued on a descrip-
forms a check on the input bit stream from the first bit follow- tor ring awaiting execution by the LANCE. Each entry in a
ing the Start bit to the last bit in the frame. The LANCE descriptor ring contains a pointer to a data buffer and an entry
continually samples the state of the CRC check on framed for the length of the buffer.
1-12
~///&@'.&/~MODE OF OPERATION
PHYSiCAL ADDRESS
LOGICAL ADDRESS FILTER INITIALIZATION
BLOCK
START ADDRESS OF RECEIVER DESCRIPTOR RING
TRANSMIT DESCRIPTOR FOR 1ST DATA BUFFER
TRANSMIT DESCRIPTOR FOR 2ND DATA BUFFER
TRANSMIT DESCRIPTOR FOR 3RD DATA BUFFER
•
•
•
RECEIVER DESCRIPTOR FOR 2ND DATA BUFFER
RECEIVER DESCRIPTOR FOR 3RD DATA BUFFER
•
•
•
TRANSMIT DATA BUFFER #2
TRANSMIT
.
TRANSMIT DATA BUFFER #3 DATA
BUFFERS
TRANSMIT DATA BUFFER #N
RECEIVER DATA BUFFER #1
RECEIVER DATA BUFFER #2
RECEIVER
RECEIVER DATA BUFFER #3 DATA
BUFFERS
RECEIVER DATA BUFFER #N
DF000130
Figure 1-6 LANCE/Processor Memory Interface
1-13
LANCE CSR REGISTERS RECEIVE DESCRIPTOR RINGS RECEIVE BUFFER
~
__jPOINTER TO INllTIALIZATION DATA
IL BLOCK PACKET
ADDRESS OF RECEIVE BUFFER 1
1
~~~ BUFFER 1 STATUS
~
m BUFFER 1 BYTE COUNT
BUFFER 1 MESSAGE COUNT DATA
PACKET
~ 2 2
vY1 2
~~~~-2~~~--t
INITIALIZATION
BLOCK
L.._ MODE OF OPERATION
VY"J 2
~/1~~----=-------t
...
PHYSICAL ADDRESS ~/·~------·-------1
LOGICAL ADDRESS FILTER
~~
~..jY...,-1 NN t - - - _ . . -. DATA
~P_o_1_NT_E_R_T_o_RE_c_E_1v_E_R1_N_G_ _---l~~A------:------~J
PACKET
N
NUMBER OF RECEIVE ENTRIES (N) ~ .,,,
POINTER TO TRANSMIT RING ~ TRANSMIT DESCRIPTOR RINGS TRANSMIT BUFFER
NUMBER OF TRANSMIT ENTRIES (M) r/ ..,..~
""· ' DATA
~ ADDRESS OF TRANSMIT BUFFER 1 PACKET
~ BUFFER 1 STATUS
1
V~ BUFFER 1 BYTE COUNT
~ BUFFER 1 ERROR STATUS ~ p~~~T
~ : 2
~ :
~ :
~ ~
:
t---_ -......-.--.
I ---... DATA
~
PACKET
M
05726A-15
Figure 1-7 LANCE Memory Management
1-14
Data buffers can be chained to handle a packet that is longer When the transmit buffers are not data-chained (current
than the buffer. The LANCE searches the descriptor rings in a descriptor's ENP = 1), the LANCE does not perform any
lookahead operation to determine the next empty buffer when lookahead operation. It transmits the current buffer and
chaining is needed or when back-to-back packets are being updates the status TMD 1 (and TMD3 it an error occurred) and
received. As each buffer is tilled, an OWN bit in the descriptor then clears the OWN bit in TMD1. The LANCE immediately
ring entry is reset, allowing the host processor to process the checks the next descriptor in the ring to see it another packet is
data in the buffer. ready to be sent. If it is ready, the LANCE proceeds to read the
buffer address and byte count and to transmit the packet. If no
RING ACCESS BY THE LANCE packet is ready, it resumes polling the ring every 1.6ms.
After the LANCE is initialized and started, the CPU and the After each complete packet has been transmitted from the Silo
LANCE communicate via transmit and receive rings (in to the cable, the LANCE updates the status in TMD1 (and
memory) for packet transmission and reception. The LANCE TMD 3 if an error occurred). Then it releases the last buffer of
contains eight 16-bit registers. The first four registers store the the packet to the CPU. It then immediately polls the transmit
four entries in the descriptor that points to the current buffer. descriptor ring for another packet to send. This guarantees the
The other four registers store the same information for the back-to-back transmission of packets when packets are ready
descriptor that points to the next buffer to be processed (the to transmit.
lookahead buffer). Refer to Figure 1-2.
RECEIVE RING BUFFER MANAGEMENT
TRANSMIT RING BUFFER MANAGEMENT When the receiver is enabled, the LANCE polls the first receive
After the LANCE has been initialized, whenever the Ethernet is ring entry once every 1.6 ms for buffer ownership so that it will
inactive, the LANCE automatically polls the first transmit ring be ieady for the nexi incoming packet. After the LANCE owns a
entry in memory. The polling occurs every 1.6ms and consists buffer, it reads the remainder of the buffer address (from
of reading the status word (TMD 1) of the transmit ring entry RMDo) and the byte count (from RMD2) into the current buffer
until it finds the OWN bit and STP bit set to one. The OWN bit in the LANCE. After the LANCE has filled the first buffer with
set to one in the transmit ring indicates a buffer ready to be data from a received packet, it polls the next receive descriptor
transmitted. The STP bit indicates that this is the start of a ring entry for the next buffer to fill.
packet.
When a packet arrives from the cable, and the LANCE does
When the LANCE finds that a buffer is to be transmitted, it not own any buffer, it polls the receive ring entry once for the
transfers the low order bits of the buffer address from TMDo buffer. If it does not get the buffer, it sets the MISS error bit in
and byte count from TMD2 into the current buffer pointer in CSRo and does not poll the receive ring entry again until the
LANCE. Each of these memory reads is done with a separate packet ends. (In the previous revision, Rev.B, the LANCE
arbitration cycle for each transfer. The high order bits of the polled the entry every few microseconds until it either received
address are in TMD1 which have already been transferred. the buffer or the Silo overflowed.)
If the packet is larger than the buffer, the buffers are data- Assuming that the LANCE owns a buffer when a packet arrives
chained and the ENP (end of the packet) is zero in all of the from the cable, the LANCE does one lookahead operation in
buffers except the buffer containing the end of the packet. If between periods of data transfer from the Silo. The LANCE
ENP equals zero for the buffer being transmitted, the LANCE needs to have a buffer ready in case the current buffer needs
does one lookahead for the next buffer. The lookahead is done data-chaining. The lookahead operation consists of one single
in between data transfers to or from the Silo. It consists of one word OMA read (RMD 1) to find out if it owns the buffer and two
single word OMA read (TMD1) to find out if it owns the buffer more reads, (RMDo and RMD2} if it does 0~11n it.
and two more reads, (TMDo and TMD2) if it does own it.
Whether the LANCE owns the next buffer or not, it will transfer
If LANCE does own the next buffer, it transfers the address and data from the Silo to the current buffer in burst mode (eight
byte count of this buffer into the lookahead buffer in the words for each OMA arbitration cycle). If the packet being
LANCE. After the LANCE completes transferring the current received requires data-chaining and the LANCE does not own
buffer into the Silo, it dears the OWN bit for this buffer and the next buffer, the LANCE updates the current buffer status by
immediately starts loading the Silo from the next buffer. setting the BUFF error bit.
If the LANCE finds during the lookahead that it does not own If the LANCE does own the next buffer and needs data-
the next transmit Descriptor Table Entry (DTE}, it will transmit chaining, when the first buffer is full it releases it by clearing the
the current buffer and update the status of the current ring OWN bit. It then starts filling the next buffer. In between data
entry by setting the BUFF bit in TMD3. BUFF error causes the transfers from the Silo, it does one lookahead operation for
transmit section of the LANCE to turn off (CSRo, TXON = 0). ownership of the next buffer to be ready for more data-chaining
The chip has to be re-initialized to turn transmitter on. if needed.
While transmitting, if a RTRY or LCOL (late collision) occurs, After each complete packet has been received and transferred
the LANCE stops transmitting the packet. It clears the OWN bit from the Silo to the buffers, the LANCE updates the status in
in TMD 1 and sets the TINT bit in CSRo causing an interrupt if RMD 1 (and RMD 3 if an error occurred). Then it releases the
INEA = 1 (interrupts enabled). The LANCE does not transmit last buffer of the packet to the CPU.
the remainder of the buffers in this packet. Instead, it clears the
own bit and sets the TINT bit in each Descriptor Table Entry it
polls until it finds a buffer with both the STP bit and OWN bit set
indicating the start of the next packet to send.
1-15
1.8.5 LANCE INTERFACE BURST MODE
CSR bits such as ACON, BCON, and BSWP are used for pro- Burst mode is used for the transfer of packets between the Silo
gramming the pin functions used for different interfacing and processor memory. Each burst transfer is eight words long
schemes. For example, ACON is used to program the polarity and is done in one DMA arbitration cycle. After the LANCE
of the Address Strobe signal ALE/AS. receives the bus acknowledge (HLDA = low) signal, it does
eight word transfers using eight OMA cycles (600 ns per cycle
BCON is the byte control bit that redefines the BYTE MASK 1/0
minimum) before it releases the bus request signal (HOLD =
pins to handle odd address boundaries and redefines the
low).
HOLD 1/0 pin for daisy-chain operation when BCON = 1. In
addressing word organized, byte addressable memories Burst transfers are always eight word transfers unless the buf-
(BCON = 1), the BYTE signal is decoded along with the least fer in memory starts on an odd byte boundary or there are
significant address bit to determine odd or even (upper or lower fewer than eight words remaining to be transferred. If the buffer
byte) byte address. starts on an odd address, one byte and seven words are trans-
ferred on the first burst transfer. If fewer than eight words
When BCON = 1 in a daisy-chain operation, the BM1 pin is
remain to be transferred at the end of a packet, the burst
used as BUSAKQthe HOLD pin is used as BUSRQ and the
transfer transfers as many full words as remain plus a single
pin HLDA is used. When a OMA controller is used for arbitra-
byte (if any) as the last transfer in the burst.
tion, only the HOLD and HLDA pins are used.
When BCON = 0, the BYTE MASK pins 15 and 16 (BMo and SINGLE WORD OMA TRANSFERS
BM 1) are used to specify byte selection on the DAL lines as The LANCE initiates single word OMA transfers to access the
whole word, upper byte, lower byte, or none. Transmit Descriptor Ring, Receive Descriptor Ring, and In-
All data transfers from the LANCE in the Bus Master mode are itialization Block. The LANCE does not initiate any burst trans-
timed by ALE, DAS, and READY . The automatic adjustment fers when it owns the descriptor and is accessing the
of the LANCE cycle by the READY signal allows synchroniza- descriptor entries (an average of 3 to 4 separate OMA cycles
tion with variable cycle time memory due either to memory are required for a multi-buffer packet) or when it is reading the
refresh or to dual port access. Bus cycles are a minimum of Initialization Block.
600ns duration and can be increased in 1OOns increments.
1.8.7 SILO OPERATION
READ SEQUENCE (Master Mode) The Silo provides temporary buffer storage for data being
The read memory cycle is started by placing valid addresses transferred between the parallel bus 1/0 pins and the serial bus
on DALoo-DAL1 5 and A15-A23. The BYTE MASK signals are 1/0 pins in the LANCE. The capacity of the Silo is 48 bytes. It is
asserted to indicate a word, upper byte, or lower byte memory a first in first out (FIFO) buffer.
reference. READ indicates the type of cycle. ALE or AS are
pulsed and the trailing edge of either can be used to latch TRANSMIT
addresses. DALoo-DAL15 go into a 3-state mode and DAS Data is loaded into the Silo from memory under internal micro-
falls low to signal the beginning of the memory access. The program control. The Silo must have more than eight words (16
memory responds by placing READY low to indicate that the bytes) empty before the LANCE requests the OMA bus (by
DAL lines have valid data. The LANCE then latches memory asserting HOLD). The LANCE starts sending the preamble to
data on the rising edge of DAS which in turn ends the memory the cable (providing the line is idle) as soon as the first byte is
cycle and READY returns to high. loaded into the Silo from memory. If a collision is detected
Data transfers between the bus transceivers and the LANCE causing the transmitter to back off, loading the Silo continues
are controlled by the DALI and DALO lines. DALI diverts data until it contains 32 bytes ready for transmission. Reception has
toward the LANCE. DALO diverts data or addresses away priority over transmission during the time that the transmitter is
from the LANCE. During a read cycle, DALO goes inactive backing off.
before DALI becomes active to avoid "spiking" the bus
transceivers. RECEIVE
Data from the cable is loaded into the Silo through the serial
WRITE SEQUENCE (Master Mode) input shift register during reception. Data is transferred from
The write to memory cycle is similar to the read cycle except the Silo into memory under internal microprogram control. The
that the DAL lines change from containing addresses to LANCE waits until the Silo has at least eight words (16 bytes)
containing data after ALE or AS goes inactive. After data is of data before initiating a OMA burst transfer. Neither the
valid on the bus, DAS goes active. Data to memory is held valid preamble nor the sync is loaded into the Silo during reception.
for some time after DAS goes inactive.
MEMORY BYTE ALIGNMENT
1.8.6 LANCE OMA TRANSFER Memory buffers begin and end on arbitrary byte boundaries.
(Bus Master Mode) Parallel data is byte-aligned between the Silo and DAL lines
(DALo-DAL15). Byte alignment can be reversed by setting the
The LANCE has two types of OMA transfers: Burst Mode and
Byte Swap (BSWP) BIT in CSR 3. Byte Swap (BSWP = 1) is
Single Word transfers.
done only on transfers between the Silo and memory. Refer to
Table 1-2.
1-16
Table 1-2. Silo - Memory Byte Alignment 7. CRC: Four byte cyclic redundancy check code supplied by
LANCE. It is an inverted 32 bit polynomial calculated from
Word/byte Silo the address, type field, and data field. It is not transmitted if
in Memory BSWP Byte DAL Pins the transmission of the data field is truncated for any rea-
Word from 0 n 0-7 son, CLSN becomes asserted {collision detected), or
even memory 0 n + 1 8- 15 MODE <3> DTCR = 1 in a normal or loopback transmis-
address 1 n 8- 15 sion mode.
1 n + 1 0-7 The format for the IEEE 802.3 MAC Frame is shown in Figure
Byte from n
v n
,.. - I...
V
1-10. It is almost identical to the Ethernet format except for the
even memory
address
1
lT l n 8- 15
j labeling and a pad preceding the CRC. The preamble is
shorter and the sync is longer but the code is identical.
Transmission is indicated at the 1/0 pin by the assertion of
1
Byte from 0 n 8- 15 i
odd memory
address
1
In 0-7
j TENA with the first bit of the preamble. TENA is negated after
the last transmitted bit.
Word to
even memory
address
0
1 tI n
n + 1
0-7
8- 15
1
j
The LANCE starts transmitting the preamble when all of the
following conditions are met:
1. There is at least one byte of data to be transmitted in the
Byte to 0 n I
0-7 lI Silo.
even memory
1 address I
i 0
1
x
n
I
I
8 - 15
8- 15
I
I
2. No carrier detected. Both RENA and CLSN are inactive.
3. The interpacket delay has elapsed.
I 1 x I 0-7 I 4. If a retransmission, the backoff interval has elapsed.
Byte to 0 x 0-7 l
odd memory 0 l n I 8 - 15 I The lnterpacket Gap Time (IPG) for back to back transmission
is 9.6 to 10.6 microseconds including synchronization. The
l
address 1 x 8 - 15
I 1
l n 0-7
interpacket delay interval begins immediately after the nega-
J tion of the RENA signal. During the first 4.1 us of the IPG,
RENA is masked internally.
When the LANCE is waiting for the interpacket deiay to elapse,
1.8.8 ETHERNET/IEEE 802.3 INTERFACE it begins transmission immediately after the interpacket delay
The Ethernet {or IEEE 802.3 standard) is the data link and interval, independent of the state of RENA. However, RENA
physical level in the communication system. The LANCE per- must be asserted during the time that TENA is high. Otherwise,
forms the encapsulationidecapsulation function of the data iink the LCAR (loss of carrier) bit is set in TMD3 after the packet
layer and also interfaces the Ethernet through a Serial Inter- has been transmitted.
face Adapter (SIA) (Am7992) and a transceiver (Am7995).
A typical EtherneUIEEE802.3 node is shown in Figure 1-8. This SERIAL RECEPTION
figure also shows a Cheapernet for comparison. Cheapernet Serial reception consists of receiving an unbroken bit stream
costs less because it does not require a drop cable to the on the RX 1/0 pin of the LANCE. The Destination Address and
transceiver. The transceiver is a part of the DTE. The bulky data are framed into bytes and enter the Silo. The Source
Ethernet coaxial cable and tap connection is replaced by Rg58 Address and Type field are part of the data which are transpar-
cable and BNC connectors. Cheapernet runs at the same ent to the LANCE. They pass through the Silo into memory
speed as Ethernet. along with the CRC. The LANCE strips off the preamble and
sync bits. Refer to Figure 1-9 and Figure 1-10. The format is:
SERIAL TRANSMISSION 1. Preamble/Start bit: Two ones occurring a minimum of eight
Serial transmission consists of sending an unbroken bit stream bit times after the assertion of RENA. The last one is the
from the TX 1/0 pin of the LANCE. The bit stream has the Start bit.
following format: (Refer to Figure 1-9)
2. Destination Address: The 48 bits (six bytes) following the
1. Preamble: A stream of alternating ones and zeros 62 bits start bit.
long supplied by LANCE.
3. Data: The serialized byte stream following the Destination
2. Sync.: Two successive ones fo!lowing the preamble sup- Address. The last four complete bytes are the CRC.
plied by LANCE.
Reception is indicated at the 1/0 pin by the assertion of RENA
3. Destination Address: Six byte address supplied by user. and the presence of clock on RCLK while TENA is inactive.
4. Source Address: Six byte address supplied by user. After the eighth RCLK, (about 800ns), after RENA is asserted
(goes high), the LANCE samples the incoming bits looking for
5. Type: Two byte field for type or length information supplied
the sync bits "11" following a zero. After it finds the sync bits, it
by user.
starts calculating CRC on the incoming bits and loading the
6. Data: 46 to 1500 bytes of data serialized with the LSB first
Silo on byte boundaries.
supplied by user.
1-17
AUi
TAP
DTE CABLE
1r-~~~ _________ J ___ l
LOCAL LOCAL Am7990 Am7992B
I CPU MEMORY LANCE SIA
I
I
L- - - - - - - - - - - - - - - - -J
LOCAL BUS
AUi - ATTACHMENT UNIT INTERFACE
DTE - DATA TERMINAL EQUIPMENT
L_____ t_J_
MAU - MEDIA ACCESS UNIT DTE
CHEAPERNET ~
.--------------- ----------, ETHERNET
I I COAX
I I
I LOCAL
CPU
LOCAL
MEMORY
Am7990
LANCE
Am7992B
SIA
Am7996
TRANSCEIVER
RG58
BNC "T"
I
I
'1 POWER I
LOCAL BUS SUPPLY
L_______________________ ~
05998A-2
Figure 1-8 Typical Ethernet/IEEE 802.3 Node
PREAMBLE SYNC DEST. SOURCE TYPE DATA FCS
1010 ... 1010 1 1 ADR ADR
62 2 6 6 2 46-1500 4
BITS BITS BYTES BYTES BYTES BYTES BYTES
05726A-22
Figure 1-9 Ethernet Frame Format
PREAMBLE SFD DEST. SOURCE
LENGTH
LLC-~:EJ
I
1010 ... 1010 10101011 ADR ADR
__,
DATA ; PAD FCS
56 8 6 6 2 46-1500 4
BITS BITS BYTES BYTES BYTES BYTES BYTES
05726A-23
Figure 1-10 IEEE 802.3 MAC Frame Format
1-18
The LANCE discards packets with less than 64 bytes (runt ETHERNET/IEEE 802.3 DIFFERENCES
packet) and reuses the receive buffer for the next packet. This The only differences in the frame formats are:
is the only case when the LANCE discards a packet. A runt 1. The Ethernet labels the first 62 bits preamble and the next
packet is normally the result of a collision. two bits sync. The IEEE 802.3 labels the first 56 bits
If RENA is asserted and remains asserted during the first 4.1 us preamble and the next 8 bits sync (SFD). The coding of the
of IPG following a receive, the LANCE will not receive the first 64 bits is identical.
packet. If this condition occurs following a transmit, the LANCE 2. Pie Ethernet has a two-byte type field to specify the type of
starts to look for the sync bits (011) about 800ns (8 bit times) packet. The length is not specified in the packet. The
after the 4.1 us window has elapsed. Therefore, the packet may LANCE supplies the packet length during reception. The
be received correctly if at least 8 bits of the preamble are packet length consists of all the bits starting at the destina-
received after the 4.1 us window. Otherwise, the packet may tion address and ending with the last byte of the packet. The
contain a CRC error. (The LANCE may be locking to a sync Ethernet frame consists of the packet plus the preamble.
pattern in the middle of data.) The packet may be discarded 3. The IEEE 802.3 has no type field but in its place is a two-
because the loss of data during the 4.1 us window made it a byte length field to specify the amount of data in the packet.
runt packet.
4. The IEEE 802.3 has a pad field at the end of the data
If RENA is asserted after the 4.1 us window, the LANCE treats portion and preceding the CRC. The use of a pad allows the
this as the start of a new packet. It starts to look for the sync user to send and receive packets that have less than 64
bits 8 bit times after RENA becomes active. bytes of data. In contrast, Ethernet requires a minimum
When a received packet terminates, if it does not end on a byte packet size of 64 bytes for packets that are not data-
boundary, a framing error has occurred. The number of bits left chained and 100 bytes for packets that are data-chained.
over after the last fuii byte are caiied dribbiing bits. The framing 5. Ethernet, Version 2, specifies that the collision detect of the
error is reported to the user as follows: transceiver must be activated during the interpacket gap
1. If there is no CRC error, then no framing error is reported time.
(FRAM = O) regardless of the number of dribbling bits.
2. If there is a CRC error, then the framing error is reported 1.9 LANCE REGISTERS AND
(FRAM = 1) if there are one or more dribbling bits. BUFFERS
3. If there are no dribbling bits, there is no framing error. There There are four Control and Status Registers (CSRs) resident
may or may not be a CRC error. within the chip. CSR 0 contains the current status information
during operation and the Start, Stop, and Initialize control sig-
THE LANCE RECOVERY AND RE-INITIALIZATION nals. CSR1 and CSR2 contain the address in memory of the
The transmitter and receiver section of the LANCE are turned Initialization Block. CSR3 contains control bits for Byte Swap,
on via the Initialization Block, Mode Register DAX and DTX ALE Control, and Byte Control. These registers are described
bits. The state of the transmitter and the receiver are monitored following a description of the two ports used to access the
through the CSRo AXON, TXON bits). The LANCE must be CSRs. The CSRs are accessed through two bus-addressable
re-initialized to transmit/receive if the transmitter and/or ports, an address port (RAP) and a data port (RDP).
receiver has not been turned on during the original initializa-
tion. The LANCE must also be re-initialized if either section 1.9.1 ADDRESS AND DATA PORTS
shuts off because of an error (MERA, UFLO, TX BUFF). The CSRs are accessed in a two-step operation. The address
The LANCE should be re-initialized with care. The user should of the CSR to be accessed is written into the address port
rearrange the descriptors in the transmit and receive rings prior (RAP) during a bus slave transaction. During a subsequent bus
to re-initialization. This is necessary because the transmit and slave transaction, the data being read from (or written into) the
receive descriptor ring pointers are reset to the beginning of data port (RDP) is read from (or written into) the CSR selected
the rings during initialization. in the RAP.
To re-initialize the LANCE, the user must stop the LANCE by Once written, the address in RAP remains unchanged until
setting the stop bit in CSRo prior to setting the INIT bit (in rewritten.
CSR 0 ). Because setting the stop bit clears CSR3, this register To distinguish the data port from the address port, a discrete
must be reprogrammed unless default values are used for 1/0 pin is provided.
BCON, ACON, and BSWP. CSR1 and CSR2 must be reloaded
when the STOP bit is set.
ADR 1/0 Pin Port
The LANCE may be restarted without initialization by setting
L Register Data Port (RDP)
the STRT bit in CSR0 . The STRT bit starts the LANCE in
H Register Address Port (RAP)
accordance with the parameters setup in the Mode register. If
DTX and DRX are set to zero in the Mode Register; the
transmitter and the receiver will be turned on again when the
STRT bit is set. However, this method of restart is not recom-
mended if the LANCE stopped in the middle of a transmission
or reception or if the buffers are data-chained.
1-19
REGISTER ADDRESS PORT (RAP) 1.9.2 CONTROL AND STATUS REGISTERS
15 2 0 CONTROL AND STATUS REGISTER 0 (CSR0 )
~SR SELECT
,__~~~~~~~~~RESERVED
ERR INIT
BABL STRT
AF001490 CERR STOP
MISS TDMD
MERR TXON
RINT RXON
Bit Name Description
TINT INEA
15:02 RES Reserved and read as zeroes. IDON INTR
01 :00 CSR(1 :0) CSR address select. READ/WRITE.
AF000860
Selects the CSR to be accessed through
the ADP. RAP is cleared by Bus RESET.
CSR(1:0) CSR The LANCE updates CSRo by logical "OR"ing the previous
00 CS Ro and present value of CSR 0 . CSR 0 is accessible when RAP =
01 CSR1 00.
10 CSR2
11 CSR3
Bit Name Description
15 ERR ERROR summary is set by the "OR" of BABL,
REGISTER DATA PORT (ADP) CERA, MISS and MERA. ERR remains set as
long as any of the error flags are true.
15 0
ERR is read only; writing to it has no effect. It
CSR DATA is cleared by Bus RESET, by setting the
STOP bit, or clearing the individual error flags.
14 BABL BABBLE is a transmitter timeout error. It indi-
AF001450 cates that the transmitter has been on the
channel longer than the time required to send
the maximum length packet.
Bit Name Description
BABL is a flag which indicates excessive
15:00 CSR Data Writing data into ADP writes the data into length in the transmit buffer. It is set after 1519
the CSR selected in RAP. Reading the data data bytes have been transmitted; the chip
from the RDP reads the data from the CSR continues to transmit until the whole packet is
selected in RAP. CSR 1, CSR2 and CSR3 transmitted or there is a failure. When BABL
are accessible only when the STOP bit of error occurs, an interrupt is generated if INEA
CSRo is set. = 1.
If the STOP bit is not set while attempting BABL is READ/CLEAR ONLY. It is set by the
to access CSR1, CSR2 or CSR3, the chip LANCE and cleared by writing a "1" into the
will return READY, but a READ operation bit. Writing a "O" has no effect. It is cleared by
will return undefined data. WRITE opera- RESET or by setting the STOP bit.
tion is ignored. 13 CERA COLLISION ERROR is a collision after
transmission transceiver test feature. It indi-
cates that the collision input to the LANCE
failed to activate within 2us after a LANCE-
initiated transmission was completed. This
function is also known as heartbeat.
CERA is READ/CLEAR ONLY It is set by the
chip and cleared by writing a "1" into the bit.
Writing a "O" has no effect. It is cleared by
RESET or by setting the STOP bit.
1-20
Bit Name Description Bit Name Description
12 MISS MISSED PACKET is set when the receiver 07 INTR INTERRUPT FLAG is set by the "OR" of
loses a packet because it does not own a BABL, MISS, MERA, RINT, TINT and IDON. If
receive buffer and the silo has overflowed, in- INEA = 1, the INTR pin will be low.
dicating loss of data.
INTR is READ ONLY; writing this bit has no
Silo overflow is not reported because there is effect. INTR is cleared by RESET, by setting
no receive ring entry in which to write status. the STOP bit, or
When MISS is set, an interrupt is generated if by clearing the condition causing the
INEA = 1. interrupt.
MISS is READ/CLEAR ONLY. It is set by the 06 INEA INTERRUPT ENABLE allows the INTR 1/0 pin
LANCE and cleared by writing a "1" into the to be driven low when the Interrupt Flag is set.
bit. Writing a "O" has no effect. It is cleared by If INEA = 1 and INTR = 1, the INTR 1/0 pin
RESET or by setting the STOP bit. will be high, regardless of the state of the Inter-
rupt Flag.
11 MERR MEMORY ERROR is set when the LANCE is
the Bus Master and has not received READY INEA is READtWRITE and cleared by RESET
within 25.6us after asserting the address on or by setting the STOP bit.
the DAL lines. INEA cannot be set while STOP bit is set.
When a Memory Error is detected, the INEA can be set in parallel or after INIT and/or
receiver and transmitter are turned STRT bit is set.
off and an interrupt is generated if 05 RXON RECEIVER ON indicates that the receiver is
INEA = 1. enabled. RXON is set when STRT is set if
MERR is READ/CLEAR ONLY. It is set by the DRX = 0 in the MODE register in the Initializa-
LANCE and cleared by writing a "1" into the tion Block and the Initialization Block has been
bit. Writing a "O" has no effect. It is cleared by read by the LANCE by setting the INIT bit.
RESET or by setting the STOP bit. RXON is cleared when IDON is set from set-
ting the INIT bit and DAX = 1 in the MODE
10 RINT RECEIVER INTERRUPT is set when the register, or a memory error (MERR) has oc-
LANCE updates an entry in the Receive curred. AXON is READ ONLY: writing this bit
Descriptor Ring for the last buffer received has no effect. RXON is cleared by RESET or
before fall of carrier. by setting the STOP bit.
When RINT is set an interrupt is generated if 04 TXON TRANSMITTER ON indicates that the
INEA = 1. transmitter is enabled. TXON is set when
RINT is READ/CLEAR ONLY. It is set by the STRT is set if DTX = 0 in the MODE register in
LANCE and cleared by writing a "1" into the the Initialization Block and the INIT bit has
bit. Writing a "O" has no effect. It is cleared by been set. TXON is cleared when IDON is set
RESET or by setting the STOP bit. and DTX = 1 in the MODE register or an error,
09 TINT TRANSMITIER INTERRUPT is set when the such as MERA, UFLO or BUFF, has occurred
LANCE updates an entry in the transmit during transmission.
descriptor ring for the last buffer sent or TXON is READ ONLY; writing this bit has no
transmission is stopped due to a failure. effect. TXON is cleared by RESET or by set-
When TINT is set, an interrupt is generated if ting the STOP bit.
INEA = 1. 03 TDMD TRANSMIT DEMAND -when set- causes the
TINT is READ/CLEAR ONLY and is set by the LANCE to access the Transmit Descriptor
LANCE and cleared by writing a "1" into the Ring without waiting for the polling time inter-
bit. Writing a "O" has no effect. It is cleared by val to elapse. TDMD need not be set to
RESET or by setting the STOP bit. transmit a packet; it merely hastens the chip's
response to a Transmit Descriptor Ring entry
08 IDON INITIALIZATION DONE indicates that the chip insertion by the host.
has completed the initialization procedure
started by setting the INIT bit. The LANCE has TDMD is WRITE WITH ONE ONLY and is
read the Initialization Block from memory and cleared by the microcode after it is used. It
stored the new parameters. may read as a "1" for a short time after it is
written because the microcode may have
When IDON is set, an interrupt is generated if been busy when TDMD was set. It is also
INEA = 1.
cleared by RESET or by setting the STOP bit.
IDON is READ/CLEAR ONLY. It is set by the Writi~ a "O" in this bit has no effect.
LANCE and cleared by writing a "'1" mto the
bit. Writing a "O" has no effect. It is cleared by
RESE-T or-by.setting the STOP bit.
1-21
Bit Name Description CONTROL AND STATUS REGISTER 2 (CSR 2 )
~---------~ READ/WRITE: Accessible only when the STOP bit of CSRo is
02 STOP STOP disables the chip from all external ac-
a ONE and RAP= 10.
tivity when set and clears the internal logic.
Setting STOP is the equivalent of asserting
15 8 7 0
RESET. The LANCE remains inactive and
STOP remains set until the STAT or INIT bit is RES IADR
set. If STRT, INIT and STOP are all set to-
gether, STOP overrides the other bits and only
STOP will be set. AF000920
STOP is READ/WRITE WITH ONE ONLY and
set by RESET. Writing a "O" to this bit has no
effect. STOP is cleared by setting either INIT
Bit Name Description
or STRT.
15:08 RES Reserved.
01 STRT START enables the LANCE to send and
receive packets, perform direct memory ac- 07:00 IADR The high order 8 bits of the address of the first
cess, and do buffer management. STOP bit word (lowest address) in the Initialization
must be set prior to setting the STRT bit. Set- Block.
ting STRT clears the STOP bit.
INIT and STRT must not be set in the same
CONTROL AND STATUS REGISTER 3 (CSRa)
cycle. Set INIT first and wait for IDON
CSR 3 allows redefinition of the Bus Master interface.
(IDON=1) before setting STAT bit. INIT is
READ/WRITE WITH ONE ONLY. Writing a "O" READ/WRITE: Accessible only when the STOP bit of CSRo is
into this bit has no effect. STRT is cleared by ONE and RAP = 11. CSR 3 is cleared by
RESET or by setting the STOP bit. RESET or by setting the STOP bit in CSR 0 .
00 INIT INITIALIZE, when set, causes the chip to
begin the initialization procedure and access
the Initialization Block. STOP bit must be set
prior to setting the INIT bit. Setting INIT clears
the STOP bit.
15
- - - - - - - - - - - - - - -..... ,-ffl
3
____
2 1 o
INIT and STAT must not be set in the same -------~------- BCON
cycle. Set INIT first and wait for IDON ACON
(IDON=1) before setting STAT bit. INIT is BSWP
READ/WRITE WITH "1" ONLY. Writing a "O" .....__ _ _ _ _ _ _ _ _ _ RES
into this bit has no effect. INIT is cleared by
RESET or by setting the STOP bit. AF000900
CONTROL AND STATUS REGISTER 1 (CSR 1)
READ/WRITE: Accessible only when the STOP bit of CSRo is Bit Name Description
a ONE and RAP= 01.
15:03 RES Reserved and read as "O".
15 0 02 BSWP BYTE SWAP allows the LANCE to operate in
systems that consider bits (15:08) of data to
IADR
be at an even address and bits (07:00) to be at
an odd address.
AF000970 When BSWP = 1, the LANCE will swap the
high and low bytes on OMA data transfers be-
tween the silo and bus memory. Only data
Bit Name Description
from silo transfers is swapped; the Initializa-
tion Block data and Descriptor Ring entries are
15:01 IADR The low order 15 bits of the address of the first
NOT swapped.
word (lowest address) in the Initialization
Block. BSWP is READ/WRITE and cleared by
RESET or by setting the STOP bit in CSR 0 .
00 Must be zero.
1-22
Bit Name Description
MODE REGISTER
The Mode Register allows alteration of the chip's operating
01 ACON ALE CONTROL defines the assertive state of parameters. Normal operation is with the Mode Register clear.
ALE when the LANCE is a Bus Master. ACON
is READ/WRITE and cleared by RESET and 15 14 7 6 5 4 3 2 1 0
by setting the STOP bit in CSRo.
ACON ALE
O Asserted High
Asserted Low I IIIIII nRx
00 BCON BYTE CONTROL redefines the Byte Mask
and Hold 1/0 pins. BCON is READ/WRITE and
I 11 L:=~~.
~ DTCR
cleared by RESET or by setting the STOP bit COLL
.....__ _ _ _ _ _ DATY
BCON
in CSRo.
Pin 15 Pin 16 Pin 17
I.__-------!NTL
.__-----------~RES
0 BMo BM1 HOLD
.__------------------PROM
BYTE BUSAKO BUSRQ
AF000510
All data transfers from the LANCE in the Bus Master mode are
in words. However, the LANCE can handle odd address
boundaries and/or packets with an odd number of bytes. Bit Name Description
1.9.3 INITIALIZATION BLOCK 15 PROM PROMISCUOUS mode. When PROM = 1, all
incoming packets are accepted.
The Initialization Block consists of five registers; Mode Regis-
ter, Physicai Address Register, Logical Address Filter, Receive 14:07 RES RESERVED.
Descriptor Ring Pointer, and Transmit Descriptor Ring Pointer. 06 INTL INTERNAL LOOPBACK is enabled when the
Chip initialization includes the reading of the Initialization Block LOOP bit is set. Internal loopback lets the
in memory to obtain the operating parameters. LANCE receive its own transmitted packet.
The Initialization Block is read by the chip when the INIT bit in Since this represents full duplex operation, the
CSRo is set. The INIT bit should be set before or concurrent packet size is 8-32 bytes. INTERNAL LOOP-
with the STRT bit to insure proper parameter initialization and BACK operates in promiscuous mode and
chip operation. After the chip has read the Initialization Block, when the packets are addressed to the node
IDON is set in CSR 0 and an interrupt is generated if INEA = 1. itself.
The following is a definition of the initialization Block. If the source and destination are different, the
LANCE must be re-initialized after each test.
Highest Address TLEN-TDRA (31 :16) IADR + 22
TORA (15:00) IADR + 20 The LANCE will not receive external packets
RLEN-RDRA (31:16) IADR + 18 in INTERNAL LOOPBACK mode.
RORA (15:00) IADR + 16 EXTERNAL LOOPBACK allows the LANCE to
LADRF (63:48) IADR + 14 transmit a packet through the SIA transceiver
LADRF (47:32) IADR + 12 cable out to the Ethernet coax. It is used to
LADRF (31:16) IADR + 10 determine the operability of all circuitry and
LADRF (15:00) IADR + 08 connections between the LANCE and the co-
PADR (47:32) IADR + 06 axial cable. Multicast addressing in EXTER-
PADR (31 :16) IADR + 04 NAL LOOPBACK is valid only when DTCR=1
PADR (15:00) IADR + 02 (user needs to append the 4-byte CRC).
Base Address MODE IADR + 00
In EXTERNAL LOOPBACK, the Silo READ/
WRITE pointers can get misaligned under
heavy traffic. The packet may get corrupted, or
not be received. Therefore, EXTERNAL
LOOPBACK should be executed several
times in order to isolate this type of error in
receiving the lost packet.
INTL is only valid if LOOP = 1; otherwise it is
ignored.
LOOP INTL LOOPBACK
O X No loopback, normal
O External
Internal
1-23
Bit Name Description Bit Name Description
05 DRTY DISABLE RETRY. When DRTY = 1, the 01 DTX DISABLE THE TRANSMITTER causes the
LANCE will attempt only one transmission of a LANCE to not access the Transmitter Descrip-
packet. If there is a collision on the first tor Ring and therefore no transmissions are
transmission attempt, a Retry Error (RTRY) attempted. DTX = 1 clears the TXON bit in
will be reported in Transmit Message Descrip- CSRo when initialization is complete.
tor 3 (TMD3). 00 DRX DISABLE THE RECEIVER causes the chip to
04 COLL FORCE COLLISION. This bit allows the colli- reject all incoming packets and not access the
sion logic to be tested. The LANCE must be in Receive Descriptor Ring. DRX = 1 clears the
internal loopback mode of COLL to be valid. If RXON bit in the CSRo when initialization is
COLL = 1, a collision will be forced during the complete.
subsequent transmission attempt. This will
result in 16 total transmission attempts with a
PHYSICAL ADDRESS REGISTER (PADR)
retry error reported in TMD 3.
47
03 DTCR DISABLE TRANSMIT CRC. When DTCR = 0,
the transmitter generates and appends a CRC PADR
to the transmitted packet. When DTCR = 1,
the CRC logic is allocated to the receiver and
AF000520
no CRC is generated or sent with the transmit-
ted packet.
Bit Name Description
During loopback, DTCR = O will cause a CRC
to be generated on the transmitted packet, but 47:00 PADR PHYSICAL ADDRESS is the unique 48-bit
no CRC check is done by the receiver since physical address assigned to the LANCE.
the CRC logic is shared and cannot generate PADR (0) must be zero.
and check CRC at the same time. The
generated CRC is written into memory with the LOGICAL ADDRESS FILTER (LADRF)
data and can be checked by the host software.
If DTCR = 1 during loopback, the host soft- 63
ware must append a CRC value to the LAD RF
transmit data. The receiver checks the CRC
on the received data and reports any errors.
Since the CRC generator is used to generate AF000500
the hash filter, the multicast addressing cannot
be used when DTCR = 1.
Bit Name Description
02 LOOP LOOPBACK allows the LANCE to operate in
full duplex mode for test purposes. The packet 63:00 LADRF The 64-bit mask used by the LANCE to accept
size is 8-32 bytes. The received packet can be logical addresses.
up to 36 bytes (32 + 4 bytes CRC) when
DTCR=O. During loopback, the runt packet fil- If the first bit of an incoming address is a "1" [PADR (0) = 1], the
ter is disabled because the packet is smaller address is deemed logical and is passed through the logical
than the minimum size Ethernet packet {64 address filter.
bytes).
The logical address filter is a 64-bit mask that is used to accept
LOOP = 1 allows simultaneous trans- incoming Logical Addresses. The incoming address is sent
mission and reception for a message con- through the CRC circuit. After all 48 bits of the address have
strained to fit within the Silo. The chip waits gone through the CRC circuit, the high order 6 bits of the
until the entire message is in the Silo before resultant CRC are strobed into a register. This register is used
serial transmission begins. The incoming data to select one of the 64-bit positins in the Logical Address Filter.
stream fills the Silo from behind as it is being If the selected filter bit is a "1" the address is accepted and the
emptied. Moving the received message out of packet is put in memory. The logical address filter only assures
the Silo to memory does not begin until recep- that there is a possibility that the incoming logical address
tion has ceased. belongs to the node. To determine if it belongs to the node, the
In loopback mode, transmit data chaining is incoming logical address that is stored in main memory is
not possible. Receive data chaining is possi- compared by software to the physical address that was loaded
ble if receive buffers are 32 bytes long to allow through the Initialization Block.
time for lookahead. The Broadcast address, which is all Ones, does not go through
the Logical Address Filter and is always enabled. If the Logical
Address Filter is loaded with all zeroes, all incoming logical
addresses except broadcast will be rejected.
1-24
RECEIVE DESCRIPTOR RING POINTER
Bit Name Description
31 2928 24 23 3 2
I I I
ALEN RES RORA
28:24 RES
23:03 TORA
RESERVED
TRANSMIT DESCRIPTOR RING ADDRESS
is the base address (lowest address) of the
AF000490 Transmit Descriptor Ring.
02:00 MUST BE ZEROES. These bits are TORA
(02:00) and must be zeroes because the
Bit Name Description Transmit Rings are aligned on quadword
boundaries.
31 :29 ALEN RECEIVE RING LENGTH is the number of
entries in the receive ring expressed as a
power of two. 1.9.4 DESCRIPTOR RINGS
Buffer Management is accompiished through message
Number
descriptors organized in ring structures in memory. Each mes-
ALEN of Entries
sage descriptor entry is four words long. There are two rings
0 1
allocated for the device: a receive ring and a transmit ring. The
1 2
device is capable of polling each ring for buffers to either empty
2 4
or fill with packets to or from the channel. The device is also
3 8
capable of entering status information in the descriptor entry.
4 16
Chip polling is limited to looking at the descriptor entry follow-
5 32
ing the current entry.
6 64
7 128 The location of the descriptor rings and their length are found in
the Initialization Block, accessed during the initialization proce-
28:24 RES RESERVED
dure by the chip. Writing a "ONE" into the STAT bit of CSRo
23:03 RORA RECEIVE DESCRIPTOR RING ADDRESS is will cause the chip to start accessing the descriptor rings and
the base address (lowest address) of the enable it to send and receive packets.
Receive Descriptor Ring.
The LANCE communicates with a HOST device through the
02:00 MUST BE ZEROES. These bits are RORA ring structures in memory. Each entry in the ring is either
(02:00) and must be zeroes because the "owned" by the chip or the HOST. There is an ownership bit
Receive Rings are aligned on quadword (OWN) in the message descriptor entry. Mutual exclusion is
boundaries. accomplished by a protocol which states that each device can
only relinquish ownership of the descriptor entry to the other
device; it can never take ownership, and no device can change
TRANSMIT DESCRIPTOR RING POINTER the state of any field in any entry after it has relinquished
ownership.
31 2928 24 23 3 2 0
Each descriptor in a ring in memory is a 4-word entry. The
TORA following is the format of the receive and the transmit descrip-
tors.
AF000480
RECEIVE MESSAGE DESCRIPTOR 0 (RMDo)
Bit Name Description
15
31 :29 TLEN TRANSMIT RING LENGTH is the number of
LADA
entries in the Transmit Ring expressed as a
power of two.
AF000940
Number
TLEN of Entries
Bit Name Description
0 1
1 2 15:00 LADA The LOW ORDER 16 address bits of the buf-
2 4 fer pointed to by this descriptor. LADA is
3 8 written by the host and unchanged by the
4 16 LANCE.
5 32
6 64
7 128
1-25
RECEIVE MESSAGE DESCRIPTOR 1 (RMD 1) Bit Name Description
15 14 13 12 11 10 9 8 7 0
09 STP START OF PACKET indicates that this is the
first buffer of a packet. It is used for data chain-
ing buffers.
- - - - - HADA 08 ENP END OF PACKET indicates that this is the last
'------------------~ENP buffer of this packet. It is used for data chain-
'-----------------------STP ing buffers. If both STP and ENP are set, the
------------------------BUFF packet fits into one buffer and there is no data
'----------------------------CRC chaining. See Note 1.
....._---------------------------OFLO
07:00 HADR The HIGH ORDER 8 address bits of the buffer
'------------------------------~FRAM
pointed to by this descriptor. This field is writ-
'-----------------------------------ERR
'------------------------------------~OWN
ten by the host and unchanged by the LANCE.
AF000870
RECEIVE MESSAGE DESCRIPTOR 2 (RMD 2 )
Bit Name Description
15 12 11
15 OWN This bit indicates that the descriptor entry is
owned by the host (OWN = 0) or by the chip 1111 BCNT
(OWN = 1). The LANCE clears the OWN bit
after filling the buffer pointed to by the descrip-
tor entry. The host sets the OWN bit after AF000930
emptying the buffer. Once the chip or host has
relinquished ownership of a buffer, it must not
change any field in the four words that com-
Bit Name Description
prise the descriptor entry.
15:12 MUST BE ONES. This field (all Ones) is writ-
14 ERR ERROR summary is the "OR" of FRAM,
ten by the Host and unchanged by the
OFLO, CRC or BUFF.
LANCE.
13 FRAM FRAMING ERROR indicates that the incom-
11 :00 BCNT BUFFER BYTE COUNT is the length of the
ing packet contains a non-integer multiple of
buffer pointed to by this descriptor, expressed
eight bits and there is a CRC error. If the
as a two's complement number. This field is
incoming packet has no CRC error, then
written by the host and unchanged by the
FRAM will not be set even if the packet has a
LANCE. Minimum buffer size is 64 bytes for
non-integer multiple of eight bits. FRAM is not
the first buffer packet.
valid in internal loopback mode. See Note 1.
12 OFLO OVERFLOW error indicates that the Silo over-
flowed and all or part of the incoming packet
was lost because no memory buffer was avail- RECEIVE MESSAGE DESCRIPTOR 3 (RMD3 )
able. See Note 1.
15 12 11
11 CRC CRC indicates that the receiver has detected
a CRC error on the incoming packet. See RES MCNT
Note 1.
10 BUFF BUFFER ERROR is set any time the chip
does not wn the next buffer while data chain- AF000950
ing a received packet. This can occur in either
of two ways: 1) the OWN bit of the next buffer
is zero, or 2) silo overflow occurred before the
Bit Name Description
chip received the next STATUS.
If a Buffer Error occurs, an Overflow Error may 15:12 RES RESERVED and read as zeroes.
also occur internally in the Silo, but is not re-
11 :00 MCNT MESSAGE BYTE COUNT is the length in
ported in the descriptor status entry unless
bytes of the received message. MCNT is valid
both BUFF and OFLO errors occur at the
only when ERR is clear and ENP is set.
same time.
Note 1. Disregard the error status in RMD 1 when both OVFL
and ENP are set (no overflow error).
ONFL is valid only when the ENP is "O".
CRC and FRAM are valid only when ENP is "1".
1-26
TRANSMIT MESSAGE DESCRIPTOR 0 {TMDo) Bit Name Description
15
09 STP START OF PACKET indicates that this is the
LADR first buffer of this packet. It is used for data
chaining buffers. STP is set by the host and
AF000940 unchanged by the chip. The STP bit must be
set in the first buffer of the packet or the
LANCE will skip over this descriptor, poll the
Bit Name Description next descriptor(s) entry until the OWN and
STP bits are set.
15:00 LADR The LOW ORDER 16 address bits of the buf-
08 ENP END OF PACKET indicates that this is the last
fer pointed to by this descriptor. LADR is writ-
buffer to be used by the chip for this packet. It
ten by the host and unchanged by the LANCE.
is used for data chaining buffers. If both STP
and ENP are set, the packet fits into one buffer
and there is no data chaining. ENP is set by
TRANSMIT MESSAGE DESCRIPTOR 1 (TMD 1) the host and unchanged by the LANCE.
07:00 HADR The HIGH ORDER 8 address bits of the buffer
15 14 13 12 11 10 9 8 7 pointed to by this descriptor. This field is writ-
ten by the host and unchanged by the LANCE.
' - - - - - - - - - - - - - STP 15 12 11 0
..__------------DEF r-~~~---,r--~~~~~~~~~~~~~-
.___ _ _ _ _ _ _ _ _ _ _ _ _ ONE
1111 BCNT
'---------------~MORE
'----------------~RES
AF000980
'-------------------ERR
"---------------------OWN
Bit Name Description
AF000880
15:12 Must be ones. This field is set by the host and
unchanged by the LANCE.
Bit Name Description
11 :00 BCNT BUFFER BYTE COUNT is the usable length in
15 OWN This bit indicates that the descriptor entry is bytes of the buffer pointed to by this descriptor
owned by the host (OWN = O) or by the expressed as a two's complement number.
LANCE (OWN = 1). The host sets the OWN This is the number of bytes from this buffer
bit after filling the buffer pointed to by this that will be transmitted by the chip. This field is
descriptor. The chip clears the OWN bit after written by the host and unchanged by the
transmitting the contents of the buffer. Neither LANCE. The first buffer of a packet has to be
the host nor the chip must alter a descriptor at least 100 bytes minimum when data chain-
entry after it has relinquished ownership. ing and 64 bytes (DTCR=1) or 60 bytes
(DTCR=O) when not data chaining.
14 ERR ERROR summary is the "OR" of LCOL,
LCAR, UFLO or RTRY.
TRANSMIT MESSAGE DESCRIPTOR 3 (TMD 3)
13 RES RESERVED bit. The LANCE will write this bit
with a "O".
15 14 13 12 11 10 9
12 MORE MORE indicates that more than one retry was
needed to transmit a packet.
11 ONE ONE indicates that exactly one retry was
needed to transmit a packet. One flag is not ' - - - - - - - TOR
.....__ _ _ _ _ _ _ _ _ _ _ _ RTRY
valid when LCOL is set.
10 DEF DEFERRED indicates that the chip had to '---------------LCAR
..__-------------~LCOL
defer while trying to transmit a packet. This
'----------------~RES
condition occurs if the channel is busy when ,___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ UFLO I
the chip is ready to transmit.
'--------------------BUFF
AF000890
1-27
Bit Name Description
15 BUFF BUFFER ERROR is set by the LANCE during
transmission when the chip does not find the
ENP flag in the current buffer and does not
own the next buffer. This can occur in either of
two ways: either the OWN bit of the next buffer
is zero, or Silo underflow occurred before the
LANCE received the next STATUS signal.
BUFF is set by the chip. BUFF error disables
the transmitter (CSR 0 = TXON = 0)
If a Buffer Error occurs, an Underflow Error will
also occur. BUFF error is not valid when
LCOL, or RTRY errors are set.
14 UFLO UNDERFLOW ERROR indicates that the
transmitter has truncated a message due to
data late from memory. UFLO indicates that
the Silo has emptied before the end of the
packet was reached.
13 RES RESERVED bit. The chip will write this bit with
a "O".
12 LCOL LATE COLLISION indicates that a collision
has occurred after the slot time of the channel
has elapsed. The LANCE does not retry on
late collisions.
11 LCAR LOSS OF CARRIER is set when the carrier
input (RENA) to the LANCE goes false during
a chip-initiated transmission. The chip does
not retry upon loss of carrier. It will continue to
transmit the whole packet LCAR until packet is
finished. LCAR is not valid in INTERNAL
LOOPBACK MODE.
10 RTRY RETRY ERROR indicates that the transmitter
has failed in 16 attempts to successfully
transmit a message due to repeated collisions
on the medium. If DRTY = 1 in the MODE
register, RTRY will set after 1 failed transmis-
sion attempt.
09:00 TDR TIME DOMAIN REFLECTOMETRY reflects
the state of an internal LANCE counter that
counts from the start of a transmission to the
occurrence of a collision. This value is useful
in determining the approximate distance to a
cable fault. The TDR value is written by the
chip and is valid only if RTRY is set.
1-28
CHAPTER 2
BUS INTERFACE CONSIDERATIONS
This chapter discusses the requirements of the LANCE in vari- 2.1 BUS BANDWIDTH DEFINITION
ous configurations relating to the bus master or masters, bus
Bus bandwidth is defined as the percentage of the time that the
bandwidth, and bus latency.
bus is held and contmlled by a device. Assuming that no wait
The LANCE may be required to fit into an already designed states are added to the OMA cycles in a simplified system
architecture or a new architecture may be designed around the environment, the LANCE acquires the bus within a few cycles
LANCE. It is obvious that the latter case results in a cleaner after requesting it. In order to handle the Ethernet transmission
design and more reliable system. The following analysis is data rate of 10 Megabits per second, the LANCE must request
being developed from a simple architecture where the LANCE the bus approximately every 12.8 us. The LANCE uses the bus
and CPU are the oniy master devices in the system, to a more for 4.8 us for eight words of OMA transfer. Therefore, 37.5%
complex system with multiple master devices. (4.8/12.8) of bus bandwidth is taken by the LANCE and the
A system may be configured with: remainder is left to the CPU to perform other tasks. Any wait
state added to the LANCE 8-word OMA cycle increases the
The LANCE and one CPU as the only bus masters
LANCE OMA cycle by 800 ns and increases the bus bandwidth
The LANCE in systems with multiple other masters
taken by the LANCE by 6.25 percentage points (see Figure
The LANCE in a Daisy Chain operation
2-1).
The LANCE with 8-bit microprocessors
Following a brief definition of bus bandwidth, bus latency, and 2.2 BUS LATENCY DEFINITION
LANCE OMA cycles, the LANCE bus latency and OMA opera-
The term "bus latency" is defined as follows:
tion are discussed in each of the above configurations. The bus
bandwidth and latency are different for each of these con- Bus latency is the amount of time from the time that the OMA
figurations. device requests the bus (LANCE, HOLD=L) until the time it
acquires the bus (LANCE, HLDA=L). Allowable Bus Latency is
the amount of time that a OMA device can wait for the bus after
requesting it without the loss of data or other functions.
100
90
80
BUS
BANDWIDTH
REQUIREMENT 70
%
60
50
40
37.5
30
0 7 NO. OF WAIT STATES
600 700 800 900 1000 1100 1200 1300 1400 OMA MEMORY CYCLE
(NANOSECONDS)
Figure 2-1 Bus Bandwidth Requirement 06363A-4
2-1
Bus latency is a limiting factor in assigning peripheral devices + 4.8) until the whole packet is transmitted or received. The
to a bus. Devices sensitive to the value of bus latency are: ring access is done with a single OMA arbitration cycle, either
communication controllers, display memory scanners, and between the time that the LANCE is transferring data to/from
dynamic memories when a OMA approach is used. the Silo (data chaining) or when the last buffer of a packet
(receive or transmit) has been relinquished to the LANCE.
Communication devices require that data be transferred
When the LANCE owns the buffer, it does three to four sepa-
to/from memory before an overflow/underflow condition oc-
rate OMA cycles, with 1.0 to 2.0 us dwel~ time for every buffer.
curs. The CRT controllers must scan the display memory to
The LANCE does not perform any OMA burst between ring
update and/or refresh the screen periodically. Each OMA
access time.
device on a bus increases the bus latency when sharing the
bus with other OMA devices. Therefore, the bus latency of
each OMA device should be taken into account in designing a 2.4.1 BUS LATENCY WITH ONE OTHER
system. MASTER
The above discussion assumes that the LANCE receives the
2.3 LANCE OMA CYCLE bus acknowledge (HLDA) fast enough (within a few cycles).
(BUS MASTER MODE) The large Silo size (48 bytes) allows the LANCE to tolerate a
longer bus latency. When the LANCE is in receive mode and
The LANCE is capable of two different types of OMA Transfers:
there are eight words in the Silo, the time required for the
- Burst mode OMA LANCE to receive the bus acknowledge can be stretched to
- Single word OMA nearly 25.6 us (16 words) before the Silo overflows. However,
Burst mode OMA is used for transmission of packets from the very next bus request (HOLD) from the LANCE should be
memory to the Silo (read) or for reception of packets from the acknowledged within 8.0 us because there are already about
Silo to memory (write). 19 words in the Silo. The LANCE always releases the bus after
eight word transfers, even if there are already eight or more
The burst transfers are eight consecutive word reads (transmit)
words residing in the Silo. The second bus request will be
or writes (receive) that are done on a single bus arbitration
asserted within 700 ns, when there are eight or more words in
cycle. In other words, after the LANCE receives the bus ac-
the Silo (dwell time).
knowledge, (HLDA = Low), it will do eight word transfers, or
one byte and seven word transfers, (8 OMA cycles, at a mini-
mum of 600 ns per cycle) before releasing the bus request
2.5 LANCE WITH MULTIPLE MASTER
signal by HOLD going high. If there are more than 8 words of DEVICES ON THE BUS
data in the Silo in Receive Mode when the LANCE releases the The LANCE is flexible when it is integrated with other master
bus (HOLD deasserted), the LANCE will request the bus again devices on the bus. A large FIFO (also referred to as Silo), 48
within 700 ns (HOLD dwell time). Burst DMAs are always eight bytes deep, and a unique programmable interface make
cycle transfers unless there are less than eight words left to be LANCE versatile in a multimaster environment.
transferred to/from the Silo.
The impact of integrating a master device onto an existing bus
The LANCE initiates single word OMA transfers to access the system requires careful investigation at the start of system
Transmit Rings, Receive Rings, or Initialization Block. The development. The following discussion summarizes the areas
LANCE will not initiate any burst OMA transfer from the time of concern to the user when designing the LANCE into a multi-
that it gets to own the descriptor to the time it accesses the master bus.
descriptor entries in the ring (an average of three to four sepa-
In designing a bus with multiple master devices, some restric-
rate OMA cycles for a multibuffer packet) or to the time it reads
tions are imposed on the master devices. These requirements
the Initialization Block.
allow the bus to be utilized efficiently, and each device gets a
fair share of the bus without degrading the bus bandwidth.
2.4 LANCE AND ONE CPU ON THE
Some typical system bus requirements are:
BUS MASTER
1. Each device on the bus is allowed to hold the bus for only a
In this configuration, the LANCE shares the bus with one mas-
limited time, once it has acquired it. There are many system
ter device. A dedicated node processor may be assigned to
requirements which must be considered to determine the maxi-
service the LANCE and the host CPU, or a single processor
mum time any bus master is allowed to remain on the bus. If
may be responsible for both the LANCE and the network tasks
this time is exceeded, some type of monitoring device gener-
management. The bus bandwidth requirement should not be
ates a bus error and forces the device off the bus.
critical with only two master devices on the bus. The LANCE
will request the bus when there are at least 16 bytes of data The LANCE holds the bus for a minimum of 4.8 us during the
available in the Silo (receive mode) or when there are more OMA burst and a minimum of 600 ns when accessing the rings
than 16 locations available in the Silo (transmit mode). The or the Initialization Block. If the memory access time is longer
CPU normally acknowledges the bus request within two to four than the LANCE OMA cycle, the LANCE OMA cycle period can
cycles. be stretched (wait states being added to the LANCE OMA
cycle) by the use of some external logic and by controlling the
Once the LANCE acquires the bus, it will transfer eight words
READY input to the LANCE. Eventually, the READY should be
to/from the Silo before it relinquishes the bus. The transfer time
granted to the LANCE before the occurrence of either an over-
is equivalent to about 4.8 us without any wait states. With 8.0
flow or underflow error condition, or a 25.6 usec memory
us Dwell time, the LANCE requests the bus every 12.8 us (8.0
timeout error (MERA).
2-2
2. Any device on the bus may be kicked off the bus 3. Within an existing bus, the master devices already on the
(preemptive DMA) at any time. This is usually enforced by a bus may not have enough bus bandwidth left to allow for any
bus arbiter when a higher priority device needs to acquire the new device to be added. The new device may be required to
bus. Refer to Figure 2-2. stay off the bus and provide its own dedicated dual port
The HLDA to the LANCE cannot be deasserted while the memory.
HOLD from the LANCE is active. Once the LANCE has ac- The LANCE supports a dual port RAM architecture with some
quired the bus, it will not release the bus until it has finished its external logic. The external logic is needed to allow access to
8 DMA cycles (or less, if it happens to be the last few bytes of the LANCE internal register, CSRo. during the normal opera-
the packet) while transferring data to/from the Silo. However, tion. This register contains the interrupt/control status register
the external logic pointed out previously may be used to add bits. The external logic must monitor and control HOLD, HLDA
wait states to the LANCE DMA cycle and to isolate its ad- of the LANCE so that the CPU can access the CSR 0 when the
dress/data bus, through buffers or transceivers, from the sys- LANCE is not in the middle of a series of DMA accesses.
tem bus. Thus preemptive DMA can be supported by the use of
external logic.
Vee
FiEADv
(SYSTEM)
T
I
M
E LANCE
R (Am7990)
BUS PREEMPTION ON
p
R
......-~~~~~~~~~~~~~~i-~~--t HOLD
0
c 11-~~~~~~~~~~~~~~~+-~~~1 HLDA
E
s
s
0 A1s-A23
l/•--~~+-~---1 ALE
R
BMO,BM1
(ARBITRATION
LOGIC)
DAL.o-DAL15
,~~~~~__,.,, DAS
READ
SYSTEM BUS
Figure 2-2 Block Diagram of Pre-emption in the LANCE 06363A-5
2-3
2.5.1 BUS LATENCY FOR MULTIMASTER The following calculation leads to the worst case allowable bus
ENVIRONMENT latency for the LANCE, for large packet (1518 bytes) and small
buffer sizes (64 bytes), when the buffers are data-chained.
The amount of allowable bus latency for a master device must
be evaluated prior to adding a new device into a multimaster Assume:
environment. We will study the allowable bus latency for the - No wait state is added to the LANCE OMA cycle.
LANCE under two different cases: a single buffer per packet
- HLOA assertion to bus driver enable delay is not in-
(no data-chaining) and multiple buffer segments per packet
cluded in the calculation.
(data-chaining). The main difference is that, in data-chaining,
the L~NCE does a separate lookahead opeiation (requiring 64.-byte transfer (1 buffei) time =
three OMA accesses for each buffer segment) to access the 4 x 4.8 = 19.2 us (4 bus requests)
ring between the periods it is doing OMA burst. Therefore, this Ring access transfer (3 single OMA) =
additional time overhead reduces the allowable bus latency. 3 x 0.6 = 1.8 us (3 bus requests)
This is especially significant when short buffer sizes are as-
Ring access dwell time =
signed and long packets are in process.
2 x 2.0 = 4.0 us
NO DATA-CHAINING 64-byte transfer time from/to Ethernet cable to/from
When the buffers are not data-chained, the single OMA access Silo = 64 x 0.8 = 51.2 us
to the ring per packet may be disregarded especially for large 51.2 - (19.2 + 1.8 + 4.0)
packets. In the receive mode, words enter the Silo from the ALLOWABLE
Ethernet at the rate of eight words every 12.8 microseconds. BUS LATENCY 7 = 3.74 us
The LANCE transfers words from the Silo is 8=word bursts
requiring 4.8 microseconds per burst. Because of the lookahead overhead, the data-chained buffer
mode has less allowable bus latency than the single buffer
Therefore the allowable bus latency for LANCE is 12.8 minus mode which does not require data-chaining.
4.8 or 8 microseconds disregarding the single OMA access to
the descriptor ring per packet. 2.6 LANCE IN A DAISY-CHAIN
The size of the Silo provides some protection against a one CONFIGURATION
time unusual delay in granting the bus after a LANCE bus
It may be desirable to integrate the LANCE into a daisy-
request. The LANCE automatically requests the OMA bus as
chained environment (for example, Z-BUS). The BCON bit in
soon as eight words are in the Silo. The Silo may accumulate
CSR3 can be programmed for daisy-chain operation. As a
an additional sixteen words (32 b;1es) on a one time basis
result, Pins 15, 16, and 17 (BM 0 , BM 1. HOLD) will function as
before the LANCE becomes the bus master. This means that
BYTE, BUSAKO, and BUSRQ respectively. In a daisy chain
the bus latency is 25.6 us (32 x .8) for the first time that the
environment with pre-emption, the LANCE should be assigned
LANCE requests the bus. However, subsequent bus requests
to a high priority slot. This is necessary to meet the bus latency
must be granted within 8 us without fail to prevent a Silo over-
requirement under the worst case conditions.
flow. The 25.6 us bus latency can apply for one bus access at
any time that the Silo has eight or fewer words in it. In a daisy-chain environment without pre-emption (Zilog daisy-
chain), it is possible for a device, independent of slot position,
The eight microsecond bus latency corresponds to an ac-
to wait for the remainder of the devices in the chain to finish
cumulation of five words in the Silo. The bus latency may be
their bus accesses before it can request the bus again. (This
stretched by some amount when the packets are shorter.
can occur when the other devices request the bus at the same
time.) The impact to the LANCE is an underflow or overflow
WITH DATA-CHAINING
error condition if the LANCE bus latency requirement is not
When the buffers are data-chained, the overhead caused by the met. The addition of hardware, to provide preemptive OMA
lookahead operation in accessing the ring must be taken into capability and/or to enforce a bus time limit to the devices on
consideration in calculating the bus latency. This lookahead is the bus, may not be worthwhile if the probability of this happen-
performed between the periods in which the LANCE is doing ing in a normal system environment is reasonably low.
OMA bursts. It consists of three separate single OMA reads
when the LANCE owns the buffer. The LANCE does not initiate 2. 7 LANCE WITH 8-BIT
any OMA burst (8 OMA cycles) between the three single OMA
reads. MICROPROCESSORS
The lookahead operation may take as long as 5.8 Although the LANCE is a 16-bit device that interfaces easily to
microseconds plus three times the bus latency of a single OMA 16-bit microprocessors, it can also be interfaced to 8-bit micro-
read. This is calculated as follows: The dwell time (the time processors with some external logic.
interval between the LANCE's request to the bus to access the In integrating the LANCE with 8-bit microprocessors, there are
ring and the acquisition of the bus) is approximately 1.0 to 2.0 two possible configurations: 16-bit memory and 8-bit memory.
us for each access. Two ring accesses are required. Three ring Each solution has trade-offs in cost, performance, and com-
access transfers at .6 microseconds each are required. plexity of implementation. Each approach is considered below.
2-4
2.7.1 8-BIT MICROPROCESSORS WITH bandwidth is almost doubled. The LANCE must request the
8-BIT MEMORY bus once every 12.8 us, and since it takes 9.6 us to do an
8-word transfer, the LANCE thus takes up 75% of the bus
At a glance, this seems to be a simple and not too costly
bandwidth and the allowable bus latency is 3.2 usec.
implementation because it requires fewer memory chips.
However, as we will see later, the implementation can be quite The bus latency and bandwidth limitations can be overcome by
complex. designing a dual-port RAM shared by the 8-bit processor and
the LANCE. Some additional logic may be required to provide
For this interface to work properly, it takes twice as long to do
an 8-bit channel for use by the 8-bit processor, and a 16-bit
the data transfers as with 16-bit memories and a 16-bit micro-
channel to be used by the LANCE and any other 16-bit control-
processor. The data transfers are between the LANCE and
lers.
CPU (LANCE in Slave Mode), or the LANCE and 8-bit
memories (LANCE in Master Mode). The interface to the
2.7.2 8-BIT MICROPROCESSORS WITH
LANCE should look like a 16-bit interface. The OMA word
transfer cycle between the LANCE and the CPU or memory 16-BIT MEMORY
must be converted to two separate byte transfers. This type of Using a 16-bit memory is equivalent to having an 8-bit proces-
architecture degrades the system performance by one-half. sor on a 16-bit bus. The memory is normally organized into
lower and upper bytes. Although this approach is costly in
For some lower cost applications, this may not be a bottleneck.
terms of using twice as many memory chips, it is a better
However, it is important to note that the LANCE OMA transfer
solution in terms of performance and ease of implementation.
cycles take twice as long. Therefore, the potential of the
LANCE getting into an overflow or underflow error condition is This architecture is nearly equivalent to the LANCE being in-
increased, especially if the LANCE bus requests are not ac- terfaced to a 16-bit processor. The LANCE OMA cycles, bus
knowledged promptly. latency, and the bus bandwidth analysis are the same as those
discussed involving 16-bit microprocessors. There is still a
Bus latency for a 16-bit microprocessor interface is based on a
drawback in the area where the CPU has to access the
4.8 us OMA cycle. The 8-bit microprocessors must perform
LANCE. The CPU must go through two separate consecutive
twice as many OMA cycles as the 16-bit microprocessor,
cycles for every word transferred to the LANCE; however, this
therefore, the bus latency for the 8-bit microprocessors is
is not significant since the LANCE to CPU interface does not
based on 9.6 us OMA cycles (assuming that an 8-bit micropro-
require a fast response time. With enough receive buffers allo-
cessor runs as fast as a 16-bit which is not a safe assumption).
cated to the LANCE, the packets are received independently of
The allowable bus latency for an 8-bit microprocessor is
therefore less than for a 16-bit microprocessor and the bus the CPU's interrupt response time.
2-5
CHAPTER 3
LANCE-CPU INTERFACE CONSIDERATIONS
GENERAL LANCE INTERFACE 3.2 68000 TO LANCE INTERFACE
REQUIREMENTS The versatility of the LANCE makes it easier for the user to
The following is a list of key points to be considered in designs interface with demultiplexed buses. Figure 3-1 is an example of
using the LANCE: how to interface the 68000 to the LANCE. The goal of this
interface is compatibility with 8-MHz and faster 68000s while
• There are three open drain outputs on the LANCE. They are
minimizing parts count. The two flip-flops are needed to adapt
INTR (Pin 11 ), HOLD (Pin 17), and READY (Pin 22). These
the LANCE bus request handshake to the 68000.
signals must be pulled up external to the LANCE chip by 3.3k
or larger resistors. Auto-vectoring is used since the Am7990 does not return a
vector during Interrupt Acknowledge cycles. The BYTE and
• DAS and ALE are usually used as strobe signals. It would
DAS signals of LANCE are used to generate UDS and LOS
therefore be a good idea to pull them up to insure that a floating
when LANCE is in Bus Master Mode. It takes two latches to
level will not affect other circuits.
demultiplex the LANCE Address/Data Lines (DAL0-DAL15) to
• Decoupling capacitors with values of 0.1 and 5.0 uf are con- adapt it to the 68000 Address Bus. The user should program
nected, in parallel, from the Vee Pin of the LANCE to Ground. the BSWP, BCON to "1", and ACON to "O" in CSR3 when
• Voltage level on the RESET Pin of the LANCE should be initializing the LANCE. The AmPAL22V1 O device could also be
maintained at above 3.4 volts with a pull-up resistor. used to eliminate the two flip-flops shown in Figure 3-1.
3.1.1 LANCE INTERFACE TO POPULAR 3.2.1 68000 TO LANCE INTERFACE PAL
MICROPROCESSORS PAL 16L8 JOE BRCICH
PAT002 2 FEB 84
Several problems are associated with interfacing a peripheral File: 68K90.PAL
device to a CPU. One major problem involves the various con-
trol signals that each chip uses. Unless the two families are 68000 TO LANCE INTERFACE
ADVANCED MICRO DEVICES
designed to be pin-for-pin compatible, there are always going
to be minor variations between them. Part of the pin incom- I AS RW BYTE /HOLD NC /BG AO NC /BGACK GND
patibility involves genuine signal differences while other pins /CS /TB IUDS /DAS /CLR1 BR /CLR2 /LDS /RB VCC
only require name changes. Another problem with interfacing a
IF C/BGACK> RB= CS *RW*UDS +CS *RW*LDS; 68000 Master
general purpose peripheral to a CPU is the timing differences.
Most of these timing differences can be resolved by adding IF C/BGACK > TB =CS* /RW; 68000 Mast er
external logic. The Am7990 LANCE has been designed to be
IF (BGACK) UDS : DAS*/AO*BYTE + /BYTE 11 DAS
interfaced easily with the popular 16-bit microprocessors
(8086/80186, 68000, Z8000*, LSI-II**). Most of the interface IF (BGACK) LDS = DAS*AO*BYTE + /BYTE*DAS
logic is embedded in the chip and is program selectable.
IF (IBGACK) DAS : UDS*LDS
Although the LANCE itself has a multiplexed bus, it can easily
be interfaced to demultiplexed buses with a minimal amount of CLR1 = /A::>*BG
effort. This chapter discusses the interfaces to four popular
CLR2 : BGACK
16-bit microprocessors (68000, Z8001, 80186, and 8086).
These designs assume that the processor and the LANCE /8R : /HOLD
reside on the same board. Address buffers and data
transceivers are set up to be shared by the processor and the
LANCE. All of these designs use PAL*** devices to reduce the
parts count.
ZBOOO is a trademark of Zilog. Inc.
LSI-II is a registered trademark of Digital Equipment Corp.
*** PAL is a registered trademark of Monolithic Memories, Inc.
3-1
ADDRESS BUS DATA BUS
.,..... .,..... Vee
it it 11 ~ ~
~ ?
J l ~t
H
J
29827 29827 29863
A23-A16
5t A23-A16
ll ~· - ADR
A1s-A1
_il_ v
29809
J 29843
OE LE
k' 1
j "I --.--.
-" AD15-AD0
"'
015-Do v1-
'I
1 DALO
DALI
.
.,... Veel
: ..... cs
DTACK .... READY
AS ~ ALE
.___ DTACK FROM
SYSTEM
BR
- ~
Q D
CP
@_ t l •
- HLDA
68000 Ao /AS /CS/RB/TB
LANCE
PR Am7990
p-- BR
/CLR2 /HOLD ~ HOLD
-.... /BG ACK
BGACK
,-4:-, /DAS
.._.... DAS
f CP
PR
"CLR
o~ AmPAL16L8
68K90.PAL
L: /CLR 1
BG ..... /BG
UDS IUDS
LOS /LOS
RiW
IPlo
..
--r-
r-- l BYTE RW
~
r,
74LS t- READ
IPL1
148 t -
-
t-
r-- , , BYTE
;:::11
IPL2
~
TO SYSTEM
FCo
FC1
-
...... 74LS
--
INTR
138 INTA
FC2
VPA
--Q
Figure 3-1 68000 to LANCE Interface
06363A-6
3-2
3.3 Z8001 TO LANCE INTERFACE Interrupt Acknowledge cycle. The PAL device uses the status
lines ST3 -ST 0 (when Z8001 is the Bus Master) or HLDA from
The Z8001 interface to the LANCE is easily accomplished
the LANCE (when LANCE is the Bus Master) to generate M,
since both have a multiplexed bus and most of the control
the memory request signal. The user should program the
signals can be directly connected (see Figure 3-2). This design
ACON, BCON, and BSWP to "1" prior to initializing the
also uses the PAL device, AmPAL 16L8, to reduce the parts
LANCE. When the LANCE is Bus Master, DALI and DALO
count. The INTR pin of the LANCE is connected to the NVI pin
control the transceiver. When the CPU is Bus Master, T and R
of Z8001, since LANCE does not return a vector during the
are generated from Rfii and D S to control the transceiver.
ADDRESS DATA BUS
BUS
0 6 r-
L
r
Vee "T"" "T""
~ ~
[ Am29841 Am29841 I ....-t=f
>~ '7
-n
LE LE ;Am29863]
AD15-AD0
0
f'\i-
I
I I I I
I fl ~
ADR
DAL15-DAlo
.
-y
SNo-SNs A2rA1s
nJ TO SYSTEM DALI
[ 29806
h • j~ ~~ DALO
cs
/AS ...-- A5
...--..
--""' DAS
IDS
_
READ/ READ
Z8001
WRITE
•
/CELE /M /AS /OS READ IT IR
w
'
Vee - r
~
~
WAIT
--"""- /WAIT /READY - READY
ST3 ~
.
.
ST3
AmPAL16L8
t
READY FROM
ST2 ~ ST2
Z8K90.PAL SYSTEivi
LANCE
Am7990
ST1
STo
--.. -
~
ST1
STo Vee Vee
-r- ""T'"
/HLDA
• ~ ~
NVI
-"""- INTR
BUSRQ
BUSAK
-- ~
...
HOLD
HLDA
BiW BYTE
Vee
"T'"
~
~
RESET
--..._
~
-- RESET
Figure 3-2 Z8001 to LANCE Interface 06363A-7
3-3
3.3.1 Z8001 TO LANCE INTERFACE PAL 3.4.2 LANCE IN BUS MASTER MODE
AflPAL 16L8 RASOUL H. OSKOUY The LANCE enters the Bus Master Mode whenever the HOLD
PAT001 MARCH 13, 1984
and HLDA signals are both active. The READ and DAS out-
File: Z8K90.PAL
puts are used to generate separate R Dand WR signals to meet
Z8001 TO LANCE IUTERFACE the 186 system requirements. The DALI and the DALO out-
ADVANCED MICRO DEVICES puts of the LANCE are used to control the data transceivers.
The DAS signal asserted by the LANCE remains asserted until
/AS /HLDA READ /CS IDS /READY sn ST2 ST1 GND either the READY input is received or 25.6 us has elapsed
STO /T /M /<IAIT LE /R llC tlC NC VCC from the time DAS was asserted. The time-out error is noted in
CSRo (MERR=1) and the 186 is notified via interrupt.
IF /(HLDA) T /READ*/CS
IF (/l!LDA) R = READ*DS*/CS 3.4.3 186 TO LANCE INTERFACE PAL
PAL16L8 JOE BRCICH
M = /HLDA*ST3*/ST2*/ST1*/STO + PAT001 1 OCT 83
File: 186-90.PAL
/HLDA*/ST2*/ST1*STO +
80186 TO LANCE INTERFACE
/IILDA*ST3*ST2*/ST1 + ADVANCED MICRO DEVICES
HLDA ALE I AS DTR NC NC DEN NC /READY HLDA GND
/CS ARDY READ /R /T /DAS /<JR /RD LE VCC
WAIT = /READY
IF (IHLDA) DAS : RD + \.JR
/LE : AS
IF (IHLDA) /READ = DTR
3.3.2 DESCRIPTION
IF (/HLDA) T = DTR • /CS
Most of the Z8001 and Am7990 control signals can directly be
connected. The Z8001 status lines outputs, STO-ST3, and IF (/HLDA) R = /DTR 1 DEN*/CS
LANCE (Am7990) HLDA input are used to indicate whether
the cycle is a memory or non-memory cycle. The INTR pin of
IF CHLDA) RD = READ* DAS
LANCE is connected to NVI pin of Z8001, since the LANCE IF (llLDA) i/R = I READ 1 DAS
does not return a vector during the interrupt acknowledge
cycle. /LE = /ALE + /AS
Note: Program ACON. BCON, BSWP to "1" in CSR3 Reg. I ARDY = /READY
3.4 80186 TO LANCE INTERFACE 3.4.4 DESCRIPTION
This interface also uses a PAL design to reduce the parts This PAL design assumes that the 186 and LANCE are on the
count. The 80186/LANCE address and data buses can be con- same board. The data bus buffer is only enabled if the LANCE
nected directly together since they both have multiplexed is not selected. It seems natural to program the LANCE for ALE
buses. It seems natural to program the LANCE for ALE output. output. However, the PAL equations or indeed a discrete
However, the PAL equations or a discrete design are easier if design is easier if AS is used. This is because the LANCE
AS (CSR 3 , ACON=1) is used. This is because the LANCE three-states ALE while the 186 does not. Note that data is valid
three-states ALE, the 186 does not. The INTR, READY, and on the falling edge of WR in min mode meeting the apparent
HOLD signals from the LANCE are open-drain and should be requirement of the LANCE in early data sheets. Data set up
pulled up. The BM 1 signal from the LANCE or BHE from the time is specified with respect to the rising edge of DAS in later
186 along with Ao can be used to decode the data transfer type data sheets giving the designer more flexibility. All transfers to
(Word/Byte). The external address buffers and data or from the LANCE must be word transfers.
transceivers are enabled by the LANCE and the 186. The buf-
Note: Program ACON to "1," and BCON, BSWP to "O" in CSR3 REG.
fers and transceivers are enabled by whichever device is the
master. The user should program the BCON, BSWP to "O,"
and ACON to "1" in CSR3 . Figure 3-3 shows the 80186 to 3.5 8086 TO LANCE INTERFACE
LANCE interface connections. The LANCE interface to the 8086 and to the 80186 is quite
similar, except that the bus request handshake is different
3.4.1 LANCE IN BUS SLAVE MODE when 8086 is configured in maximum mode. The 8086 has a
The LANCE enters the Bus Slave Mode whenever the CS is bidirectional signal for both bus request and bus grant
active. In this example, the 186 becomes the master. RD or (RQ/GT). Both the bus request (RQ), and bus grant (GT)
WR of the 186 can be used to generate DAS which can be to/from 8086 are one CPU-clock wide and are synchronous to
deasserted after the LANCE asserts its READY output. The the CPU clock. Figure 3-4 shows a PAL design to do this
DTR and DEN of the 186 are used to control the data conversion. Figure 3-5 shows the interface timing for this PAL.
transceivers. When the LANCE is not selected, the DTR of 186 This PAL design could also be utilized to include other external
is used to generate the READ signal to the LANCE since DTR logic requirements for interfacing the LANCE to 8086.
stays valid (High for Read, Low for Write operation) during the
whole cycle.
3-4
ADDRESS DATA
BUS BUS
ADR
AD15-AD0 DAL15-DAL0
A19-A15 A19-A15
DALI
DALO
Vee
LE IT /R
ALE ALE /AS A'S
DT/R DTR /DAS DAS
RD /RD PAL16L8 READ READ
WR /WR 186/90.PAL
DEN DEN
ARDY ARDY /READY READv
HLDA /CS LANCE
80186
Am7990
HLDA HLDA
PCSo cs
SRDY I Vee READY
FROM SYSTEM
INTO INTR
BHE BM1
Vee
HOLD HOLD
RES RESET
06363A-8
Figure 3-3 80186 to LANCE Interface
3-5
8086 CLK - - - - - t ><>---,
CLK
AmPAL16R4
86/90.PAL
(8086) RQ/GT ~--<o-------~ GT HOLD 1 - 4 - - - HOLD (LANCE)
----1 R2 HLDA ---~ HLDA (LANCE)
(QC)
06363A-9
Figure 3-4 8086 RQ /GT, Am7990 HOLD/HLDA Conversion PAL
CLK
(INPUT)
HOLD
(INPUT)
Ffi (OUTPUT)
02 (OUTPUT)
R2 (OUTPUT)
RQGT (INPUT)
HLDA (OUTPUT)
Figure 3-5 AmPAL 16R4, 8086 (max. mode)/LANCE Interface Timing Diagram 06363A-10
3-6
3.5.1 8086 RQ/GT CONVERSION TO 3.5.2 DESCRIPTION
LANCE HOLD/HLDA PAL This PAL converts the request and grant (RQ/GT) of 8086,
AMPAL 16R4
when configured in maximum mode, to the LANCE Am7990
RASOUL OSKOUY
PATOOl MARCH 20, 1984 HOLD/HLDA. Both request (input to 8086) and grant (output
from 8086) are one clock wide and are synchronous to the
8086 RQ/GT CONVERSION TO LANCE HOLD/HLDA CPU clock.
ADVANCED MICRO DEVICES
CLK NC HOLD GT NC tlC NC NC NC GND
NC NC NC Hri5A 152 fi2 Rf NC NC V CC
Rl :: HOLD
D2 := RT
R2 : = R, • D2 + RT• D2
HLDA :: GT*ff2 + HLDA1t"fi2
3-7
CHAPTER 4
SOFTWARE CONSIDERATIONS
4.1 SOFTWARE TASKS CSR1 and CSR2 are normally not affected when the Stop bit is
set in CSRo. (When the Stop bit is set, CSR 3 is cleared and
First the LANCE interface with the system is checked out both
CSRo is set to 0004 Hex, Stop bit set.) However, it is recom-
in Bus Master and Bus Slave Mode, and the internal logic of
mended to reload CSR1 and CSR2 whenever the Stop bit is
the LANCE is tested in diagnostic mode for both internal and
set.
external loopback test. Then, the LANCE is configured for nor-
mal operation via the Initialization Block. The user normally The Initialization Block contains the parameters (Mode Regis-
initializes the LANCE once for normal operation. Any changes ter, Node Address, Logical Address Filter, Receive, and
in LANCE configuration require re-initialization. Transmit Descriptor Ring Pointers) needed for normal or diag-
nostic operation.
The data handling tasks include assigning and chaining data
buffers and checking the format rings for format errors. The flow chart shown in Figure 4-1 shows a typical initialization
Transmit and receive drivers are required to set up the transmit routine which starts by invoking the diagnostic operation with
and receive descriptors, buffer pointers, and related tasks. error loop capabilities and if the diagnostic passes are suc-
Status monitoring routines are also required. If re-initialization cessful, it initializes the LANCE for normal operation.
is necessary, the user must first process all the transmitted or
received packets and to rearrange the packets queued for 4.3 DIAGNOSTICS
transmission in the Transmit Ring. This is necessary since the The Mode Register Initialization Block can be used to set up
LANCE sets its pointers to the beginning of the Transmit and the LANCE for diagnostic or normal operation. There are four
Receive Rings upon initialization. user-programmable diagnostic modes. Each mode requires
The user must also process the interrupts and report the er- the user to change bits in the Mode Register and re-initialize
rors. the LANCE. The four modes are discussed in the following
order:
These tasks and the software support required are discussed
in the following order: 1. Internal Loopback
2. External Loopback.
Initialization
3. CRC Logic Check.
Diagnostics
4. Collision Detection and Retry Logic.
Main Program
Descriptors and Buffers
4.3.1 INTERNAL LOOPBACK
Interrupts
Transmit Drivers Although Ethernet is half-duplex, when in Loopback Mode the
Receive Drivers LANCE can operate in full-duplex by limiting the packet size to
Status Monitoring and Error Processing 8-32 bytes. The LANCE will not start the transmission of the
loopback packet unless the whole packet (up to 32 bytes) is in
The flow charts and discussion outlined below examine one the SILO. All the logic and data paths are tested in internal
approach to typical driver routines which may be used to oper- loopback except the transmit/receive drivers and receivers for
ate the LANCE. They are designed to guide the user in pro- the transmit data and receive data.
gramming the LANCE within a typical application. However,
the flowcharts are not intended as a direct implementation, The LCAR bit should not be set in internal loopback mode
which is system dependent. since the LANCE does not monitor the RENA signal input to
the LANCE. The LCAR bit is set when the sequence described
4.2 INITIALIZATION below happens:
The LANCE is initialized (configured) for a desired operation by a) The LANCE is initialized in internal loopback mode. The
programming the CSR registers (CSRo-3) and providing the loopback test can transmit and receive normally, as long as the
parameters required by the LANCE in the Initialization Block. transmit address matches the node address.
Refer to Chapter 1 for an overview of the system including the b) If at some point the LANCE transmits a non-matching
Initialization Block. For detailed information, refer to the packet, the packet will be sent but it will not be received. LCAR
LANCE data sheet. Initialization is a prerequisite for the (lost carrier) will be set.
LANCE operation in Bus Master mode. c) After transmitting a non-matching packet, the LANCE will no
Upon power-up or hardware reset, the internal logic of the longer transmit in internal loopback mode, even if the matching
LANCE is cleared, and the Stop bit in CSR 0 gets set. Once the address is put back. If the LANCE is then set-up to send a
Stop bit is set, either by a hardware reset or by software, all the matching or a non-matching packet, the LANCE reads the
activity in the LANCE stops. The Stop bit in CSRo must be set descriptors from the Transmit Ring and relinquishes the
prior to any access to CSR1-CSR3. ACON, BCON and BSWP descriptor to the CPU with LCAR bit set. It never DMAs data
bits in the CSR3 are programmed for the desired hardware into the SILO. It does not actually transmit the packet out.
interface. CSR1 and CSR2 get updated to contain the pointer Therefore, it does not receive the packet.
to Initialization Block. (Refer to LANCE data sheet for more
description on CSR registers.)
4-1
CSRo, <STOP> - 0 PROGRAM THE PROGRAM THE
STOP THE LANCE MODE REG~ MODE REG.
FOR INTERNAL FOR EXTERNAL
LOOPBACK LOOPBACK
PROGRAM CSR3
(ACON, BCON, BSWP)
INITIALIZE,
START LANCE
CSRo:
LOAD CSR1, CSR2 STRT, INIT, INEA:
INITIALIZATION
BLOCK
POINTER
TRANSMIT
1 SETUP
INITIALIZE TX, TEST PACKET
CSRo, STOP - 0
CLEAR LOGIC RX RINGS TRANSMISSION
DESCRIPTORS,
BUFFERS
PROGRAM
MODE REG.
FOR NORMAL
·----I ----,
: INITIALIZE CSR 0
NOTE1:
I
OPERATION I FIFOS POINTERS I
L---- ____ J ERROR
REPORT
ERRORS
INIT. & START SET TEST LOOP
LANCE COUNTER=4
CSRo <INIT.
STRT, INEA > - 1
N
y
STOP LANCE
CSRo:
STOP-1
NOTE 1: Optional step if CSR stacking is used. Not required for real time Interrupt Processing
Figure 4-1 Initialization/Diagnostic Flowchart (Sheet 1 of 2)
4-2
SET CRC LOOP = 2
COLLISION
LOGIC TEST
MODE <COLL
INTL, LOOP> - 1
PROGRAM PROGRAM
MODE REG. MODE REG.
DTCR-O DTCR - 1
DISABLE CRC DISABLE CRC
CHECK GENERATOR
INITIALIZE
AND START LANCE
CRCGEN. CSR 0 :
STRT, INIT. INEA = 1
GENERATE AND
APPEND PACKET
CRC
TRANSMIT
INITIALIZE START
LANCE SETUP TEST
CS Ro PACKETS FOR
STRT, INIT, INEA =
1 TRANSMISSION
TRANSMIT
SETUP TEST
PACKETS FOR
TRANSMISSION
N
y
N
N
DECREMENT CRC
LOOP COUNT
06363A-11
Figure 4-1 Initialization/Diagnostic Flowchart (Sheet 2 of 2)
4-3
In the internal loopback mode, when a packet is transmitted 4.3.4 COLLISION DETECTION/RETRY
that is not addressed to the node itself, LCAR is set and indi-
LOGIC TEST
cates this condition. If the address detection logic of the
LANCE is being tested for a non-matching test in internal loop- The collision detection can be tested by forcing collision, set-
back mode, the first non-matching transmit packet always gets ting the COLL, LOOP, and INTL bits of the Mode Register) to
transmitted. Only the packets following the transmission of the "1." The LANCE is then initialized and started (CSR 0 :
non-matching packet fall into this condition and never get INIT,STRT,INEA=1). The collision bit, COLL, being set will
transmitted. Re-initializing the LANCE is the only option when cause the LANCE to detect a collision on each loopback at-
this problem occurs. This problem will not occur as long as the tempt. The result is 16 total transmission attempts with a retry
LANCE is transmitting packets to itself (matching addresses) in error reported in TMD3.
internal loopback mode. The external loopback can be used for The SIA/transceiver collision interface to the LANCE is
testing the packets with non-matching addresses. checked by placing the LANCE in External Loopback. The
LANCE will look for a collision detection within 2 us following
4.3.2 EXTERNAL LOOPBACK the completion of a transmission. This is a transceiver self test
External Loopback operates in much the same fashion as Inter- feature which is known as SQE (Signal Quality Error) test or
nal Loopback, except that the test packet is actually transmit- "Heartbeat." The CERR bit gets set if the Heartbeat is missing
ted out, starting from the LANCE to the SIA, to the transceiver, within the specified time. The failure can be caused by the
and finally to the coaxial cable. The transmitted data wraps external collision path (transceiver-to-SIA-to-LANCE) and/or
around, in the same fashion, from the coaxial cable to the the transceiver itself.
LANCE. External Loopback test will not interfere with any other
node attached to the Ethernet cable, since the packet is nor- 4.4 MAIN PROGRAM
mally addressed to the node itself or gets discarded as a runt The LANCE is configured for normal operation via the initializa-
packet (loopback packet size max= 32 bytes). tion Block. LANCE is initilized once for normal operation.
The multicast addressing is not operational in External Loop- However, any configuration change requires re-initialization.
back Mode. The LANCE transmits the packet but it will not Figure 4-2 shows a flow diagram of the main program for nor-
receive it. However, DTCR (Disable Transmit CRC) in the mal operation.
Mode Register can be set to "1" when multicast addressing in
External Loopback Mode is desired. In this case, the user has 4.5 DESCRIPTOR AND BUFFER
to append the correct four byte CRC when transmitting a PITFALLS
packet or there will be a CRC error when the packet is
4.5.1 TRANSMIT MESSAGE DESCRIPTORS,
received. The multicast addressing can be tested in Internal
Loopback Mode, or Receive Mode when another node is TMD1 AND TMD3
transmitting. "One" flag in TMD1 is not valid when "LCOL" is set in TMD3.
4.5.2 TRANSMIT DESCRIPTOR RING
4.3.3 CRC GENERATOR/CHECKER LOGIC
FORMAT
TEST
When the LANCE is polling the Transmit Ring, it will skip over
During the loopback test (internal or external), the CRC logic Transmit Ring entries having a bad format. For the first buffer in
may be tested. Since the LANCE operates in half-duplex a packet, when the LANCE owns the buffer and STP (Start of
mode, the CRC generator or checker must be tested sepa- Packet) is not set, it will simply turn the ownership back over to
rately as follows. The Transmit CRC Generator is tested by the host. The LANCE will then generate a TINT interrupt and
programming DTCR=O in the Mode Register. This enables the go on to the next buffer. The LANCE continues to skip over
transmit CRC generation and disables the Receive CRC transmit buffers (by clearing the OWN bit and setting TINT bit)
Checker. Assuming the test packet is 32 bytes, the LANCE will until it finds a buffer with a good format (both STP and OWN bit
transmit 32 bytes and store 36 bytes of data in the receive set) to transmit. When the LANCE finds a transmit buffer
buffer. The extra four bytes are the CRC generated by Transmit owned by the host (OWN = 0), it means that there are no more
CRC Generator. The received CRC bytes are compared buffers to transmit.
against the software generated CRC.
The Receive CRC Checker is tested by setting the DTCR bit in 4.5.3 DATA CHAINING
the Mode Register. The user then calculates the CRC for the During either a receive or a transmit with data chaining, the
test packet and appends it to the end of the test packet for LANCE generates a done flag (Rll'JT or TINT) and interrupt
transmission (test packet max size= 32 + 4 bytes CRC). The only at the end of the chain. It will not generate any interrupt
Receive CRC Checker checks the last four bytes of the packet flags whenever a buffer of the chain is filled or transmitted,
for CRC error and updates the receive descriptors accordingly. unless there is an error. The ownership bits, however, are
The CRC logic may be tested in either External or Internal turned over to the host as each buffer is completed. This can
Loopback Mode. cause a problem if the first transmit buffer is short as explained
below.
4-4
MAIN PROGRAM
•
•
•
STOP LANCE
CSRo (STOP) - 1
INITIALIZE TX RING
CLEAR DESCRIPTORS
OWN BIT
INITIALIZE RX RING
-ALLOCATE BUFFERS
-SET DESCRIPTORS
OWN BIT
INITIALIZE CSR
TX DRIVE
SETUP INITIALIZATION SETUP
BLOCK IN MEMORY DESCRIPTORS
INTX RING
CSRo <INIT, STAT,
INEA> - 1
CSRo_STATUS I
PROCESS:
'
TX_STATUS
RX STATUS
EXIT
ERR_CSR0
06363A-12
Figure 4-2 Main Program for the LANCE in Normal Operation
4-5
4.5.4 TRANSMIT BUFFERS discards it. The LANCE backs up its internal receive ring ad-
dress pointer and byte count registers to their values at the
When in Transmit Mode, the LANCE can transfer up to 32 bytes
beginning of the reception so that it can use this buffer for the
of data into the Silo before transmission is started if the cable is
next packet. However, this buffer has already been turned over
busy at the time. A collision could occur at any time during the
to the host.
transmission of the first 64 bytes (first slot time). During this
transmission, 64 additional bytes could be read from the buffer. When the next packet arrives, the LANCE will reuse the buffer
Therefore, the first transmit buffer must be at least 96 bytes that it filled during the previous runt packet although it is now
long to ensure that the LANCE does not relinquish the first owned by the host. This violates the mutual exclusion rule of
buffer before it has sent the first 64 bytes of the packet over the the ring ownership bits.
Ethernet cable. Including a small extra margin, 100 bytes was If the host had been polling the ownership bits, it could have
chosen as the minimum size required for the first buffer when already used the data in that receive buffer although it was not
data chaining to ensure proper handling of collisions. valid data. The host expects the next receive packet to start at
At the beginning of a transmission, the LANCE internally stores the next receive buffer but the LANCE starts at the previous
the address and byte count of the first transmit ring entry, in buffer. If the next receive packet is a legal packet, the LANCE
case a retransmission is required. In data-chaining, after each will data chain at least two buffers because the first buffer is too
buffer is read into the Silo, the buffer is returned to the host by small. The host then starts looking at the second buffer of the
resetting the "own" bit. As explained above, if the first transmit chain because it has already serviced the previous buffer when
buffer is too short, a collision could occur after the first buffer the ownership bit was turned over during the previous runt
was completed and the ownership bit turned over to the host. packet. Under these conditions, the host will not see the ex-
pected packet format (the destination address, source ad-
Since a collision causes an automatic retry and since the
dress, etc.) in the receive buffer.
LANCE has the address of the first buffer, the LANCE will
attempt to retransmit the buffer that it had just given back to the
host. This violates the mutual exclusion rule of the ring owner-
4.6 INTERRUPTS
ship by accessing a ring entry that it does not own. This can The interrupt pin is simply an OR of the interrupt causing
also cause incorrect and unexpected transmit ring status conditions. The occurrence of another interrupt after the inter-
changes as follows: if the host is polling the ownership bit, it rupt pin is asserted does not generate another transition on the
would see ownership of the first transmit buffer and start to interrupt pin. Interfaces that require a transition per interrupt
service it. At the same time, the LANCE may be retransmitting may use the following software routine to force a transition on
it and even updating the status for that buffer. the interrupt pin.
When data-chaining is not used, the LANCE does not return READ CSRo AND STORE IN MEMORY OR A REGISTER
the buffer to the host until the entire packet has been sent CLEAR THE INTERRUPT ENABLE (BIT 06) IN THE
without collision or other error. Therefore, for buffers that are STORED CSRo
not data-chained, the minimum buffer size for the first buffer is
WRITE CSRo WITH THE STORED VALUE (BIT 06 IS NOW
the minimum packet size of 64 bytes required by Ethenet to
CLEAR)
ensure proper handling of collisions. However, the LANCE is
capable of transmitting a packet as small as one byte. SET THE INTERRUPT ENABLE BIT IN CSRo
To summarize, when the buffers are data chained in Transmit At the time the interrupt is first serviced, this routine first reads
Mode, the minimum size for the first transmit buffer is 100 CSRo to capture the register and store its value in memory or a
bytes. When the buffers are not data-chained, the minimum register. Then the stored value is written to CSRo with Bit 06
size for the transmit buffer is 64 bytes to conform to Ethernet clear, clearing the interrupt-causing conditions present at the
standards. These minimums prevent the LANCE from violating time the register was read. They are cleared because they are
the mutual exclusion principle of the ring ownership bits as a all "write-one-to-clear" bits. This clears out the old interrupt
result of a collision. The mutual exclusion rule states that the flags and preserves any new ones set after the register was
LANCE must not access a ring entry it does not own. The slot read. It causes the LANCE to deassert the interrupt pin be-
time is the time it takes to transmit 64 bytes over Ethernet. A cause interrupt enable is now clear. The last step is to set
collision can occur at any time during the first slot time. interrupt enable again. This must be done with a Write Only
instruction, such as MOVE, so that any new interrupt flags are
not cleared by a Read-Modify-Write operation. At this time, if
4.5.5 RECEIVE BUFFERS there were any new interrupt flags set after CSRo was first
The minimum size for the first receive buffer is specified as 64 read, the interrupt pin will be reasserted generating a new
bytes. If this spec is not adhered to, the LANCE could cause transition for the new interrupt flags.
the violation of the mutual exclusion principle of the ring owner- It is possible to have more than one interrupt-causing condition
ship bits. for each interrupt generated. For example, if an interrupt is
This happens if the receive buffers are less than 64 bytes each received and the RINT bit is set, there could have been more
and a packet that is larger than the first buffer but less than 64 than one receive buffer turned over to the host, because other
bytes (a runt packet) arrives. The LANCE fills the first buffer, receive buffers could have been filled before the host services
updates that buffer's status and turns over the ring ownership the interrupt. This is also true for transmit interrupts. In fact, a
to the host. When the packet terminates as a runt, the LANCE receive buffer could have been turned over to the host after a
4-6
transmit interrupt has been generated. This happens if a
transmit interrupt was generated, if the host software read
CSR 0 , and if a receive buffer was filled before the host soft-
ware finishes the transmit routine. Therefore, it is wise to check
both the Receive and Transmit Rings for buffers owned by the READCSRo
FROM LANCE
host whenever an interrupt occurs.
LANCE asserts the interrupt signal (INTR) every time it
updates the internal register, CSR0 , provided the INEA bit is
set. Interrupt remains asserted until one of the following condi- CLEAR INTERRUPT
tions is met: WRITE SAME CSRo
TO THE LANCE
1. Source of interrupt is removed.
2. RESETis asserted.
3. Stop bit gets set in CSRo.
SAVE CSRo
There are four types of interrupts noted in CSRo: CSRo FIFO - CSRo
1. Initialization done.
2. Fatal and non-fatal errors.
3. Receive Descriptor update.
ENABLE INTERRUPTS
4. Transmit Descriptor update.
It is important and necessary to acknowledge the interrupts in
real time so that the segment of the LANCE status being
RETURN
updated is not lost. This also enables the processing of
transmit and receive buffers promptly. 06363A-13
There is only one interrupt condition, MISS error, which re-
quires a response. When MISS error occurs, it must be cleared Figure 4-3 Interrupt Service Routine
by the user, or no more packets will be received, even if some
receive buffers have been relinquished to the LANCE. (The
MISS error requirement applies only to the LANCE Rev. B. The
LANCE Rev. C does not require the MISS bit to be cleared to The user should have two pointers associated with the
receive the following packets.) However, there is enough time Transmit Ring:
(67.2 us) between the MISS error bit getting set and the arrival
1. TXDESW - Transmit Descriptor Write Pointer
of another packet. The 67.2 us is measured based on back-to-
2. TXDESR - Transmit Descriptor Read Pointer
back short packets (64 bytes) addressed to this node, and the
size of the SILO (48 bytes). TXDESW points to the first descriptor of the packet queued for
transmission by the host (OWN=1, STP=1). TXDESR points
No other interrupt bits in CSRo will result in the loss of any
to the first descriptor of the packet just relinquished by the chip
packet. If interrupt is not serviced before the next interrupt
(OWN=O, TINT=1).
occurs, then the new status bits get ORed with the old ones
before CSRo is updated. It is possible for the user to lose the TXDESR and TXDESW originally point to the same location, to
sequence of status being updated. the beginning of the Transmit Ring. Once the packet transmis-
sion starts, the TXDESW pointer normally leads the TXDESR
The discussion below describes one way of handling a long
pointer. The user sets up the descriptors by flowing/wrapping
interrupt latency. Since some software overhead may be in-
around the ring, and LANCE chases the user sequentially to
volved in responding to the interrupts, a buffering scheme
send the buffers out.
(software FIFO) may be used to ensure that all the events are
recognized and serviced in the order of occurrence. Transmit data buffers are usually scattered around in the
memory. Before initiating a transmission, the user needs to
A software FIFO as large as Transmit/Receive Ring size is invoke the lower level transmit driver routine to change the size
allocated to store the CSR0 s in the order of interrupt occur-
of large and small buffers scheduled for transmission. One
rence. The interrupt service routine merely reads the CSRo
approach, as illustrated in Figure 4-4, is to shrink down the
and stores it for later processing by status processing routines
large buffers to 1500 bytes each and chain the small buffers
thus making it as short as possible. (See Figure 4-3.) This
together by taking advantage of LANCE's buffer management
approach will assure that all the events are captured in the data chaining scheme. Three types of lists can be associated
order of occurrence.
with transmit routines to transmit a large block of data (for
example, 10K bytes).
List 1:
4. 7 TRANSMIT DRIVER This list contains pointers to buffers (any location in memory),
CONSIDERATIONS with different buffer sizes (no limitation in buffer sizes), to be
transmitted as one block in the order defined sequentially in the
The host communicates with the LANCE, via the Transmit
list. LIST1 PTA is the pointer to this list. Each entry on the list
Ring, for packet transmission. There can be up to 128 descrip-
designates the buffer pointer and buffer size. End of list is
tor entries, four words per entry, in the Transmit Ring.
recognized by an end of list flag (for example, FFFF. .. ).
4-7
LIST 1: LIST2 LIST 3:
PACKET1 PTR
I I
LIST1 PTR......,. L IST2 PTR ___. ~
FILE1 ADR
i--- PACKET1 PTR DESC1 BUFF PTR
(24 BIT ADDRESS)
2 ENTRIES 2 ENTRIES
PER FILE
BUF~~~
FILE1 SIZE PACKET2 PTR
t---- DESC1 BUFF SIZE
(16 BIT ADDRESS)
•
~
~
FILE2 ADR
•
=
DESC2 BUFF PTR
FILE2 SIZE
PACKETM PTR 1--
I DESC2 BUFF SIZE
FILE3 ADR I- •
END OF LIST •
•
FILE3 SIZE I I DESC K BUFF PTR
•
• DESC K BUFF SIZE
•
FILE N ADR END OF LIST
FILE N SIZE
I I
I I PACKET2 PTR
END OF LIST
I • DESC1 BUFF PTR
DESC1 BUFF SIZE
DESC2 BUFF PTR
DESC2 BUFF SIZE
I 0
•
•
1
DESC I BUFF PTR
1 1
DESC I BUFF SIZE
END OF LIST
PACKETM PTR
I • DESC1 BUFF PTR
DESC1 BUFF SIZE
DESC2 BUFF PTR
DESC2 BUFF SIZE
•
•
0
DESC J BUFF PTR
DESC J BUFF SIZE
END OF LIST
06363A-14
Figure 4-4 Transmit Block Buffer Packing
4-8
List 2: NOTE
One of the transmit routines uses List 1 to generate List 2. As shown in the transmit routine flowchart, the user
Each entry on List 2 is a pointer to a packet (List 3). List 2 is a should not relinquish the descriptors (buffers) until all
translation of a block of data (List 1) with large and/or small the descriptors for the packet have been set up. (ENP
buffers to one or more packets. End of list is recognized by the bit is set in the last descriptor.) After the descriptors are
end of list flag (for example, FFFF. .. ). LIST2PTR is a pointer as set up, the user should clear the OWN bit of each
an input to the lower level transmit driver routine to transmit the descriptor in the reverse order (last descriptor first, first
whole block (all the packets in List 2). descriptor last). This technique will prevent transmit
List 3: buffer error (TMD3, BUFF error).
Each entry on this list designates the buffer pointer and the As shown in Figure 4-6, there are two variables, TXDESR and
buffer size (< = 1514 bytes; see Note 1) for each buffer that is TINTCNT, used for processing the packets that LANCE has
chained together to be transmitted as one packet. At the end of transmitted. TINTCNT corresponds to the number of packets
the packet, a list flag is used to designate the end of the list. that have been transmitted (times that the TINT bit has been
The lower level transmit driver routine transfers both the buffer set in CSRo) but not processed by the CPU to update their
pointers and buffer sizes directly to the transmit ring descrip- status. TXDESR is the pointer to the first descriptor of the
tors. The buffer pointed to by the first entry in list 3 must contain packet relinquished by the LANCE and not processed by the
the header information (source address, destination address, CPU. This mechanism is used to assure servicing the packets
and type (or length) field. in the order of transmission and to prevent TINT being set
NOTE 1 twice without the CPU awareness that two packets have been
transmitted by the LANCE.
The user should be cautious about address and type
field insertion for transmission of each packet. Since When checking for errors, the user needs to check both the
LANCE does not insert destination or source ad- ERR and BUFF bits, since the ERR does not include the BUFF
dresses or type field, the user must append the ad- error. When processing errors, BUFF or UFLO errors should
dress and type field ( 14 bytes) to the beginning of each be treated as fatal errors since these errors are due to a mal-
packet. function in hardware and/or software designed around the
The transmit driver routine, TXDRIVE, shown in Figure 4-5 LANCE and it is under user's control. LCOL error should also
uses LIST2PTR as the pointer to the packet list to set-up the be treated as a fatal error. In a maximum Ethernet configura-
transmit descriptors for transmission. Transmit driver routine tion, a collision might occur within the first 64 bytes of the
(Figure 4-5) and TX_ Status routine (Figure 4-6) keep track of packet but not beyond. LCOL error can also be due to a fault
(open or short) in the coaxial cable.
the two pointers, TXDESW and TXDESR by using a software
FIFO. The transmit driver routine writes the pointer, TXDESW, LCAR error can be due to a malfunction in the receive section
to the FIFO and the TX_Status routine reads the pointer, at the transceiver or fault between transceiver and SIA
TXDESR, from the FIFO. The FIFO size should be as large as (Receive ± pair) or SIA and LANCE (RENA input to the
the transmit ring size. This approach allows the transmission LANCE). The LANCE requires RENA to become and remain
process of the packet to be performed in the correct order and active before TENA is deasserted; otherwise an LCAR error
minimizes the software complexity of managing the Transmit will be set. If RENA drops out while transmitting (TENA High),
Ring. an LCAR error will get set and the LANCE will continue to
As pointed out earlier, the TXDESW pointer normally leads the transmit the packet. A fault (short) in the coaxial cable can also
cause an LCAR error.
TXDESR. If these two pointers point to the same location
(TXDESR = TXDESW), it is an indication of having either a The RTRY error is set when the LANCE attempts 16 times to
small ring (much less than 128) or the LANCE transmitter has transmit the packet and does not succeed. This error is less
been turned off because of some particular error(s). Should the likely to occur. However, this error can occur in a very heavily
transmitter shut off, the user is notified via interrupt. CSRo loaded network, a failure of a node in the network, or an open
Register, TXON Bit, may then be checked to see if the in the coaxial cable.
transmitter is on. As shown in the flowchart in Figure 4-6, after the packet has
The LANCE normally polls the Transmit Ring descriptor once been transmitted, in particular when the buffers are data
every 1.6 ms until it finds a packet (defined/addressed in the chained, the user should check the status of all descriptors for
descriptor) to be sent out. However, the user may demand errors (ERR bit). This is because RTRY error is updated in the
faster polling time (every 1-2 us) by continuously setting the first descriptor, and LCOL and UFLO can occur anywhere from
TDMD bit in CSR0 , after it gets cleared by the LANCE. The the first descriptor to the last descriptor of the packet. When
user should normally set the TDMD bit every time it relin- late collision occurs (LCOL=1), the LANCE continues to
quishes (sets the OWN bit) the first descriptor of a packet to the transmit the packet.
LANCE.
4-9
4
INITIALIZE
BYTES-o
•••
GETTXDESW,
TMD 1
"SMALL TX RING OR
BUSY NETWORK"
SET START OF PACKET
TMD1 <STP> - 1
2
LOAD TMDo, TMD1 WITH
BUFFER POINTER
TMDo, TMD1 - LIST2 PTR (PACKET PTR(1))
LOAD TMD2 WITH BUFFER SIZE
TMD2 - LIST2 PTR (PACKET PTR (2))
BYTES - TMD2 +
BYTES
NEXT DESCRIPTOR
TXDESW - TXDESW + 4
y
RESET TXDESW
TXDESW - TXBEG
Figure 4-5 Transmit Routine {TXDRIVE) to Setup Packets for Transmission (Sheet 1 of 2)
4-10
GETTXDESW, SAVE POINTER
TMD 1 TEMP - TXDESW
TMD1 <ENP> - 1
TMD1 <OWN> - 1
NEXT BUFFER FOR THIS
PACKET IN LIST 3
PACKET PTR(1) -
PACKET PTR(1) + 2
TMD1 <STP> - 0
BACKUP TO PREVIOUS
DESCRIPTOR TO
SET OWN BIT
TXDESW - TXDESWSP • 4
RESTORE POINTER
TXDESW - TEMP
INCREMENT /WRAPAROUND TO
THE NEXT DESCRIPTOR
TXDESW - TXDESW + 4/
TXDESW - TXBEG
NEXT PACKET IN LIST 2
LIST2 PTR - LIST2 PTR + 1
BYTES = No. of bytes In the packet
TXDESW = Transmit descriptor write pointer
TXBEG = Pointer to beginning of transmit ring
PACKET PTR(1) = Pointer to buffer address
PACKET PTR(2) =Pointer to buffer size
LIST2 PTR = Pointer to a packet entry In List 2
06363A-15
Figure 4-5 Transmit Routine (TXDRIVE) to Setup Packets for Transmission (Sheet 2 of 2)
4-11
TX-STATUS
FATAL ERROR
ADJUST TXDESR PTR INVALID ERROR
TXDESR - TXDESR + 4 CONDITION
WRAPAROUND IF END OF THE RING
STOP LANCE
CSRo <STOP> - 1
REARRANGE TX
AND RX RINGS
DESCRIPTORS
ADJUST TINTCNT
RE-INITIALIZE
TINTCNT - TINTCNT • 1 THE LANCE
TINTCNT =No. of TINT interrupts
TXDESR = Pointer to the first descriptor of the packet relinquished by the LANCE and not processed by the
CPU
TXBOT = Pointer to the bottom of the ring
TXBEG = Pointer to the beginning of the ring.
06363A-16
Figure 4-6 Transmit Packet Status Processing (TX-STATUS)
4-12
4.8 RECEIVE DRIVER RINTCNT variable shown in Figure 4-7 contains the number of
times that the RINT bit has been set in CSRo without being
CONSIDERATIONS
processed by the user. This value corresponds to the number
The host communicates with the LANCE, via the Receive Ring, of packets which have been received with or without the error
for packet reception. There can be up to 128 descriptor entries, and are awaiting processing. Figure 4-7 uses RINTCNT and
four words per entry, in the Receive Ring. RXDPTR to process back-to-back packets in the order of ar-
The user needs to allocate some buffers through the descriptor rivals.
entries in the Receive Ring for the arrival packets, if the As it implies in Figure 4-7, the user should start checking the
receiver is enabled (turned on via Initialization Block). Multiple RMD 1 of each descriptor until it finds either ENP or ERR bit
buffers with different sizes scattered around in the memory set. IF ERR bit is set and ENP bit is not, it indicates that an
may be allocated to the LANCE for reception. Receive driver error (such as BUFF or OVFL) occurred before the packet
routines and buffer management tasks can be relatively com- ended. If ENP bit is set, it indicates that the packet has ended
plex when the user needs to keep up with incoming back-to- (cable has gone idle) and the current descriptor is the last
back packets. descriptor for this packet. When ENP and ERR are both set, it
The user has 3 major tasks to handle at all times: is an indication that there is a CRC or both CRC and framing
error.
1. Respond fast enough to LANCE's OMA requests
2. Always have enough available receive buffers for arriving It is important to note that the LANCE interrupts the user when
packets it updates the last descriptor (clears the OWN bit) for current
3. Provide fast interrupt response time and short interrupt ser- received packet. It does not interrupt (does not set RINT) for
vice routine to capture/distinguish the events in the order of each descriptor update when the packet consists of multiple
occurrence for each packet. However, the packets will not descriptors.
be lost if interrupt processing is not in real time; CSRo When the LANCE interrupts the CPU due to RINT, packet
update is an OR operation of the new CSRo and the previ- reception, the user should clear the source of interrupt (here
ous CSRo. RINT bit) so that it can distinguish the arrival of the next packet
The user must keep track of the incoming receive packets, from the current one when RINT bit is set again.
process the packets (check status and empty buffers), and The minimum time (worst case) for the RINT bit to be set again
allocate enough available receive buffers to store all incoming is as follows: At the end of a packet reception from the cable,
packets. A global pointer associated with the Receive Ring is the Silo has 48 bytes for the LANCE to transfer into a buffer
needed to process the received packets sequentially in the before issuing a RINT. This transfer requires three OMA se-
order of arrival. This pointer, Received Descriptor Pointer quences of 4.8 us each plus two bus dwell times of .7 us. each
(RXDPTR), is used in RX-Status routine (Figure 4-7) to locate (bus request response time, HOLD to HLDA, is ignored) for a
the buffers for the received packet, check the integrity of the total of 15.8 us. However, the transfer does not start until after
packet, and update the value of RXDPTR (pointer to the first the interpacket gap time of 9.6 us followed by 6.4 us of
descriptor of the next packet). preamble time. The transfer starts just as the data from the
The node processor and the host CPU software may use a next packet starts to enter the Silo. In this case, the RINT bit is
semaphore approach to communicate with each other. This is set 15.8 us after the next packet starts to fill the Silo. If the
accomplished by allocating a software FIFO to be a Write Only worst case happens and the Silo overflows, another RINT in-
by the node processor, and a Read Only by the host CPU. This terrupt is issued for the error condition. The time required for
FIFO has multiple entries each of which contains two locations: the second RINT to occur is 22.6 us ( [ 48 x 0.8) - 15.8). This is
a pointer to the first descriptor for a packet (RXDPTR) and the the interrupt latency of the LANCE for RINT bit to get set again.
number of descriptors (buffers) for this packet (RXDPSNO). This worst case interrupt latency only applies if the LANCE is
The host CPU is interrupted by the node processor every time not assured of prompt response to DMA bus requests. If the
an entry is added to the list (FIFO). The host CPU, in return, LANCE OMA bus latency is eight us, and the LANCE requests
reads the entry from FIFO to empty the buffer(s) and relinquish the bus as soon as eight words are in the Silo, there will be a
the buffers to the LANCE using the RXDPTR and RXDESNO. maximum of thirteen words in the Silo when the end of the
This technique speeds up the received packet processing time packet arrives. The LANCE takes 4.8 us to transfer the first
and diminishes the probability of missing packets as a result of eight words and 6.5 us (5 x (.6 + .7)) to transfer the remaining
no receive buffers being available. five words, one word at a time for a total of 11.3 us before the
The data chaining scheme in the LANCE makes efficient use of first RINT is set.
the memory during the packet reception. It is practical to assign The packet intergap time is 9.6 us and the preamble is 6.4 us
small buffers (for example, 256 bytes) for receive buffers allo- for a total of 16 us before data from the next packet starts to fill
cated to the LANCE. With small buffers, there is less unused the empty Silo. If the LANCE now fails to acquire the OMA bus,
space in each buffer when storing packets that are short. For the Silo will overflow causing a second RINT 43.1 us after the
packets larger than the buffer, data-chaining is used. Storing first RINT (16 - 11.3 + 48 x .8). This is the interrupt latency
small packets in large buffers results in large unused and un- under these more reasonable conditions.
usable areas of memory and results in the data being in frag-
The errors associated with packet reception are BUFF, OVFL,
mented areas scattered around in the memory.
CRC, and FRAM errors. The packets are normally discarded
when any of these errors occur. Note that there may be an
OVFL error when there is a BUFF error.
4-13
RXDESNO-o
GET RXDPTR
TEMPLOC - RXDPTR
GET TEMPLOC <RMD1 >
FATAL ERROR
INVALID ERROR
CONDITION
STOP LANCE RXDESNO - RXDESNO + 1
CSRo <STOP> - 1 TEMPLOC - TEMPLOC + 4
(SOFT RESET) WRAPAROUND IF END OF THE RING
PROCESS ERRORS
BUFF, OVFL,
FRAM, CRC
N
GET TEMPLOC <RMD1 > DISCARD
REUSE THE
BUFFERS
SOFT FIFO - RXDPTR,
RXDESNO
NEXT FREE BUFFER
RXDPTR ...- TEMPLOC
RINTCNT - RINTCNT - 1
RINTCNT = No. of RINT Interrupts
RXDPTR = Pointer to the first descriptor of the packet received by the LANCE and not processed by the CPU
RXDESNO = No. of descriptors for the received packet
Soft FIFO = A software FIFO shared by the host and the node processor. It contains two entries per packet,
RXDPTR, RXDESNO has write only by the node processor and read only by the host CPU.
Figure 4-7 Receive Packet Status Processing 06363A-17
4-14
4.9 STATUS MONITORING AND gets set following transmission of the next packet. When the
LANCE/SIA is interfaced with a transceiver which does not
ERROR PROCESSING have the SOE Test function, the user simply ignores the exis-
CSRo_Status routine shown in Figure 4-8 monitors a software tence of the CERR bit. Typical application where SOE Test
FIFO used by the interrupt handler to save the contents of may not be desirable is in repeater designs.
CSRo after each interrupt (Figure 4-3). Each CSR 0 record is
checked for IDON, RINT, TINT, and ERR bits. If the ERR bit is 4.9.1 MISS ERROR
set, it calls another routine, ERR_CSR0 (Figure 4-9), to In the LANCE Rev. B, when a MISS error is set in CSRo. it
process the fatal and non-fatal errors. must be cleared immediately, or the next packets addressed to
The IDON bit, when set, indicates that the initialization of this node will not be received, even if some receive buffers
LANCE has been done. have been relinquished to the LANCE. The LANCE Rev. C
The counter variable, RINTCNT is incremented whenever does not require the MISS bit to be cleared to receive the
RINT is set. RINTCNT is monitored by the routine, RX-Status following packets.
(Figure 4-7). RX-Status uses RINTCNT to determine if any
receive packets need to be processed. The value of RINTCNT 4.9.2 RECEIVER and/or TRANSMITTER
corresponds to the number of packets which have been TURN OFF DUE to ERROR
received by the LANCE but have not been processed by the There are three types of error which cause the transmitter to be
CPU. Similarly, TX-Status routine uses TINTCNT to be able to turned off (CSRo, TXON=O):
process the results of the transmitted packets in the order of
(1) Memory error (MERR)
transmission.
(2) Underflow (UFLO)
TINTCNT corresponds to the number of packets to be pro- (3) Buffer error (BUFF)
cessed by the CPU which have been transmitted by the
The only type of error which causes the receiver to be turned
LANCE. The counter variable, TINTCNT is incremented off (CSR 0 , RXON=O) is a memory error (MERR). The chip has
whenever the TINT bit is set. TINTCNT is monitored by the
to be restarted in order to turn the transceiver and/or receiver
routine, TX-Status (Figure 4-6).
back on again. The easiest way to restart the LANCE is by
ERR_ CSRo routine shown in Figure 4-9 illustrates the typical setting the Stop bit and then setting the Start bit in CSRo. This
actions which users would normally take when processing the turns the receiver and transmitter on again because DRX and
errors. The errors, MERR and BABL should be recognized as DTX are still cleared in the Mode Register. However, setting
fatal errors. CERR and MISS are considered non-fatal errors. the Stop bit may cause some confusion for the user if the
MERR error indicates that the LANCE did not receive any LANCE is in the middle of a transmission or reception or if the
acknowledgement from the system (READY High) 25.6 us after buffers are data chained.
the start of the memory cycle. The problem can be the result of It is recommended that the LANCE be re-initialized, rather than
the LANCE accessing an invalid address (wrong buffer poin- setting the Start bit when it stops. Care must be applied when
ters might have been given to the LANCE in the descriptors) or stopping the LANCE because setting the STOP bit clears
it may be a memory interface problem between the LANCE, CSR3. CSR3 must be reprogrammed if it contained a non-zero
CPU, and memory. value before the LANCE was stopped. The LANCE can also be
BABL error occurs after the LANCE starts loading the 1519th re-initialized by setting the INIT bit, but this is not necessary
byte to the SILO (maximum Ethernet packet is 1518 bytes). unless a change of operating parameters is desired.
The LANCE continues to send the remainder of the packet
following 1518 bytes. When this error occurs, the user should
stop the transmission by setting the Stop bit in CSRo. It is the
4.10 PROGRAMMER ORGANIZATION
user's responsibility not to have the packet more than 1514 OF THE LANCE REGISTER
bytes (1514 if CRC is generated by the LANCE, DTCR=O; INFORMATION
1518 if CRC is to be generated by the user, DTCR=1). It is
The 8086 System register organization is different than the
worthwhile to mention that the LANCE can send up to 4K bytes
organization of 68000 registers. Therefore the programmer
(BCNT = 12 bits in TMD 2 ) for each packet where it sets the
needs to know the organization of the system to be used with
BABL error following 1518 bytes.
the LANCE so that the Initialization Block information and the
CERR (collision, heartbeat, or SOE Test error) is a transceiver Descriptor Ring entries are stored correctly.
test feature. During this test, CERR is set if the LANCE does
In a 16-bit word in the 68000 system, byte O consists of bits 8
not see the collision within 2.0 us after a chip initiated transmis-
thru 15 (the most significant bits) and byte 1 consists of bits o
sion. Most transceivers (IEEE 802.3/Ethernet compatible)
thru 7. The word, AD 80, in 68000 assembly code is stored in
have the SOE Test feature built in. Within some delay (less
memory as AD 80. This is the correct order of bytes for the
than 2.0 us) following a transmission, they send a 10.0 MHz
LANCE control registers.
signal on collision pair. In the LANCE/SIA application, the SIA
translates the 10.0 MHz differential signal to a TTL signal on
CLSN line to the LANCE. CERR error does not cause an inter-
rupt. The user can normally check CERR when the TINT bit
4-15
CSRo_STATUS
y
START THE LANCE
IF NOT READY STARTED
CSRo (STAT) - 1
y
ERR_CSRo
PROCESS ERRORS
y
RINT CNT - RINTCNT + 1
RX_ STATUS
PROCESS RECEIVED
PACKETS
y
TINTCNT - TINTCNT + 1
TX_STATUS
PROCESS TRANSMIT
PACKETS STATUS
OR
EXIT
06363A-18
Rgure 4-8 CSR 0 Status Processing
4-16
MISS=1 MERR=1 BABL=1
CERR=1
NOT ENOUGH RX FATAL ERROR FATAL ERROR
TRANSCEIVER WITH
BUFFERS, PACKET NON_SQE TEST LANCE-MEMORY
WASLOST- OR INTERFACE SOFTWARE
ALLOCATE RX BUFFERS PROBLEM PACKET SETUP OR
TRANSCEIVER/SIA
LANCE FATAL
COLLISION PATH
FAILURE ERROR
STOP LANCE
CSRo (STOP) - 1
LOG ERRORS
06363A-19
Figure 4-9 CSRo Error Bit Processor, ERR-CSRO
However, data must be serialized for transmission and The 8086 stores sixteen-bit words with the low order byte (byte
serialized data is handled as bytes rather than words. Serial O, bits 0-7) on an even byte boundary and byte 1 (the most
byte data in ascending order is stored in memory as byte 1 significant eight bits) on the next higher byte address. For ex-
(bytes 0-7) followed by byte O (bits 8-15). In serializing the ample, a data word stored in an 8086 register or in a program
data for transmission, the byte in the low-order bit positions is as AD 80, is stored in memory as 80 AD.
sent first. Therefore, the 68000 data being transmitted or The LANCE stores word data in its control registers in the
received must be byte-swapped. The LANCE has a byte- same order as it is stored in memory. It is the programmer's
swapping mechanism to perform this function. It is a control bit responsibility to store control information in the order needed
called BSWP in the Control and Status Register 3. When it is by the LANCE. Figures 4-13, 4-14, and 4-15 give an 8086
set to 1, the LANCE swaps the high and low bytes on OMA programmer's view of the LANCE Initialization Block and
data transfers between the Silo and memory. Descriptor Ring information. Figure 4-16 shows the relation-
Figures 4-10, 4-11, and 4-12 show the Initialization Block and ship between control data in an 8086 register, in memory, and
Descriptor Ring organization of control information required in in a LANCE register.
a 68000 program for proper functioning in the LANCE. Figure Because of the order that the 8086 stores bytes in memory
4-16 shows the relationship between control data in a 68000 during word transfers, no byte swapping of transmitted or
register, in memory, and in a LANCE register. Figure 4-17 received data is required when an 8086 system is used with
shows the relationship of serialized data and memory with and the LANCE. The BSWP control bit is set to zero.
without byte swapping.
4-17
Word , ... Byte 0-----11• ..,._ _ _ _ _ _ _ _ Byte 1 -------~
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 Bits
IADR + 0 PROM I Reserved J J 1NTL J I
DRTY COLL DTcR]_ LOOP J T DTX DRX Mode Word
}~~~~~~~
IADR + 2 PADR (bits 15:8) PADR (bits 7:0)
IADR + 4 PADR (bits 31 :24) PADR (bits 23:16)
Register
IADR + 6 PADR (bits 47:40) PADR (bits 39:32)
~~~i~:~s
l
IADR + 8 LADRF (bits 15:8) LADRF (bits 7:0)
IADR + 10 LADRF (bits 31 :24) LADRF (bits 23:16)
IADR + 12 Filter
LADRF (bits 47:40) LADRF (bits 39:32)
IADR + 14 LADRF (bits 63:56) LADRF (bits 55:48)
IADR + 16 RORA (bits 15:8) RORA (bits 7:0) Receive
Descriptor
IADR + 18 RLEN (31 :29) I Reserved RORA (bits 23:16) } Ring Pointer
IADR + 20 TORA (bits 15:8) TORA (bits 7:0) Transmit
IADR + 22 TLEN (31 :29) l Reserved TORA (bits 23:16) }
Descriptor
Ring Pointer
06363A-20
Figure 4-10. Initialization Block Organization in 68000 Assembly Code
Word
Address
i~-------- Byte 0---------~1""'•4.---- Byt~ 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O
•I Bits
RORA+ 0 RBADR (bits 15:8) RBADR (bits 7:0)
RORA+ 2 OWN 1 T l
ERR FRAM OFLO CRC l BUFF l STP l ENP RBADR (bits 23:16)
RORA+ 4 1J1J1J1 BCNT (bits 11 :8) BCNT (bits 7:0)
RORA+ 6 Reserved MCNT (bits 11 :8) MCNT (bits 7:0)
06363A-21
Figure 4-11. Receive Descriptor Ring Entry Organization in 68000 Assembly Code
Word ,........; . - - - - - - - - B y t e 0 --------•~li...4 . . .--- Byte 1 Jr I
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Bits
TORA+ 0 TBADR (bits 15:8) TBADR (bits 7:0)
TORA+ 2 OWN ERR Res MORE ONE I DEF I I STP ENP TBADR (bits 23:16)
TORA+ 4 1 1 1 1 BCNT (bits 11 :8) BCNT (bits 7:0)
TORA+ 6 BUFF UFLO RES LCOL LCARJ: RTRY I I TOR (9:8) TOR (bits 7:0)
06363A-22
Figure 4-12. Transmit Descriptor Ring Entry Organization in 68000 Assembly Code
4-18
Word ~1---~~~~~~-B~e1-~~~---~·.....1·4-----B~e0 •I
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bits
IAOR + 0 l INTLJ DRTYICOLLIDTCRILOOPI DTX I DRXIPROM I Reserved Mode Word
IAOR + 2 PADR (bits 7:0) PADR (bits 15:8)
Physical
IAOR + 4 PADR (bits 23:16) PADR (bits 31 :24) Address
} Register
IAOR + 6 PADR (bits 39:32) PADR (bits 47:40)
IAOR + 8 LADRF (bits 7:0) LADRF (bits 15:8)
Logical
IAOR + 10 LADRF (bits 23:16) LADRF (bits 31 :24) Address
Filter
I
IAOR + 12 LADRF (bits 39:32) LADRF (bits 47:40)
IAOR + 14 LADRF (bits 55:48) LADRF (bits 63:56)
IAOR + 16
IAOR + 18
RORA (bits 7:0)
RORA (bits 23:16) l
RORA (bits 15:8)
ALEN (31 :29) l Reserved } Receive
Descriptor
Ring Pointer
}
IAOR + 20 TORA (bits 7:0) TORA (bits 15:8) Transmit
IAOR + 22 TORA (bits 23:16) l TLEN (31 :29) l Reserved
Descriptor
Ring Pointer
06363A-23
Figure 4-13. Initialization Block Organization in 8086 Assembly Code
Word
Address
14
15
B~e1
14 13 12 11 10 9
•I ...
8 7 6 5 4
B~eo
3 2 0
•I Bits
RORA+ 0 RBADR (bits 7:0) RBADR (bits 15:8)
RORA+ 2 RBADR (bits 23:16) OWN ERR FRAM OFLO CRC BUFF STP ENP
RORA+ 4 BCNT (bits 7:0) BCNT (bits 11 :8)
RORA+ 6 MCNT (bits 7:0) Reserved MCNT (bits 11 :8)
06363A-24
Agure 4-14. Receive Descriptor Ring Entry Organization in 8086 Assembly Code
Word
Address
I... 15
1
14 13 12 11 10 9 8
..
B~e ----l·~l •t-------- B~e o - - - - - - -......1
7 6 5 4 3 2 o Bits
TORA+ 0 TBADR (bits 7:0) TBADR (bits 15:8)
TORA+ 2 TBADR (bits 23:16) OWN ERR RES MORE ONE I DEF I STP I ENP
TORA+ 4· BCNT (bits 7:0) 1 1 1 1 BCNT (bits 11 :8)
TORA+ 6 TOR (bits 7:0) BUFF UFLO RES LCOL LCAR RTRY I I TOR (9:8)
06363A-25
Figure 4-15. Transmit Descriptor Ring Entry Organization in 8086 Assembly Code
4-19
8086 TO THE LANCE 68000 TO THE LANCE
I INIT TLB: OW AD75 I I INIT TBL: DC.W 75ADH I
15 8 7 0 8 7
15 0
8086 REGISTER
68000 REGISTER I 75 I AD I
15 0 68000 MEMORY
15
I
rl I
75
8 7
AD
0
I
8086 MEMORY
15
75
r 8 7
AD
r
I
LANCE REGISTER
15
I
l I l I
75
8 7
AD
0
LANCE REGISTER I 75
I AD
06363A-26
Figure 4-16 Control Data Transfers Between the LANCE and CPU
8086 MEMORY 68000 MEMORY
NO BYTE SWAP WITH BYTE SWAP
(BSWP = 0) (BSWP = 1)
ODD EVEN EVEN
+ +
15 8 7 0 15 8 7
B
D
F
A
c
E
*
H G
SERIALIZED
DATA
TO/FROM SILO
>
06363A-27
Figure 4-17 Serial Data Storage in Memory
4-20
APPENDIX A
GLOSSARY
ACON ALE Control bit in CSR3 OMA The time required for the LANCE to transfer one
ADR Register Data/Address Port Select Cycle word over the OMA bus (600 ns plus any wait
states). In the burst mode, the LANCE transfers
ALE Address Latch Enable output pin on the LANCE
eight words in 4.8 us each time it acquires the
AS Address Strobe output for use by slave device OMA bus.
BABL Error flag in CSRo (more than 1518 bytes in one DRTY Disable Retry flag in Moter (allows only one
packet) transmission attempt)
BCNT Buffer Byte Count entries in RMD2 and TMD2 DAX Disable the Receiver bit in Mode Register
BCON Byte Control bit in CSR3 for Byte Mask and Hold DS Data Strobe on the Z8001
1/0 pins DTCR Disable Transmit CRC bit in Mode Register
BMo/BYTE Input/output select DTX Disable Transmitter bit in Mode Register
BSWP B9te Swap bit in CSR3 Daisy- A method of connecting bus master devices to
BUFF Buffer Error flag in RMD1 and TMD3 chain control interrupt priorities.
BUSAKO Bus request output in daisy chain configuration of Dwell The time interval between the LANCE's release
the LANCE. If the LANCE is requesting the bus time of the bus to the next bus request. It is the time
when it receives HLDA, BU SAKO remains high. interval that the HOLD line remains inactive.
Otherwise, BUSAKO is set low when HLDA
ENP End of Packet flag in RMD1 and TMD1
arrives.
ERR Error flag in descriptor rings, RMD1 and TMD1
BUSRQ Bus Request output pin on the LANCE used in
and in Am7990 Control and Status Register
daisy chain configuration (CSR3 BCON = 1).
CSRo ("or" of BABL, CERA, MISS, and MERA)
Bus Percentage of time a device holds and controls
Bandwidth the OMA bus. FIFO First In First Out data buffer (Silo)
Bus Allowable bus latency is the time a device can FRAM Framing Error flag in RMD1
Latency wait for the OMA bus after requesting it without HADA High Order 8 Address Bits of buffer described in
the loss of data or other functions. this entry of RMD1 or TMD1
Bus When a device has access to a OMA bus, it is a HLDA Hold Acknowledge input to the LANCE makes it
Master bus master. the bus master.
BM Byte Mask bits on the LANCE indicating which HOLD Bus Hold Request output asserted by the LANCE
byte(s) on the DAL lines are to be read or written when it requires the bus.
CERR Collision Error flag in CSRo IADR Low order 16 bits of address of Initialization
CLSN Collision logical input to the LANCE indicating Block in CSR 1, high order 8 bits in CSR2.
the presence of a 10.0 MHz differential signal in IDON Status bit in CSRo indicates initialization has
the collision pairs (collision ±)at the transceiver been done
interface cable INEA Interrupt Enable bit in CSRo enables the LANCE
COLL Force Collision bit in the Mode Register in the INTR output.
LANCE INIT Initialize flag in CSRo in the LANCE
CRC Cyclic Redundancy Check flag in RMD1 INT Interrupt
cs Chip Select input when asserted puts the LANCE INTL Internal Loopback flag in the Mode Register
into bus slave mode
INTR Interrupt flag in CSR 0 . Active when one or more
CSR Control and Status Registers in the LANCE of the CSRo status flags, BABL, IDON, MERA,
DAL Data/Address Line pins on the LANCE MISS, RINT, or TINT, are set.
DALI Data/Address Lines input control ISO International Standards Organization
DALO Data/Address Lines output control LADA Low Order 16 Address Bits of buffer of this
DAS Data Strobe is an input/output pin on the LANCE descriptor in RMD 0 and TMDo
used to distinguish the data portion of a bus LAD RF Logical Address Filter in Initialization Block. 64-
transfer from the address portion. bit mask for logical addresses
DEF Deferred flag in TMD1. Transmission deferred LANCE Local Area Network Controller for Ethernet
OMA Direct Memory Access (Am7990)
A-1
LCAR Loss of Carrier flag in TMD 3 ALEN Receive Ring Length
LCOL Late Collision flag in TM03 RQ/GT Request/Grant bus exchange handshake
Latency See Bus Latency RTRY Retry Error flag in TMD3 (transmitter failed in 16
LOOP Mode Register bit to control loopback for test attempts)
RW Read/Write Select
MCNT Message Byte Count entry in RM03
RX Receive Input
MERA Memory error flag in CSRo set when the LANCE
as a bus mastei has not ieceived READY within AXON Receiver On flag in CSAo
25.6 us after asserting the address on the DAL Runt A packet that is less than 64 bytes long
lines. RX Receive input bit stream to the LANCE
MISS Missed Packet flag in CSRo set when the
SIA Serial Interface Adapter
receiver loses a packet because no buffers are
STP Start of Packet flag in TMD1 and RMD 1
available.
More than one entry needed (to transmit packet) STAT Start bit in CSRo
MORE
flag in TMD1 Silo A 48-byte FIFO memory in the LANCE used to
transfer data between the local memory and the
OFLO Overflow Error flag in RMD 1. Received data lost.
serial interface adapter
ONE Exactly One Entry Needed (to transmit packet)
Slave The slave mode of the LANCE (CS asserted) is
flag in TMD1
Mode used to initialize the LANCE.
OWN Descriptor entry owner (host/chip) fiag in RMD1
STOP Control bit in CSRo when set s1ops all external
and TMD1
activity of the LANCE
PADR 48-bit Physical Address assigned to chip (entry in
T-state Timing cycle (100 ns) in the LANCE. One LANCE
Initialization Block)
OMA cycle consists of six T-states plus any re-
PAL Programmable Array Logic quired wait states.
PROM Promiscuous mode (accepts all incoming pack- TDMD Transmit Demand for OMA bus. Control bit in
ets) flag in Mode Register CSR 0 to bypass OMA wait time
RAM Random Access Memory TOR Time Domain Reflectometer flag in TMD3 in the
RAP Register Address Port (bus addressable register) LANCE
in LANCE TORA Transmit Descriptor Ring base address in In-
RAS Register Address Select itialization Block
ADP Data Port (bus addressable register) in the TENA Transmit Enable output on the LANCE used to
LANCE enable external transmit logic
RORA Receive Descriptor Ring base address entry in TINT Transmitter Interrupt flag in CSR0 set after the
Initialization Block LANCE has completed sending a packet and has
updated the Transmit Descriptor Ring. Also set if
READ Input/output pin on the LANCE. High in Bus Mas-
the transmission is stopped due to a failure.
ter mode is input to read DAL lines, low means
the LANCE has placed data on the DAL lines. TLEN Transmit Ring Length
The meaning is reversed in the Bus Slave mode. TMD Transmit Message Descriptor entry in Transmit
RENA Receive Enable input to the LANCE. Indicates Descriptor Ring
presence of carrier on the channel. TX Transmit (output)
RES Reserved TXON Transmitter On flag in CSRo
RESET Reset (Am7990 input) stops the LANCE opera- TX Transmit output bit stream on the LANCE
tion, clears its internal logic (CSRo and CSR3),
UFLO Underflow Error flag in TMD3
and sets it into idle state with STOP bit set in
CSRo.
RINT Receiver Interrupt flag in CSRo set after the
LANCE has received a packet and updated the
Receive Descriptor Ring. Also set if the reception
is stopped due to a failure.
A-2
APPENDIX B
8086 program for multicast addressing and hash filter.
6 SUBROUTINE TO SET A BIT IN THE HASH FILTEA FROM A
7 GIVEN ETHERNET LOGICAL ADDRESS
8 ON ENTRY SI POINTS TO THE LOGICAL ADDRESS WITH LSB FIRST
9 DI POINTS TO THE HASH FILTEA WITH LSB FIRST
10 ON RETURN SI POINTS TO THE BYTE AFTER THE LOGICAL ADDRESS
11 ALL OTHER REGISTERS ARE UNMODIFIED
12
13 PUBLIC SETHASH
14 ASSUME CS:CSE61
15 ;
16 = 1DB6 POLYL EQU 1DB6H ;CRC POLYNOMINAL TERMS
17 =04C1 POLYH EQU 04C1H
18 ;
19 0000 CSE61 SEGMENT PUBLIC 'CODE'
20 ;
21 0000 SETHASH PROC NEAR
22 0000 50 PUSH AX ;SAVE ALL REGISTERS
23 0001 53 PUSH BX
24 0002 51 PUSH ex
25 0003 52 PUSH DX
26 0004 55 PUSH BP
27
28 0005 B8 FFFF MOV AX,OFFFFH ;AX.DX = CRC ACCUMULATOR
29 0008 BA FFFF MOV DX,OFFFFH ;PRESET CRC ACCUMULATOR TO ALL 1' S
30 OOOB B5 03 MOV CH,3 ;CH = WORD COUNTER
31 ;
32 OOOD 8B 2C SETH10: MOV BP,[S1] ;GET A WORD OF ADDRESS
33 OOOF 83 C6 02 ADD Sl,2 ;POINT TO NEXT ADDRESS
34 0012 B1 10 MOV CL,16 ;CL = BIT COUNTER
35 ;
36 0014 8B DA SETH20: MOV BX.DX ;GET HIGH WORD OF CRC
37 0016 D1 C3 AOL BX,1 ;PUT CRC31 TO LSB
38 0018 33 DD XOR BX.BP ;COMBINE CRC31 WITH INCOMING BIT
39 001A D1 EO SAL AX,1 ;LEFT SHIFT CRC ACCUMULATOR
40 001C D1 D2 RCL DX,1
41 001E 81 E3 0001 AND BX,0001H ;BX = CONTROL BIT
42 0022 74 07 JZ SETH30 ;DO NOT XOR IF CONTROL BIT = 0
43
44 PERFORM XOR OPERATION WHEN CONTROL BIT= 1
45
46 0024 35 1D86 XOR AX,POLYL
47 0027 81 F2 04C1 XOR DX,POLYH
48 ;
49 002B OB C3 SETH30: OR AX.BX ;PUT CONTROL BIT IN CRCO
50 002D D1 CD ROA BP,1 ;ROTATE ADDRESS WORD
51 002F FE C9 DEC CL ;DECREMENT BIT COUNTER
52 0031 75 E1 JNZ SETH20
53 0033 FE CD DEC CH ;DECREMENT WORD COUNTER
54 0035 75 D6 JNZ SETH10
55
FORMATION OF CRC COMPLETE, AL CONTAINS THE REVERSED HASH
56
CODE
57
58 0037 B9 OOOA MOV CX,10
49 003A DO EO SETH40: SAL AL,1 ;REVERSE THE ORDER OF BITS IN AL
60 003C DO DC RCA AH,1 ;AND PUT IT IN AH
61 003E E2 FA LOOP SETH40
B-1
62
63 AH NOW CONTAINS THE HASH CODE
64
65 0040 BA DC MOV BL,AH ;BL= HASH CODE, BH IS ALREADY ZERO
66 0042 B1 03 MOV CL,3 ;DIVIDE HASH CODE BY B
67 0044 D2 EB SHA BL,CL ;TO GET TO THE CORRECT BYTE
6B 0046 BO 01 MOV AL,01H ;PRESET FILTEA BIT
69 004B BO E45 07 AND AH,7H ;EXTRACT BIT COUNT
70 004B BA CC MOV CL,AH
71 004D D2 EO SHL AL,CL ;SHIFT BIT TO CORRECT POSITION
72 004F OB 01 OR [DI+ BX],AL ;SET IN HASH FILTEA
73 0051 5D POP BP
74 0052 5A POP DX
75 0053 59 POP ex
76 0054 5B POP BX
77 0055 5B POP AX
7B 0056 C3 RET
79 ;
BO 0057 SET HASH ENDP
B1 ;
B2 0057 CSEG1 ENDS
83
B4 END
Basic computer program example to generate the hash filter, for multicast addressing, in the LANCE.
100 REM
110 REM PROGRAM TO GENERATE A HASH NUMBER GIVEN AN ETHERNET ADDRESS
120 REM
130 DEFINT A-Z
140 DIM A(47) : REM ETHERNET ADDRESS = 4B BITS
150 DIM C(32) : REM CRC REGISTER = 32 BITS
160 PRINT "ENTER STARTING ADDRESS'; : INPUT A$
170 IF LEN (A$) < > 12 THEN 160 : REM THE INPUT ADDRESS STARTING MUST BE 12 CHARS
1BO REM
190 REM UNPACK STARTING ADDRESS INTO ADDRESS ARRAY
200 REM
210 M= 0
220 FOR I = 0 TO 47 : A(I) = 0 : NEXT i
230 FOR N = 12 TO 1 STEP -1
240 Y$ =MID$ (A$,N,1)
250 IF Y$ = "O" THEN 420
260 IF Y$ = "1" THEN A(M) = 1 : GOTO 420
270 IF Y$ = "2" THEN A(M + 1) = 1 : GOTO 420
2BO IF Y$ = "3" THEN A(M + 1) = 1 : A(M) = 1 : GOTO 420
290 IF Y$ = "4" THEN A(M + 2) = 1 : GOTO 420
300 IF Y$ = "5" THEN A(M + 2) = 1 : A(M) = 1 : GOTO 420
310 IF Y$ = "6" THEN A(M + 2) = 1 : A(M + 1) = 1 : GOTO 420
320 IF Y$ = "7" THEN A(M + 2) = 1 : A(M + 1) = 1 : A(M) = 1 : GOTO 420
330 A(M + 3) = 1
340 IF Y$ = "B" THEN 420
350 IF Y$ = "9" THEN A(M) = 1 : GOTO 420
360 IF Y$ ="A" THEN A(M + 1) = 1 : GOTO 420
370 IF Y$ = "B" THEN A(M + 1) = 1 : A(M) = 1 : GOTO 420
3BO IF Y$ = "C" THEN A(M + 2) = 1 : GOTO 420
390 IF Y$ = "D" THEN A(M + 2) = 1 : A(M) = 1 : GOTO 420
400 IF Y$ = "E" THEN A(M + 2) = 1 : A(M + 1) = 1 : GOTO 420
410 IF Y$ = "F" THEN A(M + 2) = 1 : A(M + 1) = 1 : A(M) = 1
420 M=M+4
430 NEXT N
B-2
440 REM
450 REM PERFORM CRC ALGORITHM ON ARRAY A(0-47)
460 REM
470 FOR I = 0 TO 31 : C(I) = 1 : NEXT I
480 FOR N = 0 TO 47
490 REM LEFT CRC REGISTER BY 1
500 FOR I = 32 TO 1 STEP - 1 : C(I) = C(I - 1) : NEXT I
510 C(O) = 0
520 T = C(32) XOR A(N) : REM T = CONTROL BIT
530 IF T < > THEN 600 : REM JUMP IF CONTROL BIT = 0
540 C(1) = C(1) XOR 1 : C(2) = C(2) XOR 1 : C(4) = C(4) XOR 1
550 C(5) = C(5) XOR 1 : C(7) = C(7) XOR 1 : C(8) = C(8) XOR 1
560 C(10) = C(10) XOR 1 : C(11) = C(11) XOR 1 : C(12) = C(12) XOR 1
570 C(16) = C(16) XOR 1 : C(22) = C(22) XOR 1 : C(23) = C(23) XOR 1
580 C(26) = C(26) XOR 1
590 C(O)"' 1
600 NEXT N
610 REM
620 REM CRC COMPUTATION COMPLETE, EXTRACT HASH NUMBER FROM C(O) TO C(5)
630 REM
640 HH = 32*C(O) + 16*C(1) + 8*C(2) + 4*C(3) + 2*C(4) + C(5)
650 PRINT "THE HASH NUMBER FOR ";A$;" IS ";HH
660 GOTO 160
MAPPING OF LOGICAL ADDRESS TO FILTER MASK
LAF LAF Destination LAF LAF Destination
Reg Loe Address Accepted Reg Loe Address Accepted
Bits Bits
Set Dec (Hex} Set Dec (Hex}
0 0 0000 0000 0085 0 32 0000 0000 0021
1 0000 0000 OOA5 33 0000 0000 0001
L 2 0000 0000 OOE5 L 34 0000 0000 0041
A 3 0000 0000 OOC5 A 35 0000 0000 0071
F 4 0000 0000 0045 F 36 0000 0000 OOE1
I 5 I 0000 0000 0065 I 37 I 0000 0000 OOC1 I
0 6 0000 0000 0025 2 38 0000 0000 0081
7 0000 0000 0005 39 0000 0000 OOA1
8 0000 0000 002B 40 0000 0000 008F
9 0000 0000 OOOB 41 0000 0000 OOBF
10 0000 0000 004B 42 0000 0000 OOEF
11 0000 0000 006B 43 0000 0000 OOCF
12 0000 0000 OOEB 44 0000 0000 004F
13 0000 0000 OOCB 45 0000 0000 006F
14 0000 0000 008B 46 0000 0000 002F
15 15 0000 0000 OOBB 15 47 0000 0000 OOOF
0 16 0000 0000 OOC7 0 48 0000 0000 0063
17 0000 0000 OOE7 49 0000 0000 0043
18 0000 0000 OOA7 50 0000 0000 0003
19 0000 0000 0087 51 0000 0000 0023
L 20 0000 0000 0007 L 52 0000 0000 OOA3
A 21 0000 0000 0027 A 53 0000 0000 0083
F 22 0000 0000 0067 F 54 0000 0000 OOC3
23 0000 0000 0047 55 0000 0000 OOE3
1 24 0000 0000 0069 3 56 0000 0000 OOCO
25 0000 0000 0049 57 I 0000 0000 OOEO
26 0000 0000 0009 I 58 0000 0000 OOAO
27 0000 0000 0029 59 0000 0000 0080
28 0000 0000 OOA9 60 0000 0000 0000
29 0000 0000 0089 61 0000 0000 0020
30 0000 0000 OOC9 62 0000 0000 0060
15 31 0000 0000 OOE9 15 63 0000 0000 0040
B-3
Appendix C
External Loopback Test Flow Chart External Loopback Test Procedure
Due to the problem of Silo Pointer Mis-alignment in the
+
External Loopback
LANCE's External Loopback, the following gives the
terminology used and procedures recommended for
Test performing· the External Loopback Test.
Terminology:
LANCE Hard Effors:
These can be caused by External Loopback Silo Pointer
Mis-alignment (false Hard Error), or they can be real
Hard Errors in the network that the software can correct.
Examples of real Hard Errors are: LCAR, RTRY, CRC, FRAM,
No BABL, MISS,OFLO, BUFF.
LANCE Soft Effor:
This is a real error. It is not a result of External Loopback
Silo Pointer Mis-alignment, and the software must correct.
No The Soft Error is: CERR.
System Hard Errors:
N=N-1
These errors signal a hardware failure in the system.
Examples for this type of error are: MERA, UFLO.
These are not caused by External Loopback Silo
~Nol Pointer Mis-alignment.
~
I Testing Procedure:
1
l Log Error J
When a LANCE Hard Error occurs and the source
cannot be determined, repeat the External Loopback
Test until it passes; or until a real Hard Error, a Soft
Error, or a System Hard Error is found; or until it has
_J
continuously failed for a predetermined number of
times (N). The error in the last attempt is then logged.
076NW2 If a Soft error, or System Hard Error occurs, an error
handling routine will take the proper action and the
error is logged.
N = Max. number of times to repeat the test.
C-1
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