forked from arti/vt1200
SDD
9902722165
Root cause of the missing THRA write (HOST PORT test): the level-1 host-port
test's transmit is ISR-driven, and the DUART interrupt was never wired to the
CPU. The firmware installs RAM trampolines in the fixed vector table (INT1
vector 0xffffffc0 -> stub at bit 0x0f60 = JA 0x3FA92F40, which calls the DUART
ISR L3FA78D90 with (2, 0x270860, 0x6400000)). Counters: INTENB reaches 0x0006
(INT1|INT2) at the test, so interrupts are enabled.
vt1200.cpp: wire m_duart1/m_duart2 irq_cb() to CPU external interrupt 1/2
(duart1_irq_w/duart2_irq_w), gated on VT1200_DUART. Result: THRA writes go
from 0 to 20 per run; the test's SRA-overrun and RHRA-pattern checks now pass.
MAME tree (mc68681.cpp/.h), two datasheet-backed corrections with revert notes:
1. TxRDY was asserted mid-character ("not until the end of start bit time");
the datasheet asserts it at the THR->TSR transfer. Corrected.
2. The overrun error was latched when the overrunning character *completed*
(rx_fifo_push); the datasheet latches it "upon receipt of the start bit of
the new (overrunning) character". Corrected via duart_channel::rx_w().
This clears every check in the RXCHECK sub-test (flags 1 -> 0).
Acceptance is NOT met: cap.lua still prints 'LEVEL1/2 ERROR -> HOST PORT - 15'.
The next failure is the preceding L3FA71BC0 (DUART baud/timer) sub-test
returning 6; its flag-set sites were breakpointed and never fired. Regression
holds (no VT1200_* env -> PC=3FDCE400 samples=199). Details, numbers and the
datasheet audit: harness/mame/DUART_REPORT.md sections FINAL FINDINGS / UPDATE.
44 lines
1.4 KiB
Plaintext
44 lines
1.4 KiB
Plaintext
# DUART1 IRQ assert: ISR/SRA at the moment of the interrupt
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irq=1 isr=09 sra=0C cyc=43805849
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irq=1 isr=09 sra=0C cyc=43828170
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irq=1 isr=0A sra=01 cyc=43829472
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irq=1 isr=09 sra=0C cyc=43851789
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irq=1 isr=0A sra=01 cyc=43853091
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irq=1 isr=09 sra=0C cyc=43875408
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irq=1 isr=0A sra=01 cyc=43876710
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irq=1 isr=09 sra=0C cyc=43899027
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irq=1 isr=0A sra=01 cyc=43900330
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irq=1 isr=09 sra=0C cyc=43922647
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irq=1 isr=0A sra=01 cyc=43923948
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irq=1 isr=0C sra=00 cyc=43933971
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irq=1 isr=09 sra=0C cyc=44061742
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irq=1 isr=09 sra=0C cyc=44087969
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irq=1 isr=0A sra=01 cyc=44089271
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irq=1 isr=09 sra=0C cyc=44114193
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irq=1 isr=0A sra=01 cyc=44115495
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irq=1 isr=09 sra=0C cyc=44140416
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irq=1 isr=0A sra=01 cyc=44141718
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irq=1 isr=09 sra=0C cyc=44166640
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irq=1 isr=0A sra=01 cyc=44167942
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irq=1 isr=09 sra=0C cyc=44192863
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irq=1 isr=0A sra=01 cyc=44194166
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irq=1 isr=0C sra=00 cyc=44200001
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irq=1 isr=09 sra=0C cyc=44327797
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irq=1 isr=09 sra=0C cyc=44354024
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irq=1 isr=0A sra=21 cyc=44355326
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irq=1 isr=09 sra=0C cyc=44380248
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irq=1 isr=0A sra=21 cyc=44381550
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irq=1 isr=09 sra=0C cyc=44406471
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irq=1 isr=0A sra=21 cyc=44407773
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irq=1 isr=09 sra=0C cyc=44432695
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irq=1 isr=0A sra=01 cyc=44433997
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irq=1 isr=09 sra=0C cyc=44458918
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irq=1 isr=0A sra=01 cyc=44460221
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irq=1 isr=0C sra=00 cyc=44466068
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irq=1 isr=09 sra=0C cyc=44592754
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irq=1 isr=09 sra=0C cyc=44611168
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irq=1 isr=0B sra=0D cyc=44629580
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irq=1 isr=0B sra=0D cyc=44647992
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irq=1 isr=0B sra=0F cyc=44666403
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irq=1 isr=0B sra=0F cyc=44684815
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