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SDD 031d30da67 reference: DUART datasheet verification of the two mc68681 edits (claim 1 refuted) 
Download the SCN2681 (Philips 1995), SCC2681, SCN68681 and MC68HC681 UM
datasheets into reference/duart-datasheet/ with pdftotext extractions, and
audit each claimed justification against them:

  Claim 1 (TxRDY asserted in tra_complete, not tra_callback): REFUTED.
    The quoted p.7 sentence is real, but SCN2681 p.22 says explicitly
    'TxRDY sets at the end of the start bit time' -- which is exactly the
    removed upstream behaviour.  Upstream was right.

  Claim 2 (overrun latched on the start bit, not completion): CONFIRMED.
    'the overrun error status bit (SR[4]) will be set upon receipt of the
    start bit of the new (overrunning) character' (p.8, also SRA[4] p.14).
    Caveats: p.8 also says errors are 'strobed ... at the received
    character boundary' (internal tension); and a valid start bit is
    validated ~half a bit after the falling edge, not at it.

  Claim 3 (3-deep FIFO, 4th held, overrun on 5th; MAME faithful): CONFIRMED.
    'capacity of three characters' + 4th held in the shift register (p.8);
    MAME's SIZE+1 guard overruns exactly on the 5th.

Also snapshot the worker's uncommitted MAME diff and upstream 0.289 code.
2026-10-16 12:13:07 +03:00

1754 lines
151 KiB
Plaintext
Raw Blame History

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Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
DESCRIPTION • 16-bit programmable Counter/Timer
The Philips Semiconductors SCN2681 Dual Universal – Non-standard rates to 115.2Kb
Asynchronous Receiver/Transmitter (DUART) is a single-chip
– One user-defined rate derived from programmable
MOS-LSI communications device that provides two independent
timer/counter
full-duplex asynchronous receiver/transmitter channels in a single
package. It interfaces directly with microprocessors and may be – External 1X or 16X clock
used in a polled or interrupt driven system. • Parity, framing, and overrun error detection
The operating mode and data format of each channel can be • False start bit detection
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed • Line break detection and generation
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
• Programmable channel mode
counter/timer can operate directly from a crystal or from external – Normal (full-duplex)
clock inputs. The ability to independently program the operating – Automatic echo
speed of the receiver and transmitter make the DUART particularly – Local loopback
attractive for dual-speed channel applications such as clustered – Remote loopback
terminal systems.
• Multi-function programmable 16-bit counter/timer
Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven • Multi-function 7-bit input port
systems. In addition, a flow control capability is provided to disable – Can serve as clock or control inputs
a remote DUART transmitter when the buffer of the receiving device – Change of state detection on four inputs
is full.
– 100kΩ typical pull-up resistor
Also provided on the SCN2681 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
• Multi-function 8-bit output port
purpose I/O ports or can be assigned specific functions (such as – Individual bit set/reset capability
clock inputs or status/interrupt outputs) under program control. – Outputs can be programmed to be status/interrupt signals
The SCN2681 is available in three package versions: 40-pin and • Versatile interrupt system
28–pin, both 0.6” wide DIPs; a compact 24-pin 0.4” wide DIP; and a – Single interrupt output with eight maskable interrupting
44-pin PLCC. conditions
– Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
FEATURES
• Dual full-duplex asynchronous receiver/transmitter • Maximum data transfer: 1X – 1MB/sec, 16X – 125kB/sec
• Quadruple buffered receiver data registers • Automatic wake-up mode for multidrop applications
• Programmable data format • Start-end break interrupt/status
– 5 to 8 data bits plus parity • Detects break which originates in the middle of a character
– Odd, even, no parity or force parity • On-chip crystal oscillator
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
• Single +5V power supply
• Programmable baud rate for each receiver and transmitter • Commercial and industrial temperature ranges available
selectable from:
– 22 fixed rates: 50 to 115.2k baud • DIP and PLCC packages
ORDERING INFORMATION
ORDER CODE
Commercial Industrial
DESCRIPTION
VCC = +5V +5%, TA = 0°C to +70°C VCC = +5V +10%, TA = -40°C to +85°C
Ceramic DIP Plastic DIP Plastic LCC Ceramic DIP Plastic DIP Plastic LCC
24-Pin1 Not available SCN2681AC1N24 Not available Not available SCN2681AE1N24 Not available
28-Pin2 SCN2681AC1F28 SCN2681AC1N28 Not available SCN2681AE1F28 SCN2681AE1N28 Not available
40-Pin2 Not available SCN2681AC1N40 Not available SCN2681AE1F40 SCN2681AE1N40 Not available
44-Pin Not available Not available SCN2681AC1A44 Not available Not available SCN2681AE1A44
NOTES:
1. 400mil-wide Dual In-Line Package
2. 600mil-wide Dual In-Line Package
1995 May 1 1 853-1077 15179
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
PIN CONFIGURATIONS
A0 1 40 VCC
IP3 2 39 IP4
A1 3 38 IP5
IP1 4 37 IP6 A0 1 28 VCC
A1 2 27 IP2 A1 1 24 A0
A2 5 36 IP2
A2 3 26 CEN A2 2 23 VCC
A3 6 35 CEN
A3 4 25 RESET 3 22
IP0 7 34 RESET A3 CEN
WRN 5 24 X2 4 21
WRN 8 33 X2 WRN RESET
RDN 6 23 X1/CLK 5 20
RDN 9 32 X1/CLK RDN X1/CLK
RXDB 7 22 RXDA
RXDB 10 31 RXDA RXDB 6 19 RXDA
DIP DIP
DIP
TXDB 11 30 TXDA TXDB 8 21 TXDA
TXDB 7 18 TXDA
OP1 12 29 OP0 OP1 9 20 OP0
D1 8 17 D0
D1 10 19 D0
OP3 13 28 OP2 D3 9 16 D2
D3 11 18 D2
OP5 14 27 OP4 D5 10 15 D4
D5 12 17 D4
OP7 15 26 OP6
D7 11 14 D6
D1 16 25 D0 D7 13 16 D6
GND 12 13 INTRN
D3 17 24 D2 GND 14 15 INTRN
D5 18 23 D4
D7 19 22 D6
GND 20 21 INTRN
PIN/FUNCTION PIN/FUNCTION
INDEX 1 NC 23 NC
CORNER 2 A0 24 INTRN
6 1 40 3 IP3 25 D6
4 A1 26 D4
7 39 5 IP1 27 D2
6 A2 28 D0
7 A3 29 OP6
8 IP0 30 OP4
PLCC 9 WRN 31 OP2
10 RDN 32 OP0
11 RXDB 33 TXDA
12 NC 34 NC
13 TXDB 35 RXDA
17 29 14 OP1 36 X1/CLK
15 OP3 37 X2
18 28 16 OP5 38 RESET
17 OP7 39 CEN
TOP VIEW 18 D1 40 IP2
19 D3 41 IP6
20 D5 42 IP5
21 D7 43 IP4
22 GND 44 VCC
SD00084
1995 May 1 2
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
PIN DESCRIPTION
APPLICABLE
SYMBOL TYPE NAME AND FUNCTION
40/44 28 24
D0–D7 X X X I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status be-
tween the DUART and the CPU. D0 is the least significant bit.
CEN X X X I Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the
DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When
High, places the D0-D7 lines in the 3-State condition.
WRN X X X I Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into
the addressed register. The transfer occurs on the rising edge of the signal.
RDN X X X I Read Strobe: When Low and CEN is also Low, causes the contents of the addressed regis-
ter to be presented on the data bus. The read cycle begins on the falling edge of RDN.
A0–A3 X X X I Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET X X X I Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts
OP0–OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inac-
tive state, with the TxDA and TxDB outputs in the mark (High) state. Clears Test modes, sets
MR pointer to MR1.
INTRN X X X O Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more
of the eight maskable interrupting conditions are true.
X1/CLK X X X I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be
supplied at all times. When a crystal is used, a capacitor must be connected from this pin to
ground (see Figure 5).
X2 X X I Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must
be connected from this pin to ground (see Figure 5).
RxDA X X X I Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is
High, “space” is Low.
RxDB X X X I Channel B Receive Serial Data Input: The least significant bit is received first. “Mark” is
High, “space” is Low.
TxDA X X X O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first.
This output is held in the “mark” condition when the transmitter is disabled, idle or when oper-
ating in local loopback mode. “Mark” is High, “space” is Low.
TxDB X X X O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first.
This output is held in the “mark” condition when the transmitter is disabled, idle or when oper-
ating in local loopback mode. “Mark” is High, “space” is Low.
OP0 X X O Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can
be deactivated automatically on receive or transmit.
OP1 X X O Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can
be deactivated automatically on receive or transmit.
OP2 X O Output 2: General purpose output or Channel A transmitter 1X or 16X clock output, or Chan-
nel A receiver 1X clock output.
OP3 X O Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel
B transmitter 1X clock output, or Channel B receiver 1X clock output.
OP4 X O Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYA/FFULLA
output.
OP5 X O Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYB/FFULLB
output.
OP6 X O Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYA output.
OP7 X O Output 7: General purpose output or Channel B open-drain, active-Low, TxRDYB output.
IP0 X I Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN).
IP1 X I Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN).
IP2 X X I Input 2: General purpose input or counter/timer external clock input.
IP3 X I Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When
the external clock is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock.
IP4 X I Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock.
1995 May 1 3
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
PIN DESCRIPTION (Continued)
APPLICABLE
SYMBOL TYPE NAME AND FUNCTION
40/44 28 24
IP5 X I Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When
the external clock is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock.
IP6 X I Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock.
VCC X X I Power Supply: +5V supply input.
GND X X I Ground
ABSOLUTE MAXIMUM RATINGS1
SYMBOL PARAMETER RATING UNIT
TA Operating ambient temperature range2 See Note 4 °C
TSTG Storage temperature range -65 to +150 °C
All voltages with respect to ground3 -0.5 to +6.0 V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150oC maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
supply range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SYMBOL PARAMETER TEST CONDITIONS UNIT
Min Typ Max
VIL Input low voltage 0.8 V
VIH Input high voltage (except X1/CLK)5 2 V
VIH Input high voltage (except X1/CLK)4 2.5 V
VIH Input high voltage (X1/CLK) IOL = 2.4mA 4 V
VOL Output low voltage IOH = -400µA 0.4 V
VOH Output high voltage (except o.d. outputs)5 2.4 V
VOH Output high voltage (except o.d. outputs)4 IOH = -400µA 2.9 V
IIL Input leakage current VIN = 0 to VCC -10 10 µA
ILL Data bus 3-stage leakage current VO = 0.4 to VCC -10 10 µA
IX1L X1/CLK low input current VIN = 0, X2 grounded -4 -2 0 mA
VIN = 0, X2 floated -3 -1.5 0 mA
IX1H X1/CLK high input current VIN = VCC, X2 grounded -1 0.2 1 mA
VIN = VCC, X2 floated 0 3.5 10 mA
IX2L X2 low input current VIN = 0, X1/CLK floated -100 -30 0 µA
IX2H X2 high input current VIN = VCC, X1/CLK floated 0 +30 100 µA
IOC Open-collector output leakage current VO = 0.4 to VCC -10 10 µA
IOCC Power supply current
0°C to +70°C version 150 mA
-40°C to +85°C version 175 mA
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages
of 0.8V and 2.0V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. TA < 0°C
5. TA > 0°C
1995 May 1 4
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
AC CHARACTERISTICS TA = -55°C to +125°C1, VCC = +5.0V + 10%2, 3, 4, 5
LIMITS
SYMBOL PARAMETER UNIT
Min Typ Max
Reset Timing (Figure 1)
tRES RESET pulse width 200 ns
Bus Timing (Figure )6
tAS A0-A3 setup time to RDN, WRN Low 10 ns
tAH A0-A3 hold time from RDN, WRN Low 100 ns
tCS CEN setup time to RDN, WRN Low 0 ns
tCH CEN hold time from RDN, WRN High 0 ns
tRW WRN, RDN pulse width 225 ns
tDD Data valid after RDN Low 175 ns
tDF Data bus floating after RDN High 100 ns
tDS Data setup time before WRN High 100 ns
tDH Data hold time after WRN High 20 ns
tRWD High time between READs and/or WRITE7, 8 200 ns
Port Timing (Figure 3)6
tPS Port input setup time before RDN Low 0 ns
tPH Port input hold time after RDN High 0 ns
tPD Port output valid after WRN High 400 ns
Interrupt Timing (Figure 4)
tIR INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt) 300 ns
Write THR (TxRDY interrupt) 300 ns
Reset command (delta break interrupt) 300 ns
Stop C/T command (counter interrupt) 300 ns
Read IPCR (input port change interrupt) 300 ns
Write IMR (clear of interrupt mask bit) 300 ns
Clock Timing (Figure 5)10
tCLK X1/CLK High or Low time 100 ns
fCLK X1/CLK frequency 2.0 3.6864 4.0 MHz
tCTC CTCLK (IP2) High or Low time 100 ns
fCTC CTCLK (IP2) frequency 0 4.0 MHz
tRX9 RxC High or Low time 220 ns
fRX9 RxC frequency (16X) 0 2.0 MHz
(1X) 0 1.0 MHz
tTX9 TxC High or Low time 220 ns
fTX9 TxC frequency (16X) 0 2.0 MHz
(1X) 0 1.0 MHz
Transmitter Timing (Figure 6)
tTXD9 TxD output delay from TxC Low 350 ns
tTCS9 Output delay from TxC Low to TxD data output 0 150 ns
Receiver Timing (Figure 7)
tRXS9 RxD data setup time to RxC High 240 ns
tRXH9 RxD data hold time from RxC High 200 ns
NOTES:
1. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.
2. Parameters are valid over specified temperature range.
3. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of < 20ns. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V
and 2.0V as appropriate.
4. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
5. Test condition for outputs: CL = 150pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC.
6. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN, CEN and RDN (also CEN and WRN) are ANDed
internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
8. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
9. This parameter is not applicable to the 28-pin device.
10. Operation to 0MHz is assured by design. However, operation at low frequencies is not tested and has not been characterized.
1995 May 1 5
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
BLOCK DIAGRAM
8 CHANNEL A
D0–D7 BUS BUFFER
TRANSMIT TxDA
HOLDING REG
TRANSMIT
SHIFT REGISTER
RDN OPERATION CONTROL
RECEIVE
WRN ADDRESS HOLDING REG (3)
CEN DECODE RxDA
4 RECEIVE
A0–A3 SHIFT REGISTER
R/W CONTROL
RESET
MRA1, 2
CRA
SRA
INTERRUPT CONTROL
INTRN IMR TxDB
CHANNEL B
ISR (AS ABOVE)
RxDB
INTERNAL DATABUS
INPUT PORT
CONTROL
CHANGE OF
TIMING
TIMING STATE
DETECTORS (4) 7
IP0-IP6
BAUD RATE
GENERATOR IPCR
ACR
CLOCK
SELECTORS
COUNTER/ OUTPUT PORT
TIMER
FUNCTION 8
SELECT LOGIC OP0-OP7
X1/CLK
XTAL OSC
X2 OPCR
OPR
CSRA
CSRB
ACR
CTUR
CTLR VCC
GND
SD00085
BLOCK DIAGRAM Operation Control
The SCN2681 DUART consists of the following eight major sections: The operation control logic receives operation commands from the
data bus buffer, operation control, interrupt control, timing, CPU and generates appropriate signals to internal sections to
communications Channels A and B, input port and output port. control device operation. It contains address decoding and read and
Refer to the block diagram. write circuits to permit communications with the microprocessor via
the data bus buffer.
Data Bus Buffer
The data bus buffer provides the interface between the external and Interrupt Control
internal data buses. It is controlled by the operation control block to A single active-Low interrupt output (INTRN) is provided which is
allow read and write operations to take place between the controlling activated upon the occurrence of any of eight internal events.
CPU and the DUART. Associated with the interrupt system are the Interrupt Mask Register
1995 May 1 6
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
(IMR) and the Interrupt Status Register (ISR). The IMR may be the clock input is 3.6864MHz). The detection circuitry, in order to
programmed to select only certain conditions to cause INTRN to be guarantee that a true change in level has occurred, requires two
asserted. The ISR can be read by the CPU to determine all successive samples at the new logic level be observed. As a
currently active interrupting conditions. consequence, the minimum duration of the signal change is 25µs if
the transition occurs “coincident with the first sample pulse”. The
Outputs OP3-OP7 can be programmed to provide discrete interrupt
50µs time refers to the situation in which the change-of-state is “just
outputs for the transmitter, receivers, and counter/timer.
missed” and the first change-of-state is not detected until 25µs later.
Timing Circuits Input Port
The timing block consists of a crystal oscillator, a baud rate
The inputs to this unlatched 7-bit port can be read by the CPU by
generator, a programmable 16-bit counter/timer, and four clock
performing a read operation at address D16. A High input results in
selectors. The crystal oscillator operates directly from a 3.6864MHz
a logic 1 while a Low input results in a logic 0. D7 will always read
crystal connected across the X1/CLK and X2 inputs. If an external
as a logic 1. The pins of this port can also serve as auxiliary inputs
clock of the appropriate frequency is available, it may be connected
to certain portions of the DUART logic.
to X1/CLK. The clock serves as the basic timing reference for the
Baud Rate Generator (BRG), the counter/timer, and other internal Four change-of-state detectors are provided which are associated
circuits. A clock signal within the limits specified in the with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High
specifications section of this data sheet must always be supplied to transition of these inputs lasting longer than 25 – 50µs, will set the
the DUART. corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
If an external clock is used instead of a crystal, both X1 and X2
can also be programmed to generate an interrupt to the CPU.
should use a configuration similar to the one in Figure 5.
The baud rate generator operates from the oscillator or external Output Port
clock input and is capable of generating 18 commonly used data The output port pins may be controlled by the OPR, OPCR, MR and
communications baud rates ranging from 50 to 38.4k baud. The CR registers. Via appropriate programming they may be just
clock outputs from the BRG are at 16X the actual baud rate. The another parallel port to external circuits, or they may represent many
counter/timer can be used as a timer to produce a 16X clock for any internal conditions of the UART. When this 8-bit port is used as a
other baud rate by counting down the crystal clock or an external general purpose output port, the output port pins drive a state which
clock. The four clock selectors allow the independent selection, for is the complement of the Output Port Register (OPR). OPR(n) = 1
each receiver and transmitter, of any of these baud rates or external results in OP(n) = Low and vice versa. Bits of the OPR can be
timing signal. individually set and reset. A bit is set by performing a write operation
at address E16 with the accompanying data specifying the bits to be
Counter/Timer (C/T) set (1 = set, 0 = no change).
The counter timer is a 16-bit programmable divider that operates in
Likewise, a bit is reset by a write at address F16 with the
one of three modes: counter, timer, time out. In the timer mode it
accompanying data specifying the bits to be reset (1 = reset, 0 = no
generates a square wave. In the counter mode it generates a time
change).
delay. In the time out mode it monitors the time between received
characters. The C/T uses the numbers loaded into the Outputs can be also individually assigned specific functions by
Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper appropriate programming of the Channel A mode registers (MR1A,
Register (CTUR) as its divisor. MR2A), the Channel B mode registers (MR1B, MR2B), and the
Output Port Configuration Register (OPCR).
The counter timer is controlled with six commands: Start/Stop C/T,
Read/Write Counter/Timer lower register and Read/Write
Counter/Timer upper register. These commands have slight TRANSMITTER OPERATION
differences depending on the mode of operation. Please see the The SCN2681 is conditioned to transmit data when the transmitter is
detail of the commands under the CTLR/CTUR Register enabled through the command register. The SCN2681 indicates to
descriptions. the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
Communications Channels A and B generate an interrupt request at OP6 or OP7 and INTRN. When a
Each communications channel of the SCN2681 comprises a character is loaded into the Transmit Holding Register (THR), the
full-duplex asynchronous receiver/transmitter (UART). The above conditions are negated. Data is transferred from the holding
operating frequency for each receiver and transmitter can be register to transmit shift register when it is idle or has completed
selected independently from the baud rate generator, the counter transmission of the previous character. The TxRDY conditions are
timer, or from an external input. then asserted again which means one full character time of buffering
is provided. Characters cannot be loaded into the THR while the
The transmitter accepts parallel data from the CPU, converts it to a
transmitter is disabled.
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD The transmitter converts the parallel data from the CPU to a serial
output pin. The receiver accepts serial data on the RxD pin, bit stream on the TxD output pin. It automatically sends a start bit
converts this serial input to parallel format, checks for start bit, stop followed by the programmed number of data bits, an optional parity
bit, parity bit (if any), or break condition and sends an assembled bit, and the programmed number of stop bits. The least significant
character to the CPU. bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the THR, the TxD output remains High
The input port pulse detection circuitry uses a 38.4kHz sampling
and the TxEMT bit in the Status Register (SR) will be set to 1.
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25µs (this assumes that
1995 May 1 7
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
Transmission resumes and the TxEMT bit is cleared when the CPU positions are filled with data. Either of these bits can be selected to
loads a new character into the THR. cause an interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated
If the transmitter is disabled, it continues operating until the
status bits (see below) are ‘popped’ thus emptying a FIFO position
character currently being transmitted is completely sent out. The
for new data.
transmitter can be forced to send a continuous Low condition by
issuing a send break command. Receiver Status Bits
The transmitter can be reset through a software command. If it is In addition to the data word, three status bits (parity error, framing
reset, operation ceases immediately and the transmitter must be error, and received break) are also appended to each data character
enabled through the command register before resuming operation. in the FIFO (overrun is not). Status can be provided in two ways, as
If CTS operation is enable, the CTSN input must be Low in order for programmed by the error mode control bit in the mode register. In
the character to be transmitted. If it goes High in the middle of a the ‘character’ mode, status is provided on a character-by-character
transmission, the character in the shift register is transmitted and basis; the status applies only to the character at the top of the FIFO.
TxDA then remains in the marking state until CTSN goes Low. The In the ‘block’ mode, the status provided in the SR for these three bits
transmitter can also control the deactivation of the RTSN output. If is the logical-OR of the status for all characters coming to the top of
programmed, the RTSN output will be reset one bit time after the the FIFO since the last ‘reset error’ command was issued. In either
character in the transmit shift register and transmit holding register mode reading the SR does not affect the FIFO. The FIFO is
(if any) are completely transmitted, if the transmitter has been ‘popped’ only when the RHR is read. Therefore the status register
disabled. should be read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is
Receiver
held in the receive shift register until a FIFO position is available. If
The SCN2681 is conditioned to receive data when enabled through
an additional character is received while this state exits, the
the command register. The receiver looks for a High-to-Low
contents of the FIFO are not affected; the character previously in the
(mark-to-space) transition of the start bit on the RxD input pin. If a
shift register is lost and the overrun error status bit (SR[4] will be
transition is detected, the state of the RxD pin is sampled each 16X
set-upon receipt of the start bit of the new (overrunning) character).
clock for 7 1/2 clocks (16X clock mode) or at the next rising edge of
the bit time clock (1X clock mode). If RxD is sampled High, the start The receiver can control the deactivation of RTS. If programmed to
bit is invalid and the search for a valid start bit begins again. If RxD operate in this mode, the RTSN output will be negated when a valid
is still Low, a valid start bit is assumed and the receiver continues to start bit was received and the FIFO is full. When a FIFO position
sample the input at one bit time intervals at the theoretical center of becomes available, the RTSN output will be re-asserted
the bit, until the proper number of data bits and parity bit (if any) automatically. This feature can be used to prevent an overrun, in
have been assembled, and one stop bit has been detected. The the receiver, by connecting the RTSN output to the CTSN input of
least significant bit is received first. The data is then transferred to the transmitting device.
the Receive Holding Register (RHR) and the RxRDY bit in the SR is
set to a 1. This condition can be programmed to generate an Receiver Reset and Disable
interrupt at OP4 or OP5 and INTRN. If the character length is less Receiver disable stops the receiver immediately – data being
than eight bits, the most significant unused bits in the RHR are set to assembled if the receiver shift register is lost. Data and status in the
zero. FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
After the stop bit is detected, the receiver will immediately look for characters at the next start bit detected.
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains Low for one half A receiver reset will discard the present shift register data, reset the
of the bit period after the stop bit was sampled, then the receiver receiver ready bit (RxRDY), clear the status of the byte at the top of
operates as if a new start bit transition had been detected at that the FIFO and re-align the FIFO read/write pointers. This has the
point (one-half bit time after the stop bit was sampled). appearance of “clearing or flushing” the receiver FIFO. In fact, the
FIFO is NEVER cleared! The data in the FIFO remains valid until
The parity error, framing error, overrun error and received break overwritten by another received character. Because of this,
state (if any) are strobed into the SR at the received character erroneous reading or extra reads of the receiver FIFO will miss-align
boundary, before the RxRDY status bit is set. If a break condition is the FIFO pointers and result in the reading of previously read data.
detected (RxD is Low for the entire character including the stop bit), A receiver reset will re-align the pointers.
a character consisting of all zeros will be loaded into the RHR and
the received break bit in the SR is set to 1. The RxD input must Multidrop Mode
return to high for two (2) clock edges of the X1 crystal clock for the The DUART is equipped with a wake up mode for multidrop
receiver to recognize the end of the break condition and begin the applications. This mode is selected by programming bits MR1A[4:3]
search for a start bit. This will usually require a high time of one or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this
X1 clock period or 3 X1 edges since the clock of the controller mode of operation, a ‘master’ station transmits an address character
is not synchronous to the X1 clock. followed by data characters for the addressed ‘slave’ station. The
slave stations, with receivers that are normally disabled, examine
Receiver FIFO the received data stream and ‘wake up’ the CPU (by setting RxRDY)
The RHR consists of a First-In-First-Out (FIFO) stack with a only upon receipt of an address character. The CPU compares the
capacity of three characters. Data is loaded from the receive shift received address to its station address and enables the receiver if it
register into the topmost empty position of the FIFO. The RxRDY bit wishes to receive the subsequent data characters. Upon receipt of
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all three stack
1995 May 1 8
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
another address character, the CPU may disable the receiver to while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position,
initiate the process again. which identifies the corresponding data bits as an address. The
CPU should program the mode register prior to loading the
A transmitted character consists of a start bit, the programmed
corresponding data bits into the THR.
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted In this mode, the receiver continuously looks at the received data
A/D bit is selected by the CPU by programming bit stream, whether it is enabled or disabled. If disabled, it sets the
MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the RxRDY status bit and loads the character into the RHR FIFO if the
A/D bit position, which identifies the corresponding data bits as data
Table 1. SCN2681 Register Addressing
A3 A2 A1 A0 READ (RDN = 0) WRITE (WRN = 0)
0 0 0 0 Mode Register A (MR1A, MR2A) Mode Register A (MR1A, MR2A)
0 0 0 1 Status Register A (SRA) Clock Select Register A (CSRA)
0 0 1 0 BRG Test * Command Register A (CRA)
0 0 1 1 Rx Holding Register A (RHRA) Tx Holding Register A (THRA)
0 1 0 0 Input Port Change Register (IPCR) Aux. Control Register (ACR)
0 1 0 1 Interrupt Status Register (ISR) Interrupt Mask Register (IMR)
0 1 1 0 Counter/Timer Upper (CTU) C/T Upper Register (CRUR)
0 1 1 1 Counter/Timer Lower (CTL) C/T Lower Register (CTLR)
1 0 0 0 Mode Register B (MR1B, MR2B) Mode Register B (MR1B, MR2B)
1 0 0 1 Status Register B (SRB) Clock Select Register B (CSRB)
1 0 1 0 1X/16X Test Command Register B (CRB)
1 0 1 1 Rx Holding Register B (RHRB) Tx Holding Register B (THRB)
1 1 0 0 *Reserved* *Reserved*
1 1 0 1 Input Port Output Port Conf. Register (OPCR)
1 1 1 0 Start Counter Command Set Output Port Bits Command
1 1 1 1 Stop Counter Command Reset Output Port Bits Command
* See Table 5 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” Philips Semiconductors ICs for Data Communications, IC-19, 1994.
received A/D bit is a one (address tag), but discards the received character. In general, the contents of the MR, the CSR, and the
character if the received A/D bit is a zero (data tag). If enabled, all OPCR should only be changed while the receiver(s) and
received characters are transferred to the CPU via the RHR. In transmitter(s) are not enabled, and certain changes to the ACR
either case, the data bits are loaded into the data FIFO while the should only be made while the C/T is stopped.
A/D bit is loaded into the status FIFO position normally used for
Mode registers 1 and 2 of each channel are accessed via
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
independent auxiliary pointers. The pointer is set to MR1x by
break detect operate normally whether or not the receive is enabled.
RESET or by issuing a ‘reset pointer’ command via the
corresponding command register. Any read or write of the mode
PROGRAMMING register while the pointer is at MR1x, switches the pointer to MR2x.
The operation of the DUART is programmed by writing control words The pointer then remains at MR2x, so that subsequent accesses are
into the appropriate registers. Operational feedback is provided via always to MR2x unless the pointer is reset to MR1x as described
status registers which can be read by the CPU. The addressing of above.
the registers is described in Table 1.
Mode, command, clock select, and status registers are duplicated
The contents of certain control registers are initialized to zero on for each channel to provide total independent operation and control.
RESET. Care should be exercised if the contents of a register are Refer to Table 2 for register bit descriptions. The reserved
changed during operation, since certain changes may cause registers at addresses H‘02’ and H‘OA’ should never be read during
operational problems. normal operation since they are reserved for internal diagnostics.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
1995 May 1 9
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
Table 2. Register Bit Formats
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RxRTS RxINT ERROR PARITY BITS PER
PARITY MODE
CONTROL SELECT MODE* TYPE CHARACTER
MR1A
MR1B 0 = No 0 = RxRDY 0 = Char 00 = With Parity 0 = Even 00 = 5
1 = Yes 1 = FFULL 1 = Block 01 = Force Parity 1 = Odd 01 = 6
10 = No Parity 10 = 7
11 = Multidrop Mode 11 = 8
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TxRTS CTS
CHANNEL MODE STOP BIT LENGTH*
CONTROL ENABLE Tx
MR2A
MR2B 00 = Normal 0 = No 0 = No 0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813
01 = Auto-Echo 1 = Yes 1 = Yes 1 = 0.625 5 = 0.875 9 = 1.625 D = 1.875
10 = Local loop 2 = 0.688 6 = 0.938 A = 1.688 E = 1.938
11 = Remote loop 3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
NOTE:
*Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CSRA RECEIVER CLOCK SELECT TRANSMITTER CLOCK SELECT
CSRB
See Text See Text
NOTE:
* See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” Philips Semiconductors ICs for Data
Communications, IC-19, 1994.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CRA MISCELLANEOUS COMMANDS DISABLE Tx ENABLE Tx DISABLE Rx ENABLE Rx
CRB Not used – See Text 0 = No 0 = No 0 = No 0 = No
should be 0 1 = Yes 1 = Yes 1 = Yes 1 = Yes
NOTE:
*Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter cannot
be loaded.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RECEIVED FRAMING PARITY OVERRUN
SRA TxEMT TxRDY FFULL RxRDY
BREAK* ERROR* ERROR* ERROR
SRB
0 = No 0 = No 0 = No 0 = No 0 = No 0 = No 0 = No 0 = No
1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes
NOTE:
* These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from
the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are discarded
when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using the error
reset command (command 4x) or a receiver reset.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OP7 OP6 OP5 OP4 OP3 OP2
OPCR 0 = OPR[7] 0 = OPR[6] 0 = OPR[5] 0 = OPR[4] 00 = OPR[3] 00 = OPR[2]
1 = TxRDYB 1 = TxRDYA 1 = RxRDY/ 1 = RxRDY/ 01 = C/T OUTPUT 01 = TxCA(16x)
FFULLB FFULLA 10 = TxCB(1x) 10 = TxCA(1x)
11 = RxCB(1x) 11 = RxCA(1x)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BRG SET COUNTER/TIMER DELTA DELTA DELTA DELTA
ACR SELECT MODE AND SOURCE IP 3 INT IP 2 INT IP 1 INT IP 0 INT
0 = set 1 0 = Off 0 = Off 0 = Off 0 = Off
See Table 4
1 = set 2 1 = On 1 = On 1 = On 1 = On
1995 May 1 10
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
Table 2. Register Bit Formats (Continued)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DELTA DELTA DELTA DELTA
IP 3 IP 2 IP 1 IP 0
IPCR IP 3 IP 2 IP 1 IP 0
0 = No 0 = No 0 = No 0 = No 0 = Low 0 = Low 0 = Low 0 = Low
1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = High 1 = High 1 = High 1 = High
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
INPUT
DELTA RxRDY/ COUNTER DELTA RxRDY/
PORT TxRDYB TxRDYA
ISR BREAK B FFULLB READY BREAK A FFULLA
CHANGE
0 = No 0 = No 0 = No 0 = No 0 = No 0 = No 0 = No 0 = No
1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IN. PORT DELTA RxRDY/ COUNTER DELTA RxRDY/
TxRDYB TxRDYA
CHANGE BREAK B FFULLB READY BREAK A FFULLA
IMR INT INT
INT INT INT INT INT INT
0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off
1 = On 1 = On 1 = On 1 = On 1 = On 1 = On 1 = On 1 = On
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CTUR C/T[15] C/T[14] C/T[13] C/T[12] C/T[11] C/T[10] C/T[9] C/T[8]
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CTLR C/T[7] C/T[6] C/T[5] C/T[4] C/T[3] C/T[2] C/T[1] C/T[0]
MR1A – Channel A Mode Register 1 MR1A[4:3| – Channel A Parity Mode Select
MR1A is accessed when the Channel A MR pointer points to MR1. If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
The pointer is set to MR1 by RESET or by a ‘set pointer’ command transmitted character and the receiver performs a parity check on
applied via CRA. After reading or writing MR1A, the pointer will incoming data MR1A[4:3] + 11 selects Channel A to operate in the
point to MR2A. special multidrop mode described in the Operation section.
MR1A[7] – Channel A Receiver Request-to-Send Control MR1A[2] – Channel A Parity Type Select
This bit controls the deactivation of the RTSAN output (OP0) by the This bit selects the parity type (odd or even) if the ‘with parity’ mode
receiver. This output is normally asserted by setting OPR[0] and is programmed by MR1A[4:3], and the polarity of the forced parity bit
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be if the ‘force parity’ mode is programmed. It has no effect if the ‘no
negated upon receipt of a valid start bit if the Channel A FIFO is full. parity’ mode is programmed. In the special multidrop mode it
However, OPR[0] is not reset and RTSAN will be asserted again selects the polarity of the A/D bit.
when an empty FIFO position is available. This feature can be used
MR1A[1:0] – Channel A Bits Per Character Select
for flow control to prevent overrun in the receiver by using the
This field selects the number of data bits per character to be
RTSAN output signal to control the CTSN input of the transmitting
transmitted and received. The character length does not include the
device.
start, parity, and stop bits.
MR1A[6] – Channel A Receiver Interrupt Select
This bit selects either the Channel A receiver ready status (RxRDY) MR2A – Channel A Mode Register 2
or the Channel A FIFO full status (FFULL) to be used for CPU MR2A is accessed when the Channel A MR pointer points to MR2,
interrupts. It also causes the selected bit to be output on OP4 if it is which occurs after any access to MR1A. Accesses to MR2A do not
programmed as an interrupt output via the OPCR. change the pointer.
MR1A[5] – Channel A Error Mode Select MR2A[7:6] – Channel A Mode Select
This bit select the operating mode of the three FIFOed status bits Each channel of the DUART can operate in one of four modes.
(FE, PE, received break) for Channel A. In the ‘character’ mode, MR2A[7:6] = 00 is the normal mode, with the transmitter and
status is provided on a character-by-character basis; the status receiver operating independently. MR2A[7:6] = 01 places the
applies only to the character at the top of the FIFO. In the ‘block” channel in the automatic echo mode, which automatically
mode, the status provided in the SR for these bits is the re-transmits the received data. The following conditions are true
accumulation (logical-OR) of the status for all characters coming to while in automatic echo mode:
the top of the FIFO since the last ‘reset error’ command for Channel 1. Received data is re-clocked and retransmitted on the TxDA out-
A was issued. put.
1995 May 1 11
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
2. The receive clock is used for the transmitter. This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
3. The receiver must be enabled, but the transmitter need not be
commands issued via the command register. MR2[5] set to 1
enabled.
caused the RTSN to be reset automatically one bit time after the
4. The Channel A TxRDY and TxEMT status bits are inactive. character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
5. The received parity is checked, but is not regenerated for trans-
bits) if a previously issued transmitter disable is pending. This
mission, i.e. transmitted parity bit is as received.
feature can be used to automatically terminate the transmission as
6. Character framing is checked, but the stop bits are retransmitted follows:
as received. 1. Program the auto-reset mode: MR2[5]=1
2. Enable transmitter, if not already enabled
7. A received break is echoed as received until the next valid start
3. Assert RTSN via command
bit is detected.
4. Send message
8. CPU to receiver communication continues normally, but the CPU 5. After the last character of the message is loaded to the THR,
to transmitter link is disabled. disable the transmitter. (If the transmitter is underrun, a special
case exists. See note below.)
Two diagnostic modes can also be configured. MR2A[7:6] = 10 6. The last character will be transmitted and the RTSN will be reset
selects local loopback mode. In this mode: one bit time after the last stop bit is sent.
1. The transmitter output is internally connected to the receiver
NOTE: The transmitter is in an underrun condition when both the
input.
TxRDY and the TxEMT bits are set. This condition also exists
2. The transmit clock is used for the receiver. immediately after the transmitter is enabled from the disabled or
3. The TxDA output is held High. reset state. When using the above procedure with the transmitter in
the underrun condition, the issuing of the transmitter disable must be
4. The RxDA input is ignored.
delayed from the loading of a single, or last, character until the
5. The transmitter must be enabled, but the receiver need not be TxRDY becomes active again after the character is loaded.
enabled.
6. CPU to transmitter and receiver communications continue nor- MR2A[4] – Channel A Clear-to-Send Control
mally. If this bit is 0, CTSAN has no effect on the transmitter. If this bit is a
1, the transmitter checks the state of CTSAN (IPO) each time it is
The second diagnostic mode is the remote loopback mode, selected ready to send a character. If IPO is asserted (Low), the character is
by MR2A[7:6] = 11. In this mode: transmitted. If it is negated (High), the TxDA output remains in the
1. Received data is re-clocked and re-transmitted on the TxDA marking state and the transmission is delayed until CTSAN goes
output. Low. Changes in CTSAN while a character is being transmitted do
not affect the transmission of that character..
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the error status MR2A[3:0] – Channel A Stop Bit Length Select
conditions are inactive. This field programs the length of the stop bit appended to the
4. The received parity is not checked and is not regenerated for transmitted character. Stop bit lengths of .563 TO 1 AND .563 to 2
transmission, i.e., transmitted parity is as received. bits. In increments of 0.625 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1.0625
5. The receiver must be enabled. to 2 stop bits can be programmed in increments of .0625 bit.
6. Character framing is not checked and the stop bits are retrans-
The receiver only checks for a ‘mark’ condition at the center of the
mitted as received.
first stop bit position (one bit time after the last data bit, or after the
7. A received break is echoed as received until the next valid start parity bit is enabled) in all cases.
bit is detected.
If an external 1X clock is used for the transmitter, MR2A[3] = 0
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
The user must exercise care when switching into and out of the
transmitted.
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received MR1B – Channel B Mode Register 1
or transmitted character. Likewise, if a mode is deselected the
MR1B is accessed when the Channel B MR pointer points to MR1.
device will switch out of the mode immediately. An exception to this
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
is switching out of autoecho or remote loopback modes: if the
applied via CRB. After reading or writing MR1B, the pointer will
deselection occurs just after the receiver has sampled the stop bit
point to MR2B.
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the MR2B – Channel B Mode Register 2
entire stop has been retransmitted. MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
MR2A[5] – Channel A Transmitter Request-to-Send Control
CAUTION: When the transmitter controls the OP pin (usually used change the pointer.
for the RTSN signal) the meaning of the pin is not RTSN at all! The bit definitions for mode registers 1 and 2 are identical to the bit
Rather, it signals that the transmitter has finished the transmission definitions for MRA and MR2A except that all control actions apply
(i.e., end of block).
1995 May 1 12
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
to the Channel B receiver and transmitter and the corresponding Baud Rate
inputs and outputs. CSRB[3:0] ACR[7] = 0
ACR[7] = 1
CSRA – Channel A Clock Select Register 1110 IP5–16X IP5–16X
1111 IP5–1X IP5–1X
CSRA[7:4] – Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A receiver as The transmitter clock is always a 16X clock except for CSRB[3:0] =
follows: 1111.
Baud Rate
CSRA[7:4] ACR[7] = 0 CRA – Channel A Command Register
ACR[7] = 1
CRA is a register used to supply commands to Channel A. Multiple
0000 50 75 commands can be specified in a single write to CRA as long as the
0001 110 110
0010 134.5 134.5 commands are non-conflicting, e.g., the ‘enable transmitter’ and
0011 200 150 ‘reset transmitter’ commands cannot be specified in a single
0100 300 300 command word.
0101 600 600
0110 1,200 1,200 CRA[7] – Not Used
0111 1,050 2,000 Should be set to zero for upward compatibility with newer parts.
1000 2,400 2,400
1001 4,800 4,800 CRA[6:4] – Channel A Miscellaneous Command
1010 7,200 1,800 The encoded value of this field may be used to specify a single
1011 9,600 9,600 command as follows:
1100 38.4k 19.2k
1101 Timer Timer CRA[6:4] – COMMAND
1110 IP4–16X IP4–16X 000 No command.
1111 IP4–1X IP4–1X 001 Reset MR pointer. Causes the Channel A MR pointer to point
to MR1.
010 Reset receiver. Resets the Channel A receiver as if a hard-
(See also Table 5) ware reset had been applied. The receiver is disabled and
the FIFO is flushed.
The receiver clock is always a 16X clock except for CSRA[7] = 1111.
011 Reset transmitter. Resets the Channel A transmitter as if a
CSRA[3:0] – Channel A Transmitter Clock Select hardware reset had been applied.
This field selects the baud rate clock for the Channel A transmitter. 100 Reset error status. Clears the Channel A Received Break,
Parity Error, and Overrun Error bits in the status register
The field definition is as per CSR[7:4] except as follows:
(SRA[7:4]). Used in character mode to clear OE status (al-
Baud Rate though RB, PE and FE bits will also be cleared) and in block
CSRA[3:0] ACR[7] = 0
ACR[7] = 1 mode to clear all error status after a block of data has been
1110 IP3–16X IP3–16X received.
1111 IP3–1X IP3–1X 101 Reset Channel A break change interrupt. Causes the Chan-
nel A break detect change bit in the interrupt status register
(ISR[2]) to be cleared to zero.
The transmitter clock is always a 16X clock except for CSR[3:0] = 110 Start break. Forces the TxDA output Low (spacing). If the
1111. transmitter is empty the start of the break condition will be
delayed up to two bit times. If the transmitter is active the
CSRB – Channel B Clock Select Register break begins when transmission of the character is com-
pleted. If a character is in the THR, the start of the break will
CSRB[7:4] – Channel B Receiver Clock Select be delayed until that character, or any other loaded subse-
This field selects the baud rate clock for the Channel B receiver. quently are transmitted. The transmitter must be enabled for
The field definition is as per CSRA[7:4] except as follows: this command to be accepted.
Baud Rate 111 Stop break. The TxDA line will go High (marking) within two
CSRB[7:4] ACR[7] = 0 bit times. TxDA will remain High for one bit time before the
ACR[7] = 1
next character, if any, is transmitted.
1110 IP6–16X IP6–16X
1111 IP6–1X IP6–1X CRA[3] – Disable Channel A Transmitter
This command terminates transmitter operation and reset the
The receiver clock is always a 16X clock except for CSRB[7:4] = TxDRY and TxEMT status bits. However, if a character is being
1111. transmitted or if a character is in the THR when the transmitter is
disabled, the transmission of the character(s) is completed before
CSRB[3:0] – Channel B Transmitter Clock Select assuming the inactive state. A disable transmitter cannot be loaded.
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as per CSRA[7:4] except as follows:
1995 May 1 13
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
CRA[2] – Enable Channel A Transmitter This bit is cleared by a ‘reset error status’ command.
Enables operation of the Channel A transmitter. The TxRDY status
bit will be asserted. SRA[3] – Channel A Transmitter Empty (TxEMTA)
This bit will be set when the transmitter underruns, i.e., both the
CRA[1] – Disable Channel A Receiver TxEMT and TxRDY bits are set. This bit and TxRDY are set when
This command terminates operation of the receiver immediately – a the transmitter is first enabled and at any time it is re-enabled after
character being received will be lost. The command has no effect either (a) reset, or (b) the transmitter has assumed the disabled
on the receiver status bits or any other control registers. If the state. It is always set after transmission of the last stop bit of a
special multidrop mode is programmed, the receiver operates even character if no character is in the THR awaiting transmission.
if it is disabled. See Operation section.
It is reset when the THR is loaded by the CPU, a pending
CRA[0] – Enable Channel A Receiver transmitter disable is executed, the transmitter is reset, or the
Enables operation of the Channel A receiver. If not in the special transmitter is disabled while in the underrun condition.
wake up mode, this also forces the receiver into the search for
SRA[2] – Channel A Transmitter Ready (TxRDYA)
start-bit state.
This bit, when set, indicates that the THR is empty and ready to be
CRB – Channel B Command Register loaded with a character. This bit is cleared when the THR is loaded
CRB is a register used to supply commands to Channel B. Multiple by the CPU and is set when the character is transferred to the
commands can be specified in a single write to CRB as long as the transmit shift register. TxRDY is reset when the transmitter is
commands are non-conflicting, e.g., the ‘enable transmitter’ and disabled or reset, and is set when the transmitter is first enabled,
‘reset transmitter’ commands cannot be specified in a single viz., characters loaded into the THR while the transmitter is disabled
command word. will not be transmitted.
The bit definitions for this register are identical to the bit definitions SRA[1] – Channel A FIFO Full (FFULLA)
for CRA, except that all control actions apply to the Channel B This bit is set when a character is transferred from the receive shift
receiver and transmitter and the corresponding inputs and outputs. register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all three FIFO positions are occupied. It is reset
SRA – Channel A Status Register when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, FFULL will not be
SRA[7] – Channel A Received Break reset when the CPU reads the RHR.
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO SRA[0] – Channel A Receiver Ready (RxRDYA)
position is occupied when a break is received: further entries to the This bit indicates that a character has been received and is waiting
FIFO are inhibited until the RxDA line to the marking state for at in the FIFO to be read by the CPU. It is set when the character is
least one-half a bit time two successive edges of the internal or transferred from the receive shift to the FIFO and reset when the
external 1X clock. This will usually require a high time of one X1 CPU reads the RHR, if after this read there are not more characters
clock period or 3 X1 edges since the clock of the controller is not still in the FIFO.
synchronous to the X1 clock.
SRB – Channel B Status Register
When this bit is set, the Channel A ‘change in break’ bit in the ISR The bit definitions for this register are identical to the bit definitions
(ISR[2]) is set. ISR[2] is also set when the end of the break for SRA, except that all status applies to the Channel B receiver and
condition, as defined above, is detected. transmitter and the corresponding inputs and outputs.
The break detect circuitry can detect breaks that originate in the
middle of a received character. However, if a break begins in the OPCR – Output Port Configuration Register
middle of a character, it must persist until at least the end of the next OPCR[7] – OP7 Output Select
character time in order for it to be detected. This bit programs the OP7 output to provide one of the following:
SRA[6] – Channel A Framing Error – The complement of OPR[7].
This bit, when set, indicates that a stop bit was not detected when – The Channel B transmitter interrupt output which is the comple-
the corresponding data character in the FIFO was received. The ment of TxRDYB. When in this mode OP7 acts as an Open- Col-
stop bit check is made in the middle of the first bit position. lector output. Note that this output is not masked by the contents
of the IMR.
SRA[5] – Channel A Parity Error
This bit is set when the ‘with parity’ or ‘force parity’ mode is OPCR[6] – OP6 Output Select
programmed and the corresponding character in the FIFO was This bit programs the OP6 output to provide one of the following:
received with incorrect parity. – The complement of OPR[6].
In the special multidrop mode the parity error bit stores the receive – The Channel A transmitter interrupt output which is the comple-
A/D bit. ment of TxRDYA. When in this mode OP6 acts as an Open-Col-
lector output. Note that this output is not masked by the contents
SRA[4] – Channel A Overrun Error of the IMR.
This bit, when set indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new OPCR[5] – OP5 Output Select
character when the FIFO is full and a character is already in the This bit programs the OP5 output to provide one of the following:
receive shift register waiting for an empty FIFO position. When this – The complement of OPR[5].
occurs, the character in the receive shift register (and its break – The Channel B transmitter interrupt output which is the comple-
detect, parity error and framing error status, if any) is lost. ment of ISR[5]. When in this mode OP5 acts as an Open-Collector
1995 May 1 14
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
output. Note that this output is not masked by the contents of the the generation of an interrupt output if IMR[7] = 1. If a bit is in the
IMR. ‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].
OPCR[4] – OP4 Output Select IPCR – Input Port Change Register
This field programs the OP4 output to provide one of the following:
– The complement of OPR[4]. IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
– The Channel B transmitter interrupt output which is the comple-
port section of this data sheet, occurs at the respective input pins.
ment of ISR[1]. When in this mode OP4 acts as an Open-Collec-
They are cleared when the IPCR is read by the CPU. A read of the
tor output. Note that this output is not masked by the contents of
IPCR also clears ISR[7], the input change bit in the interrupt status
the IMR.
register. The setting of these bits can be programmed to generate
OPCR[3:2] – OP3 Output Select an interrupt to the CPU.
This bit programs the OP3 output to provide one of the following: IPCR[3:0] – IP3, IP2, IP1, IP0 Current State
– The complement of OPR[3]. These bits provide the current state of the respective inputs. The
– The counter/timer output, in which case OP3 acts as an Open- information is unlatched and reflects the state of the input pins at the
Collector output. In the timer mode, this output is a square wave time the IPCR is read.
at the programmed frequency. In the counter mode, the output
remains High until terminal count is reached, at which time it goes ISR – Interrupt Status Register
Low. The output returns to the High state when the counter is This register provides the status of all potential interrupt sources.
stopped by a stop counter command. Note that this output is not The contents of this register are masked by the Interrupt Mask
masked by the contents of the IMR. Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit
– The 1X clock for the Channel B transmitter, which is the clock that in the IMR is also a ‘1’, the INTRN output will be asserted. If the
shifts the transmitted data. If data is not being transmitted, a free corresponding bit in the IMR is a zero, the state of the bit in the ISR
running 1X clock is output. has no effect on the INTRN output. Note that the IMR does not
– The 1X clock for the Channel B receiver, which is the clock that mask the reading of the ISR – the true status will be provided
samples the received data. If data is not being received, a free regardless of the contents of the IMR. The contents of this register
running 1X clock is output. are initialized to 0016 when the DUART is reset.
OPCR[1:0] – OP2 Output Select ISR[7] – Input Port Change Status
This field programs the OP2 output to provide one of the following: This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,
– The complement of OPR[2]. IP2, or IP3 inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
– The 16X clock for the Channel A transmitter. This is the clock
the CPU reads the IPCR.
selected by CSRA[3:0], and will be a 1X clock if
CSRA[3:0] = 1111. ISR[6] – Channel B Change In Break
– The 1X clock for the Channel A transmitter, which is the clock that This bit, when set, indicates that the Channel B receiver has
shifts the transmitted data. If data is not being transmitted, a free detected the beginning or the end of a received break. It is reset
running 1X clock is output. when the CPU issues a Channel B ‘reset break change interrupt’
– The 1X clock for the Channel A receiver, which is the clock that command.
samples the received data. If data is not being received, a free
ISR[5] – Channel B Receiver Ready or FIFO Full
running 1X clock is output.
The function of this bit is programmed by MR1B[6]. If programmed
as receiver ready, it indicates that a character has been received in
ACR – Auxiliary Control Register
Channel B and is waiting in the FIFO to be read by the CPU. It is
ACR[7] – Baud Rate Generator Set Select set when the character is transferred from the receive shift register
This bit selects one of two sets of baud rates to be generated by the to the FIFO and reset when the CPU reads the RHR. If after this
BRG: read there are more characters still in the FIFO the bit will be set
again after the FIFO is ‘popped’. If programmed as FIFO full, it is
Set 1: 50, 110, 134.5, 200, 300, 600, 1.05k, 1.2k, 2.4k, 4.8k,
7.2k, 9.6k, and 38.4k baud. set when a character is transferred from the receive holding register
Set 2: 75, 110, 134.5, 150, 300, 600, 1.2k, 1.8k, 2.0k, 2.4k, 4.8k, to the receive FIFO and the transfer caused the Channel B FIFO to
9.6k, and 19.2k baud. become full; i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
The selected set of rates is available for use by the Channel A and receive shift register because the FIFO is full, the bit will be set
B receivers and transmitters as described in CSRA and CSRB. again when the waiting character is loaded into the FIFO.
Baud rate generator characteristics are given in Table 3.
ISR[4] – Channel B Transmitter Ready
ACR[6:4] – Counter/Timer Mode And Clock Source Select This bit is a duplicate of TxRDYB (SRB[2]).
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 4. ISR[3] – Counter Ready.
In the counter mode, this bit is set when the counter reaches
ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable terminal count and is reset when the counter is stopped by a stop
This field selects which bits of the input port change register (IPCR) counter command.
cause the input change bit in the interrupt status register (ISR[7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit In the timer mode, this bit is set once each cycle of the generated
in the IPCR will also result in the setting of ISR[7], which results in square wave (every other time that the counter/timer reaches zero
1995 May 1 15
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
count). The bit is reset by a stop counter command. The command, mode the C/T runs continuously. Receipt of a start counter
however, does not stop the counter/timer. command (read with A3-A0 = 1110) causes the counter to terminate
the current timing cycle and to begin a new cycle using the values in
ISR[2] – Channel A Change in Break CTUR and CTLR. The waveform so generated is often used for a
This bit, when set, indicates that the Channel A receiver has data clock. The formula for calculating the divisor n to load to the
detected the beginning or the end of a received break. It is reset CTUR and CTLR for a particular 1X data clock is shown below:
when the CPU issues a Channel A ‘reset break change interrupt’
command. n = C/T Clock Frequency divided by 2 x 16 x Baud rate desired
Often this division will result in a non-integer number; 26.3, for
ISR[1] – Channel A Receiver Ready Or FIFO Full example. One can only program integer numbers in a digital divider.
The function of this bit is programmed by MR1A[6]. If programmed Therefore, 26 would be chosen. This gives a baud rate error of
as receiver ready, it indicates that a character has been received in 0.3/26.3 which is 1.14%; well within the ability asynchronous mode
Channel A and is waiting in the FIFO to be read by the CPU. It is of operation.
set when the character is transferred from the receive shift register
to the FIFO and reset when the CPU read the RHR. IF after this The counter ready status bit (ISR[3]) is set once each cycle of the
read there are more characters still in the FIFO the bit will be set square wave. The bit is reset by a stop counter command (read
again after the FIFO is ‘popped’. If programmed as FIFO full, it is with A3-A0 = 1111). The command however, does not stop the C/T.
set when a character is transferred from the receive holding register The generated square wave is output on OP3 if it is programmed
to the receive FIFO and the transfer caused the Channel A FIFO to to be the C/T output.
become full; i.e., all three FIFO positions are occupied. It is reset On power up and after reset, the timer/counter runs in timer mode
when the CPU reads the RHR. If a character is waiting in the and can only be restarted. Because it cannot be shut off or stopped,
receive shift register because the FIFO is full, the bit will be set and runs continuously in timer mode, it is recommended that at
again when the ISR[0] and IMR waiting character is loaded into the initialization, the output port (OP3) should be masked off through the
FIFO. OPCR[3:2] = 00 until the T/C is programmed to the desired
ISR[0] – Channel A Transmitter Ready operational state.
This bit is a duplicate of TxRDYA (SRA[2]). In the counter mode, the C/T counts down the number of pulses
loaded into CTUR and CTLR by the CPU. Counting begins upon
IMR – Interrupt Mask Register receipt of a counter command. Upon reaching terminal count
The programming of this register selects which bits in the ISR (000016), the counter ready interrupt bit (ISR[3]) is set. The counter
causes an interrupt output. If a bit in the ISR is a ‘1’ and the continues counting past the terminal count until stopped by the CPU.
corresponding bit in the IMR is also a ‘1’ the INTRN output will be If OP3 is programmed to be the output of the C/T, the output
asserted. If the corresponding bit in the IMR is a zero, the state of remains High until terminal count is reached, at which time it goes
the bit in the ISR has no effect on the INTRN output. Note that the Low. The output returns to the High state and ISR[3] is cleared
IMR does not mask the programmable interrupt outputs OP3–OP7 when the counter is stopped by a stop counter command. The CPU
or the reading of the ISR. may change the values of CTUR and CTLR at any time, but the new
count becomes effective only on the next start counter command. If
CTUR and CTLR – Counter/Timer Registers new values have not been loaded, the previous count values are
The CTUR and CTLR hold the eight MSBs and eight LSBs, preserved and used for the next count cycle.
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value which In the counter mode, the current value of the upper and lower 8 bits
may be loaded into the CTUR/CTLR registers is 000216. Note that of the counter (CTU, CTL) may be read by the CPU.
these registers are write-only and cannot be read by the CPU.
It is recommended that the counter be stopped when reading to
In the timer (programmable divider) mode, the CT generates a prevent potential problems which may occur if a carry from the lower
square wave with a period of twice the value (in clock periods) of the 8 bits to the upper 8 bits occurs between the times that both halves
CTUR and CTLR. of the counter are read. However, note that a subsequent start
counter command will cause the counter to begin a new count cycle
If the value in CTUR and CTLR is changed, the current half-period using the values in CTUR and CTLR.
will not be affected, but subsequent half periods will be. In this
1995 May 1 16
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
Table 3. Bit Rate Generator Characteristics Crystal or Clock = 3.6864MHz
NORMAL RATE (BAUD) ACTUAL 16x CLOCK (kHz) ERROR (%)
50 0.8 0
75 1.2 0
110 1.759 -0.069
134.5 2.153 0.059
150 2.4 0
200 3.2 0
300 4.8 0
600 9.6 0
1050 16.756 -0.260
1200 19.2 0
1800 28.8 0
2000 32.056 0.175
2400 38.4 0
4800 76.8 0
7200 115.2 0
9600 153.6 0
19.2k 307.2 0
38.4k 614.4 0
NOTE: Duty cycle of 16x clock is 50% ± 1%.
Table 4. ACR 6:4 Field Definition
ACR 6:4 MODE CLOCK SOURCE
000 Counter External (IP2)
001 Counter TxCA – 1x clock of Channel A transmitter
010 Counter TxCB – 1x clock of Channel B transmitter
011 Counter Crystal or external clock (x1/CLK) divided by 16
100 Timer External (IP2)
101 Timer External (IP2) divided by 16
110 Timer Crystal or external clock (x1/CLK)
111 Timer Crystal or external clock (x1/CLK) divided by 16
NOTE: Timer mode generates a squarewave.
1995 May 1 17
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
TIMING DIAGRAMS
RESET
tRES
SD00086
Figure 1. Reset Timing
A0–A3
tAS
tAH
CEN
tCS tCH
tRW tRWD
RDN
tDD tDF
D0–D7 NOT
FLOAT VALID VALID FLOAT
(READ)
tRWD
WDN
tDS
tDH
D0–D7 VALID
(WRITE)
SD00087
Figure 2. Bus Timing
RDN
tPS tPH
IP0–IP6
WRN
tPD
VOH
OP0–OP7 OLD DATA VM NEW DATA
VOL
VM = 1.5V
SD00089
Figure 3. Port Timing
1995 May 1 18
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
TIMING DIAGRAMS (Continued)
RDN
OR
VM
WRN
tIR
VOL +0.5V
INTERRUPT 1
OUTPUT
VOL
NOTES:
1. INTRN or OP3 – OP7 when used as interrupt outputs.
2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from themidpoint of the switching signal, VM, to a
point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced
and can greatly affect the resultant measurement.
SD00090
Figure 4. Interrupt Timing
+5V
R1: 100K - 1Meg (See design note)
C1 = C2: 0-5pF + (STRAY < 5pF)
tCLK 1K
tCTC
DRIVING FROM CLOCK
tRx EXTERNAL SOURCE TO OTHER
tTx CHIPS
X1/CLK 74LS04
CTCLK
RxC
TxC SCN2681
X1 TO THE REST
tCLK OF THE DUART
tCTC OPEN CIRCUITS
X1
tRx +5V C1
tTx R2
R1
1KΩ
C2
When using an external clock it is preferred to drive X2 and leave X1 open. U1
X2 is the input to the internal driver, while X1 is the output.
R1 is only required if U1 will not drive to X2 high level. X2 X2
Previous specifications indicated X2 should be grounded and X1
3.6864MHz
should be driven. This is still acceptable. It is electrically easier to drive
the amplifier input than to overdrive its output. CRYSTAL SERIES RESISTANCE3 SHOULD BE LESS THAN 180Ω
R2 = 50kΩ to 150kΩ
SD00091
Figure 5. Clock Timing
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
tTXD
TxD
tTCS
TxC
(1X OUTPUT)
SD00092
Figure 6. Transmit
1995 May 1 19
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
TIMING DIAGRAMS (Continued)
RxC
(1X INPUT)
tRXS tRXH
RxD
SD00093
Figure 7. Receive
TxD D1 D2 D3 BREAK D4 D6
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
D1 D2 D3 START D4 STOP D5 WILL D6
BREAK BREAK NOT BE
CTSN1 TRANSMITTED
(IP0)
RTSN2
(OP0)
OPR(0) = 1 OPR(0) = 1
NOTES:
1. Timing shown for MR2(4) = 1.
2. Timing shown for MR2(5) = 1. SD00094
Figure 8. Transmitter Timing
1995 May 1 20
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
TIMING DIAGRAMS (Continued)
RxD D1 D2 D3 D4 D5 D6 D7 D8
D6, D7, D8 WILL BE LOST
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDY/
FFULL
(OP5)2
RDN
STATUS DATA STATUS DATA STATUS DATA STATUS DATA
D1 D5 WILL D2 D3 D4
OVERRUN BE LOST
(SR4) RESET BY COMMAND
RTS1
(OP0)
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1.
2. Shown for OPCR(4) = 1 and MR(6) = 0. SD00095
Figure 9. Receiver Timing
MASTER STATION
BIT 9 BIT 9 BIT 9
TxD ADD#1 1 D0 0 ADD#2 1
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
MR1(4–3) = 11 ADD#1 MR1(2) = 0 D0 MR1(2) = 1 ADD#2
MR1(2) = 1
PERIPHERAL STATION
BIT 9 BIT 9 BIT 9 BIT 9 BIT 9
RxD 0 ADD#1 1 D0 0 ADD#2 1 0
RECEIVER
ENABLED
RxRDY
(SR0)
RDN/WRN
MR1(4–3) = 11 ADD#1 STATUS DATA STATUS DATA
D0 ADD#2
SD00096
Figure 10. Wake-Up Mode
1995 May 1 21
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
Output Port Notes MR2(4) is set to zero, the IP pin will have no effect on the operation
The output ports are controlled from three places: the OPCR of the transmitter.
register, the OPR register, and the MR registers. The OPCR MR1(7) is the bit that allows the receiver to control OP0. When OP0
register controls the source of the data for the output ports OP2 (or OP1) is controlled by the receiver, the meaning of that pin will be
through OP7. The data source for output ports OP0 and OP1 is RTS. However, a point of confusion arises in that OP0 (or OP1)
controlled by the MR and CR registers. When the OPR is the may also be controlled by the transmitter. When the transmitter is
source of the data for the output ports, the data at the ports is controlling this pin, its meaning is not RTS at all. It is, rather, that
inverted from that in the OPR register. The content of the OPR the transmitter has finished sending its last data byte. Programming
register is controlled by the “Set Output Port Bits Command” and the the OP0 or OP1 pin to be controlled by the receiver and the
“Reset Output Bits Command”. These commands are at E and F, transmitter at the same time is allowed, but would usually be
respectively. When these commands are used, action takes place incompatible.
only at the bit locations where ones exist. For example, a one in bit
location 5 of the data word used with the “Set Output Port Bits” RTS is expressed at the OP0 or OP1 pin which is still an output port.
command will result in OPR5 being set to one. The OP5 would then Therefore, the state of OP0 or OP1 should be set low for the
be set to zero (VSS). Similarly, a one in bit position 5 of the data receiver to generate the proper RTS signal. The logic at the output
word associated with the “Reset Output Ports Bits” command would is basically a NAND of the OPR register and the RTS signal as
set OPR5 to zero and, hence, the pin OP5 to a one (VDD). generated by the receiver. When the RTS flow control is selected
via the MR(7) bit state of the OPR register is not changed.
The CTS, RTS, CTS Enable Tx signals Terminating the use of “Flow Control” (via the MR registers) will
CTS (Clear To Send) is usually meant to be a signal to the return the OP0 or OP1 pins to the control of the OPR register.
transmitter meaning that it may transmit data to the receiver. The
CTS input is on pin IP0 for TxA and on IP1 for TxB. The CTS signal Transmitter Disable Note
is active low; thus, it is called CTSAN for TxA and CTSBN for TxB. The sequence of instructions enable transmitter — load transmit
holding register — disable transmitter will result in nothing being
RTS is usually meant to be a signal from the receiver indicating that sent if the time between the end of loading the transmit holding
the receiver is ready to receive data. It is also active low and is, register and the disable command is less that 3/16 bit time in the
thus, called RTSAN for RxA and RTSBN for RxB. RTSAN is on pin 16x mode or one bit time in the 1x mode. Also, if the transmitter,
op0 and RTSBN is on OP1. A receiver’s RTS output will usually be while in the enabled state and underrun condition, is immediately
connected to the CTS input of the associated transmitter. Therefore, disabled after a single character is loaded to the transmit holding
one could say that RTS and CTS are different ends of the same register, that character will not be sent.
wire!
In general, when it is desired to disable the transmitter before the
MR2(4) is the bit that allows the transmitter to be controlled by the last character is sent AND the TxEMT bit is set in the status register
CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input (TxEMT is always set if the transmitter has underrun or has just
is driven high, the transmitter will stop sending data at the end of the been enabled), be sure the TxRDY bit is active immediately before
present character being serialized. It is usually the RTS output of issuing the transmitter disable instruction. TxRDY sets at the end of
the receiver that will be connected to the transmitter’s CTS input. the “start bit” time. It is during the start bit that the data in the
The receiver will set RTS high when the receiver FIFO is full AND transmit holding register is transferred to the transmit shift register.
the start bit of the fourth character is sensed. Transmission then
stops with four valid characters in the receiver. When MR2(4) is set Non-standard baud rates are available as shown in Table [5] below,
to one, CTSN must be at zero for the transmitter to operate. If via the BRG Test function.
1995 May 1 22
Philips Semiconductors Product specification
Dual asynchronous receiver/transmitter (DUART) SCN2681
Table 5. Baud Rates Extended
Normal BRG BRG Test
CSR[7:4] ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1
0000 50 75 4,800 7,200
0001 110 110 880 880
0010 134.5 134.5 1,076 1,076
0011 200 150 19.2K 14.4K
0100 300 300 28.8K 28.8K
0101 600 600 57.6K 57.6K
0110 1,200 1,200 115.2K 115.2K
0111 1,050 2,000 1,050 2,000
1000 2,400 2,400 57.6K 57.6K
1001 4,800 4,800 4,800 4,800
1010 7,200 1,800 57.6K 14.4K
1011 9,600 9,600 9,600 9,600
1100 38.4K 19.2K 38.4K 19.2K
1101 Timer Timer Timer Timer
1110 I/O2 – 16X I/O2 – 16X I/O2 – 16X I/O2 – 16X
1111 I/O2 – 1X I/O2 – 1X I/O2 – 1X I/O2 – 1X
NOTE: Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left.
This change affects all receivers and transmitters on the DUART.
The test mode at address H‘A’ changes all transmitters and receivers to the 1x mode and connects the output ports to some internal nodes.
A condition that occurs infrequently has been observed where the receiver will ignore all data. It is caused by a corruption of the start bit
generally due to noise. When this occurs the receiver will appear to be asleep or locked up. The receiver must be reset for the UART to
continue to function properly.
Reset in the Normal Mode (Receiver Enabled)
Recovery can be accomplished easily by issuing a receiver software reset followed by a receiver enable. All receiver data, status and
programming will be preserved and available before reset. The reset will NOT affect the programming.
Reset in the Wake-Up Mode (MR1[4:3] = 11)
Recovery can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software
reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and available before
reset. The reset will NOT affect the programming.
The receiver has a digital filter designed to reject “noisy” data transitions and the receiver state machine was designed to reject noisy start
bits or noise that might be considered a start bit. In spite of these precautions, corruption of the start bit can occur in 15ns window
approximately 100ns prior to the rising edge of the data clock. The probability of this occurring is less than 10–5 at 9600 baud.
A corrupted start bit may have some deleterious effects in ASYNC operation if it occurs within a normal data block. The receiver will tend
to align its data clock to the next ‘0’ bit in the data stream, thus potentially corrupting the remainder of the data block. A good design
practice, in environments where start bit corruption is possible, is to monitor data quality (framing error, parity error, break change and
received break) and “data stopped” time out periods. Time out periods can be enabled using the counter/timer in the SCC2691, SCC2692,
SCC2698B and SC68692 products. This monitoring can indicate a potential start bit corruption problem.
SD00097
1995 May 1 23
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