forked from arti/vt1200
opencode.energia.arti.ee
45110270a7
One PIXBLT B,XY per source row paints the whole screen: DYDX names `stretch` rows and SPTCH = 0 makes each of them read the same packed source row, so the vertical stretch costs no extra CPU work. vram_b.asm carries the primitive (PSIZE=1, CONVSP/CONVDP=0x14, PMASK=0, OFFSET=0x04000000, DPTCH=0x800, raster op 0) plus DINT/EINT thunks; vidstream.c masks interrupts for the burst (spec 8.9), refuses geometry the screen cannot hold, and counts an OS repaint through a sentinel word in the unused right edge of the last screen row (OS_TOUCH, 0x01810220). MAME mode draw injects a 128-row frame (stretch 8 = 1024 screen rows, ruling R3) and dumps the screen; vidstream_check.py compares all 1024 rows against the bytes actually delivered. RED: 0/1024 rows matched. GREEN: 1024/1024, RX_OK=1, OS_TOUCH=0. Fixes a latent harness bug found on the way: `bpclear <address>` takes a breakpoint INDEX, so the idle-loop breakpoint was never cleared; once a burst masked interrupts long enough, its stale action fired again and re-entered main (a second malloc, counters back to 0).
120 lines
4.6 KiB
NASM
120 lines
4.6 KiB
NASM
; vram_b.asm -- PIXBLT B,XY: a packed 1-bpp RAM row straight to the screen.
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;
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; Task 5's blit primitive. PIXBLT's B source form reads the source as packed
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; 1-bit pixels from a LINEAR bit address and writes an XY destination, which is
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; exactly the strip decoder's shape: a 1280-pixel row (160 bytes) in the slot,
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; painted down `stretch` screen rows.
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;
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; The vertical stretch is one instruction, not a loop over screen rows: SPTCH
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; = 0 makes every source row read the SAME source address, so a PIXBLT whose
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; DYDX names `stretch` rows paints the one row `stretch` times.
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;
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; DESCRIPTION-register assignments for PIXBLT B,XY (TMS34010 User's Guide,
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; instruction reference; vram.asm already uses the same values for L,XY):
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; SADDR = B0 source bit address (1 bpp, packed)
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; SPTCH = B1 source pitch in bits; 0 = do not advance the source
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; DADDR = B2 destination XY: (y << 16) | x
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; DPTCH = B3 destination pitch in bits (0x800 = 256-byte screen row)
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; OFFSET = B4 VRAM base bit address
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; DYDX = B7 dimensions in XY form: (rows << 16) | columns
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;
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; COLOR0 = B8 pixel value for a clear source bit (0 = black)
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; COLOR1 = B9 pixel value for a set source bit (0xFFFF = white)
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;
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; B8/B9 are NOT I/O registers: COLOR0 and COLOR1 are implied B-register
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; operands of every graphics instruction (vram.asm's FILL passes its pattern in
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; B9 for the same reason). They are explicit here because a PIXBLT B expands
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; a packed 1-bpp source into pixel values, so whatever the resident OS left in
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; B9 becomes the colour of every set pixel -- measured: the first draw run
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; painted every row it blitted black because nothing had set B9 (the padding
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; past column 1280, which the blit does not write, kept the OS's old bytes).
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;
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; PSIZE (0C0000150h) 1 one bit per destination pixel
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; CONVSP (0C0000130h) 14h 0x800-bit pitch code (1 << (~0x14 & 0x1F) = 2048)
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; CONVDP (0C0000140h) 14h same, for the XY destination
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; PMASK (0C0000160h) 0 every plane writable
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; CONTROL (0C00000B0h) raster op 0 (replace), CD/RM/RR preserved
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;
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; Entry points. The TMS34010 C compiler passes arguments in its own frame-
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; pointer scheme, and no hand-written assembly in this repository has ever
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; DECODED that frame: the ROM thunks in entry.asm forward the caller's stack
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; frame through `calla` without touching it, and the two array primitives in
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; vram.asm take their inputs from published words in .bss with a no-argument
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; entry (called by lance_cmd.c, measured on the unit). This primitive follows
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; the vram.asm form, so the three interface values named in the plan live in
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; blit_src / blit_daddr / blit_dydx (blit_sptch only exists for vram.asm and is
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; ignored: this primitive always sets SPTCH = 0). The C side wraps them in
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; blit_row() so the call reads as blit_row(src, daddr_xy, dydx).
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;
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; All inputs are reloaded on every call: PIXBLT leaves SADDR/DADDR advanced, so
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; a caller that "saves" them saves a half-consumed rectangle.
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;
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; _vid_dint_ / _vid_eint_ -- interrupts off/on. The C compiler cannot emit
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; DINT/EINT, and spec section 8.9 wants the OS masked for the whole burst so a
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; resident repaint cannot tear the picture.
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.ref _blit_src
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.ref _blit_daddr
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.ref _blit_dydx
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.text
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.globl _vram_blit_b_
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_vram_blit_b_:
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setf 32, 0, 1
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move b0, -*sp, 1
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move b1, -*sp, 1
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move b2, -*sp, 1
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move b3, -*sp, 1
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move b4, -*sp, 1
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move b7, -*sp, 1
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move b8, -*sp, 1
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move b9, -*sp, 1
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move @_blit_src, b0, 1 ; SADDR: packed 1-bpp source row
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clr b1 ; SPTCH = 0: every row is the same source row
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move @_blit_daddr, b2, 1 ; DADDR (XY)
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movi 800h, b3 ; DPTCH = 2048 bits = 256-byte row pitch
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movi 04000000h, b4 ; OFFSET = VRAM base
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move @_blit_dydx, b7, 1 ; DYDX (rows, columns)
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clr b8 ; COLOR0 = 0 (black)
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movi 0FFFFh, b9 ; COLOR1 = all planes set (white)
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; --- pixel format ------------------------------------------------------
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movi 1, a1
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move a1, @0C0000150h, 0 ; PSIZE = 1
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movi 14h, a1
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move a1, @0C0000130h, 0 ; CONVSP = pitch code for 0x800 bits
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move a1, @0C0000140h, 0 ; CONVDP
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clr a1
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move a1, @0C0000160h, 0 ; PMASK = 0 (all planes writable)
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move a1, @0C0000170h, 0 ; upper half, for forward compatibility
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; --- graphics operation: replace, no transparency, no window ----------
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move @0C00000B0h, a1, 0 ; CONTROL
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andi 0801Fh, a1 ; keep CD (15) and RM/RR (2-4) only
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move a1, @0C00000B0h, 0
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move @0C00000B0h, a1, 0 ; read back: I/O writes are pipelined
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pixblt b, xy
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move *sp+, b9, 1
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move *sp+, b8, 1
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move *sp+, b7, 1
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move *sp+, b4, 1
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move *sp+, b3, 1
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move *sp+, b2, 1
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move *sp+, b1, 1
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move *sp+, b0, 1
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rets
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.globl _vid_dint_
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_vid_dint_:
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dint
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rets
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.globl _vid_eint_
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_vid_eint_:
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eint
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rets
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.end
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