diff --git a/llvm/lib/Target/TMS34010/TMS34010ISelLowering.cpp b/llvm/lib/Target/TMS34010/TMS34010ISelLowering.cpp
index fb88497a7615..47f1ce22f50a 100644
--- a/llvm/lib/Target/TMS34010/TMS34010ISelLowering.cpp
+++ b/llvm/lib/Target/TMS34010/TMS34010ISelLowering.cpp
@@ -27,6 +27,10 @@ TMS34010TargetLowering::TMS34010TargetLowering(const TargetMachine &TM,
   setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i8, Legal);
   setTruncStoreAction(MVT::i32, MVT::i8, Legal);
 
+  // MOVE with FS0 is the 16-bit sign-extending load / truncating store.
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i16, Legal);
+  setTruncStoreAction(MVT::i32, MVT::i16, Legal);
+
   computeRegisterProperties(STI.getRegisterInfo());
 
   setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/TMS34010/TMS34010InstrInfo.td b/llvm/lib/Target/TMS34010/TMS34010InstrInfo.td
index fd2f8244e531..71420d2b0ab0 100644
--- a/llvm/lib/Target/TMS34010/TMS34010InstrInfo.td
+++ b/llvm/lib/Target/TMS34010/TMS34010InstrInfo.td
@@ -104,6 +104,32 @@ def MOVE32Store : TMS34010Inst<(outs), (ins ARegs:$src, ARegs:$dst),
   let Inst{3-0} = dst{3-0};
 }
 
+// MOVE *Rs, Rd, FS0: 16-bit sign-extending load.  1000 010S SSSF DDDD (0x8400)
+def MOVE16Load : TMS34010Inst<(outs ARegs:$dst), (ins ARegs:$src),
+                              "MOVE *$src, $dst, 0",
+                              [(set ARegs:$dst, (sextloadi16 ARegs:$src))]> {
+  let mayLoad = 1;
+  bits<5> src;
+  bits<5> dst;
+  let Inst{15-9} = 0b1000010;
+  let Inst{8-5} = src{3-0};
+  let Inst{4} = src{4};
+  let Inst{3-0} = dst{3-0};
+}
+
+// MOVE Rs, *Rd, FS0: 16-bit truncating store.  1000 000S SSSF DDDD (0x8000)
+def MOVE16Store : TMS34010Inst<(outs), (ins ARegs:$src, ARegs:$dst),
+                               "MOVE $src, *$dst, 0",
+                               [(truncstorei16 ARegs:$src, ARegs:$dst)]> {
+  let mayStore = 1;
+  bits<5> src;
+  bits<5> dst;
+  let Inst{15-9} = 0b1000000;
+  let Inst{8-5} = src{3-0};
+  let Inst{4} = dst{4};
+  let Inst{3-0} = dst{3-0};
+}
+
 // MOVB *Rs, Rd: 8-bit sign-extending load.  1000 111S SSSF DDDD (0x8e00)
 def MOVBLoad : TMS34010Inst<(outs ARegs:$dst), (ins ARegs:$src),
                             "MOVB *$src, $dst",
diff --git a/llvm/test/CodeGen/TMS34010/m1-i16.ll b/llvm/test/CodeGen/TMS34010/m1-i16.ll
new file mode 100644
index 000000000000..83ab35ca9179
--- /dev/null
+++ b/llvm/test/CodeGen/TMS34010/m1-i16.ll
@@ -0,0 +1,17 @@
+; RUN: llc -march=tms34010 -O2 -filetype=asm < %s | FileCheck %s
+; FS0 selects 16-bit fields.  The M1 harness must execute SETF 16,0,0
+; before calling this code (Task 4).
+define i32 @loads(ptr %p) {
+  %v = load i16, ptr %p
+  %r = sext i16 %v to i32
+  ret i32 %r
+}
+define void @stores(ptr %p, i32 %v) {
+  %t = trunc i32 %v to i16
+  store i16 %t, ptr %p
+  ret void
+}
+; CHECK-LABEL: _loads:
+; CHECK: MOVE *A{{[0-9]+}}, A{{[0-9]+}}, 0
+; CHECK-LABEL: _stores:
+; CHECK: MOVE A{{[0-9]+}}, *A{{[0-9]+}}, 0