[ARM] Custom Lowering for SADDO_CARRY and SSUBO_CARRY (#154419)
To do this, I did refactoring to mirror what goes on with AArch64, including having the carryFlagToValue do the inversion. While the patterns are not the best, with pattern matching, I hope to at make it as good as AArch64 on Thumb2 where we have CSEL.
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SiliconA-Z authored and 
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@@ -960,6 +960,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
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setOperationAction(ISD::UADDO_CARRY, MVT::i32, Custom);
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setOperationAction(ISD::USUBO_CARRY, MVT::i32, Custom);
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setOperationAction(ISD::SADDO_CARRY, MVT::i32, Custom);
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setOperationAction(ISD::SSUBO_CARRY, MVT::i32, Custom);
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if (Subtarget->hasDSP()) {
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setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
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setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
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@@ -4721,28 +4723,45 @@ ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
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return std::make_pair(Value, OverflowCmp);
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}
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static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
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SelectionDAG &DAG) {
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SDLoc DL(BoolCarry);
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EVT CarryVT = BoolCarry.getValueType();
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static SDValue valueToCarryFlag(SDValue Value, SelectionDAG &DAG, bool Invert) {
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SDLoc DL(Value);
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EVT VT = Value.getValueType();
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// This converts the boolean value carry into the carry flag by doing
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// ARMISD::SUBC Carry, 1
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SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
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DAG.getVTList(CarryVT, MVT::i32),
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BoolCarry, DAG.getConstant(1, DL, CarryVT));
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return Carry.getValue(1);
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if (Invert)
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Value = DAG.getNode(ISD::SUB, DL, MVT::i32,
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DAG.getConstant(1, DL, MVT::i32), Value);
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SDValue Cmp = DAG.getNode(ARMISD::SUBC, DL, DAG.getVTList(VT, MVT::i32),
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Value, DAG.getConstant(1, DL, VT));
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return Cmp.getValue(1);
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}
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static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
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SelectionDAG &DAG) {
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static SDValue carryFlagToValue(SDValue Flags, EVT VT, SelectionDAG &DAG,
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bool Invert) {
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SDLoc DL(Flags);
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if (Invert) {
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// Convert flags to boolean with ADDE 0,0,Carry then compute 1 - bool.
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SDValue BoolCarry = DAG.getNode(
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ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
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DAG.getConstant(0, DL, VT), DAG.getConstant(0, DL, VT), Flags);
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return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(1, DL, VT), BoolCarry);
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}
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// Now convert the carry flag into a boolean carry. We do this
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// using ARMISD:ADDE 0, 0, Carry
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// using ARMISD::ADDE 0, 0, Carry
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return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
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DAG.getConstant(0, DL, MVT::i32),
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DAG.getConstant(0, DL, MVT::i32), Flags);
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DAG.getConstant(0, DL, VT), DAG.getConstant(0, DL, VT),
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Flags);
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}
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// Value is 1 if 'V' bit is 1, else 0
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static SDValue overflowFlagToValue(SDValue Flags, EVT VT, SelectionDAG &DAG) {
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SDLoc DL(Flags);
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SDValue Zero = DAG.getConstant(0, DL, VT);
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SDValue One = DAG.getConstant(1, DL, VT);
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SDValue ARMcc = DAG.getConstant(ARMCC::VS, DL, MVT::i32);
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return DAG.getNode(ARMISD::CMOV, DL, VT, Zero, One, ARMcc, Flags);
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}
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SDValue ARMTargetLowering::LowerALUO(SDValue Op, SelectionDAG &DAG) const {
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@@ -4762,16 +4781,12 @@ SDValue ARMTargetLowering::LowerALUO(SDValue Op, SelectionDAG &DAG) const {
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case ISD::UADDO:
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Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
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// Convert the carry flag into a boolean value.
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Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
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Overflow = carryFlagToValue(Value.getValue(1), VT, DAG, false);
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break;
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case ISD::USUBO:
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Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
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// Convert the carry flag into a boolean value.
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Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
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// ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
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// value. So compute 1 - C.
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Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
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DAG.getConstant(1, dl, MVT::i32), Overflow);
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Overflow = carryFlagToValue(Value.getValue(1), VT, DAG, true);
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break;
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default: {
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// Handle other operations with getARMXALUOOp
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@@ -6705,21 +6720,19 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG,
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static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.");
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SDValue Carry = Op.getOperand(2);
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SDValue Cond = Op.getOperand(3);
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SDLoc DL(Op);
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assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.");
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// ARMISD::SUBE expects a carry not a borrow like ISD::USUBO_CARRY so we
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// have to invert the carry first.
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Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
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DAG.getConstant(1, DL, MVT::i32), Carry);
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// This converts the boolean value carry into the carry flag.
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Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
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SDValue InvCarry = valueToCarryFlag(Carry, DAG, true);
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SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
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SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
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SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, InvCarry);
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SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
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SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
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@@ -9612,48 +9625,26 @@ static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG,
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return N0;
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}
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static SDValue LowerUADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) {
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SDNode *N = Op.getNode();
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EVT VT = N->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, MVT::i32);
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static SDValue LowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG,
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unsigned Opcode, bool IsSigned) {
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EVT VT0 = Op.getValue(0).getValueType();
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EVT VT1 = Op.getValue(1).getValueType();
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SDValue Carry = Op.getOperand(2);
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bool InvertCarry = Opcode == ARMISD::SUBE;
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SDValue OpLHS = Op.getOperand(0);
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SDValue OpRHS = Op.getOperand(1);
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SDValue OpCarryIn = valueToCarryFlag(Op.getOperand(2), DAG, InvertCarry);
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SDLoc DL(Op);
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SDValue Result;
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if (Op.getOpcode() == ISD::UADDO_CARRY) {
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// This converts the boolean value carry into the carry flag.
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Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
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SDValue Result = DAG.getNode(Opcode, DL, DAG.getVTList(VT0, MVT::i32), OpLHS,
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OpRHS, OpCarryIn);
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// Do the addition proper using the carry flag we wanted.
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Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0),
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Op.getOperand(1), Carry);
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SDValue OutFlag =
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IsSigned ? overflowFlagToValue(Result.getValue(1), VT1, DAG)
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: carryFlagToValue(Result.getValue(1), VT1, DAG, InvertCarry);
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// Now convert the carry flag into a boolean value.
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Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
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} else {
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// ARMISD::SUBE expects a carry not a borrow like ISD::USUBO_CARRY so we
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// have to invert the carry first.
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Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
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DAG.getConstant(1, DL, MVT::i32), Carry);
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// This converts the boolean value carry into the carry flag.
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Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
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// Do the subtraction proper using the carry flag we wanted.
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Result = DAG.getNode(ARMISD::SUBE, DL, VTs, Op.getOperand(0),
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Op.getOperand(1), Carry);
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// Now convert the carry flag into a boolean value.
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Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
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// But the carry returned by ARMISD::SUBE is not a borrow as expected
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// by ISD::USUBO_CARRY, so compute 1 - C.
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Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
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DAG.getConstant(1, DL, MVT::i32), Carry);
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}
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// Return both values.
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return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry);
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return DAG.getMergeValues({Result, OutFlag}, DL);
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}
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SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
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@@ -10519,8 +10510,13 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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return LowerDIV_Windows(Op, DAG, /* Signed */ false);
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return LowerUDIV(Op, DAG, Subtarget);
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case ISD::UADDO_CARRY:
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return LowerADDSUBO_CARRY(Op, DAG, ARMISD::ADDE, false /*unsigned*/);
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case ISD::USUBO_CARRY:
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return LowerUADDSUBO_CARRY(Op, DAG);
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return LowerADDSUBO_CARRY(Op, DAG, ARMISD::SUBE, false /*unsigned*/);
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case ISD::SADDO_CARRY:
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return LowerADDSUBO_CARRY(Op, DAG, ARMISD::ADDE, true /*signed*/);
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case ISD::SSUBO_CARRY:
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return LowerADDSUBO_CARRY(Op, DAG, ARMISD::SUBE, true /*signed*/);
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case ISD::UADDO:
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case ISD::USUBO:
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case ISD::UMULO:
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@@ -64,86 +64,81 @@ define i32 @func(i32 %x, i32 %y) nounwind {
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; CHECK-T16-LABEL: func2:
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; CHECK-T16: @ %bb.0:
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; CHECK-T16-NEXT: .save {r4, lr}
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; CHECK-T16-NEXT: push {r4, lr}
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; CHECK-T16-NEXT: mov r4, r1
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; CHECK-T16-NEXT: eors r1, r3
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; CHECK-T16-NEXT: adds r2, r0, r2
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; CHECK-T16-NEXT: adcs r3, r4
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; CHECK-T16-NEXT: eors r4, r3
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; CHECK-T16-NEXT: bics r4, r1
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; CHECK-T16-NEXT: asrs r0, r3, #31
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; CHECK-T16-NEXT: movs r1, #1
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; CHECK-T16-NEXT: lsls r1, r1, #31
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; CHECK-T16-NEXT: eors r1, r0
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; CHECK-T16-NEXT: cmp r4, #0
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; CHECK-T16-NEXT: bpl .LBB1_3
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; CHECK-T16-NEXT: .save {r4, r5, r7, lr}
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; CHECK-T16-NEXT: push {r4, r5, r7, lr}
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; CHECK-T16-NEXT: mov r5, r0
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; CHECK-T16-NEXT: adds r0, r0, r2
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; CHECK-T16-NEXT: mov r0, r1
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; CHECK-T16-NEXT: adcs r0, r3
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; CHECK-T16-NEXT: asrs r0, r0, #31
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; CHECK-T16-NEXT: movs r4, #1
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; CHECK-T16-NEXT: lsls r4, r4, #31
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; CHECK-T16-NEXT: eors r4, r0
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; CHECK-T16-NEXT: adds r2, r5, r2
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; CHECK-T16-NEXT: adcs r1, r3
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; CHECK-T16-NEXT: bvc .LBB1_3
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; CHECK-T16-NEXT: @ %bb.1:
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; CHECK-T16-NEXT: bpl .LBB1_4
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; CHECK-T16-NEXT: bvc .LBB1_4
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; CHECK-T16-NEXT: .LBB1_2:
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; CHECK-T16-NEXT: pop {r4, pc}
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; CHECK-T16-NEXT: mov r1, r4
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; CHECK-T16-NEXT: pop {r4, r5, r7, pc}
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; CHECK-T16-NEXT: .LBB1_3:
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; CHECK-T16-NEXT: mov r0, r2
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; CHECK-T16-NEXT: bmi .LBB1_2
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; CHECK-T16-NEXT: bvs .LBB1_2
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; CHECK-T16-NEXT: .LBB1_4:
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; CHECK-T16-NEXT: mov r1, r3
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; CHECK-T16-NEXT: pop {r4, pc}
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; CHECK-T16-NEXT: mov r4, r1
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; CHECK-T16-NEXT: mov r1, r4
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; CHECK-T16-NEXT: pop {r4, r5, r7, pc}
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;
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; CHECK-T2-LABEL: func2:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: adds r0, r0, r2
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; CHECK-T2-NEXT: eor.w r12, r1, r3
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; CHECK-T2-NEXT: adc.w r2, r1, r3
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; CHECK-T2-NEXT: eors r1, r2
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; CHECK-T2-NEXT: bics.w r1, r1, r12
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: asrmi r0, r2, #31
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; CHECK-T2-NEXT: mov.w r1, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31
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; CHECK-T2-NEXT: mov r1, r2
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; CHECK-T2-NEXT: mov.w r2, #-2147483648
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; CHECK-T2-NEXT: adcs r1, r3
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; CHECK-T2-NEXT: it vs
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; CHECK-T2-NEXT: asrvs r0, r1, #31
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; CHECK-T2-NEXT: it vs
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; CHECK-T2-NEXT: eorvs.w r1, r2, r1, asr #31
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func2:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: adds r0, r0, r2
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; CHECK-ARM-NEXT: eor r12, r1, r3
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; CHECK-ARM-NEXT: adc r2, r1, r3
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; CHECK-ARM-NEXT: eor r1, r1, r2
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; CHECK-ARM-NEXT: bics r1, r1, r12
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; CHECK-ARM-NEXT: asrmi r0, r2, #31
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; CHECK-ARM-NEXT: mov r1, #-2147483648
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; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
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; CHECK-ARM-NEXT: mov r1, r2
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; CHECK-ARM-NEXT: mov r2, #-2147483648
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; CHECK-ARM-NEXT: adcs r1, r1, r3
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; CHECK-ARM-NEXT: asrvs r0, r1, #31
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; CHECK-ARM-NEXT: eorvs r1, r2, r1, asr #31
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-T15TE-LABEL: func2:
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; CHECK-T15TE: @ %bb.0:
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; CHECK-T15TE-NEXT: .save {r4, lr}
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; CHECK-T15TE-NEXT: push {r4, lr}
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; CHECK-T15TE-NEXT: movs r4, r1
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; CHECK-T15TE-NEXT: eors r1, r3
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; CHECK-T15TE-NEXT: adds r2, r0, r2
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; CHECK-T15TE-NEXT: adcs r3, r4
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; CHECK-T15TE-NEXT: eors r4, r3
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; CHECK-T15TE-NEXT: bics r4, r1
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; CHECK-T15TE-NEXT: asrs r0, r3, #31
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; CHECK-T15TE-NEXT: movs r1, #1
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; CHECK-T15TE-NEXT: lsls r1, r1, #31
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; CHECK-T15TE-NEXT: eors r1, r0
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; CHECK-T15TE-NEXT: cmp r4, #0
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; CHECK-T15TE-NEXT: bpl .LBB1_3
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; CHECK-T15TE-NEXT: .save {r4, r5, r7, lr}
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; CHECK-T15TE-NEXT: push {r4, r5, r7, lr}
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; CHECK-T15TE-NEXT: movs r5, r0
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; CHECK-T15TE-NEXT: adds r0, r0, r2
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; CHECK-T15TE-NEXT: mov r12, r1
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; CHECK-T15TE-NEXT: mov r0, r12
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; CHECK-T15TE-NEXT: adcs r0, r3
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; CHECK-T15TE-NEXT: asrs r0, r0, #31
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; CHECK-T15TE-NEXT: movs r4, #1
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; CHECK-T15TE-NEXT: lsls r4, r4, #31
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; CHECK-T15TE-NEXT: eors r4, r0
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; CHECK-T15TE-NEXT: adds r2, r5, r2
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; CHECK-T15TE-NEXT: adcs r1, r3
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; CHECK-T15TE-NEXT: bvc .LBB1_3
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; CHECK-T15TE-NEXT: @ %bb.1:
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; CHECK-T15TE-NEXT: bpl .LBB1_4
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; CHECK-T15TE-NEXT: bvc .LBB1_4
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; CHECK-T15TE-NEXT: .LBB1_2:
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; CHECK-T15TE-NEXT: pop {r4, pc}
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; CHECK-T15TE-NEXT: movs r1, r4
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; CHECK-T15TE-NEXT: pop {r4, r5, r7, pc}
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; CHECK-T15TE-NEXT: .LBB1_3:
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; CHECK-T15TE-NEXT: mov r12, r2
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; CHECK-T15TE-NEXT: mov r0, r12
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; CHECK-T15TE-NEXT: bmi .LBB1_2
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; CHECK-T15TE-NEXT: bvs .LBB1_2
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; CHECK-T15TE-NEXT: .LBB1_4:
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; CHECK-T15TE-NEXT: movs r1, r3
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; CHECK-T15TE-NEXT: pop {r4, pc}
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; CHECK-T15TE-NEXT: movs r4, r1
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; CHECK-T15TE-NEXT: movs r1, r4
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; CHECK-T15TE-NEXT: pop {r4, r5, r7, pc}
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%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
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ret i64 %tmp
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}
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@@ -53,65 +53,54 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
|
||||
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
|
||||
; CHECK-T1-LABEL: func64:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, lr}
|
||||
; CHECK-T1-NEXT: push {r4, lr}
|
||||
; CHECK-T1-NEXT: ldr r3, [sp, #12]
|
||||
; CHECK-T1-NEXT: mov r2, r1
|
||||
; CHECK-T1-NEXT: eors r2, r3
|
||||
; CHECK-T1-NEXT: ldr r4, [sp, #8]
|
||||
; CHECK-T1-NEXT: adds r4, r0, r4
|
||||
; CHECK-T1-NEXT: adcs r3, r1
|
||||
; CHECK-T1-NEXT: eors r1, r3
|
||||
; CHECK-T1-NEXT: bics r1, r2
|
||||
; CHECK-T1-NEXT: asrs r0, r3, #31
|
||||
; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-T1-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-T1-NEXT: mov r3, r0
|
||||
; CHECK-T1-NEXT: ldr r4, [sp, #20]
|
||||
; CHECK-T1-NEXT: ldr r5, [sp, #16]
|
||||
; CHECK-T1-NEXT: adds r0, r0, r5
|
||||
; CHECK-T1-NEXT: mov r0, r1
|
||||
; CHECK-T1-NEXT: adcs r0, r4
|
||||
; CHECK-T1-NEXT: asrs r0, r0, #31
|
||||
; CHECK-T1-NEXT: movs r2, #1
|
||||
; CHECK-T1-NEXT: lsls r2, r2, #31
|
||||
; CHECK-T1-NEXT: eors r2, r0
|
||||
; CHECK-T1-NEXT: cmp r1, #0
|
||||
; CHECK-T1-NEXT: bpl .LBB1_3
|
||||
; CHECK-T1-NEXT: adds r3, r3, r5
|
||||
; CHECK-T1-NEXT: adcs r1, r4
|
||||
; CHECK-T1-NEXT: bvc .LBB1_3
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: bpl .LBB1_4
|
||||
; CHECK-T1-NEXT: bvc .LBB1_4
|
||||
; CHECK-T1-NEXT: .LBB1_2:
|
||||
; CHECK-T1-NEXT: mov r1, r2
|
||||
; CHECK-T1-NEXT: pop {r4, pc}
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-T1-NEXT: .LBB1_3:
|
||||
; CHECK-T1-NEXT: mov r0, r4
|
||||
; CHECK-T1-NEXT: bmi .LBB1_2
|
||||
; CHECK-T1-NEXT: mov r0, r3
|
||||
; CHECK-T1-NEXT: bvs .LBB1_2
|
||||
; CHECK-T1-NEXT: .LBB1_4:
|
||||
; CHECK-T1-NEXT: mov r2, r3
|
||||
; CHECK-T1-NEXT: mov r2, r1
|
||||
; CHECK-T1-NEXT: mov r1, r2
|
||||
; CHECK-T1-NEXT: pop {r4, pc}
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
|
||||
;
|
||||
; CHECK-T2-LABEL: func64:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: ldr r2, [sp]
|
||||
; CHECK-T2-NEXT: ldr.w r12, [sp, #4]
|
||||
; CHECK-T2-NEXT: adds r0, r0, r2
|
||||
; CHECK-T2-NEXT: adc.w r2, r1, r12
|
||||
; CHECK-T2-NEXT: eor.w r3, r1, r12
|
||||
; CHECK-T2-NEXT: eors r1, r2
|
||||
; CHECK-T2-NEXT: bics r1, r3
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: asrmi r0, r2, #31
|
||||
; CHECK-T2-NEXT: mov.w r1, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31
|
||||
; CHECK-T2-NEXT: mov r1, r2
|
||||
; CHECK-T2-NEXT: ldrd r3, r2, [sp]
|
||||
; CHECK-T2-NEXT: adds r0, r0, r3
|
||||
; CHECK-T2-NEXT: adcs r1, r2
|
||||
; CHECK-T2-NEXT: it vs
|
||||
; CHECK-T2-NEXT: asrvs r0, r1, #31
|
||||
; CHECK-T2-NEXT: mov.w r2, #-2147483648
|
||||
; CHECK-T2-NEXT: it vs
|
||||
; CHECK-T2-NEXT: eorvs.w r1, r2, r1, asr #31
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func64:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: ldr r12, [sp]
|
||||
; CHECK-ARM-NEXT: ldr r2, [sp, #4]
|
||||
; CHECK-ARM-NEXT: adds r0, r0, r12
|
||||
; CHECK-ARM-NEXT: eor r3, r1, r2
|
||||
; CHECK-ARM-NEXT: adc r2, r1, r2
|
||||
; CHECK-ARM-NEXT: eor r1, r1, r2
|
||||
; CHECK-ARM-NEXT: bics r1, r1, r3
|
||||
; CHECK-ARM-NEXT: asrmi r0, r2, #31
|
||||
; CHECK-ARM-NEXT: mov r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
|
||||
; CHECK-ARM-NEXT: mov r1, r2
|
||||
; CHECK-ARM-NEXT: ldm sp, {r2, r3}
|
||||
; CHECK-ARM-NEXT: adds r0, r0, r2
|
||||
; CHECK-ARM-NEXT: mov r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: adcs r1, r1, r3
|
||||
; CHECK-ARM-NEXT: asrvs r0, r1, #31
|
||||
; CHECK-ARM-NEXT: eorvs r1, r2, r1, asr #31
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%a = mul i64 %y, %z
|
||||
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
|
||||
|
||||
@@ -64,56 +64,48 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-T1-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-T1-NEXT: mov r4, r1
|
||||
; CHECK-T1-NEXT: eors r1, r3
|
||||
; CHECK-T1-NEXT: subs r5, r0, r2
|
||||
; CHECK-T1-NEXT: mov r2, r4
|
||||
; CHECK-T1-NEXT: sbcs r2, r3
|
||||
; CHECK-T1-NEXT: eors r4, r2
|
||||
; CHECK-T1-NEXT: ands r4, r1
|
||||
; CHECK-T1-NEXT: asrs r0, r2, #31
|
||||
; CHECK-T1-NEXT: movs r1, #1
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #31
|
||||
; CHECK-T1-NEXT: eors r1, r0
|
||||
; CHECK-T1-NEXT: cmp r4, #0
|
||||
; CHECK-T1-NEXT: bpl .LBB1_3
|
||||
; CHECK-T1-NEXT: mov r5, r0
|
||||
; CHECK-T1-NEXT: subs r0, r0, r2
|
||||
; CHECK-T1-NEXT: mov r0, r1
|
||||
; CHECK-T1-NEXT: sbcs r0, r3
|
||||
; CHECK-T1-NEXT: asrs r0, r0, #31
|
||||
; CHECK-T1-NEXT: movs r4, #1
|
||||
; CHECK-T1-NEXT: lsls r4, r4, #31
|
||||
; CHECK-T1-NEXT: eors r4, r0
|
||||
; CHECK-T1-NEXT: subs r2, r5, r2
|
||||
; CHECK-T1-NEXT: sbcs r1, r3
|
||||
; CHECK-T1-NEXT: bvc .LBB1_3
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: bpl .LBB1_4
|
||||
; CHECK-T1-NEXT: bvc .LBB1_4
|
||||
; CHECK-T1-NEXT: .LBB1_2:
|
||||
; CHECK-T1-NEXT: mov r1, r4
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-T1-NEXT: .LBB1_3:
|
||||
; CHECK-T1-NEXT: mov r0, r5
|
||||
; CHECK-T1-NEXT: bmi .LBB1_2
|
||||
; CHECK-T1-NEXT: mov r0, r2
|
||||
; CHECK-T1-NEXT: bvs .LBB1_2
|
||||
; CHECK-T1-NEXT: .LBB1_4:
|
||||
; CHECK-T1-NEXT: mov r1, r2
|
||||
; CHECK-T1-NEXT: mov r4, r1
|
||||
; CHECK-T1-NEXT: mov r1, r4
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
|
||||
;
|
||||
; CHECK-T2-LABEL: func2:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: subs r0, r0, r2
|
||||
; CHECK-T2-NEXT: eor.w r12, r1, r3
|
||||
; CHECK-T2-NEXT: sbc.w r2, r1, r3
|
||||
; CHECK-T2-NEXT: eors r1, r2
|
||||
; CHECK-T2-NEXT: ands.w r1, r1, r12
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: asrmi r0, r2, #31
|
||||
; CHECK-T2-NEXT: mov.w r1, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31
|
||||
; CHECK-T2-NEXT: mov r1, r2
|
||||
; CHECK-T2-NEXT: mov.w r2, #-2147483648
|
||||
; CHECK-T2-NEXT: sbcs r1, r3
|
||||
; CHECK-T2-NEXT: it vs
|
||||
; CHECK-T2-NEXT: asrvs r0, r1, #31
|
||||
; CHECK-T2-NEXT: it vs
|
||||
; CHECK-T2-NEXT: eorvs.w r1, r2, r1, asr #31
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func2:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: subs r0, r0, r2
|
||||
; CHECK-ARM-NEXT: eor r12, r1, r3
|
||||
; CHECK-ARM-NEXT: sbc r2, r1, r3
|
||||
; CHECK-ARM-NEXT: eor r1, r1, r2
|
||||
; CHECK-ARM-NEXT: ands r1, r12, r1
|
||||
; CHECK-ARM-NEXT: asrmi r0, r2, #31
|
||||
; CHECK-ARM-NEXT: mov r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
|
||||
; CHECK-ARM-NEXT: mov r1, r2
|
||||
; CHECK-ARM-NEXT: mov r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: sbcs r1, r1, r3
|
||||
; CHECK-ARM-NEXT: asrvs r0, r1, #31
|
||||
; CHECK-ARM-NEXT: eorvs r1, r2, r1, asr #31
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y)
|
||||
ret i64 %tmp
|
||||
|
||||
@@ -56,64 +56,52 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-T1-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-T1-NEXT: ldr r2, [sp, #20]
|
||||
; CHECK-T1-NEXT: mov r5, r1
|
||||
; CHECK-T1-NEXT: eors r5, r2
|
||||
; CHECK-T1-NEXT: ldr r3, [sp, #16]
|
||||
; CHECK-T1-NEXT: subs r4, r0, r3
|
||||
; CHECK-T1-NEXT: mov r3, r1
|
||||
; CHECK-T1-NEXT: sbcs r3, r2
|
||||
; CHECK-T1-NEXT: eors r1, r3
|
||||
; CHECK-T1-NEXT: ands r1, r5
|
||||
; CHECK-T1-NEXT: asrs r0, r3, #31
|
||||
; CHECK-T1-NEXT: mov r3, r0
|
||||
; CHECK-T1-NEXT: ldr r4, [sp, #20]
|
||||
; CHECK-T1-NEXT: ldr r5, [sp, #16]
|
||||
; CHECK-T1-NEXT: subs r0, r0, r5
|
||||
; CHECK-T1-NEXT: mov r0, r1
|
||||
; CHECK-T1-NEXT: sbcs r0, r4
|
||||
; CHECK-T1-NEXT: asrs r0, r0, #31
|
||||
; CHECK-T1-NEXT: movs r2, #1
|
||||
; CHECK-T1-NEXT: lsls r2, r2, #31
|
||||
; CHECK-T1-NEXT: eors r2, r0
|
||||
; CHECK-T1-NEXT: cmp r1, #0
|
||||
; CHECK-T1-NEXT: bpl .LBB1_3
|
||||
; CHECK-T1-NEXT: subs r3, r3, r5
|
||||
; CHECK-T1-NEXT: sbcs r1, r4
|
||||
; CHECK-T1-NEXT: bvc .LBB1_3
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: bpl .LBB1_4
|
||||
; CHECK-T1-NEXT: bvc .LBB1_4
|
||||
; CHECK-T1-NEXT: .LBB1_2:
|
||||
; CHECK-T1-NEXT: mov r1, r2
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-T1-NEXT: .LBB1_3:
|
||||
; CHECK-T1-NEXT: mov r0, r4
|
||||
; CHECK-T1-NEXT: bmi .LBB1_2
|
||||
; CHECK-T1-NEXT: mov r0, r3
|
||||
; CHECK-T1-NEXT: bvs .LBB1_2
|
||||
; CHECK-T1-NEXT: .LBB1_4:
|
||||
; CHECK-T1-NEXT: mov r2, r3
|
||||
; CHECK-T1-NEXT: mov r2, r1
|
||||
; CHECK-T1-NEXT: mov r1, r2
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
|
||||
;
|
||||
; CHECK-T2-LABEL: func64:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: ldr r2, [sp]
|
||||
; CHECK-T2-NEXT: ldr.w r12, [sp, #4]
|
||||
; CHECK-T2-NEXT: subs r0, r0, r2
|
||||
; CHECK-T2-NEXT: sbc.w r2, r1, r12
|
||||
; CHECK-T2-NEXT: eor.w r3, r1, r12
|
||||
; CHECK-T2-NEXT: eors r1, r2
|
||||
; CHECK-T2-NEXT: ands r1, r3
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: asrmi r0, r2, #31
|
||||
; CHECK-T2-NEXT: mov.w r1, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31
|
||||
; CHECK-T2-NEXT: mov r1, r2
|
||||
; CHECK-T2-NEXT: ldrd r3, r2, [sp]
|
||||
; CHECK-T2-NEXT: subs r0, r0, r3
|
||||
; CHECK-T2-NEXT: sbcs r1, r2
|
||||
; CHECK-T2-NEXT: it vs
|
||||
; CHECK-T2-NEXT: asrvs r0, r1, #31
|
||||
; CHECK-T2-NEXT: mov.w r2, #-2147483648
|
||||
; CHECK-T2-NEXT: it vs
|
||||
; CHECK-T2-NEXT: eorvs.w r1, r2, r1, asr #31
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func64:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: ldr r12, [sp]
|
||||
; CHECK-ARM-NEXT: ldr r2, [sp, #4]
|
||||
; CHECK-ARM-NEXT: subs r0, r0, r12
|
||||
; CHECK-ARM-NEXT: eor r3, r1, r2
|
||||
; CHECK-ARM-NEXT: sbc r2, r1, r2
|
||||
; CHECK-ARM-NEXT: eor r1, r1, r2
|
||||
; CHECK-ARM-NEXT: ands r1, r3, r1
|
||||
; CHECK-ARM-NEXT: asrmi r0, r2, #31
|
||||
; CHECK-ARM-NEXT: mov r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
|
||||
; CHECK-ARM-NEXT: mov r1, r2
|
||||
; CHECK-ARM-NEXT: ldm sp, {r2, r3}
|
||||
; CHECK-ARM-NEXT: subs r0, r0, r2
|
||||
; CHECK-ARM-NEXT: mov r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: sbcs r1, r1, r3
|
||||
; CHECK-ARM-NEXT: asrvs r0, r1, #31
|
||||
; CHECK-ARM-NEXT: eorvs r1, r2, r1, asr #31
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%a = mul i64 %y, %z
|
||||
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
|
||||
|
||||
Reference in new issue
Block a user