Move towards using the triple for representing incompatible ISA changes. Use the subarch field to represent the various incompatible cases. Previously we pretended a single triple arch was universally compatible, and only distinguished by function level subtargets. Move towards using distinct triples to enable more sophisticated toolchain handling in the future, like proper runtime library linking. Introduce a new subarch per unique ISA, but also introduce "major subarches" which are compatible by a set of covered minor ISA versions. These map to the existing generic targets. There are a few placeholder subarch entries, which currently have missing backing generic arches for codegen. This should be the preferred triple arch name going forward, but is treated as an alias of amdgcn. This does not yet change clang to emit the new triples. Part of #154925
182 lines
6.2 KiB
C++
182 lines
6.2 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "clang/Basic/OffloadArch.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/TargetParser/Triple.h"
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namespace clang {
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namespace {
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struct OffloadArchToStringMap {
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OffloadArch Arch;
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const char *ArchName;
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const char *VirtualArchName;
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};
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} // namespace
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#define SM(sm) {OffloadArch::SM_##sm, "sm_" #sm, "compute_" #sm}
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#define GFX(gpu) {OffloadArch::GFX##gpu, "gfx" #gpu, "compute_amdgcn"}
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static const OffloadArchToStringMap ArchNames[] = {
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// clang-format off
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{OffloadArch::Unused, "", ""},
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SM(20), {OffloadArch::SM_21, "sm_21", "compute_20"}, // Fermi
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SM(30), {OffloadArch::SM_32_, "sm_32", "compute_32"}, SM(35), SM(37), // Kepler
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SM(50), SM(52), SM(53), // Maxwell
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SM(60), SM(61), SM(62), // Pascal
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SM(70), SM(72), // Volta
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SM(75), // Turing
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SM(80), SM(86), // Ampere
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SM(87), // Jetson/Drive AGX Orin
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SM(88), // Ampere
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SM(89), // Ada Lovelace
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SM(90), // Hopper
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SM(90a), // Hopper
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SM(100), // Blackwell
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SM(100a), // Blackwell
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SM(100f), // Blackwell
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SM(101), // Blackwell
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SM(101a), // Blackwell
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SM(101f), // Blackwell
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SM(103), // Blackwell
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SM(103a), // Blackwell
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SM(103f), // Blackwell
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SM(110), // Blackwell
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SM(110a), // Blackwell
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SM(110f), // Blackwell
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SM(120), // Blackwell
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SM(120a), // Blackwell
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SM(120f), // Blackwell
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SM(121), // Blackwell
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SM(121a), // Blackwell
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SM(121f), // Blackwell
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GFX(600), // gfx600
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GFX(601), // gfx601
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GFX(602), // gfx602
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GFX(700), // gfx700
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GFX(701), // gfx701
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GFX(702), // gfx702
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GFX(703), // gfx703
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GFX(704), // gfx704
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GFX(705), // gfx705
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GFX(801), // gfx801
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GFX(802), // gfx802
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GFX(803), // gfx803
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GFX(805), // gfx805
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GFX(810), // gfx810
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{OffloadArch::GFX9_GENERIC, "gfx9-generic", "compute_amdgcn"},
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GFX(900), // gfx900
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GFX(902), // gfx902
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GFX(904), // gfx903
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GFX(906), // gfx906
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GFX(908), // gfx908
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GFX(909), // gfx909
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GFX(90a), // gfx90a
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GFX(90c), // gfx90c
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{OffloadArch::GFX9_4_GENERIC, "gfx9-4-generic", "compute_amdgcn"},
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GFX(942), // gfx942
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GFX(950), // gfx950
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{OffloadArch::GFX10_1_GENERIC, "gfx10-1-generic", "compute_amdgcn"},
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GFX(1010), // gfx1010
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GFX(1011), // gfx1011
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GFX(1012), // gfx1012
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GFX(1013), // gfx1013
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{OffloadArch::GFX10_3_GENERIC, "gfx10-3-generic", "compute_amdgcn"},
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GFX(1030), // gfx1030
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GFX(1031), // gfx1031
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GFX(1032), // gfx1032
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GFX(1033), // gfx1033
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GFX(1034), // gfx1034
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GFX(1035), // gfx1035
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GFX(1036), // gfx1036
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{OffloadArch::GFX11_GENERIC, "gfx11-generic", "compute_amdgcn"},
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GFX(1100), // gfx1100
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GFX(1101), // gfx1101
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GFX(1102), // gfx1102
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GFX(1103), // gfx1103
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GFX(1150), // gfx1150
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GFX(1151), // gfx1151
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GFX(1152), // gfx1152
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GFX(1153), // gfx1153
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GFX(1154), // gfx1154
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{OffloadArch::GFX11_7_GENERIC, "gfx11-7-generic", "compute_amdgcn"},
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GFX(1170), // gfx1170
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GFX(1171), // gfx1171
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GFX(1172), // gfx1172
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{OffloadArch::GFX12_GENERIC, "gfx12-generic", "compute_amdgcn"},
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GFX(1200), // gfx1200
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GFX(1201), // gfx1201
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{OffloadArch::GFX12_5_GENERIC, "gfx12-5-generic", "compute_amdgcn"},
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GFX(1250), // gfx1250
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GFX(1251), // gfx1251
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{OffloadArch::GFX13_GENERIC, "gfx13-generic", "compute_amdgcn"},
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GFX(1310), // gfx1310
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{OffloadArch::AMDGCNSPIRV, "amdgcnspirv", "compute_amdgcn"},
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// Intel CPUs
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{OffloadArch::GRANITERAPIDS, "graniterapids", ""},
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// Intel GPUS
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{OffloadArch::BMG_G21, "bmg_g21", ""},
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{OffloadArch::Generic, "generic", ""},
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// clang-format on
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};
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#undef SM
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#undef GFX
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const char *OffloadArchToString(OffloadArch A) {
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auto Result =
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llvm::find_if(ArchNames, [A](const OffloadArchToStringMap &Map) {
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return A == Map.Arch;
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});
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if (Result == std::end(ArchNames))
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return "unknown";
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return Result->ArchName;
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}
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const char *OffloadArchToVirtualArchString(OffloadArch A) {
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auto Result =
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llvm::find_if(ArchNames, [A](const OffloadArchToStringMap &Map) {
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return A == Map.Arch;
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});
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if (Result == std::end(ArchNames))
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return "unknown";
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return Result->VirtualArchName;
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}
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OffloadArch StringToOffloadArch(llvm::StringRef S) {
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auto Result =
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llvm::find_if(ArchNames, [S](const OffloadArchToStringMap &Map) {
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return S == Map.ArchName;
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});
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if (Result == std::end(ArchNames))
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return OffloadArch::Unknown;
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return Result->Arch;
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}
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llvm::Triple OffloadArchToTriple(const llvm::Triple &DefaultToolchainTriple,
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OffloadArch ID) {
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if (ID == OffloadArch::AMDGCNSPIRV)
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return llvm::Triple(llvm::Triple::spirv64, llvm::Triple::NoSubArch,
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llvm::Triple::AMD, llvm::Triple::AMDHSA);
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if (IsNVIDIAOffloadArch(ID)) {
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llvm::Triple::ArchType Arch = DefaultToolchainTriple.isArch64Bit()
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? llvm::Triple::nvptx64
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: llvm::Triple::nvptx;
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return llvm::Triple(Arch, llvm::Triple::NoSubArch, llvm::Triple::NVIDIA,
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llvm::Triple::CUDA);
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}
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if (IsAMDOffloadArch(ID))
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return llvm::Triple("amdgcn-amd-amdhsa");
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return {};
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}
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} // namespace clang
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