Quentin Colombet
422af7cca6
Adds two optional fields to the per-vreg YAML record so MIR tests can
express VirtRegMap state that previously had no representation:
registers:
- { id: 1, class: vgpr_32, split-from: '%0', assigned-phys: '$vgpr5' }
Testing passes that consume sibling-register information (e.g.
InlineSpiller) requires constructing a VirtRegMap with split
relationships from a MIR test, which implies triggering live-range
splitting at minimum and make reproducers unnecessarily complicated.
So this change introduces a mechanism to serialize/deserialize the state
of the VirtRegMap pass.
Mechanism:
- For serialization:
- MIRPrinter emits the new fields only when the VirtRegMap is available.
- For deserialization:
- MIRParser stashes parsed entries in the MachineRegisterInfo object
- VirtRegMap::init() drains the stash via assignVirt2Phys and
setIsSplitFromReg, then clears it.
Validation at parse time:
- 'assigned-phys' must be a physical register.
- 'split-from' must reference a different vreg than 'id'.
- 'split-from' physregs / named-vreg references already rejected
by parseStandaloneVirtualRegister.
I'm not super happy about stashing the VRM info in the MRI, but that's
a small price to pay.
92 lines
2.8 KiB
C++
92 lines
2.8 KiB
C++
//===- MIRPrintingPass.cpp - Pass that prints out using the MIR format ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass that prints out the LLVM module using the MIR
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// serialization format.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MIRPrinter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/IR/Function.h"
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#include "llvm/InitializePasses.h"
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using namespace llvm;
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PreservedAnalyses PrintMIRPreparePass::run(Module &M, ModuleAnalysisManager &) {
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printMIR(OS, M);
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return PreservedAnalyses::all();
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}
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PreservedAnalyses PrintMIRPass::run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM) {
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auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
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.getManager();
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const VirtRegMap *VRM = MFAM.getCachedResult<VirtRegMapAnalysis>(MF);
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printMIR(OS, FAM, MF, VRM);
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return PreservedAnalyses::all();
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}
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namespace {
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/// This pass prints out the LLVM IR to an output stream using the MIR
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/// serialization format.
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struct MIRPrintingPass : public MachineFunctionPass {
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static char ID;
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raw_ostream &OS;
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std::string MachineFunctions;
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MIRPrintingPass() : MachineFunctionPass(ID), OS(dbgs()) {}
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MIRPrintingPass(raw_ostream &OS) : MachineFunctionPass(ID), OS(OS) {}
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StringRef getPassName() const override { return "MIR Printing Pass"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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AU.addUsedIfAvailable<VirtRegMapWrapperLegacy>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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std::string Str;
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raw_string_ostream StrOS(Str);
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MachineModuleInfo *MMI =
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&getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
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const VirtRegMap *VRM = nullptr;
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if (auto *W = getAnalysisIfAvailable<VirtRegMapWrapperLegacy>())
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VRM = &W->getVRM();
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printMIR(StrOS, *MMI, MF, VRM);
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MachineFunctions.append(Str);
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return false;
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}
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bool doFinalization(Module &M) override {
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printMIR(OS, M);
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OS << MachineFunctions;
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return false;
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}
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};
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char MIRPrintingPass::ID = 0;
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} // end anonymous namespace
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char &llvm::MIRPrintingPassID = MIRPrintingPass::ID;
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INITIALIZE_PASS(MIRPrintingPass, "mir-printer", "MIR Printer", false, false)
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MachineFunctionPass *llvm::createPrintMIRPass(raw_ostream &OS) {
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return new MIRPrintingPass(OS);
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}
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