Ömer Sinan Ağacan
790f062341
Implements FIXMEs around memcpy and memmove lowering code about passing destination and source alignments to lowering functions. Fixes ARM cost model's cost estimation for an inlined `memcpy`. The test shows the generated code as two instructions so the cost should've been 2, but it was estimated as a libcall which costs 4. In the backend functions that don't care about destination and source alignments, the old alignment calculation `std::min(dstAlign, srcAlign)` used as the alignment. This gives us the old lowering behavior on those backends.
90 lines
3.6 KiB
C++
90 lines
3.6 KiB
C++
//===-- WebAssemblySelectionDAGInfo.cpp - WebAssembly SelectionDAG Info ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the WebAssemblySelectionDAGInfo class.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblySelectionDAGInfo.h"
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#include "WebAssemblyTargetMachine.h"
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#define GET_SDNODE_DESC
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#include "WebAssemblyGenSDNodeInfo.inc"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-selectiondag-info"
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WebAssemblySelectionDAGInfo::WebAssemblySelectionDAGInfo()
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: SelectionDAGGenTargetInfo(WebAssemblyGenSDNodeInfo) {}
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WebAssemblySelectionDAGInfo::~WebAssemblySelectionDAGInfo() = default; // anchor
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const char *
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WebAssemblySelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
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switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
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case WebAssemblyISD::CALL:
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return "WebAssemblyISD::CALL";
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case WebAssemblyISD::RET_CALL:
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return "WebAssemblyISD::RET_CALL";
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}
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return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode);
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}
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SDValue WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
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SDValue Size, Align DstAlign, Align SrcAlign, bool IsVolatile,
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bool AlwaysInline, MachinePointerInfo DstPtrInfo,
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MachinePointerInfo SrcPtrInfo) const {
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auto &ST = DAG.getMachineFunction().getSubtarget<WebAssemblySubtarget>();
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if (!ST.hasBulkMemoryOpt())
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return SDValue();
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SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32);
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auto LenMVT = ST.hasAddr64() ? MVT::i64 : MVT::i32;
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// Use `MEMCPY` here instead of `MEMORY_COPY` because `memory.copy` traps
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// if the pointers are invalid even if the length is zero. `MEMCPY` gets
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// extra code to handle this in the way that LLVM IR expects.
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return DAG.getNode(
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WebAssemblyISD::MEMCPY, DL, MVT::Other,
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{Chain, MemIdx, MemIdx, Dst, Src, DAG.getZExtOrTrunc(Size, DL, LenMVT)});
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}
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SDValue WebAssemblySelectionDAGInfo::EmitTargetCodeForMemmove(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2,
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SDValue Op3, Align DstAlign, Align SrcAlign, bool IsVolatile,
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MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
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return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, DstAlign,
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SrcAlign, IsVolatile, false, DstPtrInfo,
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SrcPtrInfo);
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}
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SDValue WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Val,
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SDValue Size, Align Alignment, bool IsVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo) const {
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auto &ST = DAG.getMachineFunction().getSubtarget<WebAssemblySubtarget>();
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if (!ST.hasBulkMemoryOpt())
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return SDValue();
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SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32);
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auto LenMVT = ST.hasAddr64() ? MVT::i64 : MVT::i32;
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// Use `MEMSET` here instead of `MEMORY_FILL` because `memory.fill` traps
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// if the pointers are invalid even if the length is zero. `MEMSET` gets
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// extra code to handle this in the way that LLVM IR expects.
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//
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// Only low byte matters for val argument, so anyext the i8
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return DAG.getNode(WebAssemblyISD::MEMSET, DL, MVT::Other, Chain, MemIdx, Dst,
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DAG.getAnyExtOrTrunc(Val, DL, MVT::i32),
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DAG.getZExtOrTrunc(Size, DL, LenMVT));
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}
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