Matt ArsenaultandClaude
5742a30a74
Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@anthropic.com> (Claude-Opus-4.8)
58 lines
2.0 KiB
LLVM
58 lines
2.0 KiB
LLVM
; RUN: llc -O0 -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -mtriple=amdgpu10.10 -mattr=-flat-for-global,+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -mtriple=amdgpu11.00 -mattr=-flat-for-global,+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_branch:
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; GCNNOOPT: v_writelane_b32
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; GCNNOOPT: v_writelane_b32
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; GCNNOOPT: s_cbranch_vccnz [[END:.LBB[0-9]+_[0-9]+]]
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; GCNOPT: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]
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; GCNNOOPT: v_readlane_b32
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; GCNNOOPT: v_readlane_b32
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; GCN: buffer_store_{{dword|b32}}
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; GCNNOOPT: s_endpgm
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; GCN: {{^}}[[END]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @test_branch(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i32 %val) #0 {
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%cmp = icmp ne i32 %val, 0
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br i1 %cmp, label %store, label %end
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store:
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store i32 222, ptr addrspace(1) %out
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ret void
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end:
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ret void
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}
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; GCN-LABEL: {{^}}test_brcc_i1:
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; GCN: s_load_{{dword|b32}} [[VAL:s[0-9]+]]
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; GCNNOOPT: s_and_b32 s{{[0-9]+}}, 1, [[VAL]]
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; GCNOPT: s_bitcmp0_b32 [[VAL]], 0
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; GCNNOOPT: s_cmp_{{eq|lg}}_u32
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; GCNNOOPT: s_cbranch_vccnz [[END:.LBB[0-9]+_[0-9]+]]
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; GCNOPT: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]
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; GCN: buffer_store_{{dword|b32}}
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; GCN: {{^}}[[END]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @test_brcc_i1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i1 %val) #0 {
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%cmp0 = icmp ne i1 %val, 0
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br i1 %cmp0, label %store, label %end
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store:
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store i32 222, ptr addrspace(1) %out
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ret void
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end:
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ret void
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}
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attributes #0 = { nounwind }
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