Matt ArsenaultandClaude
6e42e25efa
Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@anthropic.com> (Claude-Opus-4.8)
59 lines
2.7 KiB
LLVM
59 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=0 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GCN %s
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declare float @llvm.amdgcn.cubeid(float, float, float) #0
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declare float @llvm.amdgcn.cubesc(float, float, float) #0
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declare float @llvm.amdgcn.cubetc(float, float, float) #0
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declare float @llvm.amdgcn.cubema(float, float, float) #0
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define amdgpu_ps <4 x float> @cube_vvv(float %a, float %b, float %c) #1 {
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; GCN-LABEL: cube_vvv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_cubeid_f32 v6, v0, v1, v2
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; GCN-NEXT: v_cubesc_f32 v4, v0, v1, v2
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; GCN-NEXT: v_cubetc_f32 v5, v0, v1, v2
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; GCN-NEXT: v_cubema_f32 v3, v0, v1, v2
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; GCN-NEXT: v_mov_b32_e32 v0, v6
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; GCN-NEXT: v_mov_b32_e32 v1, v4
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; GCN-NEXT: v_mov_b32_e32 v2, v5
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; GCN-NEXT: ; return to shader part epilog
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%cubeid = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c)
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%cubesc = call float @llvm.amdgcn.cubesc(float %a, float %b, float %c)
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%cubetc = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c)
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%cubema = call float @llvm.amdgcn.cubema(float %a, float %b, float %c)
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%vec0 = insertelement <4 x float> poison, float %cubeid, i32 0
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%vec1 = insertelement <4 x float> %vec0, float %cubesc, i32 1
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%vec2 = insertelement <4 x float> %vec1, float %cubetc, i32 2
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%vec3 = insertelement <4 x float> %vec2, float %cubema, i32 3
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ret <4 x float> %vec3
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}
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define amdgpu_ps <4 x float> @cube_sss(float inreg %a, float inreg %b, float inreg %c) #1 {
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; GCN-LABEL: cube_sss:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v3, s1
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; GCN-NEXT: v_mov_b32_e32 v4, s2
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; GCN-NEXT: v_cubeid_f32 v0, s0, v3, v4
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; GCN-NEXT: v_cubesc_f32 v1, s0, v3, v4
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; GCN-NEXT: v_cubetc_f32 v2, s0, v3, v4
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; GCN-NEXT: v_cubema_f32 v3, s0, v3, v4
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; GCN-NEXT: ; return to shader part epilog
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%cubeid = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c)
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%cubesc = call float @llvm.amdgcn.cubesc(float %a, float %b, float %c)
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%cubetc = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c)
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%cubema = call float @llvm.amdgcn.cubema(float %a, float %b, float %c)
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%vec0 = insertelement <4 x float> poison, float %cubeid, i32 0
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%vec1 = insertelement <4 x float> %vec0, float %cubesc, i32 1
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%vec2 = insertelement <4 x float> %vec1, float %cubetc, i32 2
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%vec3 = insertelement <4 x float> %vec2, float %cubema, i32 3
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ret <4 x float> %vec3
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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