Matt ArsenaultandClaude
269820947e
Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@anthropic.com> (Claude-Opus-4.8)
66 lines
3.3 KiB
LLVM
66 lines
3.3 KiB
LLVM
; RUN: llc < %s -mtriple=amdgpu8.02 -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s
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; RUN: llc < %s -mtriple=amdgpu8.10 | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
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; RUN: llc < %s -mtriple=amdgpu9.00 | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
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; GCN-LABEL: {{^}}buffer_load_format_d16_x:
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; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
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define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) {
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main_body:
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%data = call half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
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ret half %data
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}
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; GCN-LABEL: {{^}}buffer_load_format_d16_xy:
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; UNPACKED: buffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
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; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
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; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
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; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
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define amdgpu_ps half @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) {
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main_body:
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%data = call <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
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%elt = extractelement <2 x half> %data, i32 1
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ret half %elt
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}
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; GCN-LABEL: {{^}}buffer_load_format_d16_xyz:
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; UNPACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
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; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
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; PACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
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; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
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define amdgpu_ps half @buffer_load_format_d16_xyz(<4 x i32> inreg %rsrc) {
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main_body:
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%data = call <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
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%elt = extractelement <3 x half> %data, i32 2
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ret half %elt
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}
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; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw:
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; UNPACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
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; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
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; PACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
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; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
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define amdgpu_ps half @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) {
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main_body:
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%data = call <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
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%elt = extractelement <4 x half> %data, i32 3
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ret half %elt
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}
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; GCN-LABEL: {{^}}buffer_load_format_i16_x:
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; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
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define amdgpu_ps half @buffer_load_format_i16_x(<4 x i32> inreg %rsrc) {
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main_body:
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%data = call i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
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%fdata = bitcast i16 %data to half
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ret half %fdata
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}
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declare half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32>, i32, i32, i32, i32)
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declare <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32>, i32, i32, i32, i32)
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declare <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32, i32)
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declare <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32>, i32, i32, i32, i32)
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declare i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32>, i32, i32, i32, i32)
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