llvm-tms34010

AsmParser

[RISCV] Check that the stack adjust immediate for cm.push/pop* has the correct sign and is divisible by 16. (#85295 )

2024-03-26 13:31:21 -07:00

Disassembler

[RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (#83896 )

2024-03-13 14:56:25 -07:00

GISel

[RISCV][GISel] Make register bank selection for unary and binary arithmetic ops more generic. (#87593 )

2024-04-04 16:17:19 -07:00

MCA

[RISCV] Add TargetParser to MCA (#84109 )

2024-03-06 11:49:28 +08:00

MCTargetDesc

[RISCV] Add validation of SPIMM for cm.push/pop. (#84989 )

2024-03-28 08:38:18 -07:00

TargetInfo

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CMakeLists.txt

[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770 )

2024-02-26 12:12:31 +00:00

RISCV.h

[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770 )

2024-02-26 12:12:31 +00:00

RISCV.td

[RISCV] Move the RISCVSchedule.td include after RISCVRegisterInfo.td. NFC

2024-03-22 11:42:12 -07:00

RISCVAsmPrinter.cpp

[RISCV] Make EmitToStreamer return whether Inst is compressed

2024-04-10 11:02:55 +08:00

RISCVCallingConv.td

[RISCV] RISCV vector calling convention (1/2) (#77560 )

2024-03-27 23:03:13 +08:00

RISCVCodeGenPrepare.cpp

[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.

2024-01-19 14:44:47 -08:00

RISCVCombine.td

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RISCVDeadRegisterDefinitions.cpp

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RISCVExpandAtomicPseudoInsts.cpp

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RISCVExpandPseudoInsts.cpp

[RISCV] Preserve MMO when expanding PseudoRV32ZdinxSD/PseudoRV32ZdinxLD. (#85877 )

2024-03-26 20:42:14 -07:00

RISCVFeatures.td

[RISCV] Zimop/Zcmop are ratified

2024-04-08 16:40:02 +08:00

RISCVFoldMasks.cpp

[RISCV] Use DenseMap to track V0 definition. NFC (#84465 )

2024-03-21 15:38:43 +08:00

RISCVFrameLowering.cpp

[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069 )

2024-04-10 10:28:54 -07:00

RISCVFrameLowering.h

[RISCV] Register fixed stack slots for callee saved registers for -msave-restore/Zcmp (#81392 )

2024-02-13 14:59:28 -08:00

RISCVGatherScatterLowering.cpp

[NFC][RemoveDIs] Use iterators for insertion at various call-sites (#84736 )

2024-03-19 16:36:29 +00:00

RISCVGISel.td

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RISCVInsertReadWriteCSR.cpp

[RISCV] Implement foward inserting save/restore FRM instructions. (#77744 )

2024-01-25 14:41:52 +08:00

RISCVInsertVSETVLI.cpp

[RISCV] Add statistic support for VSETVL insertion pass (#78543 )

2024-01-19 08:22:25 +08:00

RISCVInsertWriteVXRM.cpp

[RISCV] Don't emit vxrm writes for vnclip(u).wi with shift of 0. (#76578 )

2024-01-02 09:50:06 -08:00

RISCVInstrFormats.td

[RISCV] Rename OP-P to OP-VE. (#87546 )

2024-04-05 17:02:03 -07:00

RISCVInstrFormatsC.td

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RISCVInstrFormatsV.td

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RISCVInstrGISel.td

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

RISCVInstrInfo.cpp

[RISCV] Add MachineCombiner to fold (sh3add Z, (add X, (slli Y, 6))) -> (sh3add (sh3add Y, Z), X). (#87884 )

2024-04-10 08:39:56 -07:00

RISCVInstrInfo.h

[RISCV] Eliminate getVLENFactoredAmount and expose muladd [nfc] (#87881 )

2024-04-08 10:24:27 -07:00

RISCVInstrInfo.td

[RISCV] Add Zca predicate to BrccCompressOpt patterns used for MinSize.

2024-04-05 12:39:39 -07:00

RISCVInstrInfoA.td

[RISCV][MC] Add experimental support of Zaamo and Zalrsc

2024-01-25 17:03:25 +08:00

RISCVInstrInfoC.td

[RISCV] Fix scheduling info for compressed LD/ST of FP types. (#82339 )

2024-02-21 08:47:39 +01:00

RISCVInstrInfoD.td

[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887 )

2024-03-20 08:44:24 -07:00

RISCVInstrInfoF.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoM.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385 )

2024-03-07 14:03:58 -08:00

RISCVInstrInfoSFB.td

[RISCV][NFC] Move SFB pseudos and patterns to RISCVInstrInfoSFB.td (#80945 )

2024-02-07 16:03:30 +08:00

RISCVInstrInfoV.td

[RISCV] Model vd as a src for some Zvk* instructions in MC layer. (#86710 )

2024-03-27 12:20:24 -07:00

RISCVInstrInfoVPseudos.td

[RISCV] Support codegen of vfmv.v.f for bfloat vector with both Zvfbfmin and Zfbfmin (#87318 )

2024-04-07 10:41:47 +08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Support codegen of vfmv.v.f for bfloat vector with both Zvfbfmin and Zfbfmin (#87318 )

2024-04-07 10:41:47 +08:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Support codegen of vfmv.v.f for bfloat vector with both Zvfbfmin and Zfbfmin (#87318 )

2024-04-07 10:41:47 +08:00

RISCVInstrInfoXCV.td

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RISCVInstrInfoXSf.td

[RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (#83896 )

2024-03-13 14:56:25 -07:00

RISCVInstrInfoXTHead.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoXVentana.td

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RISCVInstrInfoZa.td

[RISCV][ISel] Add codegen support for the experimental zabha extension (#80192 )

2024-02-16 15:35:09 +08:00

RISCVInstrInfoZalasr.td

[RISCV][MC] MC layer support for the experimental zalasr extension (#79911 )

2024-02-01 10:58:21 -08:00

RISCVInstrInfoZb.td

[RISCV] Extend pattern matches involving shNadd to support disjoint or (#87001 )

2024-03-28 16:34:04 -07:00

RISCVInstrInfoZc.td

[RISCV] Add validation of SPIMM for cm.push/pop. (#84989 )

2024-03-28 08:38:18 -07:00

RISCVInstrInfoZcmop.td

[RISCV] Zimop/Zcmop are ratified

2024-04-08 16:40:02 +08:00

RISCVInstrInfoZfa.td

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RISCVInstrInfoZfbfmin.td

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RISCVInstrInfoZfh.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

[RISCV] Add MC layer support for Zicfiss. (#66043 )

2023-12-30 15:40:20 +08:00

RISCVInstrInfoZicond.td

[RISCV] Graduate Zicond to non-experimental (#79811 )

2024-01-29 15:58:54 +00:00

RISCVInstrInfoZimop.td

[RISCV] Zimop/Zcmop are ratified

2024-04-08 16:40:02 +08:00

RISCVInstrInfoZk.td

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RISCVInstrInfoZvfbf.td

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RISCVInstrInfoZvk.td

[RISCV] Rename OP-P to OP-VE. (#87546 )

2024-04-05 17:02:03 -07:00

RISCVISelDAGToDAG.cpp

[RISCV] Add patterns for fixed vector vwsll (#87316 )

2024-04-04 11:30:23 +08:00

RISCVISelDAGToDAG.h

[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407 )

2024-01-26 11:15:53 +08:00

RISCVISelLowering.cpp

[RISCV] Use vector getConstant instead of getSplatVector+getConstant. NFC

2024-04-10 19:39:41 -07:00

RISCVISelLowering.h

[RISCV] RISCV vector calling convention (2/2) (#79096 )

2024-03-30 21:05:33 +08:00

RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

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RISCVMacroFusion.td

[RISCV] Use TableGen-based macro fusion (#72224 )

2024-01-25 17:10:49 +08:00

RISCVMakeCompressible.cpp

[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83375 )

2024-03-27 13:40:38 +08:00

RISCVMergeBaseOffset.cpp

[RISCV] Merge ADDI with X0 into base offset (#78940 )

2024-01-23 09:57:05 +08:00

RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

[RISCV] Add a tune feature to disable stripping W suffix (#86255 )

2024-03-25 11:44:16 +08:00

RISCVPostRAExpandPseudoInsts.cpp

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RISCVProcessors.td

[RISCV] Add SiFiveP600Model SchedModel that is used by sifive-p670 (#84962 )

2024-03-18 13:44:21 -04:00

RISCVPushPopOptimizer.cpp

[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039 )

2024-02-07 14:30:45 -08:00

RISCVRedundantCopyElimination.cpp

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RISCVRegisterInfo.cpp

[RISCV] Address review comment from 88062

2024-04-10 07:21:41 -07:00

RISCVRegisterInfo.h

[RISCV] Store VLMul/NF into RegisterClass's TSFlags

2024-04-08 13:35:37 +08:00

RISCVRegisterInfo.td

[RISCV] Store VLMul/NF into RegisterClass's TSFlags

2024-04-08 13:35:37 +08:00

RISCVSchedRocket.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385 )

2024-03-07 14:03:58 -08:00

RISCVSchedSiFive7.td

[RISCV] ReadStoreData is read later in the pipeline for SiFive7 (#86454 )

2024-04-01 09:35:42 -04:00

RISCVSchedSiFiveP400.td

[RISCV] Add sched classes for Zbb integer min max instructions

2024-03-14 06:02:42 -07:00

RISCVSchedSiFiveP600.td

[RISCV] Add IMinMax sched resources to P600SchedModel

2024-03-18 10:49:30 -07:00

RISCVSchedSyntacoreSCR1.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385 )

2024-03-07 14:03:58 -08:00

RISCVSchedule.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385 )

2024-03-07 14:03:58 -08:00

RISCVScheduleV.td

[RISCV] Rename schedule classes for vmv.s.x, vmv.x.s, vfmv.s.f, and vfmv.f.s [nfc] (#84563 )

2024-03-11 07:52:28 -07:00

RISCVScheduleZb.td

[RISCV] Add sched classes for Zbb integer min max instructions

2024-03-14 06:02:42 -07:00

RISCVSchedXiangShanNanHu.td

[RISCV] Add sched classes for Zbb integer min max instructions

2024-03-14 06:02:42 -07:00

RISCVSubtarget.cpp

[RISCV] Use TableGen-based macro fusion (#72224 )

2024-01-25 17:10:49 +08:00

RISCVSubtarget.h

[RISCV][NFC] Add isTargetAndroid API in RISCVSubtarget (#87671 )

2024-04-04 15:21:59 -07:00

RISCVSystemOperands.td

[RISCV] Add the CSR names from Smrnmi. (#83370 )

2024-03-19 21:27:25 -07:00

RISCVTargetMachine.cpp

[RISCV][NFC] Add helpers for RVV register classes

2024-03-07 14:18:37 +08:00

RISCVTargetMachine.h

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RISCVTargetObjectFile.cpp

[RISCV] Place mergeable small read only data into srodata section (#82214 )

2024-03-11 13:57:06 +08:00

RISCVTargetObjectFile.h

[RISCV] Place mergeable small read only data into srodata section (#82214 )

2024-03-11 13:57:06 +08:00

RISCVTargetTransformInfo.cpp

[RISCV][TTI] Scale the cost of Select with LMUL (#88098 )

2024-04-10 14:18:15 +08:00

RISCVTargetTransformInfo.h

[AArch64] Add costs for ST3 and ST4 instructions, modelled as store(shuffle). (#87934 )

2024-04-09 16:36:08 +01:00