Heejin Ahn
cde083e010
FixIrreducibleControlFlow pass adds dispatch blocks with a `br_table` that has multiple predecessors and successors, because it serves as something like a traffic hub for BBs. As a result of this, there can be register uses that are not dominated by a def in every path from the entry block. For example, suppose register %a is defined in BB1 and used in BB2, and there is a single path from BB1 and BB2: ``` BB1 -> ... -> BB2 ``` After FixIrreducibleControlFlow runs, there can be a dispatch block between these two BBs: ``` BB1 -> ... -> Dispatch -> ... -> BB2 ``` And this dispatch block has multiple predecessors, now there is a path to BB2 that does not first visit BB1, and in that path %a is not dominated by a def anymore. To fix this problem, we have been adding `IMPLICIT_DEF`s to all registers in PrepareForLiveInternals pass, and then remove unnecessary ones in OptimizeLiveIntervals pass after computing `LiveIntervals`. But FixIrreducibleControlFlow pass itself ends up violating register use-def relationship, resulting in invalid code. This was OK so far because MIR verifier apparently didn't check this in validation. But @arsenm fixed this and it caught this bug in validation (https://github.com/llvm/llvm-project/issues/55249). This CL moves the `IMPLICIT_DEF` adding routine from PrepareForLiveInternals to FixIrreducibleControlFlow. We only run it when FixIrreducibleControlFlow changes the code. And then PrepareForLiveInternals doesn't do anything other than setting `TracksLiveness` property, which is a prerequisite for running `LiveIntervals` analysis, which is required by the next pass OptimizeLiveIntervals. But in our backend we don't seem to do anything that invalidates this up until OptimizeLiveIntervals, and I'm not sure why we are calling `invalidateLiveness` in ReplacePhysRegs pass, because what that pass does is to replace physical registers with virtual ones 1-to-1. I deleted the `invalidateLiveness` call there and we don't need to set that flag explicitly, which obviates all the need for PrepareForLiveInternals. (By the way, This 'Liveness' here is different from `LiveIntervals` analysis. Setting this only means BBs' live-in info is correct, all uses are dominated by defs, `kill` flag is conservatively correct, which means if there is a `kill` flag set it should be the last use. See https://github.com/llvm/llvm-project/blob/2a0837aab1489c88efb03784e34c4dc9f2e28302/llvm/include/llvm/CodeGen/MachineFunction.h#L125-L134 for details.) So this CL removes PrepareForLiveInternals pass altogether. Something similar to this was attempted by D56091 long ago but that came short of actually removing the pass, and I couldn't land it because FixIrreducibleControlFlow violated use-def relationship, which this CL fixes. This doesn't change output in any meaningful way. All test changes except `irreducible-cfg.mir` are register numbering. Also this will likely to reduce compilation time, because we have been adding `IMPLICIT_DEF` for all registers every time `-O2` is given, but now we do that only when there is irreducible control flow, which is rare. Fixes https://github.com/llvm/llvm-project/issues/55249. Reviewed By: dschuff, kripken Differential Revision: https://reviews.llvm.org/D125515
108 lines
3.7 KiB
C++
108 lines
3.7 KiB
C++
//===-- WebAssemblyReplacePhysRegs.cpp - Replace phys regs with virt regs -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements a pass that replaces physical registers with
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/// virtual registers.
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///
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/// LLVM expects certain physical registers, such as a stack pointer. However,
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/// WebAssembly doesn't actually have such physical registers. This pass is run
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/// once LLVM no longer needs these registers, and replaces them with virtual
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/// registers, so they can participate in register stackifying and coloring in
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/// the normal way.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-replace-phys-regs"
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namespace {
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class WebAssemblyReplacePhysRegs final : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyReplacePhysRegs() : MachineFunctionPass(ID) {}
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private:
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StringRef getPassName() const override {
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return "WebAssembly Replace Physical Registers";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // end anonymous namespace
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char WebAssemblyReplacePhysRegs::ID = 0;
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INITIALIZE_PASS(WebAssemblyReplacePhysRegs, DEBUG_TYPE,
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"Replace physical registers with virtual registers", false,
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false)
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FunctionPass *llvm::createWebAssemblyReplacePhysRegs() {
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return new WebAssemblyReplacePhysRegs();
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}
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bool WebAssemblyReplacePhysRegs::runOnMachineFunction(MachineFunction &MF) {
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LLVM_DEBUG({
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dbgs() << "********** Replace Physical Registers **********\n"
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<< "********** Function: " << MF.getName() << '\n';
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});
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MachineRegisterInfo &MRI = MF.getRegInfo();
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auto &TRI = *MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
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bool Changed = false;
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assert(!mustPreserveAnalysisID(LiveIntervalsID) &&
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"LiveIntervals shouldn't be active yet!");
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for (unsigned PReg = WebAssembly::NoRegister + 1;
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PReg < WebAssembly::NUM_TARGET_REGS; ++PReg) {
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// Skip fake registers that are never used explicitly.
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if (PReg == WebAssembly::VALUE_STACK || PReg == WebAssembly::ARGUMENTS)
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continue;
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// Replace explicit uses of the physical register with a virtual register.
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const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg);
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unsigned VReg = WebAssembly::NoRegister;
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for (MachineOperand &MO :
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llvm::make_early_inc_range(MRI.reg_operands(PReg))) {
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if (!MO.isImplicit()) {
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if (VReg == WebAssembly::NoRegister) {
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VReg = MRI.createVirtualRegister(RC);
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if (PReg == TRI.getFrameRegister(MF)) {
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auto FI = MF.getInfo<WebAssemblyFunctionInfo>();
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assert(!FI->isFrameBaseVirtual());
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FI->setFrameBaseVreg(VReg);
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LLVM_DEBUG({
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dbgs() << "replacing preg " << PReg << " with " << VReg << " ("
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<< Register::virtReg2Index(VReg) << ")\n";
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});
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}
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}
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MO.setReg(VReg);
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Changed = true;
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}
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}
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}
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return Changed;
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}
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