Nikita Popov
9deee6bffa
D141386 changed the semantics of !range metadata to return poison on violation. If !range is combined with !noundef, violation is immediate UB instead, matching the old semantics. In theory, these IR semantics should also carry over into SDAG. In practice, DAGCombine has at least one key transform that is invalid in the presence of poison, namely the conversion of logical and/or to bitwise and/or (https://github.com/llvm/llvm-project/blob/c7b537bf0923df05254f9fa4722b298eb8f4790d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L11252). Ideally, we would fix this transform, but this will require substantial work to avoid codegen regressions. In the meantime, avoid transferring !range metadata without !noundef, effectively restoring the old !range metadata semantics on the SDAG layer. Fixes https://github.com/llvm/llvm-project/issues/64589. Differential Revision: https://reviews.llvm.org/D157685
35 lines
1.4 KiB
LLVM
35 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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define <2 x i32> @range_metata_sext_range_0_i24_i64_bitcast(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metata_sext_range_0_i24_i64_bitcast:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i64, ptr addrspace(1) %ptr, align 4, !range !0, !noundef !{}
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%shl = shl i64 %val, 22
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%ashr = ashr i64 %shl, 22
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%cast = bitcast i64 %ashr to <2 x i32>
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ret <2 x i32> %cast
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}
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define <2 x i32> @no_range_sext_range_0_i24_i64_bitcast(ptr addrspace(1) %ptr) {
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; GCN-LABEL: no_range_sext_range_0_i24_i64_bitcast:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_lshlrev_b64 v[0:1], 22, v[0:1]
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; GCN-NEXT: v_ashrrev_i64 v[0:1], 22, v[0:1]
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i64, ptr addrspace(1) %ptr, align 4
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%shl = shl i64 %val, 22
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%ashr = ashr i64 %shl, 22
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%cast = bitcast i64 %ashr to <2 x i32>
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ret <2 x i32> %cast
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}
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!0 = !{i64 0, i64 16777216}
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