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opencode.siil.arti.ee/llvm-tms34010
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dda73336ad22bd0b5ecda17040c50fb10fcbe5fb
llvm-tms34010/llvm/test/Transforms/LoopVectorize/PowerPC
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Florian Hahn a8ec1eb843 [VPlan] Dont assign slots to VPValues with an underlying value.
This makes sure the numbering for VPValues without underlying
values is consecutive.
2024-04-09 21:30:51 +01:00
..
interleave_IC.ll
[LV] Remove unused configuration option (#82955)
2024-02-28 10:17:25 -08:00
interleaved-pointer-runtime-check-unprofitable.ll
…
large-loop-rdx.ll
…
lit.local.cfg
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massv-altivec.ll
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massv-calls.ll
…
massv-nobuiltin.ll
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massv-unsupported.ll
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optimal-epilog-vectorization-profitability.ll
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optimal-epilog-vectorization.ll
[VPlan] Update stale test after 9536a6286, fix formatting.
2024-01-31 13:45:38 +00:00
pr30990.ll
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pr41179.ll
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predcost.ll
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reg-usage.ll
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small-loop-rdx.ll
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stride-vectorization.ll
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vectorize-bswap.ll
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vectorize-force-tail-with-evl.ll
[LV, VP]VP intrinsics support for the Loop Vectorizer + adding new tail-folding mode using EVL. (#76172)
2024-04-04 18:30:17 -04:00
vectorize-only-for-real.ll
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vplan-force-tail-with-evl.ll
[VPlan] Dont assign slots to VPValues with an underlying value.
2024-04-09 21:30:51 +01:00
vsx-tsvc-s173.ll
…
widened-massv-call.ll
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widened-massv-vfabi-attr.ll
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