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opencode.siil.arti.ee/llvm-tms34010
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dda73336ad22bd0b5ecda17040c50fb10fcbe5fb
llvm-tms34010/mlir/test/Dialect/SparseTensor/GPU
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Peiming Liu fc9f1d49aa [mlir][sparse] use a consistent order between [dis]assembleOp and sto… (#84079)
…rage layout.
2024-03-06 09:57:41 -08:00
..
gpu_combi.mlir
[mlir][sparse] schedule sparse kernels in a separate pass from sparsification. (#72423)
2023-11-15 12:16:05 -08:00
gpu_matmul24_lib.mlir
[mlir][sparse] Implement parsing n out of m (#79935)
2024-02-08 14:38:42 -05:00
gpu_matmul_lib.mlir
[mlir][sparse] Use variable instead of inlining sparse encoding (#72561)
2023-11-16 19:30:21 -05:00
gpu_matmul.mlir
[mlir][sparse] schedule sparse kernels in a separate pass from sparsification. (#72423)
2023-11-15 12:16:05 -08:00
gpu_matvec_lib.mlir
[mlir][sparse] Use variable instead of inlining sparse encoding (#72561)
2023-11-16 19:30:21 -05:00
gpu_matvec.mlir
[mlir][sparse] schedule sparse kernels in a separate pass from sparsification. (#72423)
2023-11-15 12:16:05 -08:00
gpu_sampled_matmul_lib.mlir
[mlir][sparse] Use variable instead of inlining sparse encoding (#72561)
2023-11-16 19:30:21 -05:00
gpu_sddmm_lib.mlir
[mlir][sparse] Use variable instead of inlining sparse encoding (#72561)
2023-11-16 19:30:21 -05:00
gpu_spgemm_lib.mlir
[mlir][sparse] use a consistent order between [dis]assembleOp and sto… (#84079)
2024-03-06 09:57:41 -08:00
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