From 5e8dbffb01f88f19f34b44e2d74e5fbfaa2c34f0 Mon Sep 17 00:00:00 2001 From: arti Date: Wed, 11 Nov 2026 15:21:09 +0000 Subject: [PATCH] docs: move the M2 spill test to Task 3 --- ...-11-11-tms34010-m2-ti-abi-and-rom-calls.md | 54 ++++++++++++------- 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/docs/superpowers/plans/2026-11-11-tms34010-m2-ti-abi-and-rom-calls.md b/docs/superpowers/plans/2026-11-11-tms34010-m2-ti-abi-and-rom-calls.md index 4a1950d..8ce760d 100644 --- a/docs/superpowers/plans/2026-11-11-tms34010-m2-ti-abi-and-rom-calls.md +++ b/docs/superpowers/plans/2026-11-11-tms34010-m2-ti-abi-and-rom-calls.md @@ -265,29 +265,47 @@ entry: ; CHECK: RETS 2 ``` -`m2-spill.ll` (13 simultaneous values exceed the 12 allocatable A registers): +`m2-spill.ll` (13 loaded values live across a call exceed the 12 allocatable A registers; belongs to Task 3 because it needs call lowering): ```llvm ; RUN: llc -march=tms34010 -O2 -filetype=asm < %s | FileCheck %s -define i32 @sum13(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, - i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m) { +declare i32 @callee(i32) +define i32 @spill13(ptr %p0, ptr %p1, ptr %p2, ptr %p3, ptr %p4, ptr %p5, + ptr %p6, ptr %p7, ptr %p8, ptr %p9, ptr %p10, ptr %p11, + ptr %p12, i32 %a) { entry: - %s0 = add i32 %a, %b - %s1 = add i32 %c, %d - %s2 = add i32 %e, %f - %s3 = add i32 %g, %h - %s4 = add i32 %i, %j - %s5 = add i32 %k, %l + %x0 = load i32, ptr %p0 + %x1 = load i32, ptr %p1 + %x2 = load i32, ptr %p2 + %x3 = load i32, ptr %p3 + %x4 = load i32, ptr %p4 + %x5 = load i32, ptr %p5 + %x6 = load i32, ptr %p6 + %x7 = load i32, ptr %p7 + %x8 = load i32, ptr %p8 + %x9 = load i32, ptr %p9 + %x10 = load i32, ptr %p10 + %x11 = load i32, ptr %p11 + %x12 = load i32, ptr %p12 + %r = call i32 @callee(i32 %a) + %s0 = add i32 %x0, %x1 + %s1 = add i32 %x2, %x3 + %s2 = add i32 %x4, %x5 + %s3 = add i32 %x6, %x7 + %s4 = add i32 %x8, %x9 + %s5 = add i32 %x10, %x11 %s6 = add i32 %s0, %s1 %s7 = add i32 %s2, %s3 %s8 = add i32 %s4, %s5 %s9 = add i32 %s6, %s7 - %s10 = add i32 %s8, %m + %s10 = add i32 %s8, %x12 %s11 = add i32 %s9, %s10 - ret i32 %s11 + %s12 = add i32 %s11, %r + ret i32 %s12 } -; CHECK-LABEL: _sum13: +; CHECK-LABEL: _spill13: ; CHECK: MOVE {{A[0-9]+}}, *A{{[0-9]+}}, 1 +; CHECK: MOVE *A{{[0-9]+}}, A{{[0-9]+}}, 1 ; CHECK: RETS 2 ``` @@ -370,7 +388,7 @@ git -C build/llvm-clean commit -m "tms34010: replace M1 tests with failing M2 AB - Modify: `TMS34010ISelLowering.cpp/.h`, `TMS34010ISelDAGToDAG.cpp` - Modify: `TMS34010.td`, `CMakeLists.txt` - Create: `TMS34010CallingConv.td` -- Test: `m2-args.ll`, `m2-noret.ll`, `m2-locals.ll`, `m2-args-locals.ll`, `m2-callee-save.ll`, `m2-spill.ll` +- Test: `m2-args.ll`, `m2-noret.ll`, `m2-locals.ll`, `m2-args-locals.ll`, `m2-callee-save.ll` **Interfaces:** - Consumes: M1 target skeleton, `MOVE`/`MOVB`/`MOVI`/`ADDI`/`ADD`/`RETS`, asm printer. @@ -491,10 +509,10 @@ if (N->getOpcode() == ISD::FrameIndex) { ninja -C build/llvm-clean-build llc opt clang llvm-config FileCheck count not build/llvm-clean-build/bin/llvm-lit -v \ build/llvm-clean-build/test/CodeGen/TMS34010 \ - --filter='m2-(args|noret|locals|args-locals|callee-save|spill|add|load|char|i16|store|global|late-gep)' + --filter='m2-(args|noret|locals|args-locals|callee-save|add|load|char|i16|store|global|late-gep)' ``` -Expected: PASS for `m2-args`, `m2-noret`, `m2-locals`, `m2-args-locals`, `m2-spill`, and the updated positive M1-derived tests. `m2-callee-save` still fails on the call (Task 3); `m2-call*` and `m2-fs1` still fail. Record the red set. +Expected: PASS for `m2-args`, `m2-noret`, `m2-locals`, `m2-args-locals`, and the updated positive M1-derived tests. `m2-callee-save`, `m2-call*`, `m2-fs1` and `m2-spill` still fail on the call (Task 3). Record the red set. - [ ] **Step 7: Commit** @@ -508,7 +526,7 @@ git -C build/llvm-clean commit -m "tms34010: TI ABI callee frames, arguments and **Files:** - Modify: `build/llvm-clean/llvm/lib/Target/TMS34010/TMS34010ISelLowering.cpp` - Modify: `TMS34010InstrInfo.td` / `TMS34010MCInstLower.cpp` if `CALLA` symbol lowering needs it -- Test: `m2-call.ll`, `m2-call3.ll`, `m2-callee-save.ll`, `m2-fs1.ll` +- Test: `m2-call.ll`, `m2-call3.ll`, `m2-callee-save.ll`, `m2-fs1.ll`, `m2-spill.ll` **Interfaces:** - Consumes: Task 2's `PUSH32`, `PUSHARG`, `LOADSTK`, `SETF32`, `CALLA`, frames, A8 return. @@ -518,7 +536,7 @@ git -C build/llvm-clean commit -m "tms34010: TI ABI callee frames, arguments and ```sh build/llvm-clean-build/bin/llvm-lit -v \ - build/llvm-clean-build/test/CodeGen/TMS34010 --filter='m2-(call|call3|callee-save|fs1)' + build/llvm-clean-build/test/CodeGen/TMS34010 --filter='m2-(call|call3|callee-save|fs1|spill)' ``` Expected: FAIL with `M2 call lowering is Task 3`. @@ -542,7 +560,7 @@ Use chain-only machine nodes (`DAG.getMachineNode(..., MVT::Other, Chain, ...)`) ninja -C build/llvm-clean-build llc opt clang llvm-config FileCheck count not build/llvm-clean-build/bin/llvm-lit -v \ build/llvm-clean-build/test/CodeGen/TMS34010 \ - --filter='m2-(call|call3|callee-save|fs1)' + --filter='m2-(call|call3|callee-save|fs1|spill)' ``` Expected: PASS. The exact `LOADSTK` offset is not pinned here; it depends on the register allocator's callee-save set. Task 5's `dis34` check counts the `MOVE ...,-*SP,1` pushes and verifies `offset == (pushes+1)*32`.