 arti
|
5d980dc6e3
|
tests/docs: final M4 review fixes
|
2026-11-12 12:23:04 +00:00 |
|
|
arti
|
7946519828
|
symbols: correct XMapWindow, add XImage/XG entries and validation
|
2026-11-12 07:19:42 +00:00 |
|
|
arti
|
dbf71bdc5f
|
docs: M4 Xlib images, events and termtris integration plan
|
2026-11-12 05:23:33 +00:00 |
|
|
arti
|
b34016a9f3
|
docs: correct M3 ROM bit displacements and unaligned-load carry-forward
|
2026-11-11 19:14:05 +00:00 |
|
|
arti
|
d1ba1e4d86
|
docs: M3 control flow and first Xlib window plan
|
2026-11-11 17:54:01 +00:00 |
|
|
arti
|
2d4919db36
|
docs: finalize M2 ABI and tail-call notes
|
2026-11-11 17:36:17 +00:00 |
|
|
arti
|
fa00b8740b
|
docs: finish the M2 loader and returned reconciliation
|
2026-11-11 16:59:30 +00:00 |
|
|
arti
|
b614e70851
|
docs: reconcile M2 plan with JAUC, returned, loader and .data alignment
|
2026-11-11 16:59:23 +00:00 |
|
|
arti
|
d4f165fa7d
|
docs: record the M2 .data width and pointer-init rules
|
2026-11-11 16:35:43 +00:00 |
|
|
arti
|
3f30806a6d
|
docs: require width-based .data emission for i8/i16 scalars
|
2026-11-11 16:24:29 +00:00 |
|
|
arti
|
e7ba50d7a3
|
docs: add caller-side rejection tests to M2
|
2026-11-11 16:10:38 +00:00 |
|
|
arti
|
469b1d870e
|
docs: require a spill-slot frame assertion in m2-spill
|
2026-11-11 15:55:18 +00:00 |
|
|
arti
|
e60a1fdee9
|
docs: pin the M2 callee stack arithmetic in m2-args
|
2026-11-11 15:54:59 +00:00 |
|
|
arti
|
5e8dbffb01
|
docs: move the M2 spill test to Task 3
|
2026-11-11 15:21:09 +00:00 |
|
|
arti
|
c0746338b0
|
docs: M2 TI ABI and ROM call implementation plan
|
2026-11-11 14:57:27 +00:00 |
|
|
arti
|
e081921b72
|
plan: M1 minimal TMS34010 backend
|
2026-11-11 06:47:05 +00:00 |
|
|
arti
|
da553739c5
|
docs: TMS34010 LLVM design, spike, and workspace setup
|
2026-11-10 14:42:56 +00:00 |
|