6 Commits

Include renames

Author	SHA1	Message	Date
arti	5e8dbffb01	docs: move the M2 spill test to Task 3	2026-11-11 15:21:09 +00:00
arti	c0746338b0	docs: M2 TI ABI and ROM call implementation plan	2026-11-11 14:57:27 +00:00
arti	eacaab68f6	docs: correct the GEP scaling warning and M1 data limits ... Raw clang IR has byte GEP offsets that llc treats as bits, so addresses are 8x too small; always run tms-clang/tms-bitaddr --scale first. Document that M1 supports only zero-initialized globals and rejects .data/string literals loudly, and defer the spec's .data initializer probe to M2.	2026-11-11 10:15:32 +00:00
arti	e081921b72	plan: M1 minimal TMS34010 backend	2026-11-11 06:47:05 +00:00
arti	668afbbf44	fix: address final review (subtarget, bool/char alignment, spike env, late-GEP tests)	2026-11-11 03:39:15 +00:00
arti	da553739c5	docs: TMS34010 LLVM design, spike, and workspace setup	2026-11-10 14:42:56 +00:00