Files
vt1200/xie/evidence/put_tile_succeeds.txt
arti d8d54bb990 feat(xie): a client-chosen XIE image is displayed on the VT1200
The XIE path now runs end to end: XieCreateImage -> XieCreatePhoto ->
XiePutTile -> XieExport(photomap -> depth-1 pixmap) -> XCopyArea(pixmap ->
window), and the client's tile appears on screen at the client's own window
position, pixel-exact.

TWO FAULTS BEHIND THE LONG DEAD END

1. Device model (harness/mame/vt1200.cpp, opt-in VT1200_ACCEL=1).  The
   accelerator's output port 0x5600200 returns the pixel stream the firmware
   pushed into the FIFO -- the firmware then stores it into the drawable itself
   (file 0x125528: MOVE *B6,*B1 ; ADDK 0x10,B1).  The FIFO read pointer was
   never reset between transfers, so consecutive exports read stale words and
   the same fill produced 759 then 516 set pixels.  Reset m_fifo_in/out on the
   data-register write; the export is now deterministic.

2. Measurement, not the device.
   - dwt/screenshot.py without --real reads 1024x1024 at a 128-byte row stride,
     but the VR319 default programs 1280x1024 at a 2048-bit (256-byte) pitch.
     That is the "shifted" picture; --real is the correct read.
   - The earlier "0 differing bytes over 128 KiB" VRAM comparison stepped peek
     by 1024 *bit* addresses, so it scanned rows 0..63 only -- never the window
     at rows 200..263.  Over the real raster the white/black diff is 576 bytes
     spanning exactly those rows.
   - New instrument: decclient does a server-side XGetImage readback of the
     pixmap and window and counts set pixels.  That separated "the server never
     drew it" from "the framebuffer view is wrong".

EVIDENCE (reproduced twice, the second time from a fresh machine)

  no export vs 0xFF : 4096 / 4096 pixels differ
  no export vs 0x00 :    0 / 4096   (the window background is black)
  0xFF      vs 0x00 : 4096 / 4096
  0xAA      vs 0x0F : 2048 / 4096   (the two stripe phases)

Tile byte 0xAA reproduces as 1-pixel vertical stripes, 0x0F as 4-pixel, with
no shear -- so the placement is right and the pixels are the client's.

Contents: xie/ holds DEC XIE 2.3 headers, 84 man pages and complete
client+server source; a libXie.a and decclient built from DEC's own code; the
XIE probes; and evidence/ with every measurement, including explicit
retractions of the earlier wrong readings (VRAM_IDENTICAL_FOR_BOTH_FILLS and
friends).  xie/evidence/XIE_IMAGE_DISPLAYED.md is the report; frames are in
xie/evidence/png/.

The accelerator model stays opt-in: it answers the status poll and relays the
pixel stream, but performs no compositing, so it is a stand-in and the verified
default configuration is unchanged (a no-env run still parks in the level-0
diagnostics menu at PC=3FDCE400).
2026-11-01 23:22:25 +02:00

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PUT_TILE SUCCEEDS -- FIRST TIME IN THIS INVESTIGATION.
The gate operand chain is now fully decoded:
0x6BAEA A11 = *(caller frame slot) -> A11 = the out-cell's ADDRESS
0x6BAEC SETF 8 -> 8-bit field
0x6BAF2 A7 = *A7 -> ** A7 := *(object->byte36) ** (deref!)
0x6BAF4 CMP A7,A11 (A11 = 3) -> requires the BYTE AT (byte36) == 3
Measured:
SCRATCH=0x00010100 ; poke *SCRATCH = 0 and 3 ; poke object->byte36 = SCRATCH
*scratch = 0 : F2 a7=00010100 star7=00000000 ; GATE a7=0 a11=3 ; PUT_TILE ERROR 8
*scratch = 3 : F2 a7=00010100 star7=00000003 ; GATE a7=3 a11=3 ; PUT_TILE SILENT(ok)
So when the byte pointed to by object->byte36 equals 3, the gate compares 3 with 3,
passes, and the import request returns success (A8=0, no error packet).
FULL CHAIN ATTEMPT (both tiles, debug pokes labelled):
white: create w9=0x300 -> arm1 ERROR 8 -> PUT_TILE SILENT(ok) -> arm2 ERROR 8 -> EXPORT ERROR 8
black: create w9=0x300 -> arm1 ERROR 8 -> PUT_TILE SILENT(ok) -> arm2 ERROR 8 -> EXPORT ERROR 8
So:
* the IMPORT now works,
* arm (slot 20) still fails on a byte8=3 resource (its own check at 0x6ACBE),
* EXPORT consequently fails, RP never fires, src_base cannot be read.
IMPORTANT CAVEAT: the successful import depended on two DEBUG-ONLY pokes
(object->byte36 and the byte it points at). Nothing here shows a client request
can produce that state. It proves the mechanism, not reachability.
WHERE THIS LEADS: exactly the same structure almost certainly applies to arm's
check at 0x6ACBE (`A7 = *A11(0x40),0` then DSJS), which I previously read as
"requires byte8 == 1". Given that the import gate turned out to be a DEREFERENCED
byte rather than byte8 itself, arm's check should be re-read the same way before
concluding it needs byte8==1.
Status: PUT_TILE success achieved (debug-poked state); no image yet; src_base
still unread because export fails; xshow remains the only viewer that has shown
an image.