2012-12-17 05:45:21 +02:00
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/*
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2012-12-17 17:20:14 +02:00
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* swuart/swuart.c - Software-implemented UART for UBB
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2012-12-17 05:45:21 +02:00
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*
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* Written 2012 by Werner Almesberger
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* Copyright 2012 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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2012-12-17 17:20:14 +02:00
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#include <stdbool.h>
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#include <string.h>
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2012-12-29 03:55:06 +02:00
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#include <sys/mman.h>
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2012-12-17 05:45:21 +02:00
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#include <ubb/ubb.h>
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#include <ubb/regs4740.h>
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2012-12-18 03:16:32 +02:00
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#include <ubb/swuart.h>
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2012-12-17 05:45:21 +02:00
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2012-12-17 17:20:14 +02:00
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#define TIMER 7
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2012-12-17 05:45:21 +02:00
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static uint32_t tx_mask, rx_mask;
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2012-12-17 17:20:14 +02:00
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static uint32_t ticks;
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/* ----- Hardware timer ---------------------------------------------------- */
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2012-12-17 05:45:21 +02:00
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/*
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2012-12-17 17:20:14 +02:00
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* We run the hardware timer at PCLK/16 = 7 MHz. This gives us 60 cycles at
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* 115200 bps and sets the lowest data rate to 106.8 bps.
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2012-12-17 05:45:21 +02:00
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*/
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2012-12-17 17:20:14 +02:00
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#define PCLK (112*1000*1000) /* 112 MHz */
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#define TCLK (PCLK/16) /* 7 MHz */
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static void get_timer(uint32_t cycle)
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{
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TSCR = 1 << TIMER; /* enable clock to timer */
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TDFR(TIMER) = cycle-1; /* cycle = one bit time */
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TCSR(TIMER) = (2 << 3) | 1; /* count at PCLK/16 */
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}
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static void reset_timer(void)
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{
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TECR = 1 << TIMER; /* disable timer */
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TCNT(TIMER) = 0; /* reset timer */
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TFCR = 0x10001 << TIMER; /* clear flags */
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TESR = 1 << TIMER; /* enable timer */
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}
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static void set_half_cycle(uint32_t cycle)
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{
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uint32_t t;
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t = (uint16_t) TCNT(TIMER)+(cycle >> 1);
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/* TCNT+cycle/2 mod cycle-1 */
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if (t >= cycle-1)
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t -= cycle-1;
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TDHR(TIMER) = t;
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TFCR = 0x10000 << TIMER; /* clear half flags */
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}
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static void release_timer(void)
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{
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TECR = 1 << TIMER; /* disable timer */
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TFCR = 0x10001 << TIMER; /* clear flags */
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TSSR = 1 << TIMER; /* disable clock to timer */
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}
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static inline bool timer_full(void)
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{
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if (!(TFR & (1 << TIMER)))
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return 0;
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TFCR = 1 << TIMER;
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return 1;
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}
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static inline bool timer_half(void)
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{
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if (!(TFR & (0x10000 << TIMER)))
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return 0;
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TFCR = 0x10000 << TIMER;
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return 1;
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}
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/* ----- Enable/disable interrupts ----------------------------------------- */
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static uint32_t old_icmr;
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static void disable_interrupts(void)
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{
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old_icmr = ICMR;
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ICMSR = 0xffffffff;
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}
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static void enable_interrupts(void)
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{
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ICMCR = ~old_icmr;
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}
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/* ----- Transmit a block -------------------------------------------------- */
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2012-12-17 23:43:51 +02:00
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static struct swuart_err errors;
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2012-12-17 17:20:14 +02:00
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static int trx(uint8_t *out, int out_size, uint8_t *in, int in_size,
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unsigned wait_bits, unsigned idle_bits)
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{
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unsigned tx, rx = 0, idle = 0;
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int tx_bits = 0, rx_bits = 0;
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int in_len = 0;
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reset_timer();
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while (1) {
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full:
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/* timer has just crossed FULL */
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if (tx_bits) {
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if (tx & 1)
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SET(tx_mask);
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else
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CLR(tx_mask);
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tx >>= 1;
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tx_bits--;
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} else {
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if (out_size) {
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CLR(tx_mask);
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tx = *out++ | 0x100;
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out_size--;
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tx_bits = 9;
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} else {
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if (idle++ == wait_bits)
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return in_len;
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}
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}
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/* wait for reception (if any) */
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if (rx_bits) {
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while (!timer_half());
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} else {
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while (!timer_full())
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if (!PIN(rx_mask)) {
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set_half_cycle(ticks);
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rx_bits = 10;
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break;
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}
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if (!rx_bits)
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continue;
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while (!timer_half())
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if (timer_full())
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goto full;
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}
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/* timer has just crossed HALF */
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rx = (rx >> 1) | (PIN(rx_mask) ? 0x200 : 0);
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if (!--rx_bits) {
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if (rx & 1) {
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2012-12-17 23:43:51 +02:00
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errors.glitch++;
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2012-12-17 17:20:14 +02:00
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} else if (!(rx & 0x200)) {
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2012-12-17 23:43:51 +02:00
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errors.framing++;
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2012-12-17 17:20:14 +02:00
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} else if (in_len == in_size) {
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2012-12-17 23:43:51 +02:00
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errors.overflow++;
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2012-12-17 17:20:14 +02:00
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} else {
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*in++ = rx >> 1;
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in_len++;
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idle = 0;
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wait_bits = idle_bits;
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}
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}
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while (!timer_full());
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}
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}
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int swuart_trx(void *out, int out_size, void *in, int in_size,
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int wait_bits, int idle_bits)
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{
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int got;
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disable_interrupts();
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get_timer(ticks);
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got = trx(out, out_size, in, in_size, wait_bits, idle_bits);
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release_timer();
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enable_interrupts();
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return got;
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}
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2012-12-17 23:43:51 +02:00
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/* ----- Access error counters --------------------------------------------- */
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unsigned swuart_get_errors(struct swuart_err *res)
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{
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unsigned sum = errors.glitch+errors.framing+errors.overflow;
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if (res)
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*res = errors;
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return sum;
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}
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void swuart_clear_errors(void)
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{
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memset(&errors, 0, sizeof(errors));
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}
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2012-12-17 17:20:14 +02:00
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/* ----- Open/close the software UART -------------------------------------- */
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2012-12-17 05:45:21 +02:00
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int swuart_open(uint32_t tx, uint32_t rx, int bps)
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{
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2012-12-29 03:55:06 +02:00
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/*
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* Make sure code and rx/tx buffers are locked into memory before we
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* disable interrupts in swuart_trx.
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*/
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2013-01-01 00:27:16 +02:00
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if (mlockall(MCL_CURRENT | MCL_FUTURE))
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2012-12-29 03:55:06 +02:00
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return -1;
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2012-12-17 17:20:14 +02:00
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ticks = TCLK/bps-1;
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2012-12-17 05:45:21 +02:00
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tx_mask = tx;
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rx_mask = rx;
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OUT(tx);
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2012-12-18 03:44:47 +02:00
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SET(tx);
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2012-12-17 05:45:21 +02:00
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IN(rx);
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return 0;
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}
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2012-12-17 17:20:14 +02:00
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void swuart_close(void)
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2012-12-17 05:45:21 +02:00
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{
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2013-01-01 00:27:16 +02:00
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munlockall();
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2012-12-17 05:45:21 +02:00
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}
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