ben-blinkenlights/libubb/include/ubb/regs4740.h

/*
 * include/ubb/regs4740.h - Jz4740 register definitions (subset)
 *
 * Written 2011-2012 by Werner Almesberger
 * Copyright 2011-2012 Werner Almesberger
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef UBB_REGS4740_H
#define	UBB_REGS4740_H

#include <stdint.h>

#include <ubb/regbase.h>


#define	_CGU(n)		REG(0x0000000+(n))
#define	_INTC(n)	REG(0x0001000+(n))
#define	_TCU(n)		REG(0x0002000+(n))
#define	_MSC(n)		REG(0x0021000+(n))
#define	_DMAC(n)	REG(0x3020000+(n))
#define	_LCD(n)		REG(0x3050000+(n))

#define	CPCCR	_CGU(0x0000)	/* Clock Control */
#define	CLKGR	_CGU(0x0020)	/* Clock Gate */
#define	MSCCDR	_CGU(0x0068)	/* MSC device clock divider */

#define	ICMR	_INTC(0x04)	/* Interrupt controller mask */
#define	ICMSR	_INTC(0x08)	/* Interrupt controller mask set */
#define	ICMCR	_INTC(0x0c)	/* Interrupt controller mask clear */

#define	TSSR	_TCU(0x2c)		/* Timer STOP set */
#define	TSCR	_TCU(0x3c)		/* Timer STOP clear */
#define	TESR	_TCU(0x14)		/* Timer counter enable set */
#define	TECR	_TCU(0x18)		/* Timer counter enable clear */
#define	TFR	_TCU(0x20)		/* Timer flag */
#define	TFSR	_TCU(0x24)		/* Timer flag set */
#define	TFCR	_TCU(0x28)		/* Timer flag clear */
#define	TCSR(n)	_TCU(0x4c+0x10*(n))	/* Timer control */
#define	TDFR(n)	_TCU(0x40+0x10*(n))	/* Timer data full */
#define	TDHR(n)	_TCU(0x44+0x10*(n))	/* Timer data half */
#define	TCNT(n)	_TCU(0x48+0x10*(n))	/* Timer counter */

/* MSC */

#define	MSC_STRPCL	_MSC(0x00)	/* Start/stop MMC/SD clock */
#define	MSC_STRPCRL_EXIT_MULTIPLE	(1 << 7)
#define	MSC_STRPCRL_EXIT_TRANSFER	(1 << 6)
#define	MSC_STRPCRL_START_READWAIT	(1 << 5)
#define	MSC_STRPCRL_STOP_READWAIT	(1 << 4)
#define	MSC_STRPCRL_RESET		(1 << 3)
#define	MSC_STRPCRL_START_OP		(1 << 2)
#define	MSC_STRPCRL_START_CLOCK		(1 << 1)
#define	MSC_STRPCRL_STOP_CLOCK		(1 << 0)

#define	MSC_STAT	_MSC(0x04)	/* MSC status */
#define	MSC_STAT_IS_RESETTING		(1 << 15)
#define	MSC_STAT_SDIO_INT_ACTIVE	(1 << 14)
#define	MSC_STAT_PRG_DONE		(1 << 13)
#define	MSC_STAT_DATA_TRAN_DONE		(1 << 12)
#define	MSC_STAT_END_CMD_RES		(1 << 11)
#define	MSC_STAT_DATA_FIFO_AFULL	(1 << 10)	/* almost full */
#define	MSC_STAT_IS_READWAIT		(1 << 9)
#define	MSC_STAT_CLK_EN			(1 << 8)
#define	MSC_STAT_DATA_FIFO_FULL		(1 << 7)
#define	MSC_STAT_DATA_FIFO_EMPTY	(1 << 6)
#define	MSC_STAT_CRC_RES_ERR		(1 << 5)
#define	MSC_STAT_CRC_READ_ERROR		(1 << 4)
#define	MSC_STAT_CRC_WRITE_ERROR_MASK	(3 << MSC_STAT_CRC_WRITE_ERROR_SHIFT)
#define	MSC_STAT_CRC_WRITE_ERROR_SHIFT	2
#define	MSC_STAT_CRC_WRITE_ERROR_ERROR	1		/* error reported */
#define	MSC_STAT_CRC_WRITE_ERROR_NOSTAT	2		/* no CRC status */
#define	MSC_STAT_TIME_OUT_RES		(1 << 1)
#define	MSC_STAT_TIME_OUT_READ		(1 << 0)

#define	MSC_CLKRT	_MSC(0x08)	/* MSC clock rate */
#define	MSC_CLKRT_MASK			7

#define	MSC_CMDAT	_MSC(0x0c)	/* MMC/SD command and data control */
#define	MSC_CMDAT_IO_ABORT		(1 << 11)
#define	MSC_CMDAT_BUS_WIDTH_MASK	(3 << MSC_CMDAT_BUS_WIDTH_SHIFT)
#define	MSC_CMDAT_BUS_WIDTH_SHIFT	9
#define	MSC_CMDAT_BUS_WIDTH_1		0
#define	MSC_CMDAT_BUS_WIDTH_4		2
#define	MSC_CMDAT_DMA_EN		(1 << 8)
#define	MSC_CMDAT_INIT			(1 << 7)
#define	MSC_CMDAT_BUSY			(1 << 6)
#define	MSC_CMDAT_STREAM_BLOCK		(1 << 5)
#define	MSC_CMDAT_WRITE_READ		(1 << 4)
#define	MSC_CMDAT_DATA_EN		(1 << 3)
#define	MSC_CMDAT_RESPONSE_FORMAT_MASK	(7 << MSC_CMDAT_RESPONSE_FORMAT_SHIFT)
#define	MSC_CMDAT_RESPONSE_FORMAT_SHIFT	0
#define	MSC_CMDAT_RESPONSE_FORMAT_NONE	0
#define	MSC_CMDAT_RESPONSE_FORMAT_R1	1		/* or R1b */
#define	MSC_CMDAT_RESPONSE_FORMAT_R2	2
#define	MSC_CMDAT_RESPONSE_FORMAT_R3	3
#define	MSC_CMDAT_RESPONSE_FORMAT_R4	4
#define	MSC_CMDAT_RESPONSE_FORMAT_R5	5
#define	MSC_CMDAT_RESPONSE_FORMAT_R6	6

#define	MSC_RESTO	_MSC(0x10)	/* MMC/SD response time out */
#define	MSC_RESTO_MASK			0xff		/* in MSC_CLK */

#define	MSC_RDTO	_MSC(0x14)	/* MMC/SD read time out */
#define	MSC_RDTO_MASK			0xffff		/* in CLK_SRC/256 */

#define	MSC_BLKLEN	_MSC(0x18)	/* MMC/SD block length */
#define	MSC_BLKLEN_MASK			0xfff

#define	MSC_NOB		_MSC(0x1c)	/* MMC/SD number of blocks */
#define	MSC_NOB_MASK			0xffff

#define	MSC_SNOB	_MSC(0x20)	/* MMC/SD successful blocks */
#define	MSC_SNOB_MASK			0xffff

#define	MSC_IMASK	_MSC(0x24)	/* MMC/SD interrupt mask */
#define	MSC_INT_SDIO			(1 << 7)
#define	MSC_INT_TXFIFO_WR_REQ		(1 << 6)
#define	MSC_INT_RXFIFO_RD_REQ		(1 << 5)
#define	MSC_INT_END_CMD_RES		(1 << 2)
#define	MSC_INT_PRG_DONE		(1 << 1)
#define	MSC_INT_DATA_TRAN_DONE		(1 << 0)

#define	MSC_IREG	_MSC(0x28)	/* MMC/SD interrupt */

#define	MSC_CMD		_MSC(0x2c)	/* MMC/SD command index */
#define	MSC_CMD_MASK			0x3f

#define	MSC_ARG		_MSC(0x30)	/* MMC/SD command argument */

#define	MSC_RES		_MSC(0x34)	/* MMC?SD response FIFO */
#define	MSC_RXFIFO_MASK			0xffff	/* 8 x 16 bits */

#define	MSC_RXFIFO	_MSC(0x38)	/* MMC/SD receive data FIFO */

#define	MSC_TXFIFO	_MSC(0x3c)	/* MMC/SD transmit data FIFO */

/* DMA */

#define	_DMAn(n, r)	_DMAC(0x20*(n)+(r))

#define	DSA(n)		_DMAn(n, 0x00)	/* DMA source address */

#define	DTA(n)		_DMAn(n, 0x04)	/* DMA target address */

#define	DTC(n)		_DMAn(n, 0x08)	/* DMA transfer count */
#define	DTC_MASK	0xffffff

#define	DRT(n)		_DMAn(n, 0x0c)	/* DMA request type */
#define	DRT_MASK	0x1f
#define	DRT_AUTO	8		/* external to external */
#define	DRT_UART_TX	20
#define	DRT_UART_RX	21
#define	DRT_SSI_TX	22
#define	DRT_SSI_RX	23
#define	DRT_AIC_TX	24
#define	DRT_AIC_RX	25
#define	DRT_MSC_TX	26
#define	DRT_MSC_RX	27
#define	DRT_TCU		28
#define	DRT_SADC	29
#define	DRT_SLCD	30

#define	DCS(n)		_DMAn(n, 0x10)	/* DMA channel control/status */
#define	DCS_NDES	(1 << 31)	/* No-Descriptor Transfer */
#define	DCS_CDOA_MASK	(0xff << DCS_CDOA_SHIFT)
					/* Copy of Descriptor Offset Address */
#define	DCS_CDOA_SHIFT	16
#define	DCS_INV		(1 << 6)	/* Descriptor invalid error */
#define	DCS_AR		(1 << 4)	/* Address error */
#define	DCS_TT		(1 << 3)	/* Transfer terminated */
#define	DCS_HLT		(1 << 2)	/* DMA halt */
#define	DCS_CT		(1 << 1)	/* Link DMA transfer end */
#define	DCS_CTE		(1 << 0)	/* Channel enabled */

#define	DCM(n)		_DMAn(n, 0x14)	/* DMA command */
#define	DCM_SAI		(1 << 23)	/* Source address increment */
#define	DCM_DAI		(1 << 22)	/* Destination address increment */
#define	DCM_RDIL_MASK	(15 << DCM_RDIL_SHIFT)
					/* Request Detection Interval Length */
#define	DCM_RDIL_SHIFT	16
#define	DCM_RDIL_0	0
#define	DCM_RDIL_2	1		/* 2 units, etc. */
#define	DCM_RDIL_4	2
#define	DCM_RDIL_8	3
#define	DCM_RDIL_12	4
#define	DCM_RDIL_16	5
#define	DCM_RDIL_20	6
#define	DCM_RDIL_24	7
#define	DCM_RDIL_28	8
#define	DCM_RDIL_32	9
#define	DCM_RDIL_48	10
#define	DCM_RDIL_60	11
#define	DCM_RDIL_64	12
#define	DCM_RDIL_124	13
#define	DCM_RDIL_128	14
#define	DCM_RDIL_200	15
#define	DCM_SP_MASK	(3 << DCM_SP_SHIFT) /* Source port width */
#define	DCM_SP_SHIFT	14
#define	DCM_SP_32	0		/* 32 bit */
#define	DCM_SP_8	1
#define	DCM_SP_16	2
#define	DCM_DP_MASK	(3 << DCM_DP_SHIFT) /* Destination port width */
#define	DCM_DP_SHIFT	12
#define	DCM_DP_32	0		/* 32 bit */
#define	DCM_DP_8	1
#define	DCM_DP_16	2
#define	DCM_TSZ_MASK	(7 << DCM_TSZ_SHIFT) /* Transfer data size (unit) */
#define	DCM_TSZ_SHIFT	8
#define	DCM_TSZ_32BIT	0
#define	DCM_TSZ_8BIT	1
#define	DCM_TSZ_16BYTE	3
#define	DCM_TSZ_32BYTE	4
#define	DCM_TM		(1 << 7)	/* Transfer mode (0 single, 1 block) */
#define	DCM_V		(1 << 4)	/* Descriptor valid */
#define	DCM_VM		(1 << 3)	/* Descriptor valid mode */
#define	DCM_VIE		(1 << 2)	/* DMA valid error Interrupt Enable */
#define	DCM_TIE		(1 << 1)	/* Transfer Interrupt Enable (TIE) */
#define	DCM_LINK	(1 << 0)	/* Descriptor link enable */

#define	DMAC		_DMAC(0x300)	/* DMA control */
#define	DMAC_PM_MASK	(3 << DMAC_PM_SHIFT)
					/* Channel priority mode */
#define	DMAC_PM_SHIFT	8
#define	DMAC_PM_012345	0		/* CH0 > CH1 > .. */
#define	DMAC_PM_023145	1
#define	DMAC_PM_201345	2
#define	DMAC_PM_RR	3		/* Round robin */
#define	DMAC_HLT	(1 << 3)	/* Global halt status */
#define	DMAC_AR		(1 << 2)	/* Global address error status */
#define	DMAC_DMAE	(1 << 0)	/* Global DMA transfer enable */

#define	DDR		_DMAC(0x308)	/* DMA doorbell */

#define	LCDCTRL		_LCD(0x30)	/* LCD control */

#endif /* !UBB_REGS4740_H */