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libubb/mmcclk.c (BUS_LIMIT_MHZ): explain the 56 MHz limit
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@ -18,7 +18,16 @@
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#define MSCCDR_MAX 32
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#define CLKRT_MAX 8
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#define BUS_LIMIT_MHZ 56 /* nominally, the limit is 20 MHz */
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/*
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* Nominally, the limit is 20 MHz. A clock can be obtained until 84 MHz,
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* possibly even higher. Beyond 56 MHz, the MMC controller in some Bens
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* has been observed to fail to complete the operation when attempting
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* data transmission.
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*
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* Some Bens still work fine at 84 MHz.
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*/
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#define BUS_LIMIT_MHZ 56
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static int calculate_clock(struct mmcclk *dsc)
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