diff --git a/libubb/mmcclk.c b/libubb/mmcclk.c
index 80c4ca1..77c955e 100644
--- a/libubb/mmcclk.c
+++ b/libubb/mmcclk.c
@@ -18,7 +18,16 @@
 #define	MSCCDR_MAX	32
 #define	CLKRT_MAX	8
 
-#define	BUS_LIMIT_MHZ	56	/* nominally, the limit is 20 MHz */
+/*
+ * Nominally, the limit is 20 MHz. A clock can be obtained until 84 MHz,
+ * possibly even higher. Beyond 56 MHz, the MMC controller in some Bens
+ * has been observed to fail to complete the operation when attempting
+ * data transmission.
+ *
+ * Some Bens still work fine at 84 MHz.
+ */
+
+#define	BUS_LIMIT_MHZ	56
 
 
 static int calculate_clock(struct mmcclk *dsc)