From 1a7b5015f1d90088e359eba512a0c352735f6339 Mon Sep 17 00:00:00 2001 From: Werner Almesberger Date: Fri, 29 Apr 2011 21:49:23 -0300 Subject: [PATCH] regs4740.h: added DMAC registers; added virt to phys translation; cleanup - regs4740.h (REG_PADDR): translate a register access to the corresponding physical address - regs4740.h (REG_WINDOW): added register window size - regs4740.h (CGU, INT, TCU, GPIO, MSC): prefix register group macros with an underscore, to avoid name collision with DMAC - regs4740.h: added DMAC registers - regs4740.h (MSC_NOP): should be MSC_NOB --- ubb-vga/regs4740.h | 86 +++++++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 35 deletions(-) diff --git a/ubb-vga/regs4740.h b/ubb-vga/regs4740.h index bd885a6..808e26e 100644 --- a/ubb-vga/regs4740.h +++ b/ubb-vga/regs4740.h @@ -17,47 +17,63 @@ #define SOC_BASE 0x10000000 +#define REG_WINDOW 0x4000000 -#define REG(n) (*(volatile uint32_t *) ((REG_BASE_PTR)+(n))) +#define REG(n) (*(volatile uint32_t *) ((void *) (REG_BASE_PTR)+(n))) -#define CGU(n) REG(0x00000+(n)) -#define INTC(n) REG(0x01000+(n)) -#define TCU(n) REG(0x02000+(n)) -#define GPIO(n) REG(0x10000+(n)) -#define MSC(n) REG(0x21000+(n)) +#define REG_PADDR(r) ((unsigned long) \ + ((void *) &(r)-(void *) (REG_BASE_PTR)+SOC_BASE)) -#define CLKGR CGU(0x0020) /* Clock Gate */ -#define MSCCDR CGU(0x0068) /* MSC device clock divider */ +#define _CGU(n) REG(0x0000000+(n)) +#define _INTC(n) REG(0x0001000+(n)) +#define _TCU(n) REG(0x0002000+(n)) +#define _GPIO(n) REG(0x0010000+(n)) +#define _MSC(n) REG(0x0021000+(n)) +#define _DMAC(n) REG(0x3020000+(n)) -#define PDPIN GPIO(0x300) /* port D pin level */ -#define PDDATS GPIO(0x314) /* port D data set */ -#define PDDATC GPIO(0x318) /* port D data clear */ -#define PDFUNS GPIO(0x344) /* port D function set */ -#define PDFUNC GPIO(0x348) /* port D function clear */ -#define PDDIRS GPIO(0x364) /* port D direction set */ -#define PDDIRC GPIO(0x368) /* port D direction clear */ +#define CLKGR _CGU(0x0020) /* Clock Gate */ +#define MSCCDR _CGU(0x0068) /* MSC device clock divider */ -#define ICMR INTC(0x04) /* Interrupt controller mask */ -#define ICMSR INTC(0x08) /* Interrupt controller mask set */ -#define ICMCR INTC(0x0c) /* Interrupt controller mask clear */ +#define PDPIN _GPIO(0x300) /* port D pin level */ +#define PDDATS _GPIO(0x314) /* port D data set */ +#define PDDATC _GPIO(0x318) /* port D data clear */ +#define PDFUNS _GPIO(0x344) /* port D function set */ +#define PDFUNC _GPIO(0x348) /* port D function clear */ +#define PDDIRS _GPIO(0x364) /* port D direction set */ +#define PDDIRC _GPIO(0x368) /* port D direction clear */ -#define TSSR TCU(0x2c) /* Timer STOP set */ -#define TSCR TCU(0x3c) /* Timer STOP clear */ -#define TESR TCU(0x14) /* Timer counter enable set */ -#define TECR TCU(0x18) /* Timer counter enable clear */ -#define TCSR(n) TCU(0x4c+0x10*(n)) /* Timer control */ -#define TDFR(n) TCU(0x40+0x10*(n)) /* Timer data full */ -#define TCNT(n) TCU(0x48+0x10*(n)) /* Timer counter */ +#define ICMR _INTC(0x04) /* Interrupt controller mask */ +#define ICMSR _INTC(0x08) /* Interrupt controller mask set */ +#define ICMCR _INTC(0x0c) /* Interrupt controller mask clear */ -#define MSC_STRPCL MSC(0x00) /* Start/stop MMC/SD clock */ -#define MSC_STAT MSC(0x04) /* MSC status */ -#define MSC_CLKRT MSC(0x08) /* MSC clock rate */ -#define MSC_CMDAT MSC(0x0c) /* MMC/SD command and data control */ -#define MSC_RESTO MSC(0x10) /* MMC/SD response time out */ -#define MSC_BLKLEN MSC(0x18) /* MMC/SD block length */ -#define MSC_NOP MSC(0x1c) /* MMC/SD number of blocks */ -#define MSC_CMD MSC(0x2c) /* MMC/SD command index */ -#define MSC_ARG MSC(0x30) /* MMC/SD command argument */ -#define MSC_TXFIFO MSC(0x3c) /* MMC/SD transmit data FIFO */ +#define TSSR _TCU(0x2c) /* Timer STOP set */ +#define TSCR _TCU(0x3c) /* Timer STOP clear */ +#define TESR _TCU(0x14) /* Timer counter enable set */ +#define TECR _TCU(0x18) /* Timer counter enable clear */ +#define TCSR(n) _TCU(0x4c+0x10*(n)) /* Timer control */ +#define TDFR(n) _TCU(0x40+0x10*(n)) /* Timer data full */ +#define TCNT(n) _TCU(0x48+0x10*(n)) /* Timer counter */ + +#define MSC_STRPCL _MSC(0x00) /* Start/stop MMC/SD clock */ +#define MSC_STAT _MSC(0x04) /* MSC status */ +#define MSC_CLKRT _MSC(0x08) /* MSC clock rate */ +#define MSC_CMDAT _MSC(0x0c) /* MMC/SD command and data control */ +#define MSC_RESTO _MSC(0x10) /* MMC/SD response time out */ +#define MSC_BLKLEN _MSC(0x18) /* MMC/SD block length */ +#define MSC_NOB _MSC(0x1c) /* MMC/SD number of blocks */ +#define MSC_CMD _MSC(0x2c) /* MMC/SD command index */ +#define MSC_ARG _MSC(0x30) /* MMC/SD command argument */ +#define MSC_TXFIFO _MSC(0x3c) /* MMC/SD transmit data FIFO */ + +#define _DMAn(n, r) _DMAC(0x20*(n)+(r)) + +#define DSA(n) _DMAn(n, 0x00) /* DMA source address */ +#define DTA(n) _DMAn(n, 0x04) /* DMA target address */ +#define DTC(n) _DMAn(n, 0x08) /* DMA transfer count */ +#define DRT(n) _DMAn(n, 0x0c) /* DMA request type */ +#define DCS(n) _DMAn(n, 0x10) /* DMA channel control/status */ +#define DCM(n) _DMAn(n, 0x14) /* DMA command */ +#define DMAC _DMAC(0x300) /* DMA control */ +#define DDR _DMAC(0x308) /* DMA doorbell */ #endif /* !REGS4740_H */