diff --git a/ubb-patgen/ubb-patgen.c b/ubb-patgen/ubb-patgen.c
index f53c18c..e72d388 100644
--- a/ubb-patgen/ubb-patgen.c
+++ b/ubb-patgen/ubb-patgen.c
@@ -287,7 +287,9 @@ static uint32_t old_dmac;
 
 static void dma_stop(void)
 {
-	DCS(DMA) = (1 << 3) | (1 << 2);	/* halt DMA channel */
+	DCS(DMA) =
+	    DCS_TT |			/* Transfer terminated */
+	    DCS_HLT;			/* DMA halt */
 	DCS(DMA) = 0;			/* reset DMA channel */
 }
 
@@ -296,13 +298,14 @@ static void dma_init(void)
 {
 	old_dmac = DMAC;
 
-	DMAC = 1;	/* activate the DMA controller (in case it's off) */
+	DMAC = DMAC_DMAE; /* activate the DMA controller (in case it's off) */
 	dma_stop();
 
 	DCM(DMA) =
-	    (1 << 23) |	/* source address increment */
-	    (4 << 8);	/* transfer size is 32 bytes */
-	DRT(DMA) = 26;	/* MSC transmit-fifo-empty transfer request */
+	    DCM_SAI |	/* source address increment */
+	    (DCM_TSZ_32BYTE << DCM_TSZ_SHIFT);
+			/* transfer size is 32 bytes */
+	DRT(DMA) = DRT_MSC_TX;	/* MSC transmit-fifo-empty transfer request */
 }
 
 
@@ -317,7 +320,7 @@ static void dma_setup(unsigned long buf, int nibbles)
 {
 	assert(!(nibbles & 63));
 
-	DCS(DMA) = 1 << 31;			/* no-descriptor transfer */
+	DCS(DMA) = DCS_NDES;			/* no-descriptor transfer */
 	DSA(DMA) = buf;				/* source */
 	DTA(DMA) = REG_PADDR(MSC_TXFIFO);	/* MUST set this each time */
 	DTC(DMA) = nibbles >> 6;		/* 32 bytes per transfer */
@@ -326,7 +329,7 @@ static void dma_setup(unsigned long buf, int nibbles)
 
 static void wait_dma_done(void)
 {
-	while (!((DCS(DMA) >> 3) & 1));	/* DCS.TT */
+	while (!(DCS(DMA) & DCS_TT));
 }
 
 
@@ -459,8 +462,8 @@ static void mmc_buffer(const struct mmcclk *clk,
 	 */
 
 	DCS(DMA) =
-	    (1 << 31) |         /* no descriptor */
-	    1;			/* enable transfer */
+	    DCS_NDES |		/* no descriptor */
+	    DCS_CTE;		/* enable channel */
 
 	unrealtime();