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ubb-vga: try to clock MSC faster than the MMC bus; new video mode "640x480/61"

Browse Source 
- ubb-vga.c (mode_db): added new mode "640x480/61"
- ubb-vga.c (setup, line): MSC_CLKRT is reset when the MSC resets. Moved
  it from "setup" to "line".
- ubb-vga.c (clkrt, setup, line): pick the highest available MSC clock
  and adjust the bus clock divider accordingly
- ubb-vga.c (main): added commented-out clock debugging output
- README: added XEN-1510T result for "640x480/61"
This commit is contained in:
Werner Almesberger 2011-05-03 10:19:16 -03:00
parent 887012a58a
commit 5817669968
2 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
ubb-vga/README
View File

@ -48,6 +48,8 @@ Mode Monitor Image Hor. noise Cleanliness
W2243C y y 2-4 large very distorted W2243C y y 2-4 large very distorted
W2243L y y 2-3 large very distorted W2243L y y 2-3 large very distorted
640x480/61 XEN-1510T y y 1 -/10, 20% very good/distorted (5)
640x480/70 XEN-1510T y (2) 1 10, 25% distorted, flickery 640x480/70 XEN-1510T y (2) 1 10, 25% distorted, flickery
LN32R71B n - "not supported mode" LN32R71B n - "not supported mode"
206NW y (2) 3-8 - very jittery 206NW y (2) 3-8 - very jittery
@ -115,6 +117,8 @@ that the screen content cannot be recognized.
manually. manually.
(4) Places the image too far to the left. Cannot be sufficiently (4) Places the image too far to the left. Cannot be sufficiently
corrected. corrected.
(5) about 70% of all session have a clean stable image. The remaining
30% suffer significant FIFO noise.
To do To do

15
ubb-vga/ubb-vga.c
View File

@ -51,8 +51,9 @@ static int bad;
static const struct mode mode_db[] = { static const struct mode mode_db[] = {
/* name xres yres clkdiv vfront hsync hback htotal */ /* name xres yres clkdiv vfront hsync hback htotal */
/* vsync vback */ /* vsync vback */
{ "640x480", 640, 480, 12, 2, 32, 14, US(2.80), US(1.3), US(32.1) }, { "640x480", 640, 480, 12, 2, 32, 14, US(2.80), US(1.30), US(32.1) },
{ "640x480/58", 640, 480, 12, 2, 10, 33, US(3.81), US(1.91), US(32.7) }, { "640x480/58", 640, 480, 12, 2, 10, 33, US(3.81), US(1.91), US(32.7) },
{ "640x480/61", 640, 480, 11, 2, 9, 29, US(2.50), US(4.06), US(31.5) },
{ "640x480/70", 640, 480, 9, 2, 8, 29, US(1.90), US(2.06), US(24.8) }, { "640x480/70", 640, 480, 9, 2, 8, 29, US(1.90), US(2.06), US(24.8) },
{ "800x600/54", 800, 600, 8, 2, 32, 14, US(4.81), US(0.79), US(28.8) }, { "800x600/54", 800, 600, 8, 2, 32, 14, US(4.81), US(0.79), US(28.8) },
@ -109,6 +110,8 @@ static const struct mode mode_db[] = {
const struct mode *mode = mode_db; const struct mode *mode = mode_db;
static uint32_t clkrt = 0;
/* ----- I/O pin assignment ------------------------------------------------ */ /* ----- I/O pin assignment ------------------------------------------------ */
@ -265,7 +268,10 @@ static void setup(void)
MSCCDR = mode->clkdiv; /* set the MSC clock to 336 MHz / 12 = 28 MHz */ MSCCDR = mode->clkdiv; /* set the MSC clock to 336 MHz / 12 = 28 MHz */
CLKGR &= ~(1 << 7); /* enable MSC clock */ CLKGR &= ~(1 << 7); /* enable MSC clock */
MSC_CLKRT = 0; /* bus clock = MSC clock / 1 */ while (MSCCDR & 1) {
MSCCDR >>= 1;
clkrt++;
}
} }
@ -307,6 +313,7 @@ static void line(unsigned long line)
/* HSYNC */ /* HSYNC */
PDDATC = HSYNC; PDDATC = HSYNC;
MSC_CLKRT = clkrt; /* bus clock = MSC clock / n */
MSC_STRPCL = 2; /* start MMC clock output */ MSC_STRPCL = 2; /* start MMC clock output */
MSC_RESTO = 0xffff; MSC_RESTO = 0xffff;
@ -500,6 +507,10 @@ int main(int argc, char *const *argv)
session(gen, frames); session(gen, frames);
cleanup(); cleanup();
#if 0
printf("clkdiv: %d, /%d /%d\n", mode->clkdiv,
(MSCCDR & 15)+1, 1 << (MSC_CLKRT & 7));
#endif
if (bad) if (bad)
printf("%d timeout%s\n", bad, bad == 1 ? "" : "s"); printf("%d timeout%s\n", bad, bad == 1 ? "" : "s");
return 0; return 0;