From 5efafd6fccaaf589d22f9f02b5901cad6ae8ce31 Mon Sep 17 00:00:00 2001
From: Werner Almesberger <werner@almesberger.net>
Date: Sun, 20 Jan 2013 19:16:17 -0300
Subject: [PATCH] libubb/include/ubb/regs4740.h: add symbolic bit/field
 definitions for DMA

---
 libubb/include/ubb/regs4740.h | 86 +++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/libubb/include/ubb/regs4740.h b/libubb/include/ubb/regs4740.h
index b4910ea..1de8508 100644
--- a/libubb/include/ubb/regs4740.h
+++ b/libubb/include/ubb/regs4740.h
@@ -139,15 +139,101 @@
 
 #define	MSC_TXFIFO	_MSC(0x3c)	/* MMC/SD transmit data FIFO */
 
+/* DMA */
+
 #define	_DMAn(n, r)	_DMAC(0x20*(n)+(r))
 
 #define	DSA(n)		_DMAn(n, 0x00)	/* DMA source address */
+
 #define	DTA(n)		_DMAn(n, 0x04)	/* DMA target address */
+
 #define	DTC(n)		_DMAn(n, 0x08)	/* DMA transfer count */
+#define	DTC_MASK	0xffffff
+
 #define	DRT(n)		_DMAn(n, 0x0c)	/* DMA request type */
+#define	DRT_MASK	0x1f
+#define	DRT_AUTO	8		/* external to external */
+#define	DRT_UART_TX	20
+#define	DRT_UART_RX	21
+#define	DRT_SSI_TX	22
+#define	DRT_SSI_RX	23
+#define	DRT_AIC_TX	24
+#define	DRT_AIC_RX	25
+#define	DRT_MSC_TX	26
+#define	DRT_MSC_RX	27
+#define	DRT_TCU		28
+#define	DRT_SADC	29
+#define	DRT_SLCD	30
+
 #define	DCS(n)		_DMAn(n, 0x10)	/* DMA channel control/status */
+#define	DCS_NDES	(1 << 31)	/* No-Descriptor Transfer */
+#define	DCS_CDOA_MASK	(0xff << DCS_CDOA_SHIFT)
+					/* Copy of Descriptor Offset Address */
+#define	DCS_CDOA_SHIFT	16
+#define	DCS_INV		(1 << 6)	/* Descriptor invalid error */
+#define	DCS_AR		(1 << 4)	/* Address error */
+#define	DCS_TT		(1 << 3)	/* Transfer terminated */
+#define	DCS_HLT		(1 << 2)	/* DMA halt */
+#define	DCS_CT		(1 << 1)	/* Link DMA transfer end */
+#define	DCS_CTE		(1 << 0)	/* Channel enabled */
+
 #define	DCM(n)		_DMAn(n, 0x14)	/* DMA command */
+#define	DCM_SAI		(1 << 23)	/* Source address increment */
+#define	DCM_DAI		(1 << 22)	/* Destination address increment */
+#define	DCM_RDIL_MASK	(15 << DCM_RDIL_SHIFT)
+					/* Request Detection Interval Length */
+#define	DCM_RDIL_SHIFT	16
+#define	DCM_RDIL_0	0
+#define	DCM_RDIL_2	1		/* 2 units, etc. */
+#define	DCM_RDIL_4	2
+#define	DCM_RDIL_8	3
+#define	DCM_RDIL_12	4
+#define	DCM_RDIL_16	5
+#define	DCM_RDIL_20	6
+#define	DCM_RDIL_24	7
+#define	DCM_RDIL_28	8
+#define	DCM_RDIL_32	9
+#define	DCM_RDIL_48	10
+#define	DCM_RDIL_60	11
+#define	DCM_RDIL_64	12
+#define	DCM_RDIL_124	13
+#define	DCM_RDIL_128	14
+#define	DCM_RDIL_200	15
+#define	DCM_SP_MASK	(3 << DCM_SP_SHIFT) /* Source port width */
+#define	DCM_SP_SHIFT	14
+#define	DCM_SP_32	0		/* 32 bit */
+#define	DCM_SP_8	1
+#define	DCM_SP_16	2
+#define	DCM_DP_MASK	(3 << DCM_DP_SHIFT) /* Destination port width */
+#define	DCM_DP_SHIFT	12
+#define	DCM_DP_32	0		/* 32 bit */
+#define	DCM_DP_8	1
+#define	DCM_DP_16	2
+#define	DCM_TSZ_MASK	(7 << DCM_TSZ_SHIFT) /* Transfer data size (unit) */
+#define	DCM_TSZ_SHIFT	8
+#define	DCM_TSZ_32BIT	0
+#define	DCM_TSZ_8BIT	1
+#define	DCM_TSZ_16BYTE	3
+#define	DCM_TSZ_32BYTE	4
+#define	DCM_TM		(1 << 7)	/* Transfer mode (0 single, 1 block) */
+#define	DCM_V		(1 << 4)	/* Descriptor valid */
+#define	DCM_VM		(1 << 3)	/* Descriptor valid mode */
+#define	DCM_VIE		(1 << 2)	/* DMA valid error Interrupt Enable */
+#define	DCM_TIE		(1 << 1)	/* Transfer Interrupt Enable (TIE) */
+#define	DCM_LINK	(1 << 0)	/* Descriptor link enable */
+
 #define	DMAC		_DMAC(0x300)	/* DMA control */
+#define	DMAC_PM_MASK	(3 << DMAC_PM_SHIFT)
+					/* Channel priority mode */
+#define	DMAC_PM_SHIFT	8
+#define	DMAC_PM_012345	0		/* CH0 > CH1 > .. */
+#define	DMAC_PM_023145	1
+#define	DMAC_PM_201345	2
+#define	DMAC_PM_RR	3		/* Round robin */
+#define	DMAC_HLT	(1 << 3)	/* Global halt status */
+#define	DMAC_AR		(1 << 2)	/* Global address error status */
+#define	DMAC_DMAE	(1 << 0)	/* Global DMA transfer enable */
+
 #define	DDR		_DMAC(0x308)	/* DMA doorbell */
 
 #define	LCDCTRL		_LCD(0x30)	/* LCD control */