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ubb-vga.c: removed commented-out code from earlier experiments
The history of the split prefetch code: Once up on a time, I thought that it was important to stay very close to the "official" pixel clock. We could do this when copying 32 bit words from cache to the GPIO set/clear registers, but not when shifting 8 bit values as we do now. One problem with 32 bit values is that transferring that amount of data exceeds the time available in the hsync pulse. Hence the idea to split the prefetch between hsync pulse and horizontal front porch. Note that we also split prefetches between the two VGA lines of each QVGA line. This commit does not change that mechanism. - ubb-vga.c (line, frame): removed code fragments for prefetch split between hsync pulse and front porch - ubb-vga.c (line, frame): remove code fragments for measuring time relative to the rising edge of hsync (and letting the prefetch time control the hsync length), not the falling edge
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@ -254,28 +254,23 @@ static void until(uint16_t cycles)
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static void line(const uint8_t *line, const uint8_t *fetch)
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{
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const uint8_t *p = line;
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//volatile uint8_t pat = R | B | G;
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/* HSYNC */
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*tcnt = 0;
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*pddatc = HSYNC;
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// prefetch(fetch, PREFETCH_HSYNC);
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prefetch(fetch, 160);
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until(US(3.77));
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// *tcnt = 0;
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*pddats = HSYNC;
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/* Front porch */
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// prefetch(fetch+PREFETCH_HSYNC, PREFETCH_HFRONT);
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// until(US(3.77+1.79-3.77));
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until(US(3.77+1.79));
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while (p != line+320) {
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*pddats = *p++ << 8;//pat; //R | G | B; //*p++;
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*pddatc = *p++ << 8;//pat;//R | G | B; // *p++;
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*pddats = *p++ << 8;
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*pddatc = *p++ << 8;
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}
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/* Back porch */
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// until(US(31.77-3.77));
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until(US(31.77));
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until(US(36));
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}
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@ -306,14 +301,10 @@ static void frame(const uint8_t *f)
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/* Front porch */
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*tcnt = 0;
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*pddatc = HSYNC;
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// prefetch(f, PREFETCH_HSYNC);
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until(US(3.77));
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// *tcnt = 0;
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*pddats = HSYNC;
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// prefetch(f+PREFETCH_HSYNC, PREFETCH_HFRONT);
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prefetch(f, 160);
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// until(US(31.77-3.77));
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until(US(31.77));
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until(US(36));
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hdelay(31);
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