From e7ec5c8ad437d84f27190f59836b2d8135940745 Mon Sep 17 00:00:00 2001 From: Werner Almesberger Date: Mon, 31 Jan 2011 19:02:50 -0300 Subject: [PATCH] Added simple UART 8:10 card. - BOOKSHELF: ATmega48 data sheet - Makefile (dsv): added target to populate the book shelf - components/atmega48-mmu.lib, components/atmega48-mmu.dcm: ATmega48-MMU schematics symbol - usrt.pro, uart.sch, uart.cmp, uart.brd: ATmega48-based UART board --- BOOKSHELF | 13 + Makefile | 7 +- components/atmega48-mmu.dcm | 3 + components/atmega48-mmu.lib | 46 ++ uart/uart.brd | 1326 +++++++++++++++++++++++++++++++++++ uart/uart.cmp | 80 +++ uart/uart.pro | 71 ++ uart/uart.sch | 339 +++++++++ 8 files changed, 1883 insertions(+), 2 deletions(-) create mode 100644 BOOKSHELF create mode 100644 components/atmega48-mmu.dcm create mode 100644 components/atmega48-mmu.lib create mode 100644 uart/uart.brd create mode 100644 uart/uart.cmp create mode 100644 uart/uart.pro create mode 100644 uart/uart.sch diff --git a/BOOKSHELF b/BOOKSHELF new file mode 100644 index 0000000..30828b4 --- /dev/null +++ b/BOOKSHELF @@ -0,0 +1,13 @@ +# +# Tags: +# +# N name to use for dsv (must be first) +# A alias name(s) +# D data sheet url +# + +N: atmega48 +A: atmega88 +A: atmega168 +A: avr +D: http://www.atmel.com/dyn/resources/prod_documents/doc2545.pdf diff --git a/Makefile b/Makefile index a0edc36..196a1d6 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ -.PHONY: all gen generate sch brd +.PHONY: all gen generate sch brd dsv all: - @echo "make what ? target: gen sch brd xpdf" + @echo "make what ? target: dsv gen sch brd" @exit 1 gen generate: @@ -13,3 +13,6 @@ sch: brd: pcbnew `pwd`/bbl.brd + +dsv: + ../eda-tools/dsv/dsv setup BOOKSHELF diff --git a/components/atmega48-mmu.dcm b/components/atmega48-mmu.dcm new file mode 100644 index 0000000..2adb80f --- /dev/null +++ b/components/atmega48-mmu.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 Date: Mon Jan 31 15:41:03 2011 +# +#End Doc Library diff --git a/components/atmega48-mmu.lib b/components/atmega48-mmu.lib new file mode 100644 index 0000000..dcb195a --- /dev/null +++ b/components/atmega48-mmu.lib @@ -0,0 +1,46 @@ +EESchema-LIBRARY Version 2.3 Date: Mon Jan 31 15:41:03 2011 +# +# ATmega48-MMU +# +DEF ATmega48-MMU U 0 40 Y Y 1 F N +F0 "U" -1350 1200 60 H V C CNN +F1 "ATmega48-MMU" 0 0 60 H V C CNN +DRAW +T 0 -1350 350 50 0 0 0 INT1 Normal 0 L B +T 0 -1350 -550 50 0 0 0 T1 Normal 0 L B +T 0 -1350 -250 50 0 0 0 TOSC1 Normal 0 L B +T 0 -1350 -400 50 0 0 0 TOSC2 Normal 0 L B +S -1400 1100 1400 -1100 0 0 0 N +X PD3/PCINT9/OC2B/ 1 -1700 450 300 R 50 50 1 1 T +X PD4/PCINT20/XCK/T0 2 -1700 300 300 R 50 50 1 1 T +X VCC 3 -1700 150 300 R 50 50 1 1 W +X GND 4 -1700 0 300 R 50 50 1 1 W +X PB6/PCINT6/XTAL1/ 5 -1700 -150 300 R 50 50 1 1 T +X PB7/PCINT7/XTAL2/ 6 -1700 -300 300 R 50 50 1 1 T +X PD5/PCINT21/OC0B/ 7 -1700 -450 300 R 50 50 1 1 T +X PD6/PCINT22/OC0A/AIN0 8 -450 -1400 300 U 50 50 1 1 T +X PD7/PCINT23/AIN1 9 -300 -1400 300 U 50 50 1 1 T +X PB9/PCINT0/CLKO/ICP1 10 -150 -1400 300 U 50 50 1 1 T +X PC1/ADC1/PCINT9 20 1700 300 300 L 50 50 1 1 T +X PB1/PCINT1/OC1A 11 0 -1400 300 U 50 50 1 1 T +X PC2/ADC2/PCINT10 21 1700 450 300 L 50 50 1 1 T +X PB2/PCINT2/OC1B 12 150 -1400 300 U 50 50 1 1 T +X PC3/ADC3/PCINT11 22 450 1400 300 D 50 50 1 1 T +X PB3/PCINT3/OC2A/MOSI 13 300 -1400 300 U 50 50 1 1 T +X PC4/ADC4/SDA/PCINT12 23 300 1400 300 D 50 50 1 1 T +X PB4/PCINT4/MISO 14 450 -1400 300 U 50 50 1 1 T +X PC5/ADC5/SCL/PCINT13 24 150 1400 300 D 50 50 1 1 T +X PB5/SCK/PCINT5 15 1700 -450 300 L 50 50 1 1 T +X PC6/RESET/PCINT14 25 0 1400 300 D 50 50 1 1 T +X AVCC 16 1700 -300 300 L 50 50 1 1 W +X PD0/RXD/PCINT16 26 -150 1400 300 D 50 50 1 1 T +X AREF 17 1700 -150 300 L 50 50 1 1 W +X PD1/TXD/PCINT17 27 -300 1400 300 D 50 50 1 1 T +X GND 18 1700 0 300 L 50 50 1 1 W +X PD2/INT0/PCINT18 28 -450 1400 300 D 50 50 1 1 T +X PC0/ADC0/PCINT8 19 1700 150 300 L 50 50 1 1 T +X PAD 29 900 -1400 300 U 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/uart/uart.brd b/uart/uart.brd new file mode 100644 index 0000000..09f2fdc --- /dev/null +++ b/uart/uart.brd @@ -0,0 +1,1326 @@ +PCBNEW-BOARD Version 1 date Mon Jan 31 19:00:29 2011 + +# Created by Pcbnew(2010-12-27 BZR 2685)-unstable + +$GENERAL +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 13E88001 +Links 24 +NoConn 0 +Di 54659 41863 64794 47524 +Ndraw 17 +Ntrack 107 +Nzone 0 +BoardThickness 630 +Nmodule 11 +Nnets 18 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "External UART (3.3 V) as 8:10 card" +Date "31 jan 2011" +Rev "20110131" +Comp "Werner Almesberger" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +ZoneGridSize 250 +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 78 +ZoneClearence 150 +TrackMinWidth 80 +DrawSegmWidth 50 +EdgeSegmWidth 50 +ViaSize 300 +ViaDrill 100 +ViaMinSize 300 +ViaMinDrill 100 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 800 800 +PadDrill 400 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "/CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "/INT" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "/MISO" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "/MOSI" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 5 "/SCK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 6 "/nRESET" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 7 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 8 "N-000005" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 9 "N-000006" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 10 "N-000015" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 11 "N-000016" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 12 "N-000017" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 13 "N-000019" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 14 "N-000021" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 15 "N-000022" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 16 "N-000029" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 17 "VDD" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 78 +TrackWidth 80 +ViaDia 300 +ViaDrill 100 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "/CLK" +AddNet "/INT" +AddNet "/MISO" +AddNet "/MOSI" +AddNet "/SCK" +AddNet "/nRESET" +AddNet "N-000005" +AddNet "N-000006" +AddNet "N-000015" +AddNet "N-000016" +AddNet "N-000017" +AddNet "N-000019" +AddNet "N-000021" +AddNet "N-000022" +AddNet "N-000029" +$EndNCLASS +$NCLASS +Name "Power" +Desc "" +Clearance 78 +TrackWidth 90 +ViaDia 300 +ViaDrill 100 +uViaDia 200 +uViaDrill 50 +AddNet "GND" +AddNet "VDD" +$EndNCLASS +$MODULE 0402 +Po 57441 44252 1800 15 4D3AED1A 4D470BA3 ~~ +Li 0402 +Sc 4D470BA3 +AR /4D47052C +Op 0 0 0 +At SMD +T0 0 -150 200 200 1800 40 N V 25 N"R1" +T1 0 150 200 200 1800 40 N I 25 N"100" +DS -354 177 -354 -177 50 21 +DS -354 -177 354 -177 50 21 +DS 354 -177 354 177 50 21 +DS 354 177 -354 177 50 21 +$PAD +Sh "1" R 197 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 9 "N-000006" +Po -196 0 +$EndPAD +$PAD +Sh "2" R 197 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "N-000015" +Po 196 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56142 44252 0 15 4D3AED1A 4D470BA5 ~~ +Li 0402 +Sc 4D470BA5 +AR /4D47052E +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R2" +T1 0 150 200 200 0 40 N I 25 N"100" +DS -354 177 -354 -177 50 21 +DS -354 -177 354 -177 50 21 +DS 354 -177 354 177 50 21 +DS 354 177 -354 177 50 21 +$PAD +Sh "1" R 197 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 8 "N-000005" +Po -196 0 +$EndPAD +$PAD +Sh "2" R 197 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 11 "N-000016" +Po 196 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 55749 45590 2700 15 4D3AED1A 4D470BA7 ~~ +Li 0402 +Sc 4D470BA7 +AR /4D470731 +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"C1" +T1 0 150 200 200 2700 40 N I 25 N"100nF" +DS -354 177 -354 -177 50 21 +DS -354 -177 354 -177 50 21 +DS 354 -177 354 177 50 21 +DS 354 177 -354 177 50 21 +$PAD +Sh "1" R 197 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 17 "VDD" +Po -196 0 +$EndPAD +$PAD +Sh "2" R 197 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "GND" +Po 196 0 +$EndPAD +$EndMODULE 0402 +$MODULE 8:10-card +Po 58780 45039 0 15 4D34E84A 4D470BA8 ~~ +Li 8:10-card +Sc 4D470BA8 +AR /4D4702F7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"P1" +T1 0 150 200 200 0 40 N I 25 N"8:10-CARD" +DS 0 2165 0 -2165 30 21 +DS 0 -2165 2007 -2165 30 21 +DS 2007 -2165 2322 -1850 30 21 +DS 2322 -1850 2795 -1850 30 21 +DS 2795 -1850 2795 -2165 30 21 +DS 2795 -2165 3346 -2165 30 21 +DS 3346 -2165 3897 -1614 30 21 +DS 0 2165 5905 2165 30 21 +DS 3897 -1614 5905 -1614 30 21 +DS 5905 2165 5905 -1614 30 21 +DS -551 2165 -551 -2165 30 21 +$PAD +Sh "1" R 1181 355 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 6 "/nRESET" +Po 4920 -1239 +$EndPAD +$PAD +Sh "2" R 1181 355 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 2 "/INT" +Po 4920 -806 +$EndPAD +$PAD +Sh "3" R 1181 355 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 4 "/MOSI" +Po 4920 -373 +$EndPAD +$PAD +Sh "4" R 1299 354 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 17 "VDD" +Po 4979 59 +$EndPAD +$PAD +Sh "5" R 1181 355 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 1 "/CLK" +Po 4920 491 +$EndPAD +$PAD +Sh "6" R 1299 354 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 7 "GND" +Po 4979 925 +$EndPAD +$PAD +Sh "7" R 1181 354 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 5 "/SCK" +Po 4920 1358 +$EndPAD +$PAD +Sh "8" R 1181 354 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 3 "/MISO" +Po 4920 1791 +$EndPAD +$EndMODULE 8:10-card +$MODULE PIN_ARRAY_3X1 +Po 56497 43504 0 15 4D471131 4D470BA9 ~~ +Li PIN_ARRAY_3X1 +Cd Connecteur 3 pins +Kw CONN DEV +Sc 4D470BA9 +AR /4D4704D9 +Op 0 0 0 +T0 100 -850 400 400 0 60 N V 21 N"K1" +T1 0 -850 400 400 0 60 N I 21 N"CONN_3" +DS -1500 500 -1500 -500 60 21 +DS -1500 -500 1500 -500 60 21 +DS 1500 -500 1500 500 60 21 +DS 1500 500 -1500 500 60 21 +DS -500 -500 -500 500 60 21 +$PAD +Sh "1" R 800 800 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 8 "N-000005" +Po -1000 0 +$EndPAD +$PAD +Sh "2" C 800 800 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 7 "GND" +Po 0 0 +$EndPAD +$PAD +Sh "3" C 800 800 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 9 "N-000006" +Po 1000 0 +$EndPAD +$SHAPE3D +Na "pin_array/pins_array_3x1.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE PIN_ARRAY_3X1 +$MODULE 0402 +Po 55237 44685 900 15 4D3AED1A 4D472640 ~~ +Li 0402 +Sc 4D472640 +AR /4D472610 +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"R3" +T1 0 150 200 200 900 40 N I 25 N"68" +DS -354 177 -354 -177 50 21 +DS -354 -177 354 -177 50 21 +DS 354 -177 354 177 50 21 +DS 354 177 -354 177 50 21 +$PAD +Sh "1" R 197 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 15 "N-000022" +Po -196 0 +$EndPAD +$PAD +Sh "2" R 197 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "N-000017" +Po 196 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 55237 45905 2700 15 4D3AED1A 4D472641 ~~ +Li 0603 +Sc 4D472641 +AR /4D47260E +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"D1" +T1 0 150 200 200 2700 40 N I 25 N"LED" +DS -531 275 -531 -275 50 21 +DS -531 -275 531 -275 50 21 +DS 531 -275 531 275 50 21 +DS 531 275 -531 275 50 21 +$PAD +Sh "1" R 276 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 15 "N-000022" +Po -295 0 +$EndPAD +$PAD +Sh "2" R 276 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "GND" +Po 295 0 +$EndPAD +$EndMODULE 0603 +$MODULE PAD_2mm +Po 55591 46929 0 15 4D34EABB 4D4727A5 ~~ +Li PAD_2mm +Sc 4D4727A5 +AR /4D472716 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"P3" +T1 0 150 200 200 0 40 N I 25 N"CONN_1" +$PAD +Sh "1" O 786 196 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 14 "N-000021" +Po 0 0 +$EndPAD +$EndMODULE PAD_2mm +$MODULE PAD_2mm +Po 55591 46614 0 15 4D34EABB 4D4727A7 ~~ +Li PAD_2mm +Sc 4D4727A7 +AR /4D472714 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"P2" +T1 0 150 200 200 0 40 N I 25 N"CONN_1" +$PAD +Sh "1" O 786 196 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 13 "N-000019" +Po 0 0 +$EndPAD +$EndMODULE PAD_2mm +$MODULE PAD_2mm +Po 56851 46929 0 15 4D34EABB 4D4729E4 ~~ +Li PAD_2mm +Sc 4D4729E4 +AR /4D47292F +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"P4" +T1 0 150 200 200 0 40 N I 25 N"CONN_1" +$PAD +Sh "1" O 786 196 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 16 "N-000029" +Po 0 0 +$EndPAD +$EndMODULE PAD_2mm +$MODULE QFN28-Atmel +Po 57087 45630 0 15 4D472F2A 4D470C12 ~~ +Li QFN28-Atmel +Sc 4D470C12 +AR /4D4702FE +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"U1" +T1 0 150 200 200 0 40 N I 25 N"ATMEGA48-MMU" +DS -807 -807 -669 -807 50 21 +DS -807 -807 -807 -669 50 21 +DS -807 -669 -669 -807 50 21 +DS -807 807 -807 669 50 21 +DS -807 807 -669 807 50 21 +DS -669 807 -669 807 50 21 +DS 807 807 669 807 50 21 +DS 807 807 807 669 50 21 +DS 807 669 807 669 50 21 +DS 807 -807 807 -669 50 21 +DS 807 -807 669 -807 50 21 +DS 669 -807 669 -807 50 21 +$PAD +Sh "1" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -806 -531 +$EndPAD +$PAD +Sh "2" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -806 -354 +$EndPAD +$PAD +Sh "3" R 275 95 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 17 "VDD" +Po -806 -176 +$EndPAD +$PAD +Sh "4" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "GND" +Po -806 0 +$EndPAD +$PAD +Sh "5" R 275 95 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "/CLK" +Po -806 176 +$EndPAD +$PAD +Sh "6" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -806 354 +$EndPAD +$PAD +Sh "7" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "N-000019" +Po -806 531 +$EndPAD +$PAD +Sh "8" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "N-000021" +Po -531 806 +$EndPAD +$PAD +Sh "9" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 16 "N-000029" +Po -354 806 +$EndPAD +$PAD +Sh "10" R 95 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 806 +$EndPAD +$PAD +Sh "11" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 806 +$EndPAD +$PAD +Sh "12" R 95 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 806 +$EndPAD +$PAD +Sh "13" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "/MOSI" +Po 354 806 +$EndPAD +$PAD +Sh "14" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "/MISO" +Po 531 806 +$EndPAD +$PAD +Sh "15" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 5 "/SCK" +Po 806 531 +$EndPAD +$PAD +Sh "16" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 17 "VDD" +Po 806 354 +$EndPAD +$PAD +Sh "17" R 275 95 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 806 176 +$EndPAD +$PAD +Sh "18" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "GND" +Po 806 0 +$EndPAD +$PAD +Sh "19" R 275 95 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 806 -176 +$EndPAD +$PAD +Sh "20" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 806 -354 +$EndPAD +$PAD +Sh "21" R 275 94 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 2 "/INT" +Po 806 -531 +$EndPAD +$PAD +Sh "22" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 531 -806 +$EndPAD +$PAD +Sh "23" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 354 -806 +$EndPAD +$PAD +Sh "24" R 95 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 -806 +$EndPAD +$PAD +Sh "25" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "/nRESET" +Po 0 -806 +$EndPAD +$PAD +Sh "26" R 95 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "N-000015" +Po -176 -806 +$EndPAD +$PAD +Sh "27" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 11 "N-000016" +Po -354 -806 +$EndPAD +$PAD +Sh "28" R 94 275 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "N-000017" +Po -531 -806 +$EndPAD +$PAD +Sh "29" R 944 944 0 0 0 +Dr 0 0 0 +At SMD N 00808000 +Ne 7 "GND" +Po 0 0 +$EndPAD +$PAD +Sh "" R 315 315 0 0 0 +Dr 0 0 0 +At SMD N 00080000 +Ne 0 "" +Po -196 196 +$EndPAD +$PAD +Sh "" R 315 315 0 0 0 +Dr 0 0 0 +At SMD N 00080000 +Ne 0 "" +Po -196 -196 +$EndPAD +$PAD +Sh "" R 315 315 0 0 0 +Dr 0 0 0 +At SMD N 00080000 +Ne 0 "" +Po 196 196 +$EndPAD +$PAD +Sh "" R 315 315 0 0 0 +Dr 0 0 0 +At SMD N 00080000 +Ne 0 "" +Po 196 -196 +$EndPAD +$EndMODULE QFN28-Atmel +$TEXTPCB +Te "110131" +Po 59528 43425 500 500 100 0 +De 15 1 0 Normal +$EndTEXTPCB +$TEXTPCB +Te "TGR" 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46922 +55244 47002 57267 47002 +58730 47002 64511 47002 +$endFILLSEGMENTS +$endCZONE_OUTLINE +$EndBOARD diff --git a/uart/uart.cmp b/uart/uart.cmp new file mode 100644 index 0000000..19ec00f --- /dev/null +++ b/uart/uart.cmp @@ -0,0 +1,80 @@ +Cmp-Mod V01 Created by CvPCB (2010-12-27 BZR 2685)-unstable date = Mon Jan 31 18:30:06 2011 + +BeginCmp +TimeStamp = /4D470731; +Reference = C1; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4D47260E; +Reference = D1; +ValeurCmp = LED; +IdModule = 0603; +EndCmp + +BeginCmp +TimeStamp = /4D4704D9; +Reference = K1; +ValeurCmp = CONN_3; +IdModule = PIN_ARRAY_3X1; +EndCmp + +BeginCmp +TimeStamp = /4D4702F7; +Reference = P1; +ValeurCmp = 8:10-CARD; +IdModule = 8:10-card; +EndCmp + +BeginCmp +TimeStamp = /4D472714; +Reference = P2; +ValeurCmp = CONN_1; +IdModule = PAD_2mm; +EndCmp + +BeginCmp +TimeStamp = /4D472716; +Reference = P3; +ValeurCmp = CONN_1; +IdModule = PAD_2mm; +EndCmp + +BeginCmp +TimeStamp = /4D47292F; +Reference = P4; +ValeurCmp = CONN_1; +IdModule = PAD_2mm; +EndCmp + +BeginCmp +TimeStamp = /4D47052C; +Reference = R1; +ValeurCmp = 100; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4D47052E; +Reference = R2; +ValeurCmp = 100; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4D472610; +Reference = R3; +ValeurCmp = 68; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4D4702FE; +Reference = U1; +ValeurCmp = ATMEGA48-MMU; +IdModule = QFN28-Atmel; +EndCmp + +EndListe diff --git a/uart/uart.pro b/uart/uart.pro new file mode 100644 index 0000000..e6c64ac --- /dev/null +++ b/uart/uart.pro @@ -0,0 +1,71 @@ +update=Mon Jan 31 19:00:31 2011 +last_client=pcbnew +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +PrintMonochrome=1 +ShowSheetReferenceAndTitleBlock=1 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=conn +LibName4=../../kicad-libs/components/8_10-card +LibName5=../components/atmega48-mmu +[cvpcb] +version=1 +NetIExt=net +[cvpcb/libraries] +EquName1=devcms +[pcbnew] +version=1 +PadDrlX=400 +PadDimH=800 +PadDimV=800 +BoardThickness=630 +SgPcb45=1 +TxtPcbV=800 +TxtPcbH=600 +TxtModV=600 +TxtModH=600 +TxtModW=120 +VEgarde=100 +DrawLar=50 +EdgeLar=50 +TxtLar=120 +MSegLar=150 +LastNetListRead=uart.net +[pcbnew/libraries] +LibDir= +LibName1=pin_array +LibName2=../../kicad-libs/modules/stdpass +LibName3=../../kicad-libs/modules/8_10-card +LibName4=../../ben-wpan/modules/qfn +LibName5=../../kicad-libs/modules/pads diff --git a/uart/uart.sch b/uart/uart.sch new file mode 100644 index 0000000..4db4f5e --- /dev/null +++ b/uart/uart.sch @@ -0,0 +1,339 @@ +EESchema Schematic File Version 2 date Mon Jan 31 18:30:09 2011 +LIBS:power +LIBS:device +LIBS:conn +LIBS:8_10-card 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