1
0
mirror of git://projects.qi-hardware.com/ben-blinkenlights.git synced 2024-11-23 23:00:38 +02:00

ubb-vga: gently prepare the code for sharing mode information

This is tricky: if we just make "mode" global, the whole timing may
fall apart, with the DMA locking up. So let's take small bisectable
steps to get there ...

- ubb-vga.c (struct mode), ubb-vga.h: moved mode entry declaration to
  ubb-vga.h
- ubb-vga.c (mode_db): moved up
This commit is contained in:
Werner Almesberger 2011-05-01 15:08:02 -03:00
parent 90b087cea0
commit f7eb220401
2 changed files with 50 additions and 45 deletions

View File

@ -45,6 +45,47 @@ static volatile void *base;
static int bad;
#define US(us) ((uint16_t) ((us)*112))
static const struct mode mode_db[] = {
{ "640x480", 640, 480, 11, US(29.7), US(0.79+3.77-0.3) },
{ "800x600", 800, 600, 8, US(28.7), US(2.0+3.3+0.3) },
/* the next one may work after adjusting the timing in "frame" */
{ "800x600", 800, 600, 8, US(28.2), US(2.0+3.3+0.3-0.3) },
/* the 1024x768 below is not great but has good parameter tolerance */
{ "1024x768", 1024, 768, 8, US(36.0), US(2.0+3.3) },
/* illustrate underruns */
{ "1024x768ur", 1024, 768, 7, US(33.5), US(0.4+2.1+0.5) },
{ NULL }
};
/*
* Adjustment value tests with the XEN-1510 (640x480):
*
* Adjustment Tries Good Jam FIFO jitter
* Quick load
* -0.0 10 3 7 0 n
* -0.1 10 5 5 0 n
* -0.2 10 6 4 0 n
* -0.3 10 7 3 0 n
* 10 5 5 0 y
* -0.4 10 1 0 9 n
* 10 5 0 5 n repeat
* 10 5 0 5 y
* -0.5 10 3 0 7 n
* 10 7 0 3 y
* -1.0 5 0 5 0
*
* Good = image is stable
* Jam = does not detect the signal properly, loss of HSYNC, artefacts,
* or no image at all
* FIFO jitter = some lines get shifted by a "digital" amount
*/
static const struct mode *mode = mode_db;
/* ----- I/O pin assignment ------------------------------------------------ */
@ -172,9 +213,6 @@ static void cleanup(void)
/* ----- Delay logic ------------------------------------------------------- */
#define US(us) ((uint16_t) ((us)*112))
static void until(uint16_t cycles)
{
while ((TCNT(TIMER) & 0xffff) < cycles);
@ -184,48 +222,6 @@ static void until(uint16_t cycles)
/* ----- Frame buffer output ----------------------------------------------- */
static const struct mode {
const char *name;
int xres, yres;
int clkdiv; /* pixel clock = 336 MHz/(clkdiv+1) */
int line_cycles; /* 31.77 us for official VGA */
int hsync_end; /* 0.79+3.77 us for official VGA */
} mode_db[] = {
{ "640x480", 640, 480, 11, US(29.7), US(0.79+3.77-0.3) },
{ "800x600", 800, 600, 8, US(28.7), US(2.0+3.3+0.3) },
/* the next one may work after adjusting the timing in "frame" */
{ "800x600", 800, 600, 8, US(28.2), US(2.0+3.3+0.3-0.3) },
/* the 1024x768 below is not great but has good parameter tolerance */
{ "1024x768", 1024, 768, 8, US(36.0), US(2.0+3.3) },
/* illustrate underruns */
{ "1024x768ur", 1024, 768, 7, US(33.5), US(0.4+2.1+0.5) },
{ NULL }
}, *mode = mode_db;
/*
* Adjustment value tests with the XEN-1510 (640x480):
*
* Adjustment Tries Good Jam FIFO jitter
* Quick load
* -0.0 10 3 7 0 n
* -0.1 10 5 5 0 n
* -0.2 10 6 4 0 n
* -0.3 10 7 3 0 n
* 10 5 5 0 y
* -0.4 10 1 0 9 n
* 10 5 0 5 n repeat
* 10 5 0 5 y
* -0.5 10 3 0 7 n
* 10 7 0 3 y
* -1.0 5 0 5 0
*
* Good = image is stable
* Jam = does not detect the signal properly, loss of HSYNC, artefacts,
* or no image at all
* FIFO jitter = some lines get shifted by a "digital" amount
*/
static void setup(void)
{
mlockall(MCL_CURRENT | MCL_FUTURE);

View File

@ -23,6 +23,15 @@
#define Y_VAL (1 << 2)
struct mode {
const char *name; /* NULL for end of table */
int xres, yres;
int clkdiv; /* pixel clock = 336 MHz/(clkdiv+1) */
int line_cycles; /* 31.77 us for official VGA */
int hsync_end; /* 0.79+3.77 us for official VGA */
};
void *map(off_t addr, size_t size);