Sources
-------

Timing and the idea for the voltage divider is from:
http://faculty.lasierra.edu/~ehwang/public/mypublications/VGA Monitor Controller.pdf

More timing parameters:
http://tinyvga.com/vga-timing/640x480@60Hz


Signal	8:10	VGA
-------	-------	---
R	DAT2	1
VSYNC	DAT3	14
HSYNC	CMD	13
G	DAT0	2
B	DAT1	3
GND	GND	5

http://en.wikipedia.org/wiki/VGA_connector


Timing
------

Since the Ingenic CPUs take about 8.5 PCLK cycles for a GPIO set or clear,
and we can only set or clear a set of signals in GPIO operation, but not
set some and clear others, we cannot have a real 320 horizontal pixels.

Instead, set and clear operations alternate. This means that the best-case
resolution is equivalent to 320 pixels (if the original pixel boundaries
coincide with the set/clear phases), but it can be as low as 160 pixels if
the boundaries don't match.

Furthermore, timing is still a bit too tight. We therefore use a pixel
clock that's about 10% slower than the original. Luckily, most monitors
don't mind.