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94 lines
2.8 KiB
Plaintext
94 lines
2.8 KiB
Plaintext
UBB-VGA - VGA-like output via UBB
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=================================
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Sources
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-------
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Timing and the idea for the voltage divider is from:
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http://faculty.lasierra.edu/~ehwang/public/mypublications/VGA Monitor Controller.pdf
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More timing parameters:
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http://tinyvga.com/vga-timing/640x480@60Hz
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Signal 8:10 VGA
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------- ------- ---
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R DAT2 1
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VSYNC DAT3 14
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HSYNC CMD 13
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G DAT0 2
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B DAT1 3
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GND GND 5
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http://en.wikipedia.org/wiki/VGA_connector
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Timing
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------
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Since the Ingenic CPUs take about 8.5 PCLK cycles for a GPIO set or clear,
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and we can only set or clear a set of signals in GPIO operation, but not
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set some and clear others, we cannot have a real 320 horizontal pixels.
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Instead, set and clear operations alternate. This means that the best-case
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resolution is equivalent to 320 pixels (if the original pixel boundaries
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coincide with the set/clear phases), but it can be as low as 160 pixels if
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the boundaries don't match.
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Furthermore, timing is still a bit too tight. We therefore use a pixel
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clock that's about 10% slower than the original. Luckily, most monitors
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don't mind.
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Single/double mode
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------------------
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In single mode, only one set/clear can be performed per pixel. They are
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arranges such that the first pixel can only turn on channels, the
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following pixel can only turn off channels, and so on.
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In double mode, a set and a clear is performed per pixel. This changes
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the timing such that it differs substantially from VGA, but some
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monitors can still synchronize with this.
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The resulting signals for various bit patterns are shown in mapping.fig
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Each group shows the input pixels, and signal for single mode, and the
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signal for double mode. "S" indicates a point where the channel can be
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turned on, "C" indicates a point where it can be turned off.
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Note that there are probably other mapping algorithms that would yield
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better results. The mapping is not a very performance-critical part of
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ubb-vga. Improvements are welcome.
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Compatibility
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-------------
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ubb-vga in single mode has been tested with the following monitors:
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Display Monitor size Quality
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----------------------- --------------- ----------------------------------
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Xenon XEN-1510T 15", 1024x768 good
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Samsung 206NW 20", 1680x1050 poor (horizontal instability)
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LG W2243C 22", 1920x1080 acceptable (slight instability)
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LG W2243L 22", 1920x1080 acceptable (slight instability)
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In double mode:
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Display Pixels missing Quality
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left/right
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----------------------- --------------- ------------------
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Xenon XEN-1510T 5 / 25 good
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To do
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-----
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- use timer half interrupt and WAIT to synchronize (less bus traffic and
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hopefully better granularity)
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- recover from DMA lockup
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- use color cube map (5x5x5 bits)
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- read/write raw frame buffer
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- consider prefetching first word of each line, to make DRAM controller
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open the row and reduce DMA startup latency
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