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git://projects.qi-hardware.com/ben-blinkenlights.git
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6d8c8dd951
Two benefits: 1) We don't accumulate errors from the delay between the timer reset and the deadline preceding it 2) In the future, we may use WAIT to wait for timer expiration, which should cause less bus activity and is should also reduce jitter - regs4740.h (TFR. TFSR, TFCR, TDHR): added more timer registers - ubb-vga.c (until): renamed to "delay" and changed to measure relative to the last deadline - ubb-vga.c (line, hdelay, frame): replaced "until" with "delay" - ubb-vga.c (hdelay, frame, session): reset the timer only once, at the beginning of the session - ubb-vga.c (frame): we didn't wait for the horizontal back porch of the last image line
84 lines
3.1 KiB
C
84 lines
3.1 KiB
C
/*
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* regs4740.h - Jz4740 register definitions (subset)
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*
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* Written 2011 by Werner Almesberger
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* Copyright 2011 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef REGS4740_H
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#define REGS4740_H
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#include <stdint.h>
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#define SOC_BASE 0x10000000
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#define REG_WINDOW 0x4000000
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#define REG(n) (*(volatile uint32_t *) ((void *) (REG_BASE_PTR)+(n)))
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#define REG_PADDR(r) ((unsigned long) \
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((void *) &(r)-(void *) (REG_BASE_PTR)+SOC_BASE))
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#define _CGU(n) REG(0x0000000+(n))
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#define _INTC(n) REG(0x0001000+(n))
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#define _TCU(n) REG(0x0002000+(n))
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#define _GPIO(n) REG(0x0010000+(n))
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#define _MSC(n) REG(0x0021000+(n))
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#define _DMAC(n) REG(0x3020000+(n))
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#define CLKGR _CGU(0x0020) /* Clock Gate */
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#define MSCCDR _CGU(0x0068) /* MSC device clock divider */
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#define PDPIN _GPIO(0x300) /* port D pin level */
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#define PDDATS _GPIO(0x314) /* port D data set */
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#define PDDATC _GPIO(0x318) /* port D data clear */
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#define PDFUNS _GPIO(0x344) /* port D function set */
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#define PDFUNC _GPIO(0x348) /* port D function clear */
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#define PDDIRS _GPIO(0x364) /* port D direction set */
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#define PDDIRC _GPIO(0x368) /* port D direction clear */
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#define ICMR _INTC(0x04) /* Interrupt controller mask */
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#define ICMSR _INTC(0x08) /* Interrupt controller mask set */
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#define ICMCR _INTC(0x0c) /* Interrupt controller mask clear */
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#define TSSR _TCU(0x2c) /* Timer STOP set */
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#define TSCR _TCU(0x3c) /* Timer STOP clear */
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#define TESR _TCU(0x14) /* Timer counter enable set */
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#define TECR _TCU(0x18) /* Timer counter enable clear */
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#define TFR _TCU(0x20) /* Timer flag */
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#define TFSR _TCU(0x24) /* Timer flag set */
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#define TFCR _TCU(0x28) /* Timer flag clear */
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#define TCSR(n) _TCU(0x4c+0x10*(n)) /* Timer control */
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#define TDFR(n) _TCU(0x40+0x10*(n)) /* Timer data full */
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#define TDHR(n) _TCU(0x44+0x10*(n)) /* Timer data half */
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#define TCNT(n) _TCU(0x48+0x10*(n)) /* Timer counter */
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#define MSC_STRPCL _MSC(0x00) /* Start/stop MMC/SD clock */
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#define MSC_STAT _MSC(0x04) /* MSC status */
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#define MSC_CLKRT _MSC(0x08) /* MSC clock rate */
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#define MSC_CMDAT _MSC(0x0c) /* MMC/SD command and data control */
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#define MSC_RESTO _MSC(0x10) /* MMC/SD response time out */
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#define MSC_BLKLEN _MSC(0x18) /* MMC/SD block length */
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#define MSC_NOB _MSC(0x1c) /* MMC/SD number of blocks */
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#define MSC_CMD _MSC(0x2c) /* MMC/SD command index */
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#define MSC_ARG _MSC(0x30) /* MMC/SD command argument */
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#define MSC_TXFIFO _MSC(0x3c) /* MMC/SD transmit data FIFO */
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#define _DMAn(n, r) _DMAC(0x20*(n)+(r))
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#define DSA(n) _DMAn(n, 0x00) /* DMA source address */
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#define DTA(n) _DMAn(n, 0x04) /* DMA target address */
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#define DTC(n) _DMAn(n, 0x08) /* DMA transfer count */
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#define DRT(n) _DMAn(n, 0x0c) /* DMA request type */
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#define DCS(n) _DMAn(n, 0x10) /* DMA channel control/status */
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#define DCM(n) _DMAn(n, 0x14) /* DMA command */
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#define DMAC _DMAC(0x300) /* DMA control */
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#define DDR _DMAC(0x308) /* DMA doorbell */
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#endif /* !REGS4740_H */
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