mirror of
git://projects.qi-hardware.com/ben-blinkenlights.git
synced 2024-11-24 00:20:38 +02:00
91 lines
3.4 KiB
C
91 lines
3.4 KiB
C
/*
|
|
* regs4740.h - Jz4740 register definitions (subset)
|
|
*
|
|
* Written 2011 by Werner Almesberger
|
|
* Copyright 2011 Werner Almesberger
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*/
|
|
|
|
#ifndef REGS4740_H
|
|
#define REGS4740_H
|
|
|
|
#include <stdint.h>
|
|
|
|
|
|
#define SOC_BASE 0x10000000
|
|
#define REG_WINDOW 0x4000000
|
|
|
|
#define REG(n) (*(volatile uint32_t *) ((void *) (REG_BASE_PTR)+(n)))
|
|
|
|
#define REG_PADDR(r) ((unsigned long) \
|
|
((void *) &(r)-(void *) (REG_BASE_PTR)+SOC_BASE))
|
|
|
|
#define _CGU(n) REG(0x0000000+(n))
|
|
#define _INTC(n) REG(0x0001000+(n))
|
|
#define _TCU(n) REG(0x0002000+(n))
|
|
#define _GPIO(n) REG(0x0010000+(n))
|
|
#define _MSC(n) REG(0x0021000+(n))
|
|
#define _DMAC(n) REG(0x3020000+(n))
|
|
#define _LCD(n) REG(0x3050000+(n))
|
|
|
|
#define CLKGR _CGU(0x0020) /* Clock Gate */
|
|
#define MSCCDR _CGU(0x0068) /* MSC device clock divider */
|
|
|
|
#define PDPIN _GPIO(0x300) /* port D pin level */
|
|
#define PDDATS _GPIO(0x314) /* port D data set */
|
|
#define PDDATC _GPIO(0x318) /* port D data clear */
|
|
#define PDFUNS _GPIO(0x344) /* port D function set */
|
|
#define PDFUNC _GPIO(0x348) /* port D function clear */
|
|
#define PDDIRS _GPIO(0x364) /* port D direction set */
|
|
#define PDDIRC _GPIO(0x368) /* port D direction clear */
|
|
|
|
#define ICMR _INTC(0x04) /* Interrupt controller mask */
|
|
#define ICMSR _INTC(0x08) /* Interrupt controller mask set */
|
|
#define ICMCR _INTC(0x0c) /* Interrupt controller mask clear */
|
|
|
|
#define TSSR _TCU(0x2c) /* Timer STOP set */
|
|
#define TSCR _TCU(0x3c) /* Timer STOP clear */
|
|
#define TESR _TCU(0x14) /* Timer counter enable set */
|
|
#define TECR _TCU(0x18) /* Timer counter enable clear */
|
|
#define TFR _TCU(0x20) /* Timer flag */
|
|
#define TFSR _TCU(0x24) /* Timer flag set */
|
|
#define TFCR _TCU(0x28) /* Timer flag clear */
|
|
#define TCSR(n) _TCU(0x4c+0x10*(n)) /* Timer control */
|
|
#define TDFR(n) _TCU(0x40+0x10*(n)) /* Timer data full */
|
|
#define TDHR(n) _TCU(0x44+0x10*(n)) /* Timer data half */
|
|
#define TCNT(n) _TCU(0x48+0x10*(n)) /* Timer counter */
|
|
|
|
#define MSC_STRPCL _MSC(0x00) /* Start/stop MMC/SD clock */
|
|
#define MSC_STAT _MSC(0x04) /* MSC status */
|
|
#define MSC_CLKRT _MSC(0x08) /* MSC clock rate */
|
|
#define MSC_CMDAT _MSC(0x0c) /* MMC/SD command and data control */
|
|
#define MSC_RESTO _MSC(0x10) /* MMC/SD response time out */
|
|
#define MSC_BLKLEN _MSC(0x18) /* MMC/SD block length */
|
|
#define MSC_NOB _MSC(0x1c) /* MMC/SD number of blocks */
|
|
#define MSC_SNOB _MSC(0x20) /* MMC/SD successful blocks */
|
|
#define MSC_IMASK _MSC(0x24) /* MMC/SD interrupt mask */
|
|
#define MSC_IREG _MSC(0x28) /* MMC/SD interrupt */
|
|
#define MSC_CMD _MSC(0x2c) /* MMC/SD command index */
|
|
#define MSC_ARG _MSC(0x30) /* MMC/SD command argument */
|
|
#define MSC_RXFIFO _MSC(0x38) /* MMC/SD receive data FIFO */
|
|
#define MSC_TXFIFO _MSC(0x3c) /* MMC/SD transmit data FIFO */
|
|
|
|
#define _DMAn(n, r) _DMAC(0x20*(n)+(r))
|
|
|
|
#define DSA(n) _DMAn(n, 0x00) /* DMA source address */
|
|
#define DTA(n) _DMAn(n, 0x04) /* DMA target address */
|
|
#define DTC(n) _DMAn(n, 0x08) /* DMA transfer count */
|
|
#define DRT(n) _DMAn(n, 0x0c) /* DMA request type */
|
|
#define DCS(n) _DMAn(n, 0x10) /* DMA channel control/status */
|
|
#define DCM(n) _DMAn(n, 0x14) /* DMA command */
|
|
#define DMAC _DMAC(0x300) /* DMA control */
|
|
#define DDR _DMAC(0x308) /* DMA doorbell */
|
|
|
|
#define LCDCTRL _LCD(0x30) /* LCD control */
|
|
|
|
#endif /* !REGS4740_H */
|