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- README: added compatibility of double mode - ubb-vga.c (usage, main): new option -d to double the number of set/clear pairs (making lines longer and the apparent pixel clock slower) - ubb-vga.c (grab, session, main): have a complete set/clear pair for each pixel in double mode
UBB-VGA - VGA-like output via UBB ================================= Sources ------- Timing and the idea for the voltage divider is from: http://faculty.lasierra.edu/~ehwang/public/mypublications/VGA Monitor Controller.pdf More timing parameters: http://tinyvga.com/vga-timing/640x480@60Hz Signal 8:10 VGA ------- ------- --- R DAT2 1 VSYNC DAT3 14 HSYNC CMD 13 G DAT0 2 B DAT1 3 GND GND 5 http://en.wikipedia.org/wiki/VGA_connector Timing ------ Since the Ingenic CPUs take about 8.5 PCLK cycles for a GPIO set or clear, and we can only set or clear a set of signals in GPIO operation, but not set some and clear others, we cannot have a real 320 horizontal pixels. Instead, set and clear operations alternate. This means that the best-case resolution is equivalent to 320 pixels (if the original pixel boundaries coincide with the set/clear phases), but it can be as low as 160 pixels if the boundaries don't match. Furthermore, timing is still a bit too tight. We therefore use a pixel clock that's about 10% slower than the original. Luckily, most monitors don't mind. Compatibility ------------- ubb-vga in single mode has been tested with the following monitors: Display Monitor size Quality ----------------------- --------------- ---------------------------------- Xenon XEN-1510T 15", 1024x768 good Samsung 206NW 20", 1680x1050 poor (horizontal instability) LG W2243C 22", 1920x1080 acceptable (slight instability) LG W2243L 22", 1920x1080 acceptable (slight instability) In double mode: Display Pixels missing Quality left/right ----------------------- --------------- ------------------ Xenon XEN-1510T 5 / 25 good